1.3.1-rc.2

Author: dderjoel

Changelog

@@ -1,3 +1,8 @@
+version 1.3.1-rc.2 (2022-08-09)
+
+	- added four encodings for {vmovdqu, vmovupd} xmmN {xmmN,m/128}
+	    and two            for {vmovdqu, vmovupd} m/128, xmmN 
+
 version 1.3.1-rc.1 (2022-08-09)
 
 	- added encoding for movq mv

Makefile.am

@@ -133,6 +133,8 @@ TEST_TAP = \
 		test/tap/misc.tap \
 		test/tap/movq.tap \
 		test/tap/nasm_incompatible.tap \
+		test/tap/vmovupd.tap \
+		test/tap/vmovdqu.tap \
 		test/tap/xor.tap
 
 # those are the tests, where asmline is expected to fail, for the suite to be ok.

configure.ac

@@ -2,7 +2,7 @@
 # Process this file with autoconf to produce a configure script.
 
 AC_PREREQ([2.69])
-AC_INIT([assemblyline],[1.3.1-rc.1],[yval@cs.adelaide.edu.au])
+AC_INIT([assemblyline],[1.3.1-rc.2],[yval@cs.adelaide.edu.au])
 AC_CONFIG_HEADERS([config.h])
 AC_CONFIG_SRCDIR([src/assemblyline.c])
 AC_CONFIG_AUX_DIR([build-aux])

src/instructions.c

@@ -298,8 +298,12 @@ const struct instr_table INSTR_TABLE[] = {
     {"vdivpd",      vdivpd,      {yym, yyy}, RVM, VECTOR_AVX,     NA,  NA,  3,  {VEX(NDS,B256,X66,X0F,WIG), 0x5e, REG}},
     {"vmovupd",     vmovupd,     {ym, yy},   RM,  VECTOR_AVX,     NA,  NA,  3,  {VEX(NNN,B256,X66,X0F,WIG), 0x10, REG}},
     {{'\0'},        vmovupd,     {my, NA},   MR,  VECTOR_AVX,     NA,  NA,  3,  {VEX(NNN,B256,X66,X0F,WIG), 0x11, REG}},
+    {{'\0'},        vmovupd,     {vm, vv},   RM,  VECTOR_AVX,     NA,  NA,  3,  {VEX(NNN,B128,X66,X0F,WIG), 0x10, REG}},
+    {{'\0'},        vmovupd,     {mv, NA},   MR,  VECTOR_AVX,     NA,  NA,  3,  {VEX(NNN,B128,X66,X0F,WIG), 0x11, REG}},
     {"vmovdqu",     vmovdqu,     {ym, yy},   RM,  VECTOR_AVX,     NA,  NA,  3,  {VEX(NNN,B256,XF3,X0F,WIG), 0x6f, REG}},
     {{'\0'},        vmovdqu,     {my, NA},   MR,  VECTOR_AVX,     NA,  NA,  3,  {VEX(NNN,B256,XF3,X0F,WIG), 0x7f, REG}},
+    {{'\0'},        vmovdqu,     {vm, vv},   RM,  VECTOR_AVX,     NA,  NA,  3,  {VEX(NNN,B128,XF3,X0F,WIG), 0x6f, REG}},
+    {{'\0'},        vmovdqu,     {mv, NA},   MR,  VECTOR_AVX,     NA,  NA,  3,  {VEX(NNN,B128,XF3,X0F,WIG), 0x7f, REG}},
     {"vmulpd",      vmulpd,      {yym, yyy}, RVM, VECTOR_AVX,     NA,  NA,  3,  {VEX(NDS,B256,X66,X0F,WIG), 0x59, REG}},
     {"vpaddb",      vpaddb,      {yym, yyy}, RVM, VECTOR_AVX,     NA,  NA,  3,  {VEX(NDS,B256,X66,X0F,WIG), 0xfc, REG}},
     {{'\0'},        vpaddb,      {vvm, vvv}, RVM, VECTOR_AVX,     NA,  NA,  3,  {VEX(NDS,B128,X66,X0F,WIG), 0xfc, REG}},

test/tap/vmovdqu.tap

@@ -0,0 +1,21 @@
+vmovdqu xmm0, [rsp]
+vmovdqu xmm1, [rsp+ 0x08]
+vmovdqu xmm2, [rsp+ 0x18]
+vmovdqu xmm3, [rsp+ 0x28]
+vmovdqu xmm4, [rsp+ 0x38]
+vmovdqu xmm5, [rsp+ 0x48]
+vmovdqu xmm6, [rsp+ 0x58]
+vmovdqu xmm7, [rsp+ 0x68]
+vmovdqu [rsp+ 0x78],  xmm8
+vmovdqu [rsp+ 0x88],  xmm9
+vmovdqu [rsp+ 0x98],  xmm10
+vmovdqu [rsp+ 0x108], xmm11
+vmovdqu [rsp+ 0x118], xmm12
+vmovdqu [rsp+ 0x128], xmm13
+vmovdqu [rsp+ 0x138], xmm14
+vmovdqu [rsp+ 0x148], xmm15
+
+vmovdqu xmm1, xmm3
+vmovdqu xmm13, xmm3
+vmovdqu xmm13, xmm14
+

test/tap/vmovupd.tap

@@ -0,0 +1,20 @@
+vmovupd xmm0, [rsp]
+vmovupd xmm1, [rsp+ 0x08]
+vmovupd xmm2, [rsp+ 0x18]
+vmovupd xmm3, [rsp+ 0x28]
+vmovupd [rsp+ 0x38], xmm4
+vmovupd [rsp+ 0x48], xmm5
+vmovupd [rsp+ 0x58], xmm6
+vmovupd [rsp+ 0x68], xmm7
+
+vmovupd xmm8, [rsp+ 0x78]
+vmovupd xmm9, [rsp+ 0x88]
+vmovupd xmm10,[rsp+ 0x98]
+vmovupd xmm11,[rsp+ 0x108]
+vmovupd [rsp+ 0x118], xmm12
+vmovupd [rsp+ 0x128], xmm13
+vmovupd [rsp+ 0x138], xmm14
+vmovupd [rsp+ 0x148], xmm15
+
+vmovupd xmm0, xmm1
+vmovupd xmm1, xmm4