Add RDPRU support, fix bug in SHR

Author: Jasper Quirk

Makefile.am

@@ -236,6 +236,7 @@ TEST_ASM = \
 		  test/ptr.asm \
 		  test/push.asm \
 		  test/pxor.asm \
+		  test/rdpmc.asm \
 		  test/rdtsc.asm \
 		  test/rdtscp.asm \
 		  test/ror.asm \

src/enums.h

@@ -217,6 +217,7 @@ typedef enum {
   pxor,
   rcr,
   rdpmc,
+  rdpru,
   rdtsc,
   rdtscp,
   ret,

src/instructions.c

@@ -233,6 +233,7 @@ const struct instr_table INSTR_TABLE[] = {
     {"rcr",         rcr,         {mi, ri},   M,   SHIFT,          1,   3,   4,  {REX, 0xd0, REG, ib}},
     {{'\0'},        rcr,         {NA, NA},   M,   SHIFT,          1,   2,   4,  {REX, 0xc1, REG, ib}},
     {"rdpmc",       rdpmc,       {n,  n},    NA,  OTHER,          NA,  NA,  2,  {0x0f, 0x33}},
+    {"rdpru",       rdpru,       {n,  n},    NA,  OTHER,          NA,  NA,  3,  {0x0f, 0x01, 0xFD}},
     {"rdtsc",       rdtsc,       {n,  n},    NA,  OTHER,          NA,  NA,  2,  {0x0f, 0x31}},
     {"rdtscp",      rdtscp,      {n,  n},    NA,  OTHER,          NA,  NA,  3,  {0x0f, 0x01, 0xf9}},
     {"ret",         ret,         {n,  n},    NA,  CONTROL_FLOW,   NA,  NA,  1,  {0xc3}},
@@ -287,7 +288,7 @@ const struct instr_table INSTR_TABLE[] = {
     {"shld",        shld,        {rri, mri}, MR,  OTHER,          NA,  NA,  5,  {REX, 0x0f, 0xa4, REG, ib}},
     {{'\0'},        shld,        {rrr, mrr}, MR,  OTHER,          NA,  NA,  4,  {REX, 0x0f, 0xa5, REG}},
     {"shlx",        shlx,        {rrr, rmr}, RMV, VECTOR_EXT,     NA,  NA,  3,  {VEX(NDS,LZ,X66,X0F38,W0_W1), 0xf7, REG}},
-    {"shr",         shr,         {mi, ri},   M,   SHIFT,          1,   5,   4,  {REX, 0xbe, REG, ib}},
+    {"shr",         shr,         {mi, ri},   M,   SHIFT,          1,   5,   4,  {REX, 0xd0, REG, ib}},
     {{'\0'},        shr,         {NA, NA},   M,   SHIFT,          1,   5,   4,  {REX, 0xc0, REG, ib}},
     {{'\0'},        shr,         {mr, rr},   M,   SHIFT,          1,   5,   3,  {REX, 0xd2, REG}},
     {"shrd",        shrd,        {mri, rri}, MR,  OTHER,          2,   NA,  4,  {REX, 0x0f, 0xa9, REG}},

test/rdpmc.asm

@@ -0,0 +1,4 @@
+SECTION .text
+GLOBAL test
+test:
+rdpmc

test/rdpru.asm

@@ -0,0 +1,4 @@
+SECTION .text
+GLOBAL test
+test:
+rdpru

test/shr.asm

@@ -1,6 +1,7 @@
 SECTION .text
 GLOBAL test
 test:
+shr r10, 0x1
 shr r10, 0x13
 shr r10, 0x14
 shr r10, 0x15
@@ -17,6 +18,7 @@ shr r10, 0x3e
 shr r10, 0x3f
 shr r10, 0x8
 shr r10, 0x9
+shr r11, 0x1
 shr r11, 0x13
 shr r11, 0x14
 shr r11, 0x15
@@ -37,6 +39,7 @@ shr r11, 0x3e
 shr r11, 0x3f
 shr r11, 0x8
 shr r11, 0x9
+shr r12, 0x1
 shr r12, 0x14
 shr r12, 0x15
 shr r12, 0x1c
@@ -56,6 +59,7 @@ shr r12, 0x3d
 shr r12, 0x3e
 shr r12, 0x3f
 shr r12, 0x9
+shr r13, 0x1
 shr r13, 0x13
 shr r13, 0x14
 shr r13, 0x15
@@ -298,6 +302,7 @@ shr al, 0x13
 shr bl, 0x13
 shr cl, 0x13
 shr dl, 0x13
+shr dil, 0x1
 shr dil, 0x13
 shr r8w, 0x13
 shr r9w, 0x13