-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathcontrol_emulator.chk
More file actions
118 lines (116 loc) · 9.45 KB
/
control_emulator.chk
File metadata and controls
118 lines (116 loc) · 9.45 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
----------------------------------------
| P a r t i t i o n S u c c e e d |
----------------------------------------
0 Group(s)
ClkInput[3]: clk_in_j1(37, sclk) ext_clk_in(38, sclk) int_clk_in(39, sclk)
GACLK: 98
----------------- B l o c k 0 ------------------
PLApt(22/48), Fanin(24/38), Clk(2/2), Bct(1/8), Pin(5/8), Mcell(16/16), FbNand(0/0)
PLApts[22/39] 3 4 5 8 68 21 25 98 103 23 102 28 18 () 19 () () () 22 () () () 101 () 14 () () () 100 () 20 ()
17 () 15 () () () 16
Fanins[24] clk_out_p2.n N_PZ_303.n fcl_extClk_extCtrl/hold<0>.n fcl_extClk_extCtrl/hold<1>.n
fcl_extClk_extCtrl/hold<2>.n fcl_extClk_extCtrl/hold<3>.n fcl_intClk_extCtrl/hold<0>.n
fcl_intClk_extCtrl/hold<1>.n fcl_intClk_extCtrl/hold<2>.n fcl_intClk_extCtrl/hold<3>.n
miscControls/delay_reg<0>.n miscControls/delay_reg<1>.n miscControls/delay_reg<2>.n
miscControls/delay_reg<3>.n miscControls/penable_reg.n qie_reset_out_extClk_extCtrl.n
qie_reset_out_intClk_extCtrl.n aux_in.p clk_in_j1.p clk_select.p ext_clk_in.p int_clk_in.p
mode_select.p qie_reset_in.p
clk[2/2] ext_clk_in clk_in_j1
BCTpts[1] ct0:-999 ct1:-999 ct2:-999 ct3:-999 ct4:-999 ct5:-999 ct6:-999 ct7:98
Signal[19] [clk_out_p2(59),clk_out_p2(27)] [penable(54),penable(31)] [GPIO_Extra0(28)] [pgood(30)]
[qie_reset_in(35)] [fcl_extClk_extCtrl/hold<1>(53)] [fcl_extClk_extCtrl/hold<2>(60)]
[fcl_extClk_extCtrl/hold<3>(57)] [fcl_extClk_extCtrl/hold<0>(56)]
[qie_reset_out_extClk_extCtrl(51)] [fcl_intClk_extCtrl/hold<0>(50)]
[qie_reset_out_intClk_extCtrl(49)] [fcl_intClk_extCtrl/hold<3>(48)]
[fcl_intClk_extCtrl/hold<2>(47)] [fcl_intClk_extCtrl/hold<1>(58)] [miscControls/delay_reg<1>(55)]
[miscControls/delay_reg<2>(52)] [miscControls/delay_reg<3>(46)] [miscControls/delay_reg<4>(45)]
Signal[19] [ 0: miscControls/delay_reg<4>(45) qie_reset_in(35) ][ 1: miscControls/delay_reg<3>(46) (34) ]
[ 2: fcl_intClk_extCtrl/hold<2>(47) ][ 3: fcl_intClk_extCtrl/hold<3>(48) ][ 4:
qie_reset_out_intClk_extCtrl(49) ][ 5: fcl_intClk_extCtrl/hold<0>(50) ][ 6:
qie_reset_out_extClk_extCtrl(51) ][ 7: miscControls/delay_reg<2>(52) (33) ][ 8:
fcl_extClk_extCtrl/hold<1>(53) (32) ][ 9: penable(54) penable(31) ][ 10:
miscControls/delay_reg<1>(55) pgood(30) ][ 11: fcl_extClk_extCtrl/hold<0>(56) ][ 12:
fcl_extClk_extCtrl/hold<3>(57) ][ 13: fcl_intClk_extCtrl/hold<1>(58) GPIO_Extra0(28) ][ 14:
clk_out_p2(59) clk_out_p2(27) ][ 15: fcl_extClk_extCtrl/hold<2>(60) ]
FbNand[ 0]
----------------- B l o c k 1 ------------------
PLApt(45/48), Fanin(24/38), Clk(1/2), Bct(0/8), Pin(6/8), Mcell(16/16), FbNand(0/0)
PLApts[45/45] 9 24 26 27 41 69 70 6 29 30 42 67 40 52 65 31 43 64 39 51 63 38 50 62 37 49 61 36 48 60 35 47
59 34 46 58 33 45 66 57 32 44 54 55 56
Fanins[24] fcl_intClk_intCtrl/upc/out<0>.n fcl_intClk_intCtrl/upc/out<10>.n fcl_intClk_intCtrl/upc/out<11>.n
fcl_intClk_intCtrl/upc/out<1>.n fcl_intClk_intCtrl/upc/out<2>.n fcl_intClk_intCtrl/upc/out<3>.n
fcl_intClk_intCtrl/upc/out<4>.n fcl_intClk_intCtrl/upc/out<5>.n fcl_intClk_intCtrl/upc/out<6>.n
fcl_intClk_intCtrl/upc/out<7>.n fcl_intClk_intCtrl/upc/out<8>.n fcl_intClk_intCtrl/upc/out<9>.n
qie_reset_out_extClk_extCtrl.n qie_reset_out_intClk_extCtrl.n qie_reset_out_intClk_intCtrl.n
reset_out_extClk_extCtrl.n reset_out_intClk_extCtrl.n reset_out_intClk_intCtrl.n
wte_out_intClk_intCtrl.n clk_select.p ext_clk_in.p mode_select.p qie_reset_in.p qie_reset_source.p
clk[1/2] GND int_clk_in
BCTpts[0] ct0:-999 ct1:-999 ct2:-999 ct3:-999 ct4:-999 ct5:-999 ct6:-999 ct7:-999
Signal[19] [qie_reset_out(74),qie_reset_out(5)] [reset_out(71),reset_out(3)] [wte_out(75),wte_out(6)]
[clk_select(44)] [mode_select(2)] [qie_reset_source(42)] [wte_out_intClk_intCtrl(69)]
[qie_reset_out_intClk_intCtrl(76)] [fcl_intClk_intCtrl/upc/out<11>(73)]
[fcl_intClk_intCtrl/upc/out<10>(72)] [fcl_intClk_intCtrl/upc/out<9>(68)]
[fcl_intClk_intCtrl/upc/out<8>(67)] [fcl_intClk_intCtrl/upc/out<7>(66)]
[fcl_intClk_intCtrl/upc/out<6>(65)] [fcl_intClk_intCtrl/upc/out<5>(64)]
[fcl_intClk_intCtrl/upc/out<4>(70)] [fcl_intClk_intCtrl/upc/out<3>(63)]
[fcl_intClk_intCtrl/upc/out<2>(62)] [fcl_intClk_intCtrl/upc/out<1>(61)]
Signal[19] [ 0: fcl_intClk_intCtrl/upc/out<1>(61) qie_reset_source(42) ][ 1:
fcl_intClk_intCtrl/upc/out<2>(62) (43) ][ 2: fcl_intClk_intCtrl/upc/out<3>(63) clk_select(44) ]
[ 3: fcl_intClk_intCtrl/upc/out<5>(64) ][ 4: fcl_intClk_intCtrl/upc/out<6>(65) ][ 5:
fcl_intClk_intCtrl/upc/out<7>(66) ][ 6: fcl_intClk_intCtrl/upc/out<8>(67) ][ 7:
fcl_intClk_intCtrl/upc/out<9>(68) ][ 8: wte_out_intClk_intCtrl(69) (1) ][ 9:
fcl_intClk_intCtrl/upc/out<4>(70) mode_select(2) ][ 10: reset_out(71) reset_out(3) ][ 11:
fcl_intClk_intCtrl/upc/out<10>(72) ][ 12: fcl_intClk_intCtrl/upc/out<11>(73) ][ 13:
qie_reset_out(74) qie_reset_out(5) ][ 14: wte_out(75) wte_out(6) ][ 15:
qie_reset_out_intClk_intCtrl(76) ]
FbNand[ 0]
----------------- B l o c k 2 ------------------
PLApt(21/48), Fanin(26/38), Clk(2/2), Bct(0/8), Pin(5/8), Mcell(16/16), FbNand(0/0)
PLApts[21/39] 82 92 83 93 84 94 85 95 7 86 96 () 109 () 97 () 108 () 107 () 106 () 105 () () () 13 () () ()
() () () () 104 () 53 () 10
Fanins[26] N_PZ_303.n fcl_intClk_intCtrl/upc/out<0>.n miscControls/delay_reg<0>.n
miscControls/delay_reg<10>.n miscControls/delay_reg<11>.n miscControls/delay_reg<12>.n
miscControls/delay_reg<13>.n miscControls/delay_reg<14>.n miscControls/delay_reg<15>.n
miscControls/delay_reg<16>.n miscControls/delay_reg<17>.n miscControls/delay_reg<18>.n
miscControls/delay_reg<1>.n miscControls/delay_reg<2>.n miscControls/delay_reg<3>.n
miscControls/delay_reg<4>.n miscControls/delay_reg<5>.n miscControls/delay_reg<6>.n
miscControls/delay_reg<7>.n miscControls/delay_reg<8>.n miscControls/delay_reg<9>.n
qie_reset_out_intClk_intCtrl.n reset_out_intClk_intCtrl.n GPIO_Extra0.p pgood.p reset_switch.p
clk[2/2] int_clk_in ext_clk_in
BCTpts[0] ct0:-999 ct1:-999 ct2:-999 ct3:-999 ct4:-999 ct5:-999 ct6:-999 ct7:-999
Signal[20] [aux_out(86),aux_out(21)] [aux2(22)] [aux3(23)] [aux_in(20)] [reset_switch(25)]
[reset_out_intClk_intCtrl(77)] [reset_out_extClk_extCtrl(92)] [fcl_intClk_intCtrl/upc/out<0>(91)]
[miscControls/delay_reg<5>(90)] [miscControls/delay_reg<6>(84)] [miscControls/delay_reg<7>(83)]
[miscControls/delay_reg<9>(82)] [miscControls/delay_reg<11>(81)] [miscControls/delay_reg<12>(79)]
[miscControls/delay_reg<13>(89)] [miscControls/delay_reg<14>(88)]
[miscControls/delay_reg<15>(87)] [miscControls/delay_reg<16>(85)]
[miscControls/delay_reg<18>(80)] [miscControls/delay_reg<17>(78)]
Signal[20] [ 0: reset_out_intClk_intCtrl(77) (26) ][ 1: miscControls/delay_reg<17>(78) reset_switch(25) ]
[ 2: miscControls/delay_reg<12>(79) ][ 3: miscControls/delay_reg<18>(80) aux3(23) ][ 4:
miscControls/delay_reg<11>(81) ][ 5: miscControls/delay_reg<9>(82) ][ 6:
miscControls/delay_reg<7>(83) ][ 7: miscControls/delay_reg<6>(84) ][ 8:
miscControls/delay_reg<16>(85) aux2(22) ][ 9: aux_out(86) aux_out(21) ][ 10:
miscControls/delay_reg<15>(87) aux_in(20) ][ 11: miscControls/delay_reg<14>(88) (19) ][ 12:
miscControls/delay_reg<13>(89) (18) ][ 13: miscControls/delay_reg<5>(90) ][ 14:
fcl_intClk_intCtrl/upc/out<0>(91) ][ 15: reset_out_extClk_extCtrl(92) ]
FbNand[ 0]
----------------- B l o c k 3 ------------------
PLApt(20/48), Fanin(24/38), Clk(1/2), Bct(0/8), Pin(2/8), Mcell(8/16), FbNand(0/0)
PLApts[20/20] 77 99 79 80 81 91 74 75 10 76 11 88 90 71 72 73 12 78 87 89
Fanins[24] N_PZ_303.n miscControls/delay_reg<0>.n miscControls/delay_reg<10>.n miscControls/delay_reg<11>.n
miscControls/delay_reg<12>.n miscControls/delay_reg<13>.n miscControls/delay_reg<14>.n
miscControls/delay_reg<15>.n miscControls/delay_reg<16>.n miscControls/delay_reg<17>.n
miscControls/delay_reg<18>.n miscControls/delay_reg<1>.n miscControls/delay_reg<2>.n
miscControls/delay_reg<3>.n miscControls/delay_reg<4>.n miscControls/delay_reg<5>.n
miscControls/delay_reg<6>.n miscControls/delay_reg<7>.n miscControls/delay_reg<8>.n
miscControls/delay_reg<9>.n GPIO_Extra0.p aux2.p aux3.p reset_switch.p
clk[1/2] GND clk_in_j1
BCTpts[0] ct0:-999 ct1:-999 ct2:-999 ct3:-999 ct4:-999 ct5:-999 ct6:-999 ct7:-999
Signal[ 8] [peltEnab1(94),peltEnab1(8)] [peltEnab2(97),peltEnab2(11)] [reset_out_intClk_extCtrl(93)]
[miscControls/delay_reg<0>(108)] [miscControls/penable_reg(107)]
[miscControls/delay_reg<10>(106)] [miscControls/delay_reg<8>(105)] [N_PZ_303(100)]
Signal[ 8] [ 0: reset_out_intClk_extCtrl(93) (7) ][ 1: peltEnab1(94) peltEnab1(8) ][ 2: ][ 3: (10) ][ 4:
peltEnab2(97) peltEnab2(11) ][ 5: ][ 6: ][ 7: N_PZ_303(100) ][ 8: (12) ][ 9: (13) ][ 10:
(14) ][ 11: (15) ][ 12: miscControls/delay_reg<8>(105) ][ 13: miscControls/delay_reg<10>(106)
][ 14: miscControls/penable_reg(107) ][ 15: miscControls/delay_reg<0>(108) ]
FbNand[ 0]