soc/intel/cmn/block/acpi: Add new GPIO ASL Method

Ths new Method, GSCI, allows control over whether or not IRQs are routed
as SCI#s for the given GPIO.

Signed-off-by: Tim Wawrzynczak <[email protected]>
Change-Id: Ic61caaf77d2c6e295e67a1501544e8b8fc6f3b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66813
Reviewed-by: Angel Pons <[email protected]>
Reviewed-by: Subrata Banik <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>

Author: Tim Wawrzynczak

src/soc/intel/common/block/acpi/acpi/gpio_op.asl

@@ -117,3 +117,22 @@ Method (GRXE, 2, Serialized)
 
 	RXDI = !Arg1
 }
+
+/*
+ * Enable/Disable SCI interrupt route
+ * Arg0 - GPIO Number
+ * Arg1 - Route to SCI#
+ *     0 = Disable IRQ route to SCI#
+ *     1 = Enable IRQ route to SCI#
+ */
+Method (GSCI, 2, Serialized)
+{
+	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+	Field (PREG, AnyAcc, NoLock, Preserve)
+	{
+		,     19,
+		SCIR, 1,
+	}
+
+	SCIR = Arg1
+}