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robtaylorrobtaylor
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Fix lint issues from lint config changes
1 parent 5c67c72 commit cc5e3f4

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+8
-20
lines changed

10 files changed

+8
-20
lines changed

‎mcu_soc/design/design.py

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from amaranth import Module
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from amaranth.lib import wiring
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from amaranth.lib.wiring import In, Out, flipped, connect
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from amaranth.lib.wiring import Out, flipped, connect
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from amaranth_soc import csr, wishbone
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from amaranth_soc.csr.wishbone import WishboneCSRBridge

‎mcu_soc/design/ips/pdm.py

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from amaranth import *
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from amaranth import Elaboratable, Module
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from amaranth.build import Platform
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from amaranth import Module
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from amaranth.lib import wiring
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from amaranth.lib.wiring import In, Out, flipped, connect

‎mcu_soc/design/ips/pwm.py

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@@ -1,6 +1,5 @@
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from amaranth import *
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from amaranth import Elaboratable, Module
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from amaranth.build import Platform
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from amaranth import Module
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from amaranth.lib import wiring
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from amaranth.lib.wiring import In, Out, flipped, connect

‎mcu_soc/design/sim/doit_build.py

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RUNTIME_DIR = importlib.resources.files("yowasp_yosys") / "share/include/backends/cxxrtl/runtime"
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ZIG_CXX = f"{sys.executable} -m ziglang c++"
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CXXFLAGS = f"-O3 -g -std=c++17 -Wno-array-bounds -Wno-shift-count-overflow -fbracket-depth=1024"
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CXXFLAGS = "-O3 -g -std=c++17 -Wno-array-bounds -Wno-shift-count-overflow -fbracket-depth=1024"
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INCLUDES = f"-I {OUTPUT_DIR} -I {COMMON_DIR} -I {COMMON_DIR}/vendor -I {RUNTIME_DIR}"
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‎mcu_soc/design/software/doit_build.py

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import shutil
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from doit import create_after
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from doit.action import CmdAction
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import chipflow_lib.config
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@@ -15,7 +14,7 @@
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CINCLUDES = f"-I. -I{BUILD_DIR} -I{DESIGN_DIR}/software"
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LINKER_SCR = f"{BUILD_DIR}/generated/sections.lds"
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SOFTWARE_START = f"{BUILD_DIR}/generated/start.S"
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CFLAGS = f"-g -mcpu=baseline_rv32-a-c-d -mabi=ilp32 -Wl,-Bstatic,-T,"
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CFLAGS = "-g -mcpu=baseline_rv32-a-c-d -mabi=ilp32 -Wl,-Bstatic,-T,"
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CFLAGS += f"{LINKER_SCR},--strip-debug -static -ffreestanding -nostdlib {CINCLUDES}"
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‎mcu_soc/design/steps/sim.py

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from chipflow_lib.steps.sim import SimStep
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from amaranth import *
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from amaranth.lib import wiring
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from amaranth.lib.wiring import connect, flipped
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from amaranth.back import rtlil
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from ..design import MySoC

‎minimal/design/design.py

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from chipflow_lib.platforms.sim import SimPlatform
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from chipflow_lib.software.soft_gen import SoftwareGenerator
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from amaranth import Module
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from amaranth.lib import wiring
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from amaranth.lib.wiring import In, Out, flipped, connect
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from amaranth.lib.wiring import Out, flipped, connect
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from amaranth_soc import csr, wishbone
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from amaranth_soc.csr.wishbone import WishboneCSRBridge
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from amaranth_soc.wishbone.sram import WishboneSRAM
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from amaranth_orchard.io import GPIOPeripheral
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from amaranth_orchard.io import UARTPeripheral
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from amaranth_orchard.io import SPISignature, SPIPeripheral
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from amaranth_orchard.io import I2CSignature, I2CPeripheral
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from minerva.core import Minerva
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from chipflow_lib.platforms import InputPinSignature, OutputPinSignature
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# from .ips.pdm import PDMPeripheral
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__all__ = ["MySoC"]

‎minimal/design/sim/doit_build.py

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RUNTIME_DIR = importlib.resources.files("yowasp_yosys") / "share/include/backends/cxxrtl/runtime"
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ZIG_CXX = f"{sys.executable} -m ziglang c++"
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CXXFLAGS = f"-O3 -g -std=c++17 -Wno-array-bounds -Wno-shift-count-overflow -fbracket-depth=1024"
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CXXFLAGS = "-O3 -g -std=c++17 -Wno-array-bounds -Wno-shift-count-overflow -fbracket-depth=1024"
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INCLUDES = f"-I {OUTPUT_DIR} -I {COMMON_DIR} -I {COMMON_DIR}/vendor -I {RUNTIME_DIR}"
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‎minimal/design/software/doit_build.py

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import shutil
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from doit import create_after
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from doit.action import CmdAction
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import chipflow_lib.config
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@@ -15,7 +14,7 @@
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CINCLUDES = f"-I. -I{BUILD_DIR} -I{DESIGN_DIR}/software"
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LINKER_SCR = f"{BUILD_DIR}/generated/sections.lds"
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SOFTWARE_START = f"{BUILD_DIR}/generated/start.S"
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CFLAGS = f"-g -mcpu=baseline_rv32-a-c-d -mabi=ilp32 -Wl,-Bstatic,-T,"
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CFLAGS = "-g -mcpu=baseline_rv32-a-c-d -mabi=ilp32 -Wl,-Bstatic,-T,"
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CFLAGS += f"{LINKER_SCR},--strip-debug -static -ffreestanding -nostdlib {CINCLUDES}"
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‎minimal/design/steps/sim.py

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from chipflow_lib.steps.sim import SimStep
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from amaranth import *
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from amaranth.lib import wiring
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from amaranth.lib.wiring import connect, flipped
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from amaranth.back import rtlil
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from ..design import MySoC

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