Final fixes. IT WORKS!

Bug fixes made:
* Correct the assignment of output enable of `adder_sub`
* Make sure `i_en` for `dff_posedge` allowed input ONLY during +ve clk
* Make `ring_counter` shift ONLY on -ve clk edge
* Change bus split arrangement in `top` module. It is now a many-to-one assignment.

Other changes:
* Tweak test benches to conform to fixes
* Change contents of `rom16_8bit` to test different programs

Author: CodePurble

hdl/adder_sub_8.v

@@ -20,11 +20,13 @@ module adder_sub_8(
     );
     adder_ripple_8bit r1(
         .a(A), .b(B_in), .cin(cin_adder),
-        .sum(out), .cout(cout)
+        .sum(add_sub_out), .cout(cout)
     );
 
+    wire add_sub_low_out_en = ~out_en;
+
     tribuf_8bit tri8(
         .in(add_sub_out), .out(out),
-        .low_enable(out_en)
+        .low_enable(add_sub_low_out_en)
     );
 endmodule

hdl/dff_posedge.v

@@ -13,7 +13,7 @@ module dff_posedge(
     output reg [DATA_WIDTH - 1:0] q;
     output [DATA_WIDTH - 1:0] qbar;
 
-    always @(posedge clk or clr or i_en)
+    always @(posedge clk or clr)
     begin
         if(clr)
             q <= 0;

hdl/ring_counter.v

@@ -3,12 +3,12 @@
 module ring_counter (t, clk, res);
     input clk, res;
     output reg [5:0] t = 6'b100000;
-    // always @(negedge clk or res or t)
-    always @(negedge clk)
+
+    always @(negedge clk or res)
     begin
-        if(res==1)
+        if(res == 1)
             t = 6'b100000;
-        else
+        else if(clk == 0) // Essentially shift right ONLY when it is a falling edge
         begin
             if(t == 6'b000001)
                 t = 6'b100000;

hdl/rom16_8bit.v

@@ -13,15 +13,15 @@ module rom16_8bit(
         begin
             case(addr)
                 4'h0: data_out = 8'h08;
-                4'h1: data_out = 8'h19;
+                4'h1: data_out = 8'h29;
                 4'h2: data_out = 8'hee;
                 4'h3: data_out = 8'hff;
                 4'h4: data_out = 8'h00;
                 4'h5: data_out = 8'h00;
                 4'h6: data_out = 8'h00;
                 4'h7: data_out = 8'h00;
-                4'h8: data_out = 8'h08;
-                4'h9: data_out = 8'h01;
+                4'h8: data_out = 8'h01;
+                4'h9: data_out = 8'h08;
                 4'ha: data_out = 8'h00;
                 4'hb: data_out = 8'h00;
                 4'hc: data_out = 8'h00;

hdl/top.v

@@ -1,9 +1,10 @@
-module top(bus, clk, out, clr);
-    output tri [7:0] bus;
+module top(bus_high, bus_low, clk, out, clr);
+    output tri [3:0] bus_high;
+    output tri [3:0] bus_low;
     output [7:0] out;
     input clk, clr;
     // Globals
-    wire [3:0] bus_high, bus_low;
+    wire [7:0] bus;
     wire buf_clk;
 
     // Control signals
@@ -33,14 +34,14 @@ module top(bus, clk, out, clr);
     bufif1(buf_clk, clk, low_halt);
 
     program_counter pc(
-        .inc(inc), .clk(buf_clk), .pc_out_en(pc_out_en), .clr(clr), .out(bus_low)
+        .inc(inc), .clk(buf_clk), .pc_out_en(pc_out_en), .clr(clr), .out(bus[3:0])
     );
 
     wire [3:0] mar_out;
     wire ld_mar;
     not (ld_mar, low_ld_mar);
     dff_posedge #(4) mar(
-        .d(bus_low), .q(mar_out), .i_en(ld_mar), .clr(clr), .clk(buf_clk)
+        .d(bus[3:0]), .q(mar_out), .i_en(ld_mar), .clr(clr), .clk(buf_clk)
     );
 
     rom16_8bit mem(
@@ -51,37 +52,37 @@ module top(bus, clk, out, clr);
     wire ld_ir;
     not (ld_ir, low_ld_ir);
     dff_posedge #(8) ir(
-        .d({bus_high, bus_low}), .q(ir_out), .i_en(ld_ir), .clr(clr), .clk(buf_clk)
+        .d(bus), .q(ir_out), .i_en(ld_ir), .clr(clr), .clk(buf_clk)
     );
 
-    tribuf_4bit buf0(.in(ir_out[3:0]), .out(bus_low), .low_enable(low_ir_out_en));
+    tribuf_4bit buf0(.in(ir_out[3:0]), .out(bus[3:0]), .low_enable(low_ir_out_en));
     assign op_code = ir_out[7:4]; // Directly pass to control_sequencer
 
 
     wire [7:0] acc_out;
     wire ld_acc;
     not (ld_acc, low_ld_acc);
     dff_posedge #(8) acc(
-        .d({bus_high, bus_low}), .q(acc_out), .i_en(ld_acc), .clr(clr), .clk(buf_clk)
+        .d(bus), .q(acc_out), .i_en(ld_acc), .clr(clr), .clk(buf_clk)
     );
     wire low_acc_out_en;
     assign low_acc_out_en = ~acc_out_en;
-    tribuf_8bit buf1(.in(acc_out), .out({bus_high, bus_low}), .low_enable(low_acc_out_en));
+    tribuf_8bit buf1(.in(acc_out), .out(bus), .low_enable(low_acc_out_en));
 
     wire [7:0] b_reg_out;
     wire ld_b_reg;
     not (ld_b_reg, low_ld_b_reg);
     dff_posedge #(8) b_reg(
-        .d({bus_high, bus_low}), .q(b_reg_out), .i_en(ld_b_reg), .clr(clr), .clk(buf_clk)
+        .d(bus), .q(b_reg_out), .i_en(ld_b_reg), .clr(clr), .clk(buf_clk)
     );
 
-    adder_sub_8 asub(.A(acc_out), .B(b_reg_out), .sub(sub_add), .cout(), .out({bus_high, bus_low}), .out_en(subadd_out_en));
+    adder_sub_8 asub(.A(acc_out), .B(b_reg_out), .sub(sub_add), .cout(), .out(bus), .out_en(subadd_out_en));
 
     wire ld_out_reg;
     not (ld_out_reg, low_ld_out_reg);
     dff_posedge #(8) out_reg(
-        .d({bus_high, bus_low}), .q(out), .i_en(ld_out_reg), .clr(clr), .clk(buf_clk)
+        .d(bus), .q(out), .i_en(ld_out_reg), .clr(clr), .clk(buf_clk)
     );
 
-    assign bus = {bus_high, bus_low};
+    assign {bus_high, bus_low} = bus;
 endmodule

test/tb_top.v

@@ -1,14 +1,15 @@
 module tb_top();
     reg clk, clr;
     wire [7:0] out;
-    wire [7:0] bus;
+    wire [3:0] bus_high;
+    wire [3:0] bus_low;
     top uut(
-        .bus(bus), .clk(clk), .clr(clr), .out(out)
+        .bus_high(bus_high), .bus_low(bus_low), .clk(clk), .clr(clr), .out(out)
     );
 
     initial
     begin
-        #10 clk = 1'b1;
+        #10 clk = 1'b0;
     end
 
     always
@@ -26,7 +27,7 @@ module tb_top();
     begin
         #2 clr = 1'b1;
         #6 clr = 1'b0;
-        #300 $finish;
+        #500 $finish;
     end
 
     initial