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rmp_test_stm32f405rg_rvm.h
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/******************************************************************************
Filename : rmp_test_stm32f405rg_rvm.h
Author : pry
Date : 22/07/2017
Licence : The Unlicense; see LICENSE for details.
Description : The testbench for STM32F405RG, running in the RVM.
How to use this test header:
1. Add relevant test file to the project.
2. Add memory access permission as follows:
<Type>V_Device</Type>
<Base>0x40000000</Base>
<Size>0x20000000</Size>
<Align>Auto</Align>
<Type>Device</Type>
<Attribute>RWS</Attribute>
3. Add kernel function as follows:
<Name>INT_LOCAL_MOD</Name>
<Start>0xF100</Start>
<End>0xF100</End>
4. Add interrupt vector declaration as follows (optional):
<Name>TIM4</Name>
<Number>30</Number>
5. Place the following lines into the RME_Spurious_Handler (or a
dedicated handler if you'd wish to use one), so that we clear
the interrupt flags as soon as it fires.
#define TIM4_SR *((volatile rme_u32_t*)(0x40000810U))
TIM4_SR=0U;
return RME_RVM_VCT_SIG_INIT;
These steps can be automatically completed by the RVM generator.
ARMCC 6.19 -O3 (SysTick turned on, w/FPU context)
___ __ ___ ___
/ _ \ / |/ // _ \ Simple real-time kernel
/ , _// /|_/ // ___/ Standard benchmark test
/_/|_|/_/ /_//_/
====================================================
Test (number in CPU cycles) : AVG / MAX / MIN
Yield : 252 / 304 / 252
Mailbox : 432 / 2432 / 432
Semaphore : 372 / 2416 / 372
FIFO : 200 / 2180 / 200
Message queue : 704 / 2772 / 704
Blocking message queue : 914 / 2988 / 912
Alarm combination (1/2/3/5/7) : 800 / 3116 / 472
Memory allocation/free pair : 387 / 644 / 372
ISR Mailbox : 1304 / 1304 / 1304
ISR Semaphore : 1222 / 3128 / 1216
ISR Message queue : 1424 / 3332 / 1424
ISR Blocking message queue : 1578 / 3484 / 1572
ISR RVM activation relay : 2654 / 2656 / 2596
GCC 13.2.1 -O3 (SysTick turned on, w/FPU context)
___ __ ___ ___
/ _ \ / |/ // _ \ Simple real-time kernel
/ , _// /|_/ // ___/ Standard benchmark test
/_/|_|/_/ /_//_/
====================================================
Test (number in CPU cycles) : AVG / MAX / MIN
Yield : 312 / 2252 / 312
Mailbox : 549 / 2660 / 540
Semaphore : 448 / 2556 / 444
FIFO : 204 / 2264 / 204
Message queue : 671 / 2796 / 656
Blocking message queue : 1013 / 3112 / 1012
Alarm combination (1/2/3/5/7) : 740 / 2832 / 460
Memory allocation/free pair : 380 / 643 / 368
ISR Mailbox : 1440 / 1440 / 1440
ISR Semaphore : 1350 / 3272 / 1348
ISR Message queue : 1510 / 3436 / 1508
ISR Blocking message queue : 1680 / 2212 / 1680
ISR RVM activation relay : 2656 / 4440 / 2572
ARMCC 6.19 -O3 (SysTick turned on, w/o FPU context)
___ __ ___ ___
/ _ \ / |/ // _ \ Simple real-time kernel
/ , _// /|_/ // ___/ Standard benchmark test
/_/|_|/_/ /_//_/
====================================================
Test (number in CPU cycles) : AVG / MAX / MIN
Yield : 252 / 1912 / 252
Mailbox : 432 / 568 / 432
Semaphore : 372 / 2176 / 372
FIFO : 200 / 1884 / 200
Message queue : 720 / 2488 / 720
Blocking message queue : 939 / 2756 / 932
Alarm combination (1/2/3/5/7) : 799 / 2824 / 472
Memory allocation/free pair : 384 / 611 / 368
ISR Mailbox : 1201 / 2912 / 1200
ISR Semaphore : 1100 / 1516 / 1100
ISR Message queue : 1298 / 3832 / 1296
ISR Blocking message queue : 1448 / 1448 / 1448
ISR RVM activation relay : 2360 / 3984 / 2224
GCC 13.2.1 -O3 (SysTick turned on, w/o FPU context)
___ __ ___ ___
/ _ \ / |/ // _ \ Simple real-time kernel
/ , _// /|_/ // ___/ Standard benchmark test
/_/|_|/_/ /_//_/
====================================================
Test (number in CPU cycles) : AVG / MAX / MIN
Yield : 312 / 2020 / 312
Mailbox : 541 / 2352 / 540
Semaphore : 448 / 2252 / 444
FIFO : 204 / 1948 / 204
Message queue : 666 / 2508 / 656
Blocking message queue : 1013 / 2792 / 1012
Alarm combination (1/2/3/5/7) : 740 / 2452 / 460
Memory allocation/free pair : 379 / 602 / 368
ISR Mailbox : 1333 / 3012 / 1332
ISR Semaphore : 1244 / 2900 / 1244
ISR Message queue : 1410 / 4452 / 1408
ISR Blocking message queue : 1580 / 1580 / 1580
ISR RVM activation relay : 2348 / 3956 / 2284
******************************************************************************/
/* Include *******************************************************************/
#include "rmp.h"
#include "rvm_guest.h"
#define RVM_TEST_VIRTUAL_INC
#include "rvm_test.h"
#undef RVM_TEST_VIRTUAL_INC
#define RVM_BENCHMARK_VIRTUAL_INC
#include "Test/rvm_benchmark.h"
#undef RVM_BENCHMARK_VIRTUAL_INC
/* End Include ***************************************************************/
/* Define ********************************************************************/
/* Counter read wrapper */
#define RMP_CNT_READ() ((rmp_tim_t)((TIM2_CNT)<<1))
/* Memory pool test switch */
#define TEST_MEM_POOL (8192U)
/* Minimal build switch */
/* #define MINIMAL_SIZE */
/* Timestamp data type */
typedef rmp_ptr_t rmp_tim_t;
/* Hardware definitions so we don't rely on STM32 HAL */
#define TIM2_BASE (0x40000000U)
#define TIM4_BASE (0x40000800U)
#define RCC_BASE (0x40023800U)
#define RCC_APB1ENR *((volatile rmp_u32_t*)(RCC_BASE+0x40U))
#define RCC_APB1ENR_TIM2 (1U<<0)
#define RCC_APB1ENR_TIM4 (1U<<2)
#define TIM2_CR1 *((volatile rmp_u32_t*)(TIM2_BASE+0x00U))
#define TIM2_ARR *((volatile rmp_u32_t*)(TIM2_BASE+0x2CU))
#define TIM2_PSC *((volatile rmp_u32_t*)(TIM2_BASE+0x28U))
#define TIM2_CNT *((volatile rmp_u32_t*)(TIM2_BASE+0x24U))
#define TIM4_CR1 *((volatile rmp_u32_t*)(TIM4_BASE+0x00U))
#define TIM4_ARR *((volatile rmp_u32_t*)(TIM4_BASE+0x2CU))
#define TIM4_PSC *((volatile rmp_u32_t*)(TIM4_BASE+0x28U))
#define TIM4_DIER *((volatile rmp_u32_t*)(TIM4_BASE+0x0CU))
#define TIM4_SR *((volatile rmp_u32_t*)(TIM4_BASE+0x10U))
#define TIM_CR1_CEN (1U<<0)
#define TIM_COUNTERMODE_UP (0U)
#define TIM_COUNTERMODE_DOWN (1U<<4)
#define TIM_CLOCKDIVISION_DIV1 (0U)
/* End Define ****************************************************************/
/* Global ********************************************************************/
#ifndef MINIMAL_SIZE
rmp_ptr_t Stack_1[256];
rmp_ptr_t Stack_2[256];
void Timer_Init(void);
void Int_Init(void);
void Int_Handler(void);
void Int_Disable(void);
/* End Global ****************************************************************/
/* Function:Timer_Init ********************************************************
Description : Initialize the timer for timing measurements. This function needs
to be adapted to your specific hardware.
Input : None.
Output : None.
Return : None.
******************************************************************************/
void Timer_Init(void)
{
/* TIM2 clock = 1/2 CPU clock */
TIM2_CR1=TIM_COUNTERMODE_UP|TIM_CLOCKDIVISION_DIV1;
TIM2_ARR=(unsigned int)(-1);
TIM2_PSC=0U;
RCC_APB1ENR|=RCC_APB1ENR_TIM2;
TIM2_CR1|=TIM_CR1_CEN;
}
/* End Function:Timer_Init ***************************************************/
/* Function:Int_Init **********************************************************
Description : Initialize an periodic interrupt source. This function needs
to be adapted to your specific hardware.
Input : None.
Output : None.
Return : None.
******************************************************************************/
void Int_Init(void)
{
/* Connect the physical interrupt to our machine */
RMP_ASSERT(RVM_Hyp_Vct_Phys(30U,2U)==0U);
/* Set the priority of the physical interrupt and enable it */
RMP_ASSERT(RVM_A7M_Int_Local_Mod(KFN_INT_LOCAL_MOD,30U,
RVM_A7M_KFN_INT_LOCAL_MOD_STATE_SET,1U)==0);
RMP_ASSERT(RVM_A7M_Int_Local_Mod(KFN_INT_LOCAL_MOD,30U,
RVM_A7M_KFN_INT_LOCAL_MOD_PRIO_SET,0xFFU)==0);
/* Interrupt generation is initialized too, here we only register our handler */
RVM_Virt_Vct_Reg(2U,Int_Handler);
/* TIM4 clock = 1/2 CPU clock */
TIM4_CR1=TIM_COUNTERMODE_DOWN|TIM_CLOCKDIVISION_DIV1;
TIM4_ARR=16800U;
TIM4_PSC=0U;
RCC_APB1ENR|=RCC_APB1ENR_TIM4;
TIM4_SR&=~0x01U;
TIM4_DIER|=0x01U;
TIM4_CR1|=TIM_CR1_CEN;
}
/* End Function:Int_Init *****************************************************/
/* Function:Int_Disable *******************************************************
Description : Disable the periodic interrupt source. This function needs
to be adapted to your specific hardware.
Input : None.
Output : None.
Return : None.
******************************************************************************/
void Int_Disable(void)
{
/* Disable interrupt */
RMP_ASSERT(RVM_A7M_Int_Local_Mod(KFN_INT_LOCAL_MOD,30U,RVM_A7M_KFN_INT_LOCAL_MOD_STATE_SET,0U)==0);
/* Reverse registration */
RVM_Virt_Vct_Reg(2U,RMP_NULL);
}
#endif
/* End Function:Int_Disable **************************************************/
/* End Of File ***************************************************************/
/* Copyright (C) Evo-Devo Instrum. All rights reserved ***********************/