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Add 14 Artix-7 boards (openXC7 multi-part chipdb)
New FPGA entries (artix7, yosys-arch xc7): xc7a35tcsg324, xc7a35tfgg484, xc7a35tftg256, xc7a50tcsg324, xc7a50tfgg484, xc7a100tcsg324, xc7a100tfgg484, xc7a100tftg256, xc7a100tfgg676, xc7a200tfbg484 (speed 3) and xc7a200tfbg484-2 (same package, -2 speed grade for the ZXTRES++). New boards: alchitry-au, alchitry-au-plus, arty-a7-35t, arty-a7-100t, cmod-a7-35t, colorlight-i9plus, microphase-a7-lite, mimas-a7, nexys-a7-50t, nexys-a7-100t (same FPGA/pinout as Nexys 4 DDR), qmtech-xc7a100t-ft2232h, zxtres, zxtres-plus, zxtres-plus-plus. openFPGALoader board ids verified against v1.1.1 (the oss-cad-suite binary apio ships). Boards without integrated USB-JTAG follow the existing colorlight-5a-75x convention (external cable via -c). The ZXTRES family parts come from the official zxtres org Vivado project (xc7a35tfgg484-2 / xc7a100tfgg484-2 / xc7a200tfbv484-2, one shared pinout; fbv484 is the lidless, footprint-identical fbg484); their bare JTAG points use -c usb-blaster per the official manual. Requires the openxc7 package release >= 2026-07-10 (multi-part chipdb, one .bin per footprint above).
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‎definitions/boards.jsonc‎

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"pid": "6010",
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"product-regex": "^Digilent USB Device*"
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}
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},
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// https://alchitry.com/boards/au/
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"alchitry-au": {
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"description": "Alchitry Au (Xilinx, Artix7)",
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"fpga-id": "xc7a35tftg256",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "--board alchitry_au"
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},
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"usb": {
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"vid": "0403",
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"pid": "6010"
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}
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},
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// https://alchitry.com/boards/au/
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"alchitry-au-plus": {
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"description": "Alchitry Au+ (Xilinx, Artix7)",
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"fpga-id": "xc7a100tftg256",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "--board alchitry_au_plus"
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},
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"usb": {
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"vid": "0403",
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"pid": "6010"
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}
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},
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// https://digilent.com/reference/programmable-logic/arty-a7/start
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"arty-a7-35t": {
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"description": "Arty A7-35T (Xilinx, Artix7)",
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"fpga-id": "xc7a35tcsg324",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "--board arty_a7_35t"
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},
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"usb": {
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"vid": "0403",
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"pid": "6010"
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}
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},
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// https://digilent.com/reference/programmable-logic/arty-a7/start
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"arty-a7-100t": {
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"description": "Arty A7-100T (Xilinx, Artix7)",
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"fpga-id": "xc7a100tcsg324",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "--board arty_a7_100t"
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},
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"usb": {
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"vid": "0403",
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"pid": "6010"
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}
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},
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// https://digilent.com/reference/programmable-logic/cmod-a7/start
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"cmod-a7-35t": {
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"description": "Cmod A7-35T (Xilinx, Artix7)",
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"fpga-id": "xc7a35tcpg236",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "--board cmoda7_35t"
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},
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"usb": {
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"vid": "0403",
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"pid": "6010"
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}
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},
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// Artix-7 drop-in module for the Colorlight i5/i9 EVB (no onboard JTAG;
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// the EVB exposes a CMSIS-DAP USB debugger)
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// https://github.com/wuxx/Colorlight-FPGA-Projects
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"colorlight-i9plus": {
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"description": "Colorlight i9+ (Xilinx, Artix7)",
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"fpga-id": "xc7a50tfgg484",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "--board colorlight-i9+ -c cmsisdap"
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},
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"usb": {
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"vid": "0d28",
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"pid": "0204"
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}
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},
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// Onboard FT232H USB-JTAG; no openFPGALoader board id -> generic cable
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// https://github.com/microphase-tech/A7-Lite
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"microphase-a7-lite": {
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"description": "MicroPhase A7-Lite (Xilinx, Artix7)",
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"fpga-id": "xc7a200tfbg484",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "-c ft232 --fpga-part xc7a200tfbg484"
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},
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"usb": {
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"vid": "0403",
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"pid": "6014"
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}
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},
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// https://numato.com/product/mimas-a7-fpga-development-board/
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"mimas-a7": {
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"description": "Mimas A7 (Xilinx, Artix7)",
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"fpga-id": "xc7a50tfgg484",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "--board mimas_a7"
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},
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"usb": {
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"vid": "2a19",
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"pid": "1009"
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}
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},
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// https://digilent.com/reference/programmable-logic/nexys-a7/start
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"nexys-a7-50t": {
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"description": "Nexys A7-50T (Xilinx, Artix7)",
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"fpga-id": "xc7a50tcsg324",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "--board nexys_a7_50"
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},
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"usb": {
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"vid": "0403",
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"pid": "6010"
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}
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},
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// https://digilent.com/reference/programmable-logic/nexys-a7/start
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// Same fpga and pinout as the older Nexys 4 DDR
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"nexys-a7-100t": {
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"description": "Nexys A7-100T / Nexys 4 DDR (Xilinx, Artix7)",
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"fpga-id": "xc7a100tcsg324",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "--board nexys_a7_100"
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},
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"usb": {
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"vid": "0403",
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"pid": "6010"
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}
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},
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// QMTECH XC7A100T core board: no onboard JTAG -> external FT2232H cable
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// https://github.com/ChinaQMTECH
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"qmtech-xc7a100t-ft2232h": {
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"description": "QMTECH XC7A100T core board (Xilinx, Artix7)",
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"fpga-id": "xc7a100tfgg676",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "-c ft2232 --fpga-part xc7a100tfgg676"
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}
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},
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// ZX Spectrum clone family; bare JTAG points (TMS/TDI/TDO/TCK/GND), the
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// official manual documents openFPGALoader with an Altera USB-Blaster
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// (alternative: -c ft232). All three variants share the PCB/pinout.
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// https://zxtres.github.io/wiki/manual_en.html
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"zxtres": {
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"description": "ZXTRES (Xilinx, Artix7)",
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"fpga-id": "xc7a35tfgg484",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "-c usb-blaster"
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},
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"usb": {
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"vid": "09fb",
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"pid": "6001"
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}
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},
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// https://zxtres.github.io/wiki/manual_en.html
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"zxtres-plus": {
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"description": "ZXTRES+ (Xilinx, Artix7)",
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"fpga-id": "xc7a100tfgg484",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "-c usb-blaster"
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},
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"usb": {
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"vid": "09fb",
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"pid": "6001"
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}
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},
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// The ++ mounts the lidless FBV484 package (Vivado name); prjxray/openXC7
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// use the footprint-identical xc7a200tfbg484
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// https://zxtres.github.io/wiki/manual_en.html
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"zxtres-plus-plus": {
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"description": "ZXTRES++ (Xilinx, Artix7)",
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"fpga-id": "xc7a200tfbg484-2",
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"programmer": {
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"id": "openfpgaloader",
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"extra-args": "-c usb-blaster"
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},
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"usb": {
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"vid": "09fb",
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"pid": "6001"
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}
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}
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}

‎definitions/fpgas.jsonc‎

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"package": "xc7a35tcpg236",
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"speed": "1"
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}
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},
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"xc7a35tcsg324": {
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"part-num": "XC7A35TCSG324",
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"arch": "xilinx",
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"size": "35k",
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"xilinx-params": {
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"family": "artix7",
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"yosys-arch": "xc7",
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"package": "xc7a35tcsg324",
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"speed": "1"
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}
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},
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"xc7a35tfgg484": {
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"part-num": "XC7A35TFGG484",
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"arch": "xilinx",
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"size": "35k",
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"xilinx-params": {
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"family": "artix7",
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"yosys-arch": "xc7",
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"package": "xc7a35tfgg484",
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"speed": "2"
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}
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},
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"xc7a35tftg256": {
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"part-num": "XC7A35TFTG256",
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"arch": "xilinx",
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"size": "35k",
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"xilinx-params": {
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"family": "artix7",
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"yosys-arch": "xc7",
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"package": "xc7a35tftg256",
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"speed": "1"
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}
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},
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"xc7a50tcsg324": {
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"part-num": "XC7A50TCSG324",
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"arch": "xilinx",
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"size": "50k",
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"xilinx-params": {
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"family": "artix7",
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"yosys-arch": "xc7",
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"package": "xc7a50tcsg324",
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"speed": "1"
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}
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},
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"xc7a50tfgg484": {
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"part-num": "XC7A50TFGG484",
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"arch": "xilinx",
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"size": "50k",
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"xilinx-params": {
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"family": "artix7",
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"yosys-arch": "xc7",
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"package": "xc7a50tfgg484",
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"speed": "1"
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}
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},
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"xc7a100tcsg324": {
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"part-num": "XC7A100TCSG324",
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"arch": "xilinx",
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"size": "100k",
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"xilinx-params": {
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"family": "artix7",
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"yosys-arch": "xc7",
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"package": "xc7a100tcsg324",
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"speed": "1"
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}
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},
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"xc7a100tftg256": {
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"part-num": "XC7A100TFTG256",
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"arch": "xilinx",
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"size": "100k",
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"xilinx-params": {
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"family": "artix7",
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"yosys-arch": "xc7",
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"package": "xc7a100tftg256",
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"speed": "1"
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}
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},
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"xc7a100tfgg484": {
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"part-num": "XC7A100TFGG484",
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"arch": "xilinx",
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"size": "100k",
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"xilinx-params": {
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"family": "artix7",
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"yosys-arch": "xc7",
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"package": "xc7a100tfgg484",
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"speed": "2"
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}
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},
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"xc7a100tfgg676": {
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"part-num": "XC7A100TFGG676",
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"arch": "xilinx",
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"size": "100k",
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"xilinx-params": {
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"family": "artix7",
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"yosys-arch": "xc7",
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"package": "xc7a100tfgg676",
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"speed": "1"
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}
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},
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"xc7a200tfbg484": {
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"part-num": "XC7A200TFBG484",
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"arch": "xilinx",
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"size": "200k",
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"xilinx-params": {
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"family": "artix7",
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"yosys-arch": "xc7",
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"package": "xc7a200tfbg484",
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"speed": "3"
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}
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},
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// Same package as above, -2 speed grade (ZXTres++); the chipdb .bin is
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// shared, only fasm2frames/xc7frames2bit use the speed
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"xc7a200tfbg484-2": {
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"part-num": "XC7A200TFBG484",
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"arch": "xilinx",
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"size": "200k",
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"xilinx-params": {
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"family": "artix7",
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"yosys-arch": "xc7",
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"package": "xc7a200tfbg484",
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"speed": "2"
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}
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}
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}

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