SSBL STM32N657x #39
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SSBL STM32N657x #39
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Igor-Misic
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Igor-Misic
November 12, 2025 10:10
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Pull Request Overview
This pull request adds Second Stage Bootloader (SSBL) support for the STM32N657X0-Q (NUCLEO-N657X0-Q) microcontroller, which lacks internal flash and relies on external flash memory. The implementation enables execution from external flash at XSPI2 addresses starting from 0x70100400 in memory-mapped mode.
Key Changes:
- Added STM32 External Memory Manager middleware with drivers for NOR SFDP, PSRAM, SDCARD, and user-defined memory types
- Implemented boot mechanisms for execute-in-place (XIP) and load-and-run (LRUN) modes
- Created linker scripts for external flash execution with proper memory region definitions
- Added build targets and configurations for external flash support
- Fixed HAL driver issues in USB, RCC, FMC, UART, and utility modules
Reviewed Changes
Copilot reviewed 112 out of 113 changed files in this pull request and generated no comments.
Show a summary per file
| File | Description |
|---|---|
| Middlewares/ST/STM32_ExtMem_Manager/user/* | User-defined driver API, types, and weak implementations for custom memory support |
| Middlewares/ST/STM32_ExtMem_Manager/sdcard/* | SD card driver implementation with SAL integration |
| Middlewares/ST/STM32_ExtMem_Manager/psram/* | PSRAM driver for APS memory configuration |
| Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/* | NOR flash SFDP driver with JEDEC parameter parsing |
| Middlewares/ST/STM32_ExtMem_Manager/sal/* | Software Adaptation Layer for XSPI and SD peripherals |
| Middlewares/ST/STM32_ExtMem_Manager/boot/* | XIP and LRUN boot mechanism implementations |
| Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem.* | Core external memory manager API |
| Linker/STM32N6xx_EXT_FLASH*.ld | Linker scripts for external flash execution with CACHEAXI and AXISRAM regions |
| Makefile* | Build system updates for external flash targets |
| Drivers/STM32N6xx_HAL_Driver/Src/* | Bug fixes in USB LL, RCC LL, FMC LL, UART HAL, and utility functions |
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Support for Second Stage Bootloader (SSBL) for board NUCLEO-N657X0-Q with STM32N657X0 Microcontroller (MCU)
The STM32N6xx series of MCUs does not have internal flash memory, so it relies on external flash. It includes an integrated mechanism that copies up to 255 KB of the First Stage Bootloader (FSBL) from external flash to RAM, starting at address 0x34180400, which corresponds to the AXISRAM2 segment. This functionality is implemented in this PR #38.
To use the AXISRAM2 segment for firmware, we cannot run the FSBL from it, so the software must run from another location. The best solution is an SSBL that runs from external memory. The SSBL allows us to unlock the full potential of the MCU's RAM, providing a total of 4.2 MB of contiguous embedded memory.
This PR introduces a linker script that prepares the firmware to run at XSPI2 addresses starting from 0x70100400 in memory-mapped mode, as well as drivers for the external flash MX25UM51245G, which comes with the board.
The sequence is as follows: the FSBL is placed at address 0x70100400, and the SSBL is placed at 0x70200400.
The SSBL runs from external flash and uses the CACHEAXI address space, which allows the firmware to be programmed at the beginning of AXISRAM.
At the time of working on this, I was not able to utilize VENCRAM for the SSBL.