Fix FPGA build

Author: MichaelBell

cpu/buffer.v

@@ -11,7 +11,7 @@ module tinyqv_buffer (
     /* verilator lint_off ASSIGNDLY */
     buf #1 i_buf (X, A);
     /* verilator lint_on ASSIGNDLY */
-    `elsif ICE40
+    `elsif SYNTH_FPGA
     assign X = A;
     `elsif SCL_sky130_fd_sc_hd
     /* verilator lint_off PINMISSING */

pico_ice/Makefile

@@ -11,7 +11,7 @@ pico_ice:
 	#verilator --lint-only -Wall -Wno-DECLFILENAME -Wno-MULTITOP $(FILES)
 
 	# synthesize using Yosys
-	yosys -p "synth_ice40 -abc9 -device u -top tinyQV_top -json $(PROJ).json" -DICE40 $(FILES) > yosys.log
+	yosys -p "synth_ice40 -abc9 -device u -top tinyQV_top -json $(PROJ).json" -DICE40 -DSYNTH_FPGA $(FILES) > yosys.log
 	@grep Warn yosys.log || true
 	@grep Error yosys.log || true
 	@egrep "[0-9]+ submodules" yosys.log | head -1

pico_ice/pico_ice.v

@@ -3,7 +3,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-`define default_netname none
+`default_nettype none
 
 module tinyQV_top (
         input clk,