t.ant

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 10.1
--  \   \         Application : ISE
--  /   /         Filename : t.ant
-- /___/   /\     Timestamp : Wed Apr 03 16:20:14 2013
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: t
--Device: Xilinx
--

library UNISIM;
use UNISIM.Vcomponents.ALL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE STD.TEXTIO.ALL;

ENTITY t IS
END t;

ARCHITECTURE testbench_arch OF t IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "D:\Documents\Profissional\aulas\2012-2013\AC\Labs\L2\CicloUnico3\t.ano";

    COMPONENT Processador2012
        PORT (
            CLK : In std_logic
        );
    END COMPONENT;

    SIGNAL CLK : std_logic := '0';

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 200 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 100 ns;

    BEGIN
        UUT : Processador2012
        PORT MAP (
            CLK => CLK
        );

        PROCESS    -- clock process for CLK
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                CLK <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                CLK <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS
            BEGIN
                WAIT FOR 1200 ns;

                STD.TEXTIO.write(TX_OUT, string'("Total[]"));
                STD.TEXTIO.writeline(RESULTS, TX_OUT);
                ASSERT (FALSE) REPORT
                    "Success! Simulation for annotation completed"
                    SEVERITY FAILURE;
            END PROCESS;

    END testbench_arch;