datapath.ext

timestamp 1765751372
version 8.3
tech scmos
style TSMC0.18um(tsmc18)from:t24i
scale 1000 1 9
resistclasses 6900 7800 946000 946000 1 8000 8000 80 80 80 80 80 40
use staticizer staticizer_1 -1 0 39 0 1 1753
use latch latch_4 -1 0 -355 0 1 463
use latch latch_0 1 0 445 0 1 463
use inv2 inv2_0 -1 0 -22 0 1 1852
use 4nor2 4nor2_0 0 1 81 -1 0 1980
use staticizer staticizer_0 1 0 51 0 1 1753
use shift shift_0 1 0 330 0 1 2153
use latch latch_3 1 0 768 0 1 456
use fblock fblock_0 1 0 535 0 1 2993
use latch latch_1 1 0 975 0 1 456
use addsub addsub_0 1 0 675 0 1 712
use reg_one reg_one_0 1 0 991 0 1 1924
use staticizer_one staticizer_one_0 1 0 867 0 1 1967
use latch latch_2 1 0 1236 0 1 459
use reg reg_0 1 0 928 0 1 936
use reg reg_1 1 0 1035 0 1 936
use 2nor 2nor_0 -1 0 1042 0 1 1940
use latch_one latch_one_1 1 0 873 0 1 2033
use latch_one latch_one_0 1 0 873 0 1 1978
use reg reg_2 1 0 1142 0 1 936
use mux_8bit mux_8bit_0 1 0 1342 0 1 1766
use reg reg_3 1 0 1249 0 1 936
use inv2 inv2_6 0 -1 1417 -1 0 1926
use inv2 inv2_3 0 -1 1417 -1 0 1896
use inv2 inv2_8 0 -1 1417 -1 0 1986
use inv2 inv2_7 0 -1 1417 -1 0 1956
use addsub addsub_1 1 0 1550 0 1 712
use reg reg_4 1 0 1449 0 1 936
use latch latch_5 1 0 2111 0 1 459
use inv2 inv2_4 1 0 1776 0 -1 1880
use staticizer staticizer_2 1 0 1717 0 1 1756
use mux_8bit mux_8bit_1 1 0 1842 0 1 1766
use reg reg_5 1 0 1949 0 1 936
use inv2 inv2_12 0 -1 1917 -1 0 1926
use inv2 inv2_11 0 -1 1917 -1 0 1896
use inv2 inv2_10 0 -1 1917 -1 0 1956
use inv2 inv2_9 0 -1 1917 -1 0 1986
use reg reg_6 1 0 2056 0 1 936
use mux_8bit mux_8bit_2 1 0 2142 0 1 1766
use reg reg_7 1 0 2249 0 1 936
use inv2 inv2_16 0 -1 2217 -1 0 1926
use inv2 inv2_15 0 -1 2217 -1 0 1896
use inv2 inv2_14 0 -1 2217 -1 0 1986
use inv2 inv2_13 0 -1 2217 -1 0 1956
use addsub addsub_2 1 0 2350 0 1 712
use latch latch_6 1 0 2911 0 1 459
use staticizer staticizer_3 1 0 2517 0 1 1756
use latch latch_7 1 0 3035 0 1 459
use inv2 inv2_5 1 0 2576 0 -1 1880
use inv2 inv2_1 1 0 2700 0 -1 1880
use staticizer staticizer_5 1 0 2765 0 1 1756
use staticizer staticizer_4 1 0 2641 0 1 1756
use latch latch_8 1 0 3159 0 1 459
use inv2 inv2_2 1 0 2824 0 -1 1880
node "ABH_w" 0 5.948 2319 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0
node "ABH_r1" 0 5.948 2246 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0
node "ABL_w" 0 5.948 2126 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0
node "ABL_r1" 0 5.948 2053 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0
node "PCH_w" 0 5.076 2019 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0
node "PCH_r1" 0 5.076 1946 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0
node "PCL_w" 0 5.076 1519 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0
node "PCL_r1" 0 5.076 1446 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0
node "Y_w" 0 5.948 1319 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0
node "Y_r1" 0 5.948 1246 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0
node "X_w" 0 5.948 1212 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0
node "X_r1" 0 5.948 1139 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0
node "DB_w" 0 5.948 1105 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0
node "DB_r1" 0 5.948 1032 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0
node "A_w" 0 5.948 998 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0
node "A_r1" 0 5.948 925 1876 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0
node "Cflag_w" 0 6.82 1059 2000 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0
node "os_s" 0 6.82 346 1885 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0
node "os_u" 0 6.82 284 1885 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0
node "fb_g0" 0 25.132 555 1922 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 130 62 0 0 0 0 0 0
node "fb_g1" 0 25.132 522 1922 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 130 62 0 0 0 0 0 0
node "fb_g2" 0 25.132 488 1922 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 130 62 0 0 0 0 0 0
node "fb_g3" 0 25.132 456 1922 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 130 62 0 0 0 0 0 0
node "PCLplus1_7" 0 9.866 1704 569 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCL7" 0 9.866 1492 612 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCLplus1_6" 0 9.866 1704 745 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCL6" 0 9.866 1492 788 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCLplus1_5" 0 9.866 1704 921 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCL5" 0 9.866 1492 964 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCLplus1_4" 0 9.866 1704 1097 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCL4" 0 9.866 1492 1140 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCLplus1_3" 0 9.866 1704 1273 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCL3" 0 9.866 1492 1316 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCLplus1_2" 0 9.866 1704 1449 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCL2" 0 9.866 1492 1492 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCLplus1_1" 0 9.866 1704 1625 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCL1" 0 9.866 1492 1668 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCLplus1_0" 0 9.866 1704 1801 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCL0" 0 9.866 1492 1844 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "ABH_r0" 0 9.866 2235 1876 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "ABL_r0" 0 9.866 2042 1876 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "PCH_r0" 0 8.417 1935 1876 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0 0 0
node "PCL_r0" 0 8.417 1435 1876 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0 0 0
node "Y_r0" 0 9.866 1235 1876 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "X_r0" 0 9.866 1128 1876 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "DB_r0" 0 9.866 1021 1876 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "A_r0" 0 9.866 914 1876 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 18 0 0 0 0 0 0 0 0
node "Cflag" 0 11.315 1058 1902 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0 0 0
node "m2_980_1900#" 0 10.094 980 1900 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0 0 0
node "m1_2132_555#" 0 24.562 2132 555 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0 0 0 0 0
node "wz_addrH7" 15 930.583 1849 559 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 60 150 90 75 60 3985 1604 0 0 0 0
node "m1_2209_542#" 2 447.334 2209 542 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "m1_1909_542#" 2 447.334 1909 542 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "wz_addrL7" 10 571.937 1343 559 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 40 75 50 235 114 2435 984 0 0 0 0
node "PCL_w_muxout7" 2 447.334 1409 542 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "data_out7" 0 33.19 -80 593 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0 0 0 0 0
node "wz7" 45 2755.22 160 593 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 425 290 575 350 675 380 10115 4066 0 0 0 0
node "m1_2132_731#" 0 24.562 2132 731 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0 0 0 0 0
node "wz_addrH6" 15 935.619 1849 735 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 60 150 90 75 60 3985 1604 0 0 0 0
node "m1_2209_718#" 2 447.334 2209 718 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "m1_1909_718#" 2 447.334 1909 718 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "wz_addrL6" 10 571.937 1343 735 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 40 75 50 235 114 2435 984 0 0 0 0
node "PCL_w_muxout6" 2 447.334 1409 718 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "data_out6" 0 33.19 -80 769 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0 0 0 0 0
node "wz6" 45 2755.22 160 769 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 425 290 575 350 675 380 10115 4066 0 0 0 0
node "m1_2132_907#" 0 24.562 2132 907 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0 0 0 0 0
node "wz_addrH5" 15 935.619 1849 911 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 60 150 90 75 60 3985 1604 0 0 0 0
node "m1_2209_894#" 2 447.334 2209 894 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "m1_1909_894#" 2 447.334 1909 894 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "wz_addrL5" 10 571.937 1343 911 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 40 75 50 235 114 2435 984 0 0 0 0
node "PCL_w_muxout5" 2 447.334 1409 894 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "data_out5" 0 33.19 -80 945 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0 0 0 0 0
node "wz5" 45 2755.22 160 945 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 425 290 575 350 675 380 10115 4066 0 0 0 0
node "m1_2132_1083#" 0 24.562 2132 1083 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0 0 0 0 0
node "wz_addrH4" 15 935.619 1849 1087 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 60 150 90 75 60 3985 1604 0 0 0 0
node "m1_2209_1070#" 2 447.334 2209 1070 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "m1_1909_1070#" 2 447.334 1909 1070 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "wz_addrL4" 10 571.937 1343 1087 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 40 75 50 235 114 2435 984 0 0 0 0
node "PCL_w_muxout4" 2 447.334 1409 1070 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "data_out4" 0 33.19 -80 1121 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0 0 0 0 0
node "wz4" 45 2755.22 160 1121 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 425 290 575 350 675 380 10115 4066 0 0 0 0
node "m1_2132_1259#" 0 24.562 2132 1259 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0 0 0 0 0
node "wz_addrH3" 15 935.619 1849 1263 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 60 150 90 75 60 3985 1604 0 0 0 0
node "m1_2209_1246#" 2 447.334 2209 1246 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "m1_1909_1246#" 2 447.334 1909 1246 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "wz_addrL3" 10 571.937 1343 1263 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 40 75 50 235 114 2435 984 0 0 0 0
node "PCL_w_muxout3" 2 447.334 1409 1246 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "data_out3" 0 33.19 -80 1297 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0 0 0 0 0
node "wz3" 45 2755.22 160 1297 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 425 290 575 350 675 380 10115 4066 0 0 0 0
node "m1_2132_1435#" 0 24.562 2132 1435 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0 0 0 0 0
node "wz_addrH2" 15 935.619 1849 1439 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 60 150 90 75 60 3985 1604 0 0 0 0
node "m1_2209_1422#" 2 447.334 2209 1422 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "m1_1909_1422#" 2 447.334 1909 1422 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "wz_addrL2" 10 571.937 1343 1439 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 40 75 50 235 114 2435 984 0 0 0 0
node "PCL_w_muxout2" 2 447.334 1409 1422 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "data_out2" 0 33.19 -80 1473 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0 0 0 0 0
node "wz2" 45 2755.22 160 1473 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 425 290 575 350 675 380 10115 4066 0 0 0 0
node "m1_2132_1611#" 0 24.562 2132 1611 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0 0 0 0 0
node "wz_addrH1" 15 935.619 1849 1615 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 60 150 90 75 60 3985 1604 0 0 0 0
node "m1_2209_1598#" 2 447.334 2209 1598 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "m1_1909_1598#" 2 447.334 1909 1598 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "wz_addrL1" 10 571.937 1343 1615 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 40 75 50 235 114 2435 984 0 0 0 0
node "PCL_w_muxout1" 2 447.334 1409 1598 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "data_out1" 0 33.19 -80 1649 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0 0 0 0 0
node "wz1" 45 2755.22 160 1649 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 425 290 575 350 675 380 10115 4066 0 0 0 0
node "Vdd!" 29 6220.62 739 1711 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 315 156 630 186 3255 1612 62286 5974 0 0 0 0
node "GND!" 29 6073.51 833 1741 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 390 158 590 178 3115 1556 59204 5990 0 0 0 0
node "m1_2132_1787#" 0 24.562 2132 1787 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 0 0 0 0 0 0 0 0 0 0
node "wz_addrH0" 15 935.619 1849 1791 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75 60 150 90 75 60 3985 1604 0 0 0 0
node "m1_2336_1834#" 0 72.016 2336 1834 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70 38 0 0 0 0 0 0 0 0 0 0
node "m1_2828_1843#" 0 54.97 2828 1843 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 75 40 0 0 0 0 0 0
node "m1_2704_1843#" 0 54.97 2704 1843 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 75 40 0 0 0 0 0 0
node "m1_2580_1843#" 0 54.97 2580 1843 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 75 40 0 0 0 0 0 0
node "m1_2209_1774#" 2 447.334 2209 1774 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "m1_1909_1774#" 2 447.334 1909 1774 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "wz_addrL0" 10 571.937 1343 1791 v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 40 75 50 235 114 2435 984 0 0 0 0
node "m1_1536_1834#" 0 54.76 1536 1834 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 30 0 0 0 0 0 0 0 0 0 0
node "m1_1780_1843#" 0 54.97 1780 1843 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 75 40 0 0 0 0 0 0
node "PCL_w_muxout0" 2 447.334 1409 1774 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 505 212 0 0 0 0 0 0 0 0 0 0
node "as_sub" 0 33.19 661 1829 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0 0 0 0 0
node "data_out0" 0 33.19 -80 1825 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 0 0 0 0 0 0 0 0 0 0
node "m1_150_1845#" 1 84.618 150 1845 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 270 118 0 0 0 0 0 0
node "wz0" 45 2740.04 160 1825 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 425 290 575 350 675 380 10115 4066 0 0 0 0
node "m1_136_1836#" 1 133.625 136 1836 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 125 60 25 20 50 30 0 0 0 0 0 0
node "m1_65_1845#" 1 90.853 65 1845 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 73 38 25 20 70 38 0 0 0 0 0 0
node "m1_n42_1842#" 0 55.842 -42 1842 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 80 42 0 0 0 0 0 0
node "rd_dataout" 1 71.538 -20 1860 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 170 78 0 0 0 0 0 0
node "m1_n56_1860#" 1 145.925 -56 1860 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 115 56 25 20 170 78 0 0 0 0 0 0
node "m1_2844_1867#" 1 119.215 2844 1867 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 42 25 20 190 86 0 0 0 0 0 0
node "rd_addrH" 1 81.13 2819 1867 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 225 100 0 0 0 0 0 0
node "m1_2720_1867#" 1 119.215 2720 1867 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 42 25 20 190 86 0 0 0 0 0 0
node "rd_addrL" 1 81.13 2695 1867 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 225 100 0 0 0 0 0 0
node "m1_2596_1867#" 1 119.215 2596 1867 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 42 25 20 190 86 0 0 0 0 0 0
node "rPCplus1H" 1 81.13 2571 1867 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 225 100 0 0 0 0 0 0
node "m1_2222_1870#" 0 50.446 2222 1870 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45 28 0 0 0 0 0 0 0 0 0 0
node "m1_2180_1876#" 0 42.216 2180 1876 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 24 0 0 0 0 0 0 0 0 0 0
node "m1_1922_1870#" 0 50.446 1922 1870 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45 28 0 0 0 0 0 0 0 0 0 0
node "m1_1796_1867#" 1 119.215 1796 1867 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 42 25 20 190 86 0 0 0 0 0 0
node "rPCplus1L" 1 81.13 1771 1867 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 225 100 0 0 0 0 0 0
node "m1_1880_1876#" 0 42.216 1880 1876 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 24 0 0 0 0 0 0 0 0 0 0
node "m1_1422_1870#" 0 50.446 1422 1870 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45 28 0 0 0 0 0 0 0 0 0 0
node "m1_1380_1876#" 0 42.216 1380 1876 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 24 0 0 0 0 0 0 0 0 0 0
node "m1_2841_1885#" 1 88.732 2841 1885 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 280 122 0 0 0 0 0 0
node "m1_2717_1885#" 1 88.732 2717 1885 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 280 122 0 0 0 0 0 0
node "m1_2593_1885#" 1 88.732 2593 1885 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 280 122 0 0 0 0 0 0
node "m1_1793_1885#" 1 88.732 1793 1885 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 280 122 0 0 0 0 0 0
node "m1_n30_1884#" 1 92.466 -30 1884 m123c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 20 25 20 290 126 0 0 0 0 0 0
node "m1_2222_1899#" 1 313.6 2222 1899 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 350 150 0 0 0 0 0 0 0 0 0 0
node "m1_2180_1902#" 1 313.6 2180 1902 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 350 150 0 0 0 0 0 0 0 0 0 0
node "m1_1922_1899#" 1 313.6 1922 1899 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 350 150 0 0 0 0 0 0 0 0 0 0
node "m1_1880_1902#" 1 313.6 1880 1902 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 350 150 0 0 0 0 0 0 0 0 0 0
node "m1_1422_1899#" 1 313.6 1422 1899 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 350 150 0 0 0 0 0 0 0 0 0 0
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cap "ry5" "as_cout" 58.7
cap "m1_952_1914#" "ras" 286.712
cap "m1_2209_542#" "rx_addrH7" 11.825
cap "ry4" "m1_1909_1070#" 39.006
cap "m1_2209_1422#" "wz_addrH2" 11.825
cap "wz2" "rx_PCL2" 58.7
cap "rx_addrH2" "wz_addrH2" 615.863
cap "wz_addrH1" "a_2516_1625#" 19.61
cap "wz0" "a_373_1796#" 18.273
cap "rx1" "wz1" 408.534
cap "PCL_w_muxout6" "ry6" 39.006
cap "rfb" "a_860_1991#" 9.35
cap "rx1" "a_373_1620#" 11.66
cap "a_373_564#" "rx7" 11.66
cap "a_373_1444#" "wz2" 18.273
cap "rx3" "as_cout" 58.7
cap "wz_addrL4" "PCL_w_muxout4" 11.825
cap "rx_PCL7" "wz_addrL7" 196.459
cap "m1_865_1958#" "m1_877_1966#" 1162.34
cap "wz_addrH6" "m1_1909_718#" 11.825
cap "ry5" "m1_1909_894#" 39.006
cap "m1_2209_542#" "wz_addrH7" 11.825
cap "m1_1909_1598#" "ry1" 39.006
cap "rx_addrH1" "m1_2209_1598#" 11.825
cap "wz_addrH4" "rx_addrH4" 615.863
cap "m1_1780_1843#" "m1_1793_1885#" 107.3
cap "wz_addrH6" "ry6" 165.38
cap "wzCflag" "rfb" 7.422
cap "PCLplus1_7" "a_1716_569#" 84.9167
cap "wz_addrH1" "m1_2209_1598#" 11.825
cap "wz_addrH1" "rx_addrH1" 615.863
cap "rx6" "ry6" 74.772
cap "rx_addrH7" "wz_addrH7" 615.863
cap "wz_addrH6" "rx_addrH6" 615.863
cap "a_2516_1449#" "wz_addrH2" 19.61
cap "wz0" "ras" 228.012
cap "ry6" "ry_addrH6" 22198.4
cap "wz_addrH3" "a_2516_1273#" 19.61
cap "wzCflag" "ras" 6.794
cap "wz0" "m1_1796_1867#" 58.7
cap "wz_addrL4" "a_2510_1893#" 58.7
cap "os_s" "rfb" 37.79
cap "wz3" "a_373_1268#" 18.273
cap "ry_addrH0" "GND!" 26650.6
cap "m1_865_1958#" "m1_952_1914#" 36.385
cap "rx2" "data_in2" 153.19
cap "ry_addrH0" "ry0" 22198.4
cap "rfb" "ros" 5728.25
cap "rx7" "data_in7" 153.19
cap "wz0" "m1_1793_1885#" 58.7
cap "GND!" "a_2510_1893#" 156.28
cap "ry6" "m1_1909_718#" 39.006
cap "wz_addrH0" "a_2575_1804#" 13.073
cap "ry0" "a_2510_1893#" 58.7
cap "wz6" "a_2510_1893#" 58.7
cap "m1_150_1845#" "ld_datain" 96.57
cap "m1_2844_1867#" "m1_2841_1885#" 7.2
cap "wz_addrL4" "rx_PCL4" 196.459
cap "wz_addrL3" "rx_PCL3" 196.459
cap "wz_addrH7" "a_2516_569#" 18.875
cap "wz_addrL2" "rx_PCL2" 196.459
cap "ry5" "wz5" 58.7
cap "rx1" "data_in1" 153.19
cap "wz4" "a_2510_1893#" 58.7
cap "m1_2132_555#" "rx_addrH7" 6.105
cap "wz1" "a_2510_1893#" 58.7
cap "GND!" "as_cout" 170.22
cap "ry5" "rx5" 74.772
cap "wz_addrL6" "a_2510_1893#" 58.7
cap "wz6" "as_cout" 58.7
cap "ry0" "as_cout" 58.7
cap "m1_n30_1884#" "m1_n42_1842#" 122.629
cap "a_2516_745#" "wz_addrH6" 19.61
cap "wz_addrL0" "rx0" 209.742
cap "wz0" "rx0" 408.534
cap "rx3" "a_373_1268#" 11.66
cap "wz_addrH0" "a_2516_1801#" 19.61
cap "wz_addrL0" "a_1776_1804#" 4.95
cap "m1_865_1958#" "a_860_1991#" 23.91
cap "wz4" "rx_PCL4" 58.7
cap "PCL_w_muxout1" "ry1" 39.006
cap "PCL_w_muxout3" "ry3" 39.006
cap "ry0" "PCL_w_muxout0" 39.006
cap "wz_addrH6" "a_2575_748#" 13.073
cap "wz4" "as_cout" 58.7
cap "wz_addrH0" "a_2351_1801#" 9.995
cap "PCL_w_muxout7" "wz_addrL7" 11.825
cap "m1_2209_1246#" "rx_addrH3" 11.825
cap "wz1" "as_cout" 58.7
cap "wz3" "ry3" 58.7
cap "a_2351_569#" "wz_addrH7" 13.715
cap "rx_addrH2" "m1_2209_1422#" 11.825
cap "m1_2209_1774#" "rx_addrH0" 11.825
cap "rx6" "data_in6" 153.19
cap "rx7" "as_cout" 58.7
cap "m1_865_1958#" "wzCflag" 6.992
cap "a_1776_1452#" "wz_addrL2" 4.95
cap "wz_addrL1" "a_1776_1628#" 4.95
cap "ry2" "ry_addrH2" 22198.4
cap "wz_addrL5" "a_1776_924#" 4.95
cap "wz_addrH4" "ry4" 165.38
cap "wz_addrH4" "a_2575_1100#" 13.073
cap "PCL_w_muxout1" "wz_addrL1" 11.825
cap "ry7" "m1_2209_542#" 39.006
cap "wz_addrL3" "a_1776_1276#" 4.95
cap "a_2516_921#" "wz_addrH5" 19.61
cap "ry2" "a_2510_1893#" 58.7
cap "rx2" "as_cout" 58.7
cap "rd_dataout" "m1_n30_1884#" 364.82
cap "PCL_w_muxout5" "ry5" 39.006
cap "wz1" "a_373_1620#" 18.273
cap "wz_addrH3" "ry3" 165.38
cap "m1_2132_1611#" "rx_addrH1" 6.105
cap "a_373_564#" "wz7" 18.273
cap "wz_addrL5" "a_2510_1893#" 58.7
cap "ry2" "PCL_w_muxout2" 39.006
cap "a_2351_1273#" "wz_addrH3" 9.995
cap "rx3" "ry3" 74.772
cap "wz_addrL6" "a_1776_748#" 4.95
cap "wz5" "a_2510_1893#" 58.7
cap "wz_addrL3" "PCL_w_muxout3" 11.825
cap "ry2" "as_cout" 58.7
cap "wz0" "rx_PCL0" 58.7
cap "wz_addrL0" "rx_PCL0" 196.459
cap "ry7" "a_2510_1893#" 61.338
cap "wz_addrH1" "m1_1909_1598#" 11.825
cap "m1_1780_1843#" "rPCplus1L" 163.632
cap "ry4" "rx4" 74.772
cap "m2_980_1900#" "m1_985_1902#" 7.608
cap "m1_2209_894#" "wz_addrH5" 11.825
cap "wz_addrH0" "rx_addrH0" 615.863
cap "m1_2209_1774#" "ry0" 39.006
cap "wz5" "as_cout" 58.7
cap "ry0" "rfb" 58.7
cap "m1_2209_1246#" "wz_addrH3" 11.825
cap "rx_PCL1" "wz_addrL1" 196.459
cap "ry_addrH1" "ry1" 22198.4
cap "m1_2209_718#" "wz_addrH6" 11.825
cap "wz2" "a_2510_1893#" 58.7
cap "Vdd!" "a_2510_1893#" 170.22
cap "rx5" "as_cout" 58.7
cap "ry7" "wz_addrH7" 165.38
cap "m1_2209_1070#" "rx_addrH4" 11.825
cap "ry7" "as_cout" 63.976
cap "ras" "as_cout" 58.7
cap "ry3" "a_2510_1893#" 58.7
cap "wz_addrH3" "m1_1909_1246#" 11.825
cap "wz0" "rPCplus1L" 58.7
cap "m2_980_1900#" "m1_952_1914#" 42.4583
cap "wz6" "rx_PCL6" 58.7
cap "wz3" "rx_PCL3" 58.7
cap "m1_940_1901#" "ras" 58.7
cap "m1_2580_1843#" "m1_2593_1885#" 107.3
cap "wz6" "a_373_740#" 18.273
cap "wz2" "as_cout" 58.7
cap "wz_addrH4" "a_2351_1097#" 9.995
cap "rx3" "wz_addrL3" 209.742
cap "Vdd!" "as_cout" 170.22
cap "ry2" "rx2" 74.772
cap "ry3" "as_cout" 58.7
cap "a_373_1092#" "rx4" 11.66
cap "wz_addrL6" "rx_PCL6" 196.459
cap "m1_2209_718#" "ry6" 39.006
cap "ry0" "m1_1909_1774#" 39.006
cap "ry4" "ry_addrH4" 22198.4
cap "m1_2209_718#" "rx_addrH6" 11.825
cap "ry7" "rx7" 74.772
cap "wz7" "a_2510_1893#" 58.7
cap "ry5" "wz_addrH5" 165.38
cap "as_cout" "rx0" 58.7
cap "wz_addrH0" "ry0" 165.38
cap "m1_865_1958#" "m1_979_1961#" 17.421
cap "ry0" "rx0" 74.772
cap "ry5" "m1_2209_894#" 39.006
cap "wz_addrL5" "rx_PCL5" 196.459
cap "data_in0" "rx0" 153.19
cap "wz5" "a_373_916#" 18.273
cap "wz7" "as_cout" 58.7
cap "wz_addrL3" "a_2510_1893#" 58.7
cap "wz5" "rx_PCL5" 58.7
cap "rx1" "ry1" 74.772
cap "ry7" "ry_addrH7" 22198.4
cap "wz_addrL6" "PCL_w_muxout6" 11.825
cap "wz_addrL2" "a_2510_1893#" 58.7
cap "a_373_916#" "rx5" 11.66
cap "rx6" "as_cout" 58.7
cap "wz_addrH2" "a_2351_1449#" 9.995
cap "wz2" "rx2" 408.534
cap "a_2351_921#" "wz_addrH5" 9.995
cap "rx6" "wz6" 408.534
cap "m1_2828_1843#" "rd_addrH" 163.632
cap "m1_2717_1885#" "m1_2704_1843#" 107.3
cap "PCL_w_muxout2" "wz_addrL2" 11.825
cap "ry6" "a_2510_1893#" 58.7
cap "ry4" "PCL_w_muxout4" 39.006
cap "ras" "as_cin" 15.466
cap "m1_2828_1843#" "m1_2841_1885#" 107.3
cap "m1_2132_907#" "rx_addrH5" 6.105
cap "m1_2209_1070#" "wz_addrH4" 11.825
cap "m1_2132_1435#" "rx_addrH2" 6.105
cap "m1_865_1958#" "m1_940_1901#" 36.385
cap "wz_addrL5" "rx5" 209.742
cap "ry2" "wz_addrH2" 165.38
cap "m1_1909_542#" "wz_addrH7" 11.825
cap "ras" "rfb" 11738.6
cap "wz_addrL6" "rx6" 209.742
cap "wz5" "rx5" 408.534
cap "m1_2209_1070#" "ry4" 39.006
cap "ry2" "wz2" 58.7
cap "wz7" "rx7" 408.534
cap "rx1" "wz_addrL1" 209.742
cap "ry6" "as_cout" 58.7
cap "wz_addrH3" "rx_addrH3" 615.863
cap "wz6" "ry6" 58.7
cap "wz_addrH1" "a_2575_1628#" 13.073
cap "ry4" "a_2510_1893#" 58.7
cap "a_373_1796#" "rx0" 11.66
cap "a_1710_1893#" "a_2510_1893#" 26.298
cap "m1_150_1845#" "m1_136_1836#" 78.7625
cap "m1_952_1914#" "m1_940_1901#" 574.821
cap "rx_addrH6" "m1_2132_731#" 6.105
cap "a_2575_1452#" "wz_addrH2" 13.073
cap "wz_addrL4" "a_1776_1100#" 4.95
cap "m1_1796_1867#" "m1_1793_1885#" 7.2
cap "m1_2209_1774#" "wz_addrH0" 11.825
cap "ry4" "as_cout" 58.7
cap "m1_2209_1598#" "ry1" 39.006
cap "rd_addrL" "m1_2704_1843#" 163.632
cap "wz_addrH4" "a_2516_1097#" 19.61
cap "a_2575_924#" "wz_addrH5" 13.073
cap "ry1" "a_2510_1893#" 58.7
cap "wz1" "rx_PCL1" 58.7
cap "ry3" "ry_addrH3" 22198.4
cap "wz_addrL2" "rx2" 209.742
cap "wz_addrL5" "PCL_w_muxout5" 11.825
cap "wz_addrL7" "a_2510_1893#" 58.7
cap "wz_addrH1" "ry1" 165.38
cap "rx3" "wz3" 408.534
cap "rx_PCL7" "wz7" 58.7
cap "wz_addrL0" "a_2510_1893#" 58.7
cap "wz0" "a_2510_1893#" 58.7
cap "ry4" "wz4" 58.7
cap "wz_addrL4" "rx4" 209.742
cap "m1_2132_1259#" "rx_addrH3" 6.105
cap "ry2" "m1_1909_1422#" 39.006
cap "m1_2596_1867#" "m1_2593_1885#" 7.2
cap "m1_2132_1787#" "rx_addrH0" 6.105
cap "wz_addrH6" "a_2351_745#" 9.995
cap "rx3" "data_in3" 153.19
cap "m1_865_1958#" "rfb" 178.92
cap "ry1" "as_cout" 58.7
cap "rx4" "as_cout" 58.7
cap "ry7" "wz7" 58.7
cap "os_u" "rfb" 37.79
cap "a_1776_572#" "wz_addrL7" 4.95
cap "wz_addrL1" "a_2510_1893#" 58.7
cap "ry7" "PCL_w_muxout7" 39.006
cap "wz_addrH0" "m1_1909_1774#" 11.825
cap "wz_addrH1" "a_2351_1625#" 9.995
cap "wz0" "as_cout" 58.7
cap "m1_865_1958#" "ras" 212.547
cap "data_in5" "rx5" 153.19
cap "wz0" "ry0" 58.7
cap "a_373_1444#" "rx2" 11.66
cap "wz4" "rx4" 408.534
cap "rx6" "a_373_740#" 11.66
cap "rx_addrH5" "wz_addrH5" 615.863
cap "a_2575_572#" "wz_addrH7" 13.073
cap "wz_addrL0" "PCL_w_muxout0" 11.825
cap "m1_877_1966#" "ras" 58.7
cap "m1_2580_1843#" "rPCplus1H" 163.632
cap "wz1" "ry1" 58.7
cap "m1_1909_894#" "wz_addrH5" 11.825
cap "wz3" "a_2510_1893#" 58.7
cap "rx_addrH5" "m1_2209_894#" 11.825
cap "m1_2132_1083#" "rx_addrH4" 6.105
cap "m1_2209_1246#" "ry3" 39.006
cap "m1_1909_1422#" "wz_addrH2" 11.825
cap "ry5" "a_2510_1893#" 58.7
cap "ry2" "m1_2209_1422#" 39.006
cap "ry_addrH5" "ry5" 22198.4
cap "ry7" "m1_1909_542#" 39.006
cap "m1_2720_1867#" "m1_2717_1885#" 7.2
cap "data_in4" "rx4" 153.19
cap "a_373_1092#" "wz4" 18.273
cap "rx7" "wz_addrL7" 209.742
cap "a_2575_1276#" "wz_addrH3" 13.073
cap "ry3" "m1_1909_1246#" 39.006
cap "wz3" "as_cout" 58.7
cap "wz_addrH4" "m1_1909_1070#" 11.825
cap "latch_4/latch_one_7/c" "staticizer_1/in7" 0.492
cap "staticizer_1/w_90_n1211#" "staticizer_1/in7" 18.828
cap "staticizer_1/w_90_n1211#" "latch_4/latch_one_7/c" 18.4696
cap "staticizer_1/staticizer_one_7/Vdd!" "staticizer_1/staticizer_one_7/a_60_n45#" -2.27374e-13
cap "latch_4/latch_one_7/a_12_n54#" "staticizer_1/staticizer_one_7/Vdd!" -7.10543e-15
cap "staticizer_1/in7" "staticizer_1/staticizer_one_7/Vdd!" 73.946
cap "latch_4/latch_one_7/c" "staticizer_1/staticizer_one_7/Vdd!" 922.78
cap "staticizer_1/in7" "staticizer_1/staticizer_one_7/c" 1.42109e-14
cap "staticizer_1/w_90_n1211#" "staticizer_1/staticizer_one_7/Vdd!" 1.13687e-13
cap "staticizer_1/in7" "staticizer_1/staticizer_one_7/a_60_n45#" 57.7175
subcap "a_109_568#" -134.574
subcap "data_in7" -6.948
subcap "rx7" -1753.63
cap "latch_0/latch_one_7/a_12_n54#" "latch_0/latch_one_7/Vdd!" -1.13687e-13
cap "latch_4/in7" "latch_4/latch_one_7/Vdd!" 348.725
cap "latch_0/latch_one_7/c" "latch_0/latch_one_7/GND!" 18.4696
cap "latch_0/latch_one_7/GND!" "latch_0/latch_one_7/Vdd!" -0.246
cap "latch_0/in7" "latch_0/latch_one_7/a_n5_n54#" 32.9814
cap "staticizer_0/staticizer_one_7/a_60_n45#" "latch_0/latch_one_7/Vdd!" -4.648
cap "latch_0/latch_one_7/c" "latch_0/latch_one_7/Vdd!" 922.78
cap "latch_0/latch_one_7/GND!" "latch_0/out7" 18.828
cap "latch_0/latch_one_7/GND!" "latch_4/in7" 1.293
cap "latch_4/in7" "latch_4/latch_one_7/a_n5_n54#" 69.3743
cap "latch_0/latch_one_7/GND!" "latch_0/latch_one_7/a_n5_n54#" 5.68434e-14
cap "latch_0/in7" "latch_0/latch_one_7/Vdd!" 67.0625
cap "staticizer_0/staticizer_one_7/a_60_n45#" "latch_0/out7" 57.7175
cap "latch_0/latch_one_7/c" "latch_0/out7" 0.492
cap "latch_4/in7" "latch_0/latch_one_7/Vdd!" 27.88
cap "latch_0/latch_one_7/Vdd!" "latch_0/out7" 73.946
cap "latch_0/latch_one_7/a_n5_n54#" "latch_0/latch_one_7/Vdd!" 1.13687e-13
subcap "wz7" -2636.74
cap "staticizer_0/w_90_n1211#" "latch_0/out7" 6.22
cap "staticizer_0/staticizer_one_7/a_77_n45#" "staticizer_0/staticizer_one_7/Vdd!" 1.13687e-13
cap "shift_0/shift_one_7/Vdd!" "latch_0/out7" 19.78
cap "staticizer_0/staticizer_one_7/a_60_n45#" "staticizer_0/staticizer_one_7/Vdd!" -2.744
cap "shift_0/a7" "staticizer_0/staticizer_one_7/Vdd!" -14.495
cap "staticizer_0/staticizer_one_7/a_60_n45#" "latch_0/out7" 31.249
cap "latch_0/out7" "staticizer_0/staticizer_one_7/Vdd!" 35.6
cap "staticizer_0/w_90_n1211#" "staticizer_0/staticizer_one_7/Vdd!" -0.984
cap "shift_0/a7" "latch_0/out7" 58.7
cap "staticizer_0/staticizer_one_7/c" "shift_0/a7" 65.01
cap "staticizer_0/w_90_n1211#" "shift_0/a7" 61.5
cap "wz7" "shift_0/shift_one_7/m1_n60_n65#" 11.825
cap "shift_0/shift_one_7/inv_2/GND!" "rx7" 11.43
cap "rx7" "shift_0/shift_one_7/inv_2/in" 22.99
cap "shift_0/shift_one_7/Vdd!" "rx7" 9.144
cap "wz7" "shift_0/shift_one_7/inv_2/out" 29.152
cap "wz7" "shift_0/shift_one_7/inv_2/GND!" 22.28
cap "wz7" "shift_0/shift_one_7/Vdd!" 116.788
cap "latch_3/latch_one_7/GND!" "rx7" 95.958
cap "latch_3/latch_one_7/a_12_n54#" "wz7" 4.95
cap "latch_3/latch_one_7/a_n5_n54#" "latch_3/latch_one_7/Vdd!" -1.13687e-13
cap "latch_3/latch_one_7/Vdd!" "shift_0/o7" 9.594
cap "wz7" "shift_0/shift_one_7/inv_3/Vdd!" 87.531
cap "shift_0/shift_one_7/2mux_nr_1/out" "shift_0/o7" 57.7175
cap "latch_3/latch_one_7/a_n5_n54#" "wz7" 30.853
cap "wz7" "shift_0/o7" 2.184
cap "latch_3/latch_one_7/GND!" "shift_0/o7" 30.043
cap "shift_0/shift_one_7/inv_3/Vdd!" "rx7" 9.144
cap "wz7" "latch_3/latch_one_7/c" 1.248
cap "rx7" "shift_0/o7" 22.87
cap "wz7" "shift_0/shift_one_7/inv_3/GND!" 3.152
cap "shift_0/shift_one_7/inv_3/Vdd!" "shift_0/o7" 1.162
cap "latch_3/latch_one_7/c" "rx7" 3.12
cap "shift_0/shift_one_7/inv_3/GND!" "rx7" 6.096
cap "latch_3/latch_one_7/a_n5_n54#" "shift_0/o7" 57.7175
cap "latch_3/latch_one_7/Vdd!" "shift_0/shift_one_7/2mux_nr_1/out" 46.174
cap "wz7" "latch_3/latch_one_7/Vdd!" 64.715
cap "wz7" "shift_0/shift_one_7/2mux_nr_1/out" 8.599
cap "latch_3/latch_one_7/GND!" "wz7" 66.689
cap "latch_3/latch_one_7/Vdd!" "rx7" 44.76
cap "fblock_0/b7" "fblock_0/fblock_one_7/2mux_nr_0/in0" 7.975
cap "fblock_0/fblock_one_7/inv_0/GND!" "latch_3/out7" 47.754
cap "fblock_0/a7" "fblock_0/fblock_one_7/inv_0/GND!" 56.9869
cap "latch_3/latch_one_7/c" "latch_3/out7" 140.424
cap "fblock_0/a7" "latch_3/latch_one_7/c" 77.883
cap "latch_3/latch_one_7/a_12_n54#" "latch_3/latch_one_7/Vdd!" 2.84217e-14
cap "fblock_0/fblock_one_7/2mux_nr_0/out" "latch_3/out7" 13.769
cap "fblock_0/fblock_one_7/2mux_nr_2/a_n17_n11#" "latch_3/out7" 17.157
cap "fblock_0/fblock_one_7/2mux_nr_2/a_n17_n11#" "fblock_0/a7" 12.912
cap "fblock_0/a7" "fblock_0/fblock_one_7/2mux_nr_0/out" 7.134
cap "fblock_0/fblock_one_7/2mux_nr_1/Vdd!" "fblock_0/b7" 14.287
cap "latch_3/latch_one_7/GND!" "latch_3/latch_one_7/c" 2.84217e-14
cap "latch_3/out7" "fblock_0/fblock_one_7/inv_0/in" 19.302
cap "fblock_0/fblock_one_7/2mux_nr_0/in1" "fblock_0/b7" 4.95
cap "fblock_0/a7" "fblock_0/fblock_one_7/inv_0/in" 9.081
cap "fblock_0/b7" "fblock_0/fblock_one_7/inv_0/GND!" 72.394
cap "fblock_0/fblock_one_7/2mux_nr_2/in0" "latch_3/out7" 13.769
cap "fblock_0/fblock_one_7/2mux_nr_2/in0" "fblock_0/a7" 7.134
cap "fblock_0/fblock_one_7/2mux_nr_0/out" "fblock_0/b7" 11.825
cap "fblock_0/b7" "fblock_0/fblock_one_7/2mux_nr_0/a_n17_n11#" 38.545
cap "fblock_0/fblock_one_7/2mux_nr_0/a_n17_n11#" "fblock_0/fblock_one_7/inv_0/GND!" 2.84217e-14
cap "fblock_0/a7" "latch_3/out7" 8.336
cap "latch_3/latch_one_7/Vdd!" "latch_3/out7" 0.959
cap "fblock_0/a7" "fblock_0/fblock_one_7/2mux_nr_2/Vdd!" 111.926
cap "latch_3/latch_one_7/GND!" "fblock_0/a7" 0.333
cap "latch_3/latch_one_7/GND!" "latch_3/out7" 1.209
cap "latch_1/latch_one_7/Vdd!" "wz7" 58.7
cap "latch_1/latch_one_7/c" "wz7" 4.324
cap "rx7" "fblock_0/fblock_one_7/inv_0/in" 2.844
cap "rx7" "latch_1/latch_one_7/GND!" 58.7
cap "ry7" "latch_1/latch_one_7/GND!" 58.7
cap "latch_1/latch_one_7/a_12_n54#" "wz7" 9.731
cap "fblock_0/f7" "wz7" 18.093
cap "fblock_0/fblock_one_7/2mux_nr_1/s" "ry7" 25.728
cap "fblock_0/fblock_one_7/2mux_nr_1/GND!" "ry7" 28.388
cap "ry7" "fblock_0/fblock_one_7/2mux_nr_1/in0" 7.975
cap "fblock_0/f7" "latch_1/latch_one_7/GND!" 12.326
cap "fblock_0/fblock_one_7/2mux_nr_1/out" "ry7" 11.825
cap "ry7" "fblock_0/fblock_one_7/2mux_nr_1/in1" 4.95
cap "fblock_0/fblock_one_7/inv_0/in" "wz7" 7.973
cap "rx7" "latch_1/latch_one_7/a_n5_n54#" 7.807
cap "fblock_0/fblock_one_7/inv_0/GND!" "fblock_0/fblock_one_7/inv_0/in" 5.68434e-14
cap "fblock_0/fblock_one_7/inv_0/GND!" "wz7" 25.025
cap "latch_1/latch_one_7/GND!" "wz7" 69.742
cap "latch_1/latch_one_7/Vdd!" "rx7" 103.828
cap "latch_1/latch_one_7/Vdd!" "ry7" 58.7
cap "fblock_0/f7" "latch_1/latch_one_7/a_n5_n54#" 57.7175
cap "fblock_0/fblock_one_7/2mux_nr_1/Vdd!" "ry7" 9.101
cap "latch_1/latch_one_7/Vdd!" "fblock_0/f7" 6.108
cap "rx7" "fblock_0/fblock_one_7/f" 107.499
cap "rx7" "fblock_0/f7" 13.492
cap "ry7" "fblock_0/fblock_one_7/2mux_nr_1/a_n17_n11#" 38.545
cap "ry7" "fblock_0/fblock_one_7/f" 19.78
cap "latch_1/latch_one_7/a_n5_n54#" "wz7" 43.4
subcap "ry7" -2434.89
cap "latch_1/latch_one_7/GND!" "latch_1/out7" 2.361
cap "latch_1/latch_one_7/a_30_n54#" "latch_1/out7" 1.524
cap "addsub_0/b7" "addsub_0/xor_7/a_100_n42#" 0.707
cap "rx7" "latch_1/latch_one_7/Vdd!" -1.405
cap "latch_1/latch_one_7/c" "rx7" 58.7
cap "latch_1/latch_one_7/GND!" "latch_1/out7" 3.821
cap "latch_1/out7" "latch_1/latch_one_7/Vdd!" 1.221
cap "addsub_0/b7" "addsub_0/xor_7/a_89_n31#" 3.068
cap "latch_1/latch_one_7/c" "latch_1/out7" 144.632
cap "rx7" "latch_1/latch_one_7/a_30_n35#" 4.828
cap "addsub_0/b7" "rx7" 4.324
cap "addsub_0/b7" "addsub_0/xor_7/a_69_n42#" 2.457
cap "latch_1/latch_one_7/Vdd!" "rx7" -4.367
cap "addsub_0/b7" "addsub_0/xor_7/b" 15.993
cap "addsub_0/b7" "addsub_0/xor_7/out" 31.486
cap "latch_1/latch_one_7/a_12_n54#" "rx7" 4.948
cap "latch_1/out7" "rx7" 9.182
cap "rx7" "addsub_0/xor_7/Vdd!" 8.496
cap "addsub_0/b7" "addsub_0/xor_7/GND!" 96.5174
cap "latch_1/latch_one_7/a_n5_n54#" "rx7" 4.948
cap "latch_1/latch_one_7/a_n5_n54#" "latch_1/out7" 15.975
cap "addsub_0/xor_7/GND!" "rx7" 14.868
cap "addsub_0/b7" "addsub_0/xor_7/a_61_n31#" 7.218
cap "latch_1/latch_one_7/c" "addsub_0/b7" 58.7
cap "addsub_0/xor_7/a" "rx7" 2.424
cap "ry7" "addsub_0/addsub_one_7/GND!" 20.178
cap "addsub_0/addsub_one_7/GND!" "rx7" 20.114
cap "addsub_0/addsub_one_7/a_35_n41#" "rx7" 19.78
cap "addsub_0/cout" "addsub_0/addsub_one_7/s" 41.11
cap "addsub_0/addsub_one_7/GND!" "rx7" -0.341
cap "addsub_0/cout" "addsub_0/addsub_one_7/a_89_n41#" 22.875
cap "addsub_0/cout" "addsub_0/addsub_one_7/a_72_n41#" 1.575
cap "addsub_0/xor_7/a_61_n1#" "rx7" 112.452
cap "addsub_0/cout" "addsub_0/addsub_one_7/a_78_n41#" 15.064
cap "addsub_0/cout" "addsub_0/addsub_one_7/b" 4.204
cap "addsub_0/xor_7/a_89_n31#" "rx7" 2.424
cap "addsub_0/cout" "addsub_0/addsub_one_7/GND!" 28.222
cap "addsub_0/cout" "addsub_0/addsub_one_7/cin" 8.408
cap "addsub_0/cout" "addsub_0/addsub_one_7/GND!" 33
cap "addsub_0/cout" "addsub_0/addsub_one_7/a_35_n41#" 8.408
cap "addsub_0/cout" "ry7" 2.97
cap "addsub_0/addsub_one_7/a_89_9#" "rx7" 4.7
cap "addsub_0/addsub_one_7/Vdd!" "wz7" 43.982
cap "addsub_0/xor_7/b" "rx7" 2.424
cap "wz7" "addsub_0/addsub_one_7/GND!" 18.211
cap "addsub_0/addsub_one_7/a_35_n41#" "wz7" 65.763
cap "wz7" "addsub_0/addsub_one_7/GND!" 0.308
cap "addsub_0/cout" "addsub_0/addsub_one_7/a" 4.204
cap "addsub_0/addsub_one_7/b" "rx7" 94.487
cap "addsub_0/addsub_one_7/a_78_n41#" "rx7" 11.825
cap "addsub_0/xor_7/a_61_n31#" "rx7" 2.424
cap "addsub_0/addsub_one_7/Vdd!" "ry7" 19.647
cap "addsub_0/addsub_one_7/Vdd!" "rx7" 87.252
subcap "a_841_569#" -38.45
cap "reg_0/reg_one_0/r0" "ry7" 17.308
cap "rx7" "addsub_0/s7" 3.468
cap "ry7" "latch_2/latch_one_7/GND!" 99.72
cap "latch_2/out7" "rx7" 4.341
cap "latch_2/out7" "addsub_0/addsub_one_7/GND!" 7.422
cap "latch_2/out7" "reg_0/reg_one_0/r0" 217.183
cap "rx7" "latch_2/latch_one_7/a_n5_n54#" 6.195
cap "rx7" "latch_2/latch_one_7/a_12_n54#" 37.778
cap "rx7" "addsub_0/addsub_one_7/b" -2.068
cap "latch_2/out7" "latch_2/latch_one_7/GND!" 90.233
cap "rx7" "latch_2/latch_one_7/Vdd!" 116.636
cap "rx7" "addsub_0/addsub_one_7/GND!" 7.942
cap "latch_2/out7" "addsub_0/s7" 4.948
cap "latch_2/out7" "addsub_0/addsub_one_7/a_35_n41#" -1.814
cap "ry7" "latch_2/latch_one_7/Vdd!" 44.76
cap "rx7" "latch_2/latch_one_7/c" 61.544
cap "latch_2/out7" "latch_2/latch_one_7/a_12_n54#" 12.473
cap "addsub_0/s7" "latch_2/latch_one_7/a_n5_n54#" 57.7175
cap "latch_2/out7" "latch_2/latch_one_7/a_30_n54#" 2.592
cap "latch_2/out7" "latch_2/latch_one_7/a_n5_n54#" 12.196
cap "addsub_0/s7" "latch_2/latch_one_7/Vdd!" 19.399
cap "latch_2/out7" "latch_2/latch_one_7/Vdd!" 59.921
cap "latch_2/latch_one_7/c" "ry7" 81.003
cap "rx7" "addsub_0/addsub_one_7/GND!" 5.148
cap "latch_2/out7" "addsub_0/addsub_one_7/GND!" 3.399
cap "rx7" "reg_0/reg_one_0/r0" 19.78
cap "rx7" "latch_2/latch_one_7/a_30_n35#" 1.524
cap "rx7" "latch_2/latch_one_7/GND!" 58.7
cap "ry7" "addsub_0/addsub_one_7/GND!" 4.005
cap "latch_2/out7" "latch_2/latch_one_7/c" 727.057
cap "wz7" "reg_1/reg_one_0/r0" 63.6875
cap "reg_0/reg_one_0/Vdd!" "reg_0/port71" 58.7
cap "reg_0/reg_one_0/Vdd!" "reg_0/port70" 134.044
cap "reg_0/reg_one_0/a_21_n13#" "reg_0/port70" 20.118
cap "reg_0/in7" "wz7" 14.786
cap "reg_0/reg_one_0/tmp" "wz7" 4.389
cap "reg_0/in7" "reg_0/reg_one_0/r0" -5.072
cap "reg_0/w" "reg_0/reg_one_0/w_n11_n27#" 2.84217e-14
cap "reg_0/reg_one_0/a_16_27#" "wz7" 8.264
cap "reg_0/reg_one_0/tmp" "wz7" 4.324
cap "reg_0/reg_one_0/a_4_n13#" "reg_0/port70" 20.417
cap "reg_0/reg_one_0/w_n11_n27#" "wz7" 66.94
cap "reg_0/port71" "reg_0/reg_one_0/w_n11_n27#" 121.694
cap "reg_0/w" "wz7" 58.7
cap "reg_0/reg_one_0/tmp" "reg_0/port70" 4.948
cap "reg_0/reg_one_0/w_n11_n27#" "reg_0/port70" 194.315
cap "reg_0/port71" "reg_0/w" 127.744
cap "wz7" "reg_0/reg_one_0/w" 4.382
cap "wz7" "reg_0/reg_one_0/r0" -7.416
cap "reg_0/w" "reg_0/port70" 434.25
cap "reg_0/port71" "reg_0/reg_one_0/r0" 23.94
cap "wz7" "reg_0/reg_one_0/r1" 58.7
cap "reg_0/reg_one_0/r0" "reg_0/port70" -7.416
cap "reg_0/port71" "reg_0/reg_one_0/r1" 64.004
cap "reg_0/reg_one_0/r1" "reg_0/port70" 70.642
cap "reg_0/reg_one_0/a_33_32#" "wz7" 65.474
cap "reg_0/reg_one_0/Vdd!" "wz7" 165.083
cap "reg_1/in7" "reg_1/reg_one_0/a_16_27#" 8.264
cap "reg_1/reg_one_0/tmp" "reg_1/port70" 4.694
cap "reg_1/reg_one_0/a_4_n13#" "reg_1/port70" 118.494
cap "reg_1/in7" "reg_1/reg_one_0/tmp" 4.324
cap "reg_1/reg_one_0/r1" "reg_1/port71" 64.004
cap "reg_1/port71" "reg_1/reg_one_0/r0" 48.664
cap "reg_1/reg_one_0/r1" "reg_1/port70" 60.064
cap "reg_1/port70" "reg_1/reg_one_0/r0" 21.144
cap "reg_1/in7" "reg_1/reg_one_0/r1" 58.7
cap "reg_1/in7" "reg_1/reg_one_0/r0" 89.8075
cap "reg_1/in7" "reg_1/reg_one_0/a_33_32#" 65.474
cap "reg_1/reg_one_0/w_n11_n27#" "reg_1/w" 2.84217e-14
cap "reg_1/in7" "reg_1/reg_one_0/w" 4.382
cap "reg_1/in7" "reg_1/reg_one_0/tmp" 4.389
cap "reg_1/reg_one_0/w_n11_n27#" "reg_1/port71" 121.694
cap "reg_1/reg_one_0/w_n11_n27#" "reg_1/port70" 198.775
cap "reg_1/in7" "reg_1/reg_one_0/w_n11_n27#" 66.94
cap "reg_1/port71" "reg_1/w" 127.744
cap "reg_1/port71" "reg_1/reg_one_0/Vdd!" 58.7
cap "reg_1/w" "reg_1/port70" 125.763
cap "reg_1/port70" "reg_1/reg_one_0/Vdd!" 75.185
cap "reg_1/reg_one_0/a_21_n13#" "reg_1/port70" 2.238
cap "reg_1/in7" "reg_1/w" 58.7
cap "reg_1/in7" "reg_1/reg_one_0/Vdd!" 165.083
cap "reg_1/port71" "reg_1/port70" 3.85
cap "reg_2/port71" "reg_2/reg_one_0/r0" 48.664
cap "reg_2/reg_one_0/w_n11_n27#" "reg_1/port70" 135.088
cap "reg_2/port71" "reg_2/reg_one_0/Vdd!" 58.7
cap "reg_2/reg_one_0/a_33_32#" "reg_2/in7" 65.474
cap "reg_2/reg_one_0/w_n11_n27#" "reg_2/w" 2.84217e-14
cap "reg_2/port71" "reg_2/reg_one_0/r1" 64.004
cap "reg_2/w" "reg_1/port70" 92.2312
cap "reg_2/reg_one_0/a_16_27#" "reg_2/in7" 8.264
cap "reg_2/port71" "reg_2/reg_one_0/w_n11_n27#" 121.694
cap "reg_2/port71" "reg_1/port70" 3.85
cap "reg_2/reg_one_0/w" "reg_2/in7" 4.382
cap "reg_2/reg_one_0/r0" "reg_2/in7" 153.495
cap "reg_2/reg_one_0/tmp" "reg_2/in7" 4.324
cap "reg_2/port71" "reg_2/w" 94.2122
cap "reg_2/reg_one_0/Vdd!" "reg_2/in7" 165.083
cap "reg_2/reg_one_0/tmp" "reg_2/in7" 4.389
cap "reg_2/reg_one_0/a_4_n13#" "reg_1/port70" 118.494
cap "reg_2/reg_one_0/r1" "reg_2/in7" 58.7
cap "reg_2/reg_one_0/w_n11_n27#" "reg_2/in7" 66.94
cap "reg_2/reg_one_0/tmp" "reg_1/port70" 4.694
cap "reg_2/reg_one_0/r0" "reg_1/port70" 21.144
cap "reg_2/reg_one_0/a_21_n13#" "reg_1/port70" 2.238
cap "reg_2/reg_one_0/Vdd!" "reg_1/port70" 75.185
cap "reg_2/w" "reg_2/in7" 58.7
cap "reg_2/reg_one_0/r1" "reg_1/port70" 60.064
cap "reg_2/port70" "reg_3/reg_one_0/Vdd!" 74.654
cap "reg_2/port71" "reg_3/port71" 73.199
cap "reg_2/port70" "reg_2/w" 33.5312
cap "reg_2/port70" "reg_3/port70" 8.58
cap "reg_2/port71" "reg_3/reg_one_0/r0" 48.664
cap "reg_2/port70" "reg_2/reg_one_0/w_n11_n27#" 63.6875
cap "reg_3/in7" "reg_3/reg_one_0/r1" 58.7
cap "reg_2/port70" "reg_3/reg_one_0/a_21_n13#" 2.238
cap "reg_2/port70" "reg_3/reg_one_0/r1" 60.064
cap "reg_3/port71" "reg_3/w" 5.072
cap "reg_3/in7" "reg_3/reg_one_0/w" 1.248
cap "reg_3/reg_one_0/w_n11_n27#" "reg_2/port71" 106.567
cap "reg_3/in7" "reg_3/reg_one_0/w_n11_n27#" 17.302
cap "reg_2/port70" "reg_3/port71" 3.85
cap "reg_2/port70" "reg_3/reg_one_0/a_4_n13#" 118.494
cap "reg_3/in7" "reg_3/reg_one_0/tmp" 6.6
cap "reg_3/in7" "reg_3/reg_one_0/a_16_27#" 7.446
cap "reg_2/port71" "reg_3/reg_one_0/Vdd!" 58.7
cap "reg_3/in7" "reg_3/reg_one_0/r0" 153.495
cap "reg_3/reg_one_0/w_n11_n27#" "reg_3/port71" 1.628
cap "reg_2/port70" "reg_3/reg_one_0/r0" 21.144
cap "reg_2/port71" "reg_2/w" 33.5312
cap "reg_3/in7" "reg_3/reg_one_0/tmp" 1.248
cap "reg_3/in7" "reg_3/reg_one_0/w_n11_n27#" 58.7
cap "reg_3/reg_one_0/w_n11_n27#" "reg_2/port70" 63.11
cap "reg_2/port70" "reg_3/reg_one_0/tmp" 4.694
cap "reg_2/port71" "reg_3/reg_one_0/r1" 64.004
cap "reg_3/in7" "reg_3/reg_one_0/a_33_32#" 39.098
cap "reg_3/in7" "reg_3/reg_one_0/Vdd!" 75.24
subcap "wz_addrL7" -530.816
subcap "PCL_w_muxout7" -380.236
cap "reg_3/port71" "reg_3/reg_one_0/w_n11_n27#" -1.039
cap "reg_3/port70" "reg_3/reg_one_0/w" 125.763
cap "mux_8bit_0/in0_7" "mux_8bit_0/out7" 35.938
cap "mux_8bit_0/in0_7" "mux_8bit_0/mux_one_7/GND!" 12.579
cap "reg_3/reg_one_0/w_n11_n27#" "reg_3/port70" 135.615
cap "mux_8bit_0/in1_7" "mux_8bit_0/mux_one_7/Vdd!" 90.117
cap "mux_8bit_0/out7" "mux_8bit_0/mux_one_7/GND!" 37.928
cap "mux_8bit_0/in1_7" "mux_8bit_0/mux_one_7/2mux_nr_0/s" 4.556
cap "reg_3/port71" "reg_3/reg_one_0/w" 127.744
cap "mux_8bit_0/in1_7" "reg_3/reg_one_0/Vdd!" -2.948
cap "reg_3/port71" "mux_8bit_0/out7" -10.01
cap "reg_3/reg_one_0/w_n11_n27#" "reg_3/port71" 12.7375
cap "mux_8bit_0/mux_one_7/inv2_1/a_1_8#" "mux_8bit_0/in0_7" 26.669
cap "reg_3/port71" "mux_8bit_0/mux_one_7/GND!" 69.613
cap "mux_8bit_0/in1_7" "reg_3/reg_one_0/w_n11_n27#" -2.948
cap "mux_8bit_0/in0_7" "mux_8bit_0/mux_one_7/Vdd!" 29.483
cap "mux_8bit_0/in1_7" "mux_8bit_0/mux_one_7/2mux_nr_0/a_n17_n11#" 47.632
cap "reg_3/reg_one_0/Vdd!" "reg_3/port70" -2.898
cap "mux_8bit_0/in1_7" "reg_3/reg_one_0/w" 58.7
cap "mux_8bit_0/in1_7" "reg_3/reg_one_0/a_33_32#" -4.455
cap "mux_8bit_0/in0_7" "mux_8bit_0/mux_one_7/2mux_nr_0/in0" 29.025
cap "reg_3/reg_one_0/w_n11_n27#" "reg_3/port70" -3.379
cap "reg_3/reg_one_0/w_n11_n27#" "mux_8bit_0/in1_7" 8.24
cap "reg_3/reg_one_0/w" "reg_3/reg_one_0/w_n11_n27#" -7.10543e-15
cap "mux_8bit_0/in1_7" "mux_8bit_0/mux_one_7/2mux_nr_0/in1" 18.535
cap "mux_8bit_0/in1_7" "mux_8bit_0/mux_one_7/GND!" 15.908
cap "reg_4/reg_one_0/w_n11_n27#" "wz_addrL7" 76.564
cap "wz_addrL7" "reg_4/port71" 4.95
cap "ry7" "reg_4/reg_one_0/r0" 48.664
cap "wz7" "reg_4/reg_one_0/r1" 58.7
cap "reg_4/reg_one_0/r0" "mux_8bit_0/mux_one_7/GND!" 63.6875
cap "reg_4/reg_one_0/a_16_27#" "wz7" 8.022
cap "wz_addrL7" "mux_8bit_0/mux_one_7/GND!" 13.606
cap "reg_4/reg_one_0/a_4_n13#" "wz_addrL7" 47.175
cap "wz_addrL7" "reg_4/port70" 9.229
cap "ry7" "reg_4/reg_one_0/r1" 64.004
cap "mux_8bit_0/out7" "reg_4/reg_one_0/Vdd!" 56.544
cap "wz7" "reg_4/reg_one_0/Vdd!" 58.7
cap "wz_addrL7" "reg_4/reg_one_0/r0" 21.028
cap "reg_4/reg_one_0/tmp" "wz7" 6.507
cap "mux_8bit_0/out7" "wz7" 2.844
cap "mux_8bit_0/mux_one_7/2mux_nr_0/a_n17_n11#" "mux_8bit_0/mux_one_7/GND!" 3.55271e-15
cap "reg_4/reg_one_0/w_n11_n27#" "wz7" 192.228
cap "ry7" "reg_4/reg_one_0/Vdd!" 58.7
cap "wz_addrL7" "reg_4/reg_one_0/r1" 59.948
cap "ry7" "mux_8bit_0/out7" -12.177
cap "reg_4/reg_one_0/w_n11_n27#" "reg_4/port71" 1.628
cap "mux_8bit_0/out7" "mux_8bit_0/mux_one_7/GND!" 462.156
cap "wz7" "mux_8bit_0/mux_one_7/GND!" 15.961
cap "reg_4/reg_one_0/w_n11_n27#" "ry7" 106.567
cap "mux_8bit_0/mux_one_7/2mux_nr_0/a_n17_n11#" "wz7" -5.178
cap "reg_4/reg_one_0/w" "wz7" 5.064
cap "wz7" "reg_4/reg_one_0/a_33_32#" 7.959
cap "ry7" "reg_4/port71" 73.199
cap "reg_4/reg_one_0/r0" "reg_4/reg_one_0/Vdd!" -9.768
cap "wz_addrL7" "reg_4/reg_one_0/Vdd!" 73.616
cap "ry7" "mux_8bit_0/mux_one_7/GND!" -1.312
cap "mux_8bit_0/out7" "mux_8bit_0/mux_one_7/2mux_nr_0/out" 85.4219
cap "mux_8bit_0/mux_one_7/inv2_1/a_1_8#" "wz_addrL7" -1.132
cap "wz_addrL7" "reg_4/reg_one_0/tmp" 4.68
cap "reg_4/reg_one_0/w" "reg_4/port71" 5.072
cap "mux_8bit_0/out7" "reg_4/reg_one_0/r0" 314.001
cap "wz7" "reg_4/reg_one_0/r0" 19.78
cap "wz_addrL7" "mux_8bit_0/out7" -3.85
cap "mux_8bit_0/mux_one_7/2mux_nr_0/s" "wz7" 4.948
subcap "a_1545_576#" -104.338
cap "addsub_1/addsub_one_7/b" "wz7" 97.913
cap "reg_4/reg_one_0/w_n11_n27#" "wz_addrL7" 8.24
cap "reg_4/port70" "wz_addrL7" -7.348
cap "addsub_1/b7" "wz7" 26.517
cap "addsub_1/addsub_one_7/Vdd!" "wz7" 15.72
cap "wz_addrL7" "reg_4/reg_one_0/w_n11_n27#" -3.379
cap "wz7" "addsub_1/xor_7/a_61_n1#" 5.568
cap "addsub_1/xor_7/a_89_n31#" "wz7" 17.316
cap "wz7" "reg_4/reg_one_0/w" 58.7
cap "reg_4/reg_one_0/w_n11_n27#" "wz7" -8.24
cap "addsub_1/xor_7/b" "reg_4/port70" 2.424
cap "addsub_1/addsub_one_7/b" "reg_4/port70" 36.877
cap "addsub_1/b7" "reg_4/port70" 2.424
cap "addsub_1/xor_7/a_61_n31#" "wz7" 19.78
cap "addsub_1/addsub_one_7/Vdd!" "reg_4/port70" 27.048
cap "addsub_1/addsub_one_7/Vdd!" "reg_4/port71" 2.655
cap "reg_4/port70" "addsub_1/xor_7/a_61_n1#" 106.684
cap "addsub_1/xor_7/a_89_n31#" "reg_4/port70" 2.424
cap "addsub_1/xor_7/a_61_n31#" "addsub_1/b7" -1.13687e-13
cap "wz7" "reg_4/reg_one_0/w_n11_n27#" -2.417
cap "reg_4/port71" "reg_4/reg_one_0/w" 127.744
cap "reg_4/reg_one_0/a_33_32#" "wz7" -12.339
cap "addsub_1/addsub_one_7/Vdd!" "wz_addrL7" 5.06
cap "wz_addrL7" "reg_4/reg_one_0/Vdd!" -2.948
cap "reg_4/port71" "reg_4/reg_one_0/w_n11_n27#" 12.7375
cap "reg_4/reg_one_0/w_n11_n27#" "reg_4/port70" 63.6875
cap "wz_addrL7" "reg_4/reg_one_0/w" 58.7
cap "addsub_1/xor_7/b" "wz7" 11.825
cap "reg_4/port71" "reg_4/reg_one_0/w_n11_n27#" -1.039
cap "addsub_1/xor_7/a_61_n31#" "reg_4/port70" 2.424
subcap "a_1716_569#" -30.357
cap "wz_addrL7" "addsub_1/addsub_one_7/Vdd!" 37.175
cap "addsub_1/s7" "addsub_1/cout" 41.11
cap "wz7" "addsub_1/addsub_one_7/a_78_n41#" 35.835
cap "addsub_1/addsub_one_7/a_35_n41#" "addsub_1/cout" 8.408
cap "ry7" "addsub_1/cout" 3.96
cap "addsub_1/cout" "addsub_1/addsub_one_7/b" 4.204
cap "addsub_1/addsub_one_7/a_72_n41#" "addsub_1/cout" 1.575
cap "addsub_1/addsub_one_7/GND!" "wz7" 14.639
cap "addsub_1/cout" "addsub_1/addsub_one_7/a_78_n41#" 15.064
cap "addsub_1/addsub_one_7/cin" "wz7" 1.56
cap "addsub_1/addsub_one_7/GND!" "wz_addrL7" 10.505
cap "addsub_1/addsub_one_7/GND!" "addsub_1/cout" 28.222
cap "addsub_1/addsub_one_7/a" "addsub_1/cout" 4.204
cap "addsub_1/s7" "latch_5/latch_one_7/a_n5_n54#" 19.2392
cap "addsub_1/addsub_one_7/cin" "addsub_1/cout" 8.408
cap "addsub_1/addsub_one_7/Vdd!" "wz7" 3.171
cap "wz_addrL7" "addsub_1/addsub_one_7/a_35_n41#" 24.622
cap "addsub_1/addsub_one_7/a_89_n41#" "addsub_1/cout" 22.875
cap "addsub_1/addsub_one_7/GND!" "addsub_1/addsub_one_7/a_35_n41#" -1.13687e-13
cap "addsub_1/addsub_one_7/GND!" "ry7" 27.612
cap "addsub_1/addsub_one_7/GND!" "wz7" 11.825
cap "addsub_1/addsub_one_7/GND!" "wz_addrL7" 43.659
cap "addsub_1/addsub_one_7/GND!" "addsub_1/cout" 33
cap "ry7" "addsub_1/addsub_one_7/Vdd!" 13.563
cap "addsub_1/s7" "latch_5/latch_one_7/Vdd!" -12.402
cap "addsub_1/addsub_one_7/a_35_n41#" "wz7" 51.712
cap "addsub_1/addsub_one_7/b" "wz7" 95.736
subcap "a_1716_569#" -107.014
cap "latch_5/latch_one_7/Vdd!" "wz7" 117.4
cap "latch_5/latch_one_7/GND!" "wz7" 117.4
cap "staticizer_2/staticizer_one_7/c" "wz7" 58.7
cap "latch_5/out7" "staticizer_2/staticizer_one_7/a_77_n45#" 9.998
cap "latch_5/latch_one_7/Vdd!" "addsub_1/s7" 19.399
cap "latch_5/latch_one_7/c" "wz7" 58.7
cap "latch_5/latch_one_7/Vdd!" "latch_5/latch_one_7/GND!" -0.984
cap "latch_5/latch_one_7/GND!" "staticizer_2/staticizer_one_7/c" -5.68434e-14
cap "latch_5/latch_one_7/Vdd!" "latch_5/latch_one_7/c" 963.732
cap "latch_5/latch_one_7/Vdd!" "latch_5/latch_one_7/a_12_n54#" 1.13687e-13
cap "latch_5/out7" "staticizer_2/staticizer_one_7/a_60_n45#" 212.283
cap "latch_5/latch_one_7/a_n5_n54#" "addsub_1/s7" 57.7175
cap "latch_5/latch_one_7/c" "latch_5/latch_one_7/GND!" 13.8522
cap "latch_5/latch_one_7/Vdd!" "latch_5/out7" 231.426
cap "latch_5/out7" "addsub_1/s7" 4.324
cap "latch_5/latch_one_7/GND!" "latch_5/out7" 167.247
cap "latch_5/latch_one_7/Vdd!" "ry7" 91.535
cap "latch_5/latch_one_7/GND!" "ry7" 158.184
cap "latch_5/out7" "staticizer_2/staticizer_one_7/c" 63.648
cap "ry7" "staticizer_2/staticizer_one_7/c" 65.01
cap "latch_5/out7" "latch_5/latch_one_7/a_12_n54#" 9.731
cap "latch_5/out7" "latch_5/latch_one_7/a_n5_n54#" 59.375
cap "latch_5/latch_one_7/c" "latch_5/out7" 75.182
cap "latch_5/latch_one_7/c" "ry7" 81.003
cap "latch_5/latch_one_7/a_30_n54#" "latch_5/out7" 1.524
subcap "wz_addrH7" -910.871
subcap "m1_1909_542#" -380.236
cap "staticizer_2/staticizer_one_7/out" "staticizer_2/staticizer_one_7/a_60_n45#" -5.616
cap "staticizer_2/w_90_n1211#" "staticizer_2/staticizer_one_7/out" 2.59
cap "mux_8bit_1/mux_one_7/Vdd!" "mux_8bit_1/in1_7" 87.831
cap "staticizer_2/staticizer_one_7/Vdd!" "staticizer_2/staticizer_one_7/out" 11.587
cap "mux_8bit_1/mux_one_7/2mux_nr_0/a_n17_n11#" "mux_8bit_1/in1_7" 47.632
cap "staticizer_2/staticizer_one_7/c" "staticizer_2/staticizer_one_7/out" 3.996
cap "staticizer_2/w_90_n1211#" "ry7" 4.329
cap "mux_8bit_1/mux_one_7/GND!" "mux_8bit_1/in1_7" 15.908
cap "mux_8bit_1/mux_one_7/2mux_nr_0/in1" "mux_8bit_1/in1_7" 18.535
cap "staticizer_2/staticizer_one_7/out" "staticizer_2/staticizer_one_7/a_95_n45#" 4.212
cap "mux_8bit_1/in0_7" "mux_8bit_1/mux_one_7/2mux_nr_0/in0" 34.083
cap "mux_8bit_1/mux_one_7/GND!" "mux_8bit_1/out7" 37.928
cap "mux_8bit_1/in0_7" "mux_8bit_1/mux_one_7/Vdd!" 104.197
cap "staticizer_2/staticizer_one_7/a_95_n27#" "staticizer_2/staticizer_one_7/out" 5.61
cap "mux_8bit_1/out7" "ry7" -10.01
cap "mux_8bit_1/mux_one_7/2mux_nr_0/s" "mux_8bit_1/in1_7" 4.556
cap "staticizer_2/staticizer_one_7/out" "staticizer_2/staticizer_one_7/a_77_n45#" 19.052
cap "mux_8bit_1/mux_one_7/GND!" "ry7" 69.613
cap "mux_8bit_1/mux_one_7/GND!" "mux_8bit_1/in0_7" 18.437
cap "mux_8bit_1/in0_7" "mux_8bit_1/mux_one_7/inv2_1/a_1_8#" 17.59
cap "reg_5/reg_one_0/Vdd!" "reg_5/reg_one_0/r0" -9.768
cap "wz7" "reg_5/reg_one_0/tmp" 6.507
cap "reg_5/reg_one_0/r0" "mux_8bit_1/out7" 314.001
cap "ry7" "reg_5/reg_one_0/r0" 48.664
cap "reg_5/reg_one_0/Vdd!" "wz_addrH7" 162.612
cap "wz_addrH7" "mux_8bit_1/out7" -3.85
cap "mux_8bit_1/mux_one_7/2mux_nr_0/a_n17_n11#" "wz7" -5.178
cap "reg_5/reg_one_0/Vdd!" "mux_8bit_1/out7" 56.544
cap "reg_5/port70" "wz_addrH7" 6.6
cap "mux_8bit_1/mux_one_7/2mux_nr_0/out" "mux_8bit_1/out7" 85.4219
cap "ry7" "reg_5/reg_one_0/Vdd!" 58.7
cap "wz7" "reg_5/reg_one_0/r0" 19.78
cap "ry7" "mux_8bit_1/out7" -12.177
cap "reg_5/reg_one_0/a_54_5#" "wz_addrH7" 4.828
cap "wz7" "reg_5/reg_one_0/a_33_32#" 7.959
cap "mux_8bit_1/mux_one_7/GND!" "mux_8bit_1/mux_one_7/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "wz7" "reg_5/reg_one_0/Vdd!" 58.7
cap "wz7" "mux_8bit_1/out7" 2.844
cap "wz7" "reg_5/reg_one_0/a_16_27#" 8.022
cap "reg_5/reg_one_0/w_n11_n27#" "wz_addrH7" 58.7
cap "mux_8bit_1/mux_one_7/GND!" "reg_5/reg_one_0/r0" 63.6875
cap "reg_5/reg_one_0/r1" "wz_addrH7" 58.7
cap "ry7" "reg_5/port71" 73.199
cap "reg_5/reg_one_0/w" "wz7" 5.064
cap "mux_8bit_1/mux_one_7/GND!" "wz_addrH7" 17.872
cap "ry7" "reg_5/reg_one_0/w_n11_n27#" 106.567
cap "mux_8bit_1/mux_one_7/2mux_nr_0/s" "wz7" 4.948
cap "reg_5/reg_one_0/tmp" "wz_addrH7" 4.948
cap "reg_5/reg_one_0/w" "reg_5/port71" 5.072
cap "mux_8bit_1/mux_one_7/GND!" "mux_8bit_1/out7" 462.156
cap "ry7" "reg_5/reg_one_0/r1" 64.004
cap "reg_5/reg_one_0/a_4_n13#" "wz_addrH7" 27.497
cap "mux_8bit_1/mux_one_7/GND!" "ry7" -1.312
cap "wz7" "reg_5/reg_one_0/w_n11_n27#" 192.228
cap "wz7" "reg_5/reg_one_0/r1" 58.7
cap "reg_5/reg_one_0/r0" "wz_addrH7" 24.728
cap "mux_8bit_1/mux_one_7/GND!" "wz7" 15.961
cap "reg_5/port71" "reg_5/reg_one_0/w_n11_n27#" 1.628
cap "reg_6/reg_one_0/a_4_n13#" "reg_5/port70" 87.672
cap "reg_6/reg_one_0/a_16_27#" "reg_6/in7" 8.022
cap "wz_addrH7" "reg_6/reg_one_0/a_4_n13#" 17.113
cap "ry7" "reg_5/port71" -17.146
cap "reg_6/reg_one_0/w_n11_n27#" "reg_5/port71" 31.032
cap "reg_6/reg_one_0/r1" "reg_6/reg_one_0/Vdd!" 2.27374e-13
cap "reg_5/w" "reg_5/port71" 1.981
cap "reg_6/reg_one_0/a_21_n13#" "reg_5/port70" 3.96
cap "reg_5/port71" "reg_5/reg_one_0/w_n11_n27#" 12.7375
cap "reg_6/in7" "reg_6/reg_one_0/a_33_32#" 2.844
cap "reg_6/reg_one_0/tmp" "reg_5/port70" 5.92
cap "wz_addrH7" "reg_6/reg_one_0/tmp" 4.948
cap "reg_6/reg_one_0/r0" "reg_5/port70" 26.208
cap "wz_addrH7" "reg_6/reg_one_0/r0" 24.728
cap "reg_6/in7" "reg_6/reg_one_0/w" 2.844
cap "reg_6/reg_one_0/port1" "reg_5/port70" 5.5
cap "reg_6/reg_one_0/r0" "ry7" 48.664
cap "reg_6/reg_one_0/r0" "reg_6/reg_one_0/w_n11_n27#" 1.13687e-13
cap "reg_6/in7" "reg_6/reg_one_0/tmp" 4.461
cap "reg_6/reg_one_0/port1" "ry7" 68.579
cap "reg_6/reg_one_0/r0" "reg_6/in7" 128.02
cap "reg_5/reg_one_0/w_n11_n27#" "ry7" -2.667
cap "reg_6/reg_one_0/w_n11_n27#" "reg_5/port70" 151.215
cap "wz_addrH7" "reg_6/reg_one_0/w_n11_n27#" 58.7
cap "reg_6/reg_one_0/w" "reg_6/in7" 2.22
cap "reg_6/reg_one_0/w_n11_n27#" "ry7" 101.233
cap "reg_6/reg_one_0/w_n11_n27#" "reg_6/in7" 182.433
cap "reg_5/w" "reg_5/port70" 67.0625
cap "wz_addrH7" "reg_5/w" 58.7
cap "wz_addrH7" "reg_6/reg_one_0/a_54_5#" 4.828
cap "reg_6/reg_one_0/Vdd!" "reg_5/port70" 58.7
cap "wz_addrH7" "reg_5/reg_one_0/Vdd!" -2.417
cap "wz_addrH7" "reg_6/reg_one_0/Vdd!" 160.588
cap "reg_5/w" "ry7" 58.7
cap "reg_6/in7" "reg_5/reg_one_0/a_33_32#" -12.339
cap "reg_5/reg_one_0/w_n11_n27#" "reg_5/port70" 127.375
cap "wz_addrH7" "reg_5/reg_one_0/w_n11_n27#" 8.24
cap "reg_6/reg_one_0/Vdd!" "ry7" 58.7
cap "reg_6/in7" "reg_5/w" 58.7
cap "reg_6/reg_one_0/Vdd!" "reg_6/in7" 58.7
cap "reg_6/reg_one_0/r1" "reg_5/port70" 64.504
cap "reg_6/reg_one_0/r1" "wz_addrH7" 58.7
cap "reg_5/reg_one_0/w_n11_n27#" "reg_6/in7" -2.417
cap "reg_6/in7" "reg_5/reg_one_0/w_n11_n27#" -8.24
cap "reg_6/reg_one_0/r1" "ry7" 64.004
cap "reg_6/reg_one_0/r1" "reg_6/in7" 58.7
cap "reg_5/reg_one_0/w_n11_n27#" "reg_5/port71" 1.628
subcap "m1_2209_542#" -380.236
cap "mux_8bit_2/in0_7" "reg_6/reg_one_0/Vdd!" -0.393
cap "reg_6/reg_one_0/w" "mux_8bit_2/in0_7" 58.7
cap "reg_6/port70" "mux_8bit_2/in0_7" 3.171
cap "reg_6/reg_one_0/w_n11_n27#" "mux_8bit_2/in1_7" 48.9529
cap "mux_8bit_2/mux_one_7/GND!" "reg_6/port71" 69.613
cap "mux_8bit_2/out7" "reg_6/port71" -10.01
cap "reg_6/reg_one_0/w_n11_n27#" "reg_6/port71" 4.295
cap "mux_8bit_2/out7" "mux_8bit_2/mux_one_7/GND!" 37.928
cap "reg_6/reg_one_0/a_4_n13#" "mux_8bit_2/in0_7" -1.152
cap "reg_6/reg_one_0/w" "reg_6/port71" 127.744
cap "mux_8bit_2/mux_one_7/Vdd!" "mux_8bit_2/in1_7" 2.035
cap "mux_8bit_2/mux_one_7/GND!" "mux_8bit_2/in1_7" 2.035
cap "reg_6/reg_one_0/w" "mux_8bit_2/in1_7" 97.0214
cap "reg_6/reg_one_0/w" "reg_6/reg_one_0/Vdd!" 3.55271e-15
cap "reg_6/port70" "reg_6/reg_one_0/Vdd!" -7.10543e-15
cap "mux_8bit_2/mux_one_7/inv2_1/a_1_8#" "mux_8bit_2/in0_7" 17.59
cap "rx_addrH7" "mux_8bit_2/in0_7" 16.569
cap "rx_addrH7" "reg_6/reg_one_0/w_n11_n27#" 19.776
cap "reg_6/reg_one_0/a_4_n13#" "reg_6/reg_one_0/Vdd!" -7.10543e-15
cap "rx_addrH7" "mux_8bit_2/mux_one_7/2mux_nr_0/in0" 30.259
cap "reg_6/reg_one_0/w_n11_n27#" "mux_8bit_2/in0_7" 8.24
cap "rx_addrH7" "mux_8bit_2/mux_one_7/Vdd!" 27.291
cap "rx_addrH7" "reg_6/reg_one_0/w_n11_n27#" -2.286
cap "reg_6/reg_one_0/w_n11_n27#" "mux_8bit_2/in1_7" -1.886
cap "rx_addrH7" "mux_8bit_2/out7" 24.305
cap "rx_addrH7" "mux_8bit_2/mux_one_7/GND!" 23.285
cap "mux_8bit_2/in1_7" "reg_6/reg_one_0/tmp" -4.818
cap "mux_8bit_2/mux_one_7/2mux_nr_0/in0" "mux_8bit_2/in0_7" 34.083
cap "rx_addrH7" "reg_6/reg_one_0/w" 58.7
cap "rx_addrH7" "reg_6/port70" 4.411
cap "reg_6/reg_one_0/a_33_32#" "mux_8bit_2/in1_7" 5.115
cap "reg_6/reg_one_0/a_33_32#" "reg_6/reg_one_0/Vdd!" -7.10543e-15
cap "mux_8bit_2/mux_one_7/GND!" "mux_8bit_2/in0_7" 18.437
cap "mux_8bit_2/mux_one_7/Vdd!" "mux_8bit_2/in0_7" 94.154
cap "reg_6/reg_one_0/w_n11_n27#" "ry_addrH7" 2.174
cap "reg_6/reg_one_0/w_n11_n27#" "reg_6/port71" 12.7375
cap "rx_addrH7" "reg_6/reg_one_0/a_4_n13#" -10.448
cap "wz_addrH7" "reg_7/port70" 6.6
cap "wz_addrH7" "reg_7/reg_one_0/r0" 24.728
cap "reg_7/reg_one_0/Vdd!" "mux_8bit_2/out7" 56.544
cap "ry7" "reg_7/reg_one_0/r0" 48.664
cap "mux_8bit_2/mux_one_7/GND!" "mux_8bit_2/out7" 462.156
cap "rx_addrH7" "reg_7/reg_one_0/r1" 64.504
cap "reg_7/reg_one_0/a_21_n13#" "rx_addrH7" 3.96
cap "rx_addrH7" "mux_8bit_2/out7" -3.85
cap "wz_addrH7" "reg_7/reg_one_0/a_54_5#" 4.828
cap "mux_8bit_2/mux_one_7/GND!" "mux_8bit_2/mux_one_7/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "rx_addrH7" "reg_7/reg_one_0/w_n11_n27#" 163.513
cap "reg_7/reg_one_0/Vdd!" "rx_addrH7" 58.7
cap "rx_addrH7" "mux_8bit_2/mux_one_7/GND!" 20.233
cap "wz_addrH7" "reg_7/reg_one_0/r1" 58.7
cap "wz_addrH7" "mux_8bit_2/out7" -3.85
cap "ry7" "reg_7/reg_one_0/r1" 64.004
cap "reg_7/port71" "reg_7/reg_one_0/w_n11_n27#" 1.628
cap "ry7" "mux_8bit_2/out7" -12.177
cap "wz_addrH7" "reg_7/reg_one_0/w_n11_n27#" 58.7
cap "reg_7/port71" "rx_addrH7" 5.5
cap "wz_addrH7" "mux_8bit_2/mux_one_7/GND!" 17.872
cap "reg_7/reg_one_0/Vdd!" "wz_addrH7" 162.612
cap "ry7" "reg_7/reg_one_0/w_n11_n27#" 106.567
cap "ry7" "mux_8bit_2/mux_one_7/GND!" -1.312
cap "reg_7/reg_one_0/Vdd!" "ry7" 58.7
cap "reg_7/reg_one_0/a_4_n13#" "rx_addrH7" 93.704
cap "mux_8bit_2/out7" "mux_8bit_2/mux_one_7/2mux_nr_0/out" 85.4219
cap "ry7" "reg_7/port71" 73.199
cap "wz_addrH7" "reg_7/reg_one_0/a_4_n13#" 27.497
cap "reg_7/reg_one_0/tmp" "rx_addrH7" 5.92
cap "mux_8bit_2/out7" "reg_7/reg_one_0/r0" 314.001
cap "rx_addrH7" "reg_7/port70" 6.006
cap "wz_addrH7" "reg_7/reg_one_0/tmp" 4.948
cap "reg_7/reg_one_0/w_n11_n27#" "ry_addrH7" 34.049
cap "reg_7/reg_one_0/Vdd!" "reg_7/reg_one_0/r0" -9.768
cap "mux_8bit_2/mux_one_7/GND!" "reg_7/reg_one_0/r0" 63.6875
cap "reg_7/reg_one_0/w" "reg_7/port71" 5.072
cap "rx_addrH7" "reg_7/reg_one_0/r0" 26.208
subcap "a_2351_569#" -49.894
cap "reg_7/reg_one_0/Vdd!" "wz_addrH7" -2.417
cap "wz_addrH7" "reg_7/reg_one_0/w_n11_n27#" 8.24
cap "addsub_2/addsub_one_7/Vdd!" "wz_addrH7" 5.06
cap "reg_7/port70" "reg_7/reg_one_0/w_n11_n27#" -3.048
cap "reg_7/reg_one_0/w_n11_n27#" "reg_7/port71" 12.7375
cap "addsub_2/xor_7/a_61_n1#" "reg_7/port70" 106.684
cap "ry7" "addsub_2/addsub_one_7/Vdd!" 2.655
cap "addsub_2/b7" "reg_7/port70" 2.424
cap "reg_7/port70" "addsub_2/xor_7/b" 2.424
cap "wz_addrH7" "reg_7/reg_one_0/w" 58.7
cap "ry7" "reg_7/port71" -17.146
cap "reg_7/reg_one_0/w" "reg_7/port71" 1.981
cap "reg_7/port71" "reg_7/reg_one_0/w_n11_n27#" 0.785
cap "ry7" "reg_7/reg_one_0/w" 58.7
cap "ry7" "reg_7/reg_one_0/w_n11_n27#" -2.667
cap "addsub_2/xor_7/a_89_n31#" "reg_7/port70" 2.424
cap "addsub_2/b7" "wz_addrH7" 0.624
cap "addsub_2/b7" "addsub_2/xor_7/a_61_n31#" -9.50351e-14
cap "reg_7/port70" "reg_7/reg_one_0/w_n11_n27#" 135.615
cap "reg_7/port70" "addsub_2/addsub_one_7/Vdd!" 27.048
cap "addsub_2/addsub_one_7/b" "reg_7/port70" 36.877
cap "reg_7/port70" "addsub_2/xor_7/a_61_n31#" 2.424
cap "reg_7/port70" "reg_7/reg_one_0/w" 125.763
subcap "a_2516_569#" -30.357
cap "addsub_2/addsub_one_7/GND!" "addsub_2/addsub_one_7/a_35_n41#" -1.13687e-13
cap "latch_6/latch_one_7/Vdd!" "addsub_2/s7" -12.402
cap "wz_addrH7" "addsub_2/addsub_one_7/a_35_n41#" 19.78
cap "ry7" "addsub_2/addsub_one_7/GND!" 27.612
cap "latch_6/latch_one_7/a_n5_n54#" "addsub_2/s7" 19.2392
cap "wz_addrH7" "addsub_2/addsub_one_7/GND!" 34.459
cap "ry7" "addsub_2/addsub_one_7/Vdd!" 13.563
cap "wz_addrH7" "addsub_2/addsub_one_7/GND!" 4.95
cap "wz_addrH7" "addsub_2/addsub_one_7/Vdd!" 27.16
cap "wz_addrH7" "addsub_2/s7" 50.994
cap "ry7" "addsub_2/cout" 11.825
subcap "a_2516_569#" -107.014
cap "staticizer_3/staticizer_one_7/a_60_n45#" "staticizer_3/staticizer_one_7/out" 75.3524
cap "latch_6/latch_one_7/Vdd!" "latch_6/out7" 107.428
cap "latch_6/latch_one_7/a_30_n35#" "staticizer_3/staticizer_one_7/out" 1.88
cap "latch_6/latch_one_7/Vdd!" "ry7" 91.535
cap "latch_6/latch_one_7/Vdd!" "addsub_2/s7" 19.399
cap "staticizer_3/staticizer_one_7/c" "staticizer_3/staticizer_one_7/out" 61.544
cap "latch_6/latch_one_7/a_12_n54#" "staticizer_3/staticizer_one_7/out" 9.708
cap "latch_6/latch_one_7/c" "latch_6/latch_one_7/GND!" 13.8522
cap "latch_6/latch_one_7/a_n5_n54#" "addsub_2/s7" 57.7175
cap "latch_6/latch_one_7/Vdd!" "staticizer_3/staticizer_one_7/out" 169.606
cap "latch_6/out7" "latch_6/latch_one_7/GND!" 10.156
cap "ry7" "latch_6/latch_one_7/GND!" 158.184
cap "latch_6/latch_one_7/c" "latch_6/out7" 9.252
cap "latch_6/latch_one_7/Vdd!" "latch_6/latch_one_7/a_12_n54#" 1.13687e-13
cap "ry7" "latch_6/latch_one_7/c" 81.003
cap "latch_6/latch_one_7/a_n5_n54#" "staticizer_3/staticizer_one_7/out" 59.464
cap "staticizer_3/staticizer_one_7/a_77_n45#" "staticizer_3/staticizer_one_7/out" 5.115
cap "staticizer_3/staticizer_one_7/out" "latch_6/latch_one_7/GND!" 117.4
cap "latch_6/latch_one_7/c" "staticizer_3/staticizer_one_7/out" 61.66
cap "staticizer_3/staticizer_one_7/c" "latch_6/latch_one_7/GND!" 5.68434e-14
cap "staticizer_3/staticizer_one_7/a_60_n45#" "latch_6/out7" 150.065
cap "latch_6/out7" "staticizer_3/staticizer_one_7/out" 7.047
cap "latch_6/latch_one_7/Vdd!" "latch_6/latch_one_7/GND!" -1.13687e-13
cap "staticizer_3/staticizer_one_7/out" "addsub_2/s7" 3.932
cap "staticizer_3/staticizer_one_7/c" "ry7" 65.01
cap "latch_6/latch_one_7/Vdd!" "latch_6/latch_one_7/c" 963.124
subcap "addr_out7" -56.838
cap "staticizer_4/staticizer_one_7/a_60_n45#" "latch_7/latch_one_7/GND!" 5.68434e-14
cap "latch_7/in7" "staticizer_3/w_90_n1211#" 17.972
cap "latch_7/latch_one_7/a_n5_n54#" "latch_7/latch_one_7/Vdd!" -1.13687e-13
cap "staticizer_3/staticizer_one_7/a_77_n45#" "staticizer_3/staticizer_one_7/Vdd!" 2.84217e-14
cap "latch_7/out7" "staticizer_4/staticizer_one_7/a_60_n45#" 150.065
cap "staticizer_3/w_90_n1211#" "staticizer_3/staticizer_one_7/out" 8.272
cap "latch_7/latch_one_7/Vdd!" "latch_7/latch_one_7/GND!" -0.738
cap "latch_7/in7" "staticizer_3/staticizer_one_7/out" 23.087
cap "latch_7/out7" "latch_7/latch_one_7/GND!" 10.156
cap "latch_7/latch_one_7/c" "latch_7/latch_one_7/GND!" 13.8522
cap "latch_7/out7" "latch_7/latch_one_7/Vdd!" 107.428
cap "latch_7/latch_one_7/a_n5_n54#" "latch_7/in7" 57.7175
cap "latch_7/latch_one_7/c" "latch_7/latch_one_7/Vdd!" 963.124
cap "latch_7/in7" "staticizer_3/staticizer_one_7/Vdd!" 11.463
cap "latch_7/latch_one_7/c" "latch_7/out7" 9.252
cap "latch_7/in7" "latch_7/latch_one_7/GND!" 6.956
cap "staticizer_3/staticizer_one_7/out" "staticizer_3/staticizer_one_7/Vdd!" 6.001
cap "latch_7/in7" "latch_7/latch_one_7/Vdd!" 268.902
cap "staticizer_3/staticizer_one_7/a_60_n45#" "staticizer_3/staticizer_one_7/out" 0.709429
cap "latch_7/latch_one_7/a_12_n54#" "latch_7/latch_one_7/Vdd!" 1.13687e-13
cap "staticizer_3/staticizer_one_7/c" "staticizer_3/w_90_n1211#" -1.42109e-14
cap "staticizer_3/staticizer_one_7/a_77_n45#" "staticizer_3/staticizer_one_7/out" 2.728
subcap "ry_addrH7" -832.199
subcap "addr_out15" -305.874
cap "latch_8/latch_one_7/Vdd!" "latch_8/latch_one_7/a_12_n54#" 1.13687e-13
cap "staticizer_4/staticizer_one_7/a_77_n45#" "staticizer_4/staticizer_one_7/Vdd!" 1.13687e-13
cap "staticizer_5/in7" "latch_8/latch_one_7/Vdd!" -1.162
cap "staticizer_5/in7" "latch_8/latch_one_7/c" -0.42
cap "latch_8/in7" "staticizer_4/staticizer_one_7/Vdd!" 11.463
cap "latch_8/in7" "staticizer_4/staticizer_one_7/out" 57.7175
cap "latch_8/latch_one_7/a_n5_n54#" "latch_8/latch_one_7/Vdd!" -1.13687e-13
cap "latch_8/in7" "latch_8/latch_one_7/a_n5_n54#" 57.7175
cap "latch_8/in7" "staticizer_4/w_90_n1211#" 14.505
cap "latch_8/in7" "latch_8/latch_one_7/Vdd!" 268.902
cap "staticizer_4/staticizer_one_7/out" "staticizer_4/staticizer_one_7/Vdd!" -5.68434e-14
cap "staticizer_4/w_90_n1211#" "staticizer_4/staticizer_one_7/a_60_n45#" 2.84217e-14
cap "latch_8/in7" "staticizer_5/staticizer_one_7/w_54_n57#" 6.956
subcap "addr_out15" -36.486
cap "staticizer_5/in7" "staticizer_5/staticizer_one_7/w_54_n57#" 10.156
cap "latch_8/latch_one_7/Vdd!" "staticizer_5/in7" 107.428
cap "staticizer_5/in7" "staticizer_5/staticizer_one_7/a_60_n45#" 150.065
cap "staticizer_5/staticizer_one_7/w_54_n57#" "latch_8/latch_one_7/c" 13.8522
cap "latch_8/latch_one_7/Vdd!" "latch_8/latch_one_7/c" 963.124
cap "staticizer_5/in7" "latch_8/latch_one_7/c" 9.252
cap "latch_4/latch_one_6/c" "staticizer_1/Vdd!" 1073
cap "staticizer_1/staticizer_one_6/w_54_n57#" "latch_4/latch_one_6/c" 18.4696
cap "staticizer_1/staticizer_one_6/w_54_n57#" "staticizer_1/Vdd!" -3.55271e-15
cap "staticizer_0/Vdd!" "rx6" 37.42
cap "staticizer_0/Vdd!" "latch_0/latch_one_6/GND!" -0.246
cap "latch_0/latch_one_6/c" "rx6" 58.7
cap "latch_0/latch_one_6/c" "latch_0/latch_one_6/GND!" 18.4696
cap "staticizer_0/Vdd!" "latch_0/latch_one_6/c" 1073
cap "rx6" "latch_4/Vdd!" 241.425
cap "latch_0/Vdd!" "rx6" 58.7
cap "rx6" "latch_0/latch_one_6/GND!" 59.993
cap "staticizer_0/staticizer_one_6/w_54_n57#" "staticizer_0/Vdd!" -0.984
cap "staticizer_0/staticizer_one_6/c" "shift_0/a6" 76.935
cap "staticizer_0/staticizer_one_6/w_54_n57#" "staticizer_0/staticizer_one_6/c" -2.27374e-13
cap "staticizer_0/staticizer_one_6/w_54_n57#" "shift_0/a6" 73.425
cap "staticizer_0/Vdd!" "shift_0/a6" -12.11
cap "shift_0/a7" "shift_0/a6" 125.762
cap "shift_0/u" "rx6" 58.7
cap "rx6" "shift_0/shift_one_6/Vdd!" 7.239
cap "shift_0/GND!" "rx6" 58.7
cap "shift_0/Vdd!" "rx6" 58.7
cap "shift_0/shift_one_6/inv_2/in" "rx6" 14.74
cap "shift_0/shift_one_6/inv_2/GND!" "rx6" 11.43
subcap "a_373_740#" -110.995
cap "latch_3/Vdd!" "rx6" 58.7
cap "shift_0/shift_one_6/inv_3/Vdd!" "shift_0/o6" 1.162
cap "latch_3/latch_one_6/GND!" "shift_0/o6" 23.087
cap "shift_0/shift_one_6/inv_3/Vdd!" "rx6" 7.239
cap "latch_3/latch_one_6/GND!" "rx6" 107.383
cap "shift_0/shift_one_7/s" "rx6" 58.7
cap "rx6" "latch_3/latch_one_6/c" 3.12
cap "rx6" "shift_0/shift_one_6/inv_2/GND!" 6.096
cap "rx6" "shift_0/o6" 20.945
cap "fblock_0/fblock_one_6/inv_0/in" "fblock_0/fblock_one_6/inv_0/GND!" 5.68434e-14
cap "rx6" "latch_3/latch_one_6/GND!" 0.083
cap "rx6" "latch_3/latch_one_6/c" 78.258
cap "latch_3/latch_one_6/GND!" "latch_3/latch_one_6/c" 2.84217e-14
cap "latch_3/out6" "fblock_0/fblock_one_6/inv_0/GND!" 2.475
cap "fblock_0/fblock_one_7/g3" "rx6" 241.425
cap "fblock_0/fblock_one_6/inv_0/in" "latch_3/out6" 1.485
subcap "a_580_739#" -325.426
cap "fblock_0/fblock_one_7/inv_3/Vdd!" "latch_1/Vdd!" 362.137
cap "latch_1/latch_one_6/GND!" "wz6" 1.485
cap "wz6" "fblock_0/fblock_one_6/inv_0/GND!" 2.475
cap "latch_1/out6" "latch_1/latch_one_6/GND!" 0.99
cap "addsub_0/xor_7/a_61_n1#" "addsub_0/a7" 32.447
cap "addsub_0/addsub_one_7/a_66_n41#" "as_cout" 2.1
cap "as_cout" "addsub_0/c7" 14.329
cap "wz6" "addsub_0/addsub_one_6/a_35_n41#" 18.72
cap "as_cout" "addsub_0/addsub_one_7/GND!" 67.072
cap "as_cout" "addsub_0/addsub_one_7/a_35_n41#" 10.65
cap "ry6" "addsub_0/c7" 10.71
cap "ry6" "addsub_0/addsub_one_7/Vdd!" 11.825
cap "addsub_0/addsub_one_7/Vdd!" "addsub_0/a7" 18.922
cap "ry6" "addsub_0/addsub_one_7/GND!" 24.288
cap "as_cout" "addsub_0/a7" 12.612
cap "addsub_0/addsub_one_7/a_11_n41#" "as_cout" 21.93
cap "addsub_0/addsub_one_7/a_72_n41#" "as_cout" 0.525
cap "addsub_0/addsub_one_7/b" "as_cout" 12.612
cap "as_cout" "addsub_0/addsub_one_6/a_35_n41#" 3.332
cap "as_cout" "addsub_0/addsub_one_7/a_29_n41#" 2.1
cap "addsub_0/addsub_one_7/GND!" "addsub_0/addsub_one_7/a_35_n41#" -5.68434e-14
cap "addsub_0/addsub_one_6/Vdd!" "ry6" 16.992
cap "as_cout" "addsub_0/addsub_one_7/cin" 4.204
cap "addsub_0/addsub_one_7/Vdd!" "addsub_0/a7" 76.9567
cap "addsub_0/addsub_one_6/a_35_n41#" "latch_2/out6" 0.312
cap "reg_0/reg_one_1/r0" "ry6" 17.308
cap "latch_2/latch_one_6/GND!" "ry6" 110.895
cap "latch_2/latch_one_6/c" "ry6" 81.378
cap "latch_2/Vdd!" "ry6" 58.7
cap "addsub_0/c7" "ry6" 1.486
cap "latch_2/latch_one_6/GND!" "latch_2/out6" 4.95
cap "ry6" "addsub_0/GND!" 20.633
cap "reg_0/reg_one_1/r1" "reg_0/port61" 5.304
cap "reg_0/reg_one_1/w_n11_n27#" "reg_0/port60" 12.7375
cap "reg_0/r1" "reg_0/port61" 58.7
cap "reg_0/reg_one_1/w_n11_n27#" "reg_0/port61" 121.694
cap "reg_0/reg_one_1/r0" "reg_0/port61" 23.94
cap "reg_0/Vdd!" "reg_0/port61" 58.7
cap "reg_0/reg_one_1/r0" "reg_0/reg_one_1/w_n11_n27#" -1.13687e-13
cap "reg_0/port61" "reg_0/reg_one_0/w" 127.744
cap "reg_1/reg_one_1/w_n11_n27#" "reg_1/port61" 121.694
cap "reg_1/reg_one_1/r1" "reg_1/port61" 5.304
cap "reg_1/r1" "reg_1/port61" 58.7
cap "reg_1/reg_one_1/r0" "reg_1/port61" 48.664
cap "reg_1/reg_one_0/w" "reg_1/port61" 127.744
cap "reg_1/port60" "reg_1/reg_one_1/w_n11_n27#" 12.7375
cap "reg_1/Vdd!" "reg_1/port61" 58.7
cap "reg_2/port61" "reg_2/reg_one_1/r0" 48.664
cap "reg_2/port61" "reg_2/r1" 58.7
cap "reg_2/port61" "reg_2/reg_one_1/w_n11_n27#" 121.694
cap "reg_2/port61" "reg_2/reg_one_0/w" 94.2122
cap "reg_2/port61" "reg_2/reg_one_1/r1" 5.304
cap "reg_2/port61" "reg_2/Vdd!" 58.7
cap "reg_1/port60" "reg_2/reg_one_1/w_n11_n27#" 6.36875
cap "reg_3/Vdd!" "reg_2/port61" 58.7
cap "reg_3/port61" "reg_2/port61" 73.199
cap "reg_3/port61" "reg_3/reg_one_0/w" 5.072
cap "reg_2/reg_one_1/w_n11_n27#" "reg_2/port60" 6.36875
cap "reg_3/port61" "reg_3/reg_one_1/w_n11_n27#" 1.628
cap "reg_3/reg_one_1/w_n11_n27#" "reg_2/port61" 106.567
cap "reg_3/r1" "reg_2/port61" 58.7
cap "reg_3/reg_one_1/r1" "reg_2/port61" 5.304
cap "reg_2/reg_one_0/w" "reg_2/port61" 33.5312
cap "reg_3/reg_one_1/r0" "reg_2/port61" 48.664
subcap "wz_addrL6" -637.467
subcap "PCL_w_muxout6" -415.526
cap "mux_8bit_0/out6" "mux_8bit_0/mux_one_6/inv2_2/GND!" 37.928
cap "reg_3/port61" "mux_8bit_0/mux_one_7/2mux_nr_0/Vdd!" 58.7
cap "reg_3/reg_one_1/w_n11_n27#" "reg_3/port60" 12.7375
cap "mux_8bit_0/out6" "reg_3/port61" -10.01
cap "reg_3/port61" "mux_8bit_0/mux_one_6/inv2_2/GND!" 63.013
cap "reg_3/reg_one_1/w_n11_n27#" "reg_3/port61" -1.039
cap "reg_3/reg_one_0/w" "reg_3/reg_one_0/w_n11_n27#" -1.42109e-14
cap "reg_3/reg_one_0/w" "reg_3/port61" 127.744
cap "mux_8bit_0/mux_one_7/sel" "mux_8bit_0/out6" 0.84
cap "reg_3/reg_one_1/w_n11_n27#" "reg_3/port61" 12.7375
cap "mux_8bit_0/mux_one_7/sel" "reg_3/port61" 58.7
cap "reg_4/reg_one_1/r0" "ry6" 48.664
cap "reg_4/Vdd!" "ry6" 58.7
cap "mux_8bit_0/out6" "mux_8bit_0/mux_one_6/inv2_1/GND!" 161.835
cap "reg_4/r1" "ry6" 58.7
cap "reg_4/port61" "reg_4/reg_one_0/w" 5.072
cap "mux_8bit_0/mux_one_7/GND!" "reg_4/reg_one_1/r0" 101.9
cap "mux_8bit_0/mux_one_6/inv2_1/GND!" "ry6" -6.916
cap "mux_8bit_0/out6" "ry6" -17.369
cap "reg_4/port61" "ry6" 73.199
cap "mux_8bit_0/mux_one_7/GND!" "mux_8bit_0/out6" 15.66
cap "reg_4/reg_one_1/r1" "ry6" 5.304
cap "reg_4/port61" "reg_4/reg_one_1/w_n11_n27#" 1.628
cap "ry6" "reg_4/reg_one_1/w_n11_n27#" 106.567
cap "mux_8bit_0/out6" "reg_4/reg_one_1/r0" 123.751
cap "reg_4/r1" "reg_4/reg_one_0/w_n11_n27#" 1.77636e-15
cap "mux_8bit_0/mux_one_7/GND!" "ry6" 58.7
subcap "rx_PCL7" -162.355
cap "reg_4/port61" "addsub_1/sub" 11.825
cap "reg_4/port61" "reg_4/reg_one_1/w_n11_n27#" 12.7375
cap "addsub_1/a7" "addsub_1/xor_7/a_61_n1#" 70.9253
cap "reg_4/port61" "addsub_1/xor_7/GND!" 11.825
cap "addsub_1/a7" "addsub_1/Vdd!" 76.9567
cap "reg_4/port61" "reg_4/reg_one_1/w_n11_n27#" -1.039
cap "addsub_1/sub" "reg_4/port60" 26.4723
cap "reg_4/reg_one_1/w_n11_n27#" "reg_4/port60" 12.7375
cap "reg_4/reg_one_0/w" "reg_4/port61" 127.744
cap "addsub_1/xor_7/GND!" "reg_4/port60" 11.081
cap "addsub_1/Vdd!" "reg_4/port61" 11.825
cap "addsub_1/a7" "addsub_1/addsub_one_7/Vdd!" 23.511
cap "addsub_1/addsub_one_6/a_35_n41#" "a_2510_1893#" 3.332
cap "ry6" "addsub_1/addsub_one_7/Vdd!" -4.455
cap "addsub_1/addsub_one_7/a_29_n41#" "a_2510_1893#" 2.1
cap "addsub_1/addsub_one_7/a_11_n41#" "a_2510_1893#" 21.93
cap "addsub_1/a7" "a_2510_1893#" 12.612
cap "addsub_1/addsub_one_7/a_72_n41#" "a_2510_1893#" 0.525
cap "addsub_1/addsub_one_7/a_66_n41#" "a_2510_1893#" 2.1
cap "ry6" "addsub_1/c7" 17.812
cap "a_2510_1893#" "addsub_1/addsub_one_7/a_35_n41#" 10.65
cap "ry6" "addsub_1/addsub_one_6/Vdd!" 13.563
cap "addsub_1/c7" "a_2510_1893#" 18.533
cap "ry6" "addsub_1/GND!" 48.35
cap "addsub_1/GND!" "a_2510_1893#" 67.072
cap "addsub_1/addsub_one_7/b" "a_2510_1893#" 12.612
cap "latch_5/latch_one_6/GND!" "latch_5/latch_one_6/c" 13.8522
cap "staticizer_2/Vdd!" "ry6" 58.7
cap "latch_5/latch_one_6/GND!" "ry6" 181.284
cap "latch_5/Vdd!" "ry6" 58.7
cap "latch_5/latch_one_6/c" "staticizer_2/Vdd!" 1073
cap "staticizer_2/staticizer_one_6/c" "ry6" 76.935
cap "latch_5/latch_one_6/c" "ry6" 81.378
subcap "wz_addrH6" -996.074
subcap "m1_1909_718#" -415.526
cap "ry6" "mux_8bit_1/out6" -10.01
cap "ry6" "staticizer_2/staticizer_one_6/w_54_n57#" 4.329
cap "mux_8bit_1/out6" "mux_8bit_1/mux_one_6/inv2_2/GND!" 37.928
cap "ry6" "mux_8bit_1/mux_one_7/sel" 58.7
cap "mux_8bit_1/out6" "mux_8bit_1/mux_one_7/sel" 0.84
cap "staticizer_2/staticizer_one_6/c" "staticizer_2/staticizer_one_6/w_54_n57#" 7.10543e-15
cap "ry6" "mux_8bit_1/mux_one_7/2mux_nr_0/Vdd!" 58.7
cap "ry6" "mux_8bit_1/mux_one_6/inv2_2/GND!" 63.013
cap "mux_8bit_1/mux_one_7/GND!" "ry6" 58.7
cap "mux_8bit_1/out6" "mux_8bit_1/mux_one_6/inv2_1/GND!" 161.835
cap "ry6" "mux_8bit_1/mux_one_6/inv2_1/GND!" -6.916
cap "ry6" "reg_5/port61" 73.199
cap "ry6" "reg_5/reg_one_1/w_n11_n27#" 106.567
cap "ry6" "reg_5/Vdd!" 58.7
cap "reg_5/r1" "ry6" 58.7
cap "reg_5/reg_one_1/w_n11_n27#" "reg_5/port61" 1.628
cap "mux_8bit_1/out6" "reg_5/reg_one_1/r0" 123.751
cap "ry6" "reg_5/reg_one_1/r1" 5.304
cap "reg_5/r1" "reg_5/reg_one_0/w_n11_n27#" 1.77636e-15
cap "ry6" "reg_5/reg_one_1/r0" 48.664
cap "mux_8bit_1/mux_one_7/GND!" "reg_5/reg_one_1/r0" 101.9
cap "reg_5/reg_one_0/w" "reg_5/port61" 5.072
cap "mux_8bit_1/out6" "ry6" -17.369
cap "mux_8bit_1/mux_one_7/GND!" "mux_8bit_1/out6" 15.66
cap "reg_5/port60" "reg_6/reg_one_1/r0" 13.276
cap "reg_5/port61" "reg_5/reg_one_0/w" 69.0435
cap "reg_6/Vdd!" "ry6" 58.7
cap "reg_5/port60" "reg_6/reg_one_1/w_n11_n27#" 128.332
cap "reg_5/port60" "reg_6/reg_one_1/a_4_n13#" 1.371
cap "reg_5/port60" "reg_6/r1" 18.895
cap "reg_5/port60" "reg_6/reg_one_1/r1" 2.104
cap "reg_6/reg_one_1/r0" "ry6" 48.664
cap "reg_6/Vdd!" "reg_5/port61" 58.7
cap "reg_5/port60" "reg_6/reg_one_1/tmp" 1.48
cap "reg_5/port61" "reg_6/reg_one_1/r0" 19.78
cap "reg_6/reg_one_1/w_n11_n27#" "ry6" 101.233
cap "ry6" "reg_6/r1" 58.7
cap "ry6" "reg_6/reg_one_1/r1" 5.304
cap "reg_5/reg_one_0/w_n11_n27#" "reg_5/reg_one_0/w" -1.42109e-14
cap "reg_5/port61" "ry6" -17.146
cap "reg_6/reg_one_1/w_n11_n27#" "reg_5/port61" 83.267
cap "reg_5/port61" "reg_6/r1" 58.7
cap "reg_5/port60" "reg_6/reg_one_1/port1" 1.375
cap "reg_5/reg_one_1/w_n11_n27#" "ry6" -2.667
cap "reg_5/port60" "reg_5/reg_one_1/w_n11_n27#" 12.7375
cap "reg_5/port61" "reg_5/reg_one_1/w_n11_n27#" 1.628
cap "ry6" "reg_6/reg_one_1/port1" 68.579
cap "reg_5/port60" "reg_6/Vdd!" 18.895
cap "reg_5/port61" "reg_5/reg_one_1/w_n11_n27#" 12.7375
cap "reg_5/port60" "reg_6/reg_one_1/a_21_n13#" 0.99
cap "ry6" "reg_5/reg_one_0/w" 58.7
subcap "m1_2132_731#" -30.166
subcap "m1_2209_718#" -415.526
cap "reg_6/port60" "rx_addrH6" 1.111
cap "mux_8bit_2/out6" "reg_6/port61" -10.01
cap "mux_8bit_2/out6" "rx_addrH6" 2.838
cap "mux_8bit_2/mux_one_7/sel" "ry_addrH6" 58.7
cap "ry_addrH6" "reg_6/reg_one_0/w" 58.7
cap "reg_6/port61" "reg_6/reg_one_0/w" 127.744
cap "reg_6/port61" "mux_8bit_2/mux_one_7/sel" 58.7
cap "rx_addrH6" "mux_8bit_2/mux_one_7/sel" 30.82
cap "rx_addrH6" "reg_6/reg_one_0/w" 30.82
cap "mux_8bit_2/out6" "mux_8bit_2/mux_one_6/inv2_2/GND!" 37.928
cap "mux_8bit_2/in0_6" "rx_addrH6" 1.364
cap "mux_8bit_2/mux_one_7/2mux_nr_0/Vdd!" "ry_addrH6" 58.7
cap "mux_8bit_2/mux_one_7/2mux_nr_0/Vdd!" "reg_6/port61" 58.7
cap "reg_6/reg_one_1/w_n11_n27#" "reg_6/port61" 12.7375
cap "rx_addrH6" "mux_8bit_2/mux_one_6/inv2_2/a_6_n1#" 4.993
cap "reg_6/reg_one_0/w_n11_n27#" "reg_6/reg_one_0/w" 2.84217e-14
cap "mux_8bit_2/mux_one_7/2mux_nr_0/Vdd!" "rx_addrH6" 30.82
cap "reg_6/reg_one_1/w_n11_n27#" "rx_addrH6" 13.184
cap "reg_6/reg_one_1/w_n11_n27#" "ry_addrH6" 0.019
cap "mux_8bit_2/mux_one_6/inv2_2/GND!" "reg_6/port61" 63.013
cap "reg_6/reg_one_1/w_n11_n27#" "reg_6/port61" 4.295
cap "mux_8bit_2/out6" "mux_8bit_2/mux_one_7/sel" 0.84
cap "mux_8bit_2/mux_one_6/inv2_2/GND!" "rx_addrH6" 31.677
cap "reg_6/reg_one_1/w_n11_n27#" "rx_addrH6" 1.524
cap "mux_8bit_2/mux_one_6/inv2_2/Vdd!" "rx_addrH6" 20.417
cap "ry6" "reg_7/Vdd!" 58.7
cap "rx_addrH6" "mux_8bit_2/mux_one_7/GND!" 30.82
cap "ry6" "reg_7/port61" 73.199
cap "mux_8bit_2/out6" "mux_8bit_2/mux_one_6/inv2_1/GND!" 161.835
cap "ry6" "reg_7/reg_one_1/r1" 5.304
cap "ry_addrH6" "reg_7/r1" 58.7
cap "reg_7/reg_one_1/a_21_n13#" "rx_addrH6" 0.99
cap "reg_7/reg_one_1/r0" "mux_8bit_2/out6" 123.751
cap "rx_addrH6" "mux_8bit_2/mux_one_6/inv2_1/GND!" 9.45
cap "reg_7/reg_one_1/tmp" "rx_addrH6" 1.48
cap "rx_addrH6" "reg_7/r1" 30.82
cap "reg_7/Vdd!" "ry_addrH6" 58.7
cap "ry_addrH6" "reg_7/reg_one_1/r0" 19.78
cap "ry6" "mux_8bit_2/out6" -17.369
cap "rx_addrH6" "reg_7/port60" 1.034
cap "reg_7/reg_one_1/a_4_n13#" "rx_addrH6" 1.371
cap "rx_addrH6" "reg_7/reg_one_1/r0" 13.276
cap "reg_7/Vdd!" "rx_addrH6" 30.82
cap "ry6" "reg_7/reg_one_1/w_n11_n27#" 106.567
cap "reg_7/reg_one_1/w_n11_n27#" "reg_7/port61" 1.628
cap "reg_7/reg_one_1/r0" "mux_8bit_2/mux_one_7/GND!" 101.9
cap "rx_addrH6" "reg_7/port61" 1.375
cap "reg_7/reg_one_0/w" "reg_7/port61" 5.072
cap "ry6" "mux_8bit_2/mux_one_7/GND!" 58.7
cap "reg_7/r1" "reg_7/reg_one_0/w_n11_n27#" 1.77636e-15
cap "rx_addrH6" "reg_7/reg_one_1/r1" 2.104
cap "ry_addrH6" "reg_7/reg_one_1/w_n11_n27#" 86.284
cap "rx_addrH6" "mux_8bit_2/out6" -4.037
cap "ry6" "mux_8bit_2/mux_one_6/inv2_1/GND!" -6.916
cap "mux_8bit_2/out6" "mux_8bit_2/mux_one_7/GND!" 15.66
cap "ry6" "reg_7/r1" 58.7
cap "rx_addrH6" "reg_7/reg_one_1/w_n11_n27#" 154.46
cap "ry_addrH6" "mux_8bit_2/mux_one_7/GND!" 58.7
cap "ry6" "reg_7/reg_one_1/r0" 48.664
subcap "rx_addrH7" -541.527
cap "addsub_2/Vdd!" "reg_7/port61" 11.825
cap "reg_7/port61" "addsub_2/xor_7/GND!" 11.825
cap "reg_7/reg_one_0/w" "reg_7/port61" 127.744
cap "addsub_2/sub" "reg_7/port61" 11.825
cap "addsub_2/Vdd!" "addsub_2/a7" 76.9567
cap "addsub_2/addsub_one_7/Vdd!" "addsub_2/a7" 23.511
cap "reg_7/port61" "ry6" -17.146
cap "reg_7/reg_one_1/w_n11_n27#" "reg_7/port60" -1.143
cap "reg_7/reg_one_1/w_n11_n27#" "ry6" -2.667
cap "reg_7/reg_one_1/w_n11_n27#" "reg_7/port61" -1.37
cap "reg_7/reg_one_1/w_n11_n27#" "reg_7/port60" 18.5055
cap "reg_7/port60" "addsub_2/xor_7/GND!" 11.081
cap "reg_7/reg_one_0/w" "reg_7/port60" 30.82
cap "addsub_2/Vdd!" "ry6" 11.825
cap "ry6" "addsub_2/xor_7/GND!" 11.825
cap "addsub_2/sub" "reg_7/port60" 26.4723
cap "addsub_2/xor_7/a_61_n1#" "addsub_2/a7" 70.9253
cap "reg_7/reg_one_0/w" "ry6" 58.7
cap "reg_7/reg_one_1/w_n11_n27#" "reg_7/port61" 12.7375
cap "addsub_2/sub" "ry6" 11.825
cap "addsub_2/GND!" "ry6" 52.91
cap "addsub_2/c7" "ry6" 19.952
cap "ry_addrH6" "addsub_2/GND!" 45.221
cap "ry_addrH6" "addsub_2/c7" 2.474
cap "addsub_2/addsub_one_7/Vdd!" "ry6" -4.455
cap "addsub_2/addsub_one_7/Vdd!" "ry_addrH6" -4.455
cap "addsub_2/addsub_one_6/Vdd!" "ry6" 13.563
cap "ry6" "latch_6/Vdd!" 58.7
cap "ry6" "latch_6/latch_one_6/c" 81.378
cap "latch_6/latch_one_6/c" "latch_6/latch_one_6/GND!" 13.8522
cap "ry_addrH6" "latch_6/Vdd!" 58.7
cap "ry_addrH6" "latch_6/latch_one_6/c" 58.7
cap "ry6" "staticizer_3/staticizer_one_6/c" 76.935
cap "ry6" "latch_6/latch_one_6/GND!" 181.284
cap "latch_6/latch_one_6/c" "staticizer_3/Vdd!" 1073
cap "staticizer_3/staticizer_one_6/c" "ry_addrH6" 58.7
cap "ry_addrH6" "latch_6/latch_one_6/GND!" 117.4
cap "ry6" "staticizer_3/Vdd!" 58.7
cap "ry_addrH6" "staticizer_3/Vdd!" 58.7
cap "latch_7/latch_one_6/c" "ry_addrH6" 58.7
cap "latch_7/Vdd!" "ry6" 134.125
cap "latch_7/latch_one_6/c" "staticizer_4/Vdd!" 1073
cap "ry_addrH6" "staticizer_4/Vdd!" 58.7
cap "latch_7/Vdd!" "ry_addrH6" 58.7
cap "ry_addrH6" "latch_7/latch_one_6/GND!" 77.41
cap "latch_7/latch_one_6/c" "latch_7/latch_one_6/GND!" 13.8522
cap "ry6" "staticizer_3/staticizer_one_6/w_54_n57#" 7.845
cap "latch_8/Vdd!" "ry_addrH6" 214.6
cap "staticizer_4/staticizer_one_6/c" "ry_addrH6" 58.7
cap "staticizer_4/staticizer_one_6/w_54_n57#" "ry_addrH6" 10.978
cap "staticizer_5/Vdd!" "latch_8/latch_one_6/c" 1073
cap "staticizer_5/staticizer_one_6/w_54_n57#" "latch_8/latch_one_6/c" 13.8522
cap "staticizer_1/in6" "staticizer_1/staticizer_one_6/a_60_n45#" 57.7175
cap "staticizer_1/staticizer_one_6/Vdd!" "staticizer_1/staticizer_one_6/a_60_n45#" -2.27374e-13
cap "latch_4/latch_one_6/GND!" "staticizer_1/staticizer_one_6/a_60_n45#" 2.84217e-14
cap "staticizer_1/in6" "latch_4/latch_one_6/c" 0.492
cap "staticizer_1/staticizer_one_6/Vdd!" "latch_4/latch_one_6/c" 1073
cap "staticizer_1/in6" "staticizer_1/staticizer_one_6/Vdd!" 73.946
cap "latch_4/latch_one_6/a_12_n54#" "staticizer_1/staticizer_one_6/Vdd!" -7.10543e-15
cap "latch_4/latch_one_6/GND!" "latch_4/latch_one_6/c" 8.88178e-16
cap "latch_4/latch_one_6/GND!" "staticizer_1/in6" 18.828
subcap "a_109_744#" -110.924
subcap "data_in6" -11.58
subcap "rx6" -1847.46
cap "latch_0/in6" "latch_0/latch_one_6/a_n5_n54#" 32.9814
cap "latch_0/latch_one_6/c" "latch_0/latch_one_6/GND!" 2.84217e-14
cap "latch_0/latch_one_6/c" "latch_0/out6" 0.492
cap "latch_0/latch_one_6/c" "latch_0/latch_one_6/Vdd!" 1073
cap "latch_0/latch_one_6/a_n5_n54#" "latch_0/latch_one_6/GND!" 5.68434e-14
cap "latch_0/in6" "latch_0/latch_one_6/Vdd!" 67.0625
cap "latch_0/latch_one_6/a_12_n54#" "latch_0/latch_one_6/Vdd!" -1.13687e-13
cap "latch_4/latch_one_6/a_n5_n54#" "latch_4/in6" 69.3743
cap "latch_4/in6" "latch_4/latch_one_6/Vdd!" 228.012
cap "latch_0/latch_one_6/a_n5_n54#" "latch_0/latch_one_6/Vdd!" 1.13687e-13
cap "latch_0/out6" "staticizer_0/staticizer_one_6/a_60_n45#" 57.7175
cap "latch_0/out6" "latch_0/latch_one_6/GND!" 18.828
cap "staticizer_0/staticizer_one_6/a_60_n45#" "latch_0/latch_one_6/Vdd!" -4.648
cap "latch_0/latch_one_6/GND!" "latch_0/latch_one_6/Vdd!" 2.27374e-13
cap "latch_0/out6" "latch_0/latch_one_6/Vdd!" 73.946
subcap "wz6" -2646.33
cap "latch_0/out6" "shift_0/shift_one_6/ad" 58.7
cap "latch_0/out6" "shift_0/shift_one_6/Vdd!" 8.24
cap "latch_0/out6" "staticizer_0/staticizer_one_6/a_60_n45#" 31.249
cap "staticizer_0/staticizer_one_6/a_60_n45#" "staticizer_0/staticizer_one_6/Vdd!" -2.744
cap "latch_0/out6" "staticizer_0/staticizer_one_6/Vdd!" 35.6
cap "staticizer_0/staticizer_one_6/Vdd!" "staticizer_0/staticizer_one_6/a_77_n45#" 1.13687e-13
cap "latch_0/out6" "shift_0/a6" 58.7
cap "latch_0/out6" "latch_0/latch_one_6/GND!" 6.22
cap "wz6" "shift_0/u" 58.7
cap "wz6" "shift_0/Vdd!" 58.7
cap "wz6" "shift_0/shift_one_6/Vdd!" 91.858
cap "shift_0/shift_one_6/inv_2/GND!" "wz6" 21.418
cap "wz6" "shift_0/shift_one_6/inv_2/out" 25.522
cap "shift_0/shift_one_6/m1_n60_n65#" "wz6" 11.825
cap "wz6" "shift_0/GND!" 58.7
subcap "a_373_740#" -159.568
cap "wz6" "latch_3/in6" 2.184
cap "wz6" "latch_3/GND!" 58.7
cap "shift_0/shift_one_6/2mux_nr_1/Vdd!" "wz6" 72.651
cap "latch_3/latch_one_6/Vdd!" "latch_3/in6" 9.594
cap "shift_0/shift_one_6/2mux_nr_1/out" "wz6" 8.599
cap "wz6" "latch_3/latch_one_6/GND!" 7.989
cap "shift_0/shift_one_6/2mux_nr_1/out" "latch_3/latch_one_6/Vdd!" 46.174
cap "shift_0/shift_one_6/s" "wz6" 58.7
cap "wz6" "latch_3/latch_one_6/a_n5_n54#" 30.853
cap "latch_3/latch_one_6/c" "wz6" 1.248
cap "latch_3/latch_one_6/a_n5_n54#" "latch_3/latch_one_6/Vdd!" -2.27374e-13
cap "wz6" "latch_3/latch_one_6/Vdd!" 64.715
cap "shift_0/shift_one_6/2mux_nr_1/out" "latch_3/in6" 57.7175
cap "latch_3/in6" "latch_3/latch_one_6/GND!" 6.956
cap "latch_3/latch_one_6/a_12_n54#" "wz6" 4.95
cap "wz6" "shift_0/shift_one_6/inv_3/GND!" 3.152
cap "latch_3/latch_one_6/a_n5_n54#" "latch_3/in6" 57.7175
cap "fblock_0/fblock_one_6/2mux_nr_2/Vdd!" "fblock_0/a6" 82.685
cap "fblock_0/a6" "fblock_0/fblock_one_6/2mux_nr_2/in0" 4.389
cap "latch_3/latch_one_6/Vdd!" "latch_3/latch_one_6/a_12_n54#" 2.84217e-14
cap "fblock_0/b6" "fblock_0/fblock_one_6/2mux_nr_1/Vdd!" 11.239
cap "fblock_0/b6" "fblock_0/g3" 140.424
cap "fblock_0/fblock_one_6/2mux_nr_2/a_n17_n11#" "latch_3/out6" 14.683
cap "fblock_0/a6" "latch_3/out6" 4.948
cap "fblock_0/fblock_one_6/2mux_nr_1/GND!" "fblock_0/a6" 114.873
cap "fblock_0/a6" "fblock_0/g2" 58.7
cap "latch_3/out6" "fblock_0/g3" 58.7
cap "fblock_0/fblock_one_6/2mux_nr_0/a_n17_n11#" "fblock_0/b6" 33.597
cap "fblock_0/fblock_one_6/2mux_nr_2/in0" "latch_3/out6" 7.975
cap "fblock_0/a6" "fblock_0/fblock_one_6/2mux_nr_0/out" 5.115
cap "fblock_0/b6" "fblock_0/g2" 58.7
cap "fblock_0/fblock_one_6/2mux_nr_1/GND!" "fblock_0/b6" 68.584
cap "fblock_0/a6" "fblock_0/fblock_one_6/inv_0/in" 9.081
cap "fblock_0/fblock_one_6/inv_0/GND!" "fblock_0/fblock_one_6/2mux_nr_2/a_n17_n11#" 2.84217e-14
cap "fblock_0/fblock_one_6/inv_0/GND!" "fblock_0/a6" 0.814
cap "latch_3/out6" "fblock_0/g2" 58.7
cap "fblock_0/fblock_one_6/2mux_nr_1/GND!" "latch_3/out6" 78.48
cap "fblock_0/b6" "fblock_0/fblock_one_6/2mux_nr_0/in0" 7.975
cap "fblock_0/fblock_one_6/2mux_nr_2/GND!" "latch_3/out6" 3.663
cap "fblock_0/b6" "fblock_0/fblock_one_6/2mux_nr_0/out" 11.825
cap "latch_3/latch_one_6/GND!" "latch_3/out6" 1.209
cap "fblock_0/b6" "fblock_0/fblock_one_6/2mux_nr_0/in1" 4.95
cap "latch_3/c" "latch_3/out6" 140.424
cap "fblock_0/fblock_one_6/2mux_nr_0/out" "latch_3/out6" 9.35
cap "fblock_0/fblock_one_6/2mux_nr_2/a_n17_n11#" "fblock_0/a6" 11.004
cap "fblock_0/a6" "fblock_0/g3" 301.374
cap "latch_3/latch_one_6/Vdd!" "latch_3/out6" 0.959
cap "fblock_0/fblock_one_6/inv_0/GND!" "latch_3/out6" 14.88
cap "latch_3/out6" "fblock_0/fblock_one_6/inv_0/in" 19.302
subcap "a_580_739#" -10.846
cap "latch_1/latch_one_6/a_n5_n54#" "wz6" 43.4
cap "latch_1/latch_one_6/Vdd!" "fblock_0/f6" 6.108
cap "rx6" "fblock_0/f6" 13.492
cap "rx6" "fblock_0/g0" 58.7
cap "rx6" "latch_1/latch_one_6/Vdd!" 103.828
cap "fblock_0/fblock_one_6/2mux_nr_1/s" "ry6" 16.386
cap "fblock_0/g1" "ry6" 58.7
cap "latch_1/latch_one_6/a_n5_n54#" "fblock_0/f6" 57.7175
cap "latch_1/GND!" "wz6" 58.7
cap "rx6" "latch_1/latch_one_6/a_n5_n54#" 7.807
cap "latch_1/latch_one_6/a_12_n54#" "wz6" 9.731
cap "fblock_0/Vdd!" "wz6" 58.7
cap "fblock_0/fblock_one_6/2mux_nr_1/in0" "ry6" 2.75
cap "fblock_0/g0" "ry6" 58.7
cap "wz6" "latch_1/latch_one_6/GND!" 7.31
cap "latch_1/latch_one_6/Vdd!" "ry6" 58.7
cap "fblock_0/Vdd!" "fblock_0/f6" 12.684
cap "fblock_0/fblock_one_6/inv_0/GND!" "wz6" 11.019
cap "rx6" "latch_1/GND!" 58.7
cap "fblock_0/fblock_one_6/2mux_nr_1/in1" "ry6" 4.95
cap "fblock_0/fblock_one_6/2mux_nr_1/out" "ry6" 11.825
cap "fblock_0/fblock_one_6/inv_0/in" "wz6" 4.123
cap "fblock_0/fblock_one_6/inv_0/GND!" "wz6" 9.958
cap "fblock_0/Vdd!" "rx6" 58.7
cap "fblock_0/Vdd!" "latch_1/latch_one_6/Vdd!" 1341.25
cap "fblock_0/f6" "latch_1/latch_one_6/GND!" 12.326
cap "latch_1/latch_one_6/GND!" "wz6" 0.762
cap "fblock_0/fblock_one_6/2mux_nr_1/a_n17_n11#" "ry6" 31.949
cap "rx6" "fblock_0/fblock_one_6/f" 85.724
cap "fblock_0/g1" "wz6" 58.7
cap "ry6" "fblock_0/fblock_one_6/2mux_nr_1/GND!" 24.128
cap "latch_1/GND!" "ry6" 58.7
cap "fblock_0/fblock_one_6/inv_0/in" "rx6" 2.844
cap "fblock_0/Vdd!" "ry6" 58.7
cap "wz6" "fblock_0/f6" 18.093
cap "fblock_0/g0" "wz6" 58.7
cap "wz6" "latch_1/latch_one_6/c" 4.324
cap "wz6" "latch_1/latch_one_6/GND!" 1.485
cap "ry6" "fblock_0/fblock_one_6/f" 25.152
cap "rx6" "fblock_0/g1" 58.7
cap "latch_1/latch_one_6/Vdd!" "wz6" 58.7
subcap "ry6" -2483.37
cap "addsub_0/xor_6/Vdd!" "rx6" 8.496
cap "addsub_0/xor_6/a_100_n42#" "addsub_0/b6" 0.707
cap "latch_1/latch_one_6/Vdd!" "rx6" -4.367
cap "latch_1/latch_one_6/a_12_n54#" "rx6" 4.948
cap "latch_1/out6" "latch_1/latch_one_6/Vdd!" 1.221
cap "addsub_0/xor_6/a_89_n31#" "addsub_0/b6" 3.068
cap "addsub_0/xor_6/GND!" "addsub_0/b6" 173.474
cap "latch_1/c" "rx6" 58.7
cap "latch_1/out6" "rx6" 9.182
cap "latch_1/latch_one_6/a_n5_n54#" "rx6" 4.948
cap "latch_1/out6" "latch_1/c" 140.424
cap "latch_1/out6" "latch_1/latch_one_6/c" 4.208
cap "latch_1/latch_one_6/a_n5_n54#" "latch_1/out6" 15.975
cap "latch_1/latch_one_6/a_30_n35#" "rx6" 4.828
cap "addsub_0/xor_6/b" "rx6" 11.825
cap "addsub_0/xor_6/b" "latch_1/out6" 11.825
cap "addsub_0/xor_6/GND!" "rx6" 24.038
cap "latch_1/latch_one_6/GND!" "latch_1/out6" 1.371
cap "rx6" "addsub_0/b6" 2.764
cap "addsub_0/xor_6/a_61_n31#" "addsub_0/b6" 7.218
cap "latch_1/c" "addsub_0/b6" 58.7
cap "latch_1/out6" "addsub_0/xor_6/GND!" 11.825
cap "addsub_0/xor_6/out" "addsub_0/b6" 31.486
cap "addsub_0/xor_6/a_69_n42#" "addsub_0/b6" 2.457
cap "latch_1/latch_one_6/a_30_n54#" "latch_1/out6" 1.524
cap "latch_1/latch_one_6/Vdd!" "rx6" -1.405
cap "latch_1/out6" "latch_1/latch_one_6/GND!" 3.821
cap "addsub_0/xor_6/b" "addsub_0/b6" 15.993
cap "addsub_0/a6" "addsub_0/addsub_one_6/GND!" -0.341
cap "addsub_0/addsub_one_6/Vdd!" "addsub_0/a6" 189.896
cap "as_cout" "addsub_0/addsub_one_6/GND!" 44.7
cap "addsub_0/a6" "addsub_0/addsub_one_6/b" 94.487
cap "addsub_0/addsub_one_6/a_35_n41#" "wz6" 65.763
cap "addsub_0/a6" "addsub_0/xor_6/a" 2.424
cap "as_cout" "addsub_0/addsub_one_6/b" 12.612
cap "as_cout" "addsub_0/addsub_one_6/s" 41.11
cap "addsub_0/addsub_one_6/a_35_n41#" "addsub_0/addsub_one_6/GND!" 2.27374e-13
cap "as_cout" "addsub_0/addsub_one_6/a_11_n41#" 6.99
cap "addsub_0/addsub_one_6/cin" "as_cout" 8.408
cap "addsub_0/addsub_one_6/GND!" "addsub_0/a6" 20.114
cap "wz6" "addsub_0/addsub_one_6/GND!" 0.308
cap "wz6" "addsub_0/addsub_one_6/Vdd!" 50.747
cap "addsub_0/a6" "addsub_0/addsub_one_6/a_78_n41#" 11.825
cap "addsub_0/a6" "addsub_0/xor_6/a_89_n31#" 2.424
cap "addsub_0/addsub_one_6/GND!" "as_cout" 30.928
cap "addsub_0/a6" "addsub_0/xor_6/b" 2.424
cap "as_cout" "addsub_0/addsub_one_6/a_78_n41#" 15.064
cap "addsub_0/xor_6/a_61_n1#" "addsub_0/a6" 141.539
cap "addsub_0/addsub_one_6/a_89_n41#" "as_cout" 22.875
cap "addsub_0/a6" "addsub_0/addsub_one_6/a_89_9#" 4.7
cap "addsub_0/addsub_one_6/a_35_n41#" "addsub_0/a6" 19.78
cap "as_cout" "addsub_0/addsub_one_6/a_72_n41#" 2.1
cap "addsub_0/addsub_one_6/a_66_n41#" "as_cout" 2.1
cap "addsub_0/addsub_one_6/a_35_n41#" "as_cout" 7.536
cap "addsub_0/xor_6/a_61_n31#" "addsub_0/a6" 2.424
cap "as_cout" "addsub_0/a6" 8.408
cap "wz6" "addsub_0/addsub_one_6/GND!" 18.211
subcap "a_841_745#" -42.234
cap "latch_2/latch_one_6/a_30_n54#" "latch_2/out6" 2.592
cap "latch_2/out6" "addsub_0/GND!" 11.825
cap "latch_2/out6" "addsub_0/addsub_one_6/GND!" 7.422
cap "latch_2/latch_one_6/c" "rx6" 2.844
cap "latch_2/GND!" "latch_2/out6" 58.7
cap "latch_2/latch_one_6/a_30_n35#" "rx6" 1.524
cap "latch_2/out6" "latch_2/latch_one_6/a_12_n54#" 12.473
cap "latch_2/out6" "latch_2/c" 717.161
cap "reg_0/r0" "latch_2/out6" 217.183
cap "addsub_0/addsub_one_6/GND!" "rx6" 7.942
cap "rx6" "addsub_0/addsub_one_6/b" -2.068
cap "latch_2/latch_one_6/Vdd!" "addsub_0/s6" 19.399
cap "latch_2/latch_one_6/Vdd!" "latch_2/out6" 59.921
cap "rx6" "addsub_0/s6" 3.468
cap "latch_2/out6" "rx6" 4.341
cap "rx6" "latch_2/latch_one_6/a_n5_n54#" 6.195
cap "latch_2/out6" "latch_2/latch_one_6/GND!" 31.533
cap "latch_2/latch_one_6/c" "latch_2/out6" 9.896
cap "rx6" "addsub_0/GND!" 11.825
cap "rx6" "addsub_0/addsub_one_6/GND!" 5.148
cap "addsub_0/addsub_one_6/GND!" "latch_2/out6" 3.399
cap "latch_2/out6" "addsub_0/addsub_one_6/a_35_n41#" -1.814
cap "latch_2/out6" "addsub_0/s6" 4.948
cap "latch_2/GND!" "rx6" 58.7
cap "rx6" "latch_2/latch_one_6/a_12_n54#" 37.778
cap "rx6" "latch_2/c" 58.7
cap "latch_2/latch_one_6/a_n5_n54#" "addsub_0/s6" 57.7175
cap "reg_0/r0" "rx6" 19.78
cap "latch_2/out6" "latch_2/latch_one_6/a_n5_n54#" 12.196
cap "latch_2/latch_one_6/Vdd!" "rx6" 116.636
cap "addsub_0/s6" "addsub_0/GND!" 76.9567
cap "wz6" "reg_0/GND!" 58.7
cap "reg_0/port60" "reg_0/reg_one_1/a_4_n13#" 20.417
cap "reg_0/reg_one_1/r1" "wz6" 58.7
cap "reg_0/reg_one_1/Vdd!" "wz6" 165.083
cap "reg_0/reg_one_1/a_16_27#" "wz6" 8.264
cap "reg_0/reg_one_1/tmp" "reg_0/port60" 4.948
cap "reg_0/port60" "reg_0/w" 434.25
cap "reg_0/in6" "wz6" 14.786
cap "reg_0/port60" "reg_0/r0" -7.416
cap "reg_0/reg_one_1/w_n11_n27#" "wz6" 8.24
cap "reg_0/port60" "reg_0/reg_one_1/a_21_n13#" 20.118
cap "reg_0/port60" "reg_0/GND!" 58.7
cap "reg_0/port60" "reg_0/reg_one_1/r1" 70.642
cap "reg_0/port60" "reg_0/reg_one_1/Vdd!" 134.044
cap "wz6" "reg_1/r0" 63.6875
cap "wz6" "reg_0/reg_one_1/a_33_32#" 65.474
cap "reg_0/port60" "reg_0/reg_one_1/w_n11_n27#" 122.877
cap "wz6" "reg_0/reg_one_1/w" 4.382
cap "reg_0/reg_one_1/tmp" "wz6" 4.324
cap "wz6" "reg_0/w" 58.7
cap "wz6" "reg_0/r0" -7.416
cap "reg_0/reg_one_1/tmp" "wz6" 4.389
cap "reg_0/in6" "reg_0/r0" -5.072
cap "reg_1/in6" "reg_1/reg_one_1/tmp" 4.389
cap "reg_1/port60" "reg_1/r0" 19.78
cap "reg_1/reg_one_1/w_n11_n27#" "reg_1/port60" 4.46
cap "reg_1/port60" "reg_1/w" 125.762
cap "reg_1/reg_one_1/w_n11_n27#" "reg_1/reg_one_1/r1" 7.10543e-15
cap "reg_1/in6" "reg_1/reg_one_1/a_33_32#" 65.474
cap "reg_1/in6" "reg_1/r0" 89.8075
cap "reg_1/in6" "reg_1/w" 58.7
cap "reg_1/port60" "reg_1/reg_one_1/a_21_n13#" 2.238
cap "reg_1/reg_one_1/tmp" "reg_1/port60" 4.694
cap "reg_1/port60" "reg_1/reg_one_1/r0" 1.364
cap "reg_1/in6" "reg_1/reg_one_1/w" 4.382
cap "reg_1/port60" "reg_1/reg_one_1/r1" 60.064
cap "reg_1/reg_one_1/tmp" "reg_1/in6" 4.324
cap "reg_1/reg_one_1/w_n11_n27#" "reg_1/port60" 122.877
cap "reg_1/port60" "reg_1/reg_one_1/Vdd!" 75.185
cap "reg_1/GND!" "reg_1/port60" 58.7
cap "reg_1/reg_one_1/a_16_27#" "reg_1/in6" 8.264
cap "reg_1/in6" "reg_1/reg_one_1/r1" 58.7
cap "reg_1/reg_one_1/a_4_n13#" "reg_1/port60" 118.494
cap "reg_1/in6" "reg_1/reg_one_1/w_n11_n27#" 8.24
cap "reg_1/in6" "reg_1/reg_one_1/Vdd!" 165.083
cap "reg_1/GND!" "reg_1/in6" 58.7
cap "reg_1/port60" "reg_1/reg_one_1/port1" 3.85
cap "reg_1/port60" "reg_2/reg_one_1/a_21_n13#" 2.238
cap "reg_2/w" "reg_1/port60" 92.2312
cap "reg_1/port60" "reg_2/r0" 19.78
cap "reg_2/reg_one_1/r1" "reg_2/in6" 58.7
cap "reg_2/reg_one_1/Vdd!" "reg_1/port60" 75.185
cap "reg_1/port60" "reg_2/reg_one_1/w_n11_n27#" 4.46
cap "reg_2/in6" "reg_2/reg_one_1/a_33_32#" 65.474
cap "reg_2/reg_one_1/w_n11_n27#" "reg_1/port60" 65.5588
cap "reg_2/reg_one_1/w" "reg_2/in6" 4.382
cap "reg_2/w" "reg_2/in6" 58.7
cap "reg_2/r0" "reg_2/in6" 153.495
cap "reg_1/port60" "reg_2/reg_one_1/r0" 1.364
cap "reg_1/port60" "reg_2/reg_one_1/tmp" 4.694
cap "reg_2/reg_one_1/port1" "reg_1/port60" 3.85
cap "reg_2/reg_one_1/Vdd!" "reg_2/in6" 165.083
cap "reg_2/GND!" "reg_1/port60" 58.7
cap "reg_2/reg_one_1/w_n11_n27#" "reg_2/in6" 8.24
cap "reg_2/reg_one_1/w_n11_n27#" "reg_2/reg_one_1/r1" 7.10543e-15
cap "reg_1/port60" "reg_2/reg_one_1/a_4_n13#" 118.494
cap "reg_2/reg_one_1/tmp" "reg_2/in6" 4.324
cap "reg_2/in6" "reg_2/reg_one_1/a_16_27#" 8.264
cap "reg_1/port60" "reg_2/reg_one_1/r1" 60.064
cap "reg_2/GND!" "reg_2/in6" 58.7
cap "reg_2/reg_one_1/tmp" "reg_2/in6" 4.389
cap "reg_2/port60" "reg_3/reg_one_1/port1" 3.85
cap "reg_2/port60" "reg_2/reg_one_1/w_n11_n27#" 57.3188
cap "reg_3/reg_one_1/Vdd!" "reg_2/port60" 74.654
cap "reg_3/in6" "reg_3/reg_one_1/a_16_27#" 7.446
cap "reg_2/port60" "reg_3/reg_one_1/r0" 1.364
cap "reg_3/in6" "reg_3/reg_one_1/w_n11_n27#" 17.302
cap "reg_3/reg_one_1/w_n11_n27#" "reg_3/reg_one_1/r1" 7.10543e-15
cap "reg_2/port60" "reg_3/GND!" 58.7
cap "reg_3/in6" "reg_3/r0" 153.495
cap "reg_2/port60" "reg_3/reg_one_1/tmp" 4.694
cap "reg_3/in6" "reg_3/reg_one_1/r1" 58.7
cap "reg_2/port60" "reg_3/reg_one_1/a_4_n13#" 118.494
cap "reg_2/port60" "reg_2/w" 33.5312
cap "reg_3/in6" "reg_3/reg_one_1/w" 1.248
cap "reg_3/in6" "reg_3/reg_one_1/tmp" 6.6
cap "reg_3/in6" "reg_3/reg_one_1/Vdd!" 75.24
cap "reg_3/in6" "reg_3/GND!" 58.7
cap "reg_3/in6" "reg_3/reg_one_1/tmp" 1.248
cap "reg_2/port60" "reg_3/port60" 8.58
cap "reg_2/port60" "reg_3/reg_one_1/a_21_n13#" 2.238
cap "reg_2/port60" "reg_3/r0" 19.78
cap "reg_3/reg_one_1/w_n11_n27#" "reg_2/port60" 4.41
cap "reg_2/port60" "reg_3/reg_one_1/r1" 60.064
cap "reg_3/in6" "reg_3/reg_one_1/a_33_32#" 39.098
subcap "wz_addrL6" -546.95
cap "reg_3/reg_one_1/w_n11_n27#" "mux_8bit_0/in1_6" 8.24
cap "reg_3/port60" "reg_3/reg_one_1/w" 125.762
cap "mux_8bit_0/mux_one_6/GND!" "mux_8bit_0/in1_6" 15.908
cap "reg_3/reg_one_1/w" "mux_8bit_0/in1_6" 58.7
cap "mux_8bit_0/mux_one_6/2mux_nr_0/in0" "mux_8bit_0/in0_6" 29.025
cap "mux_8bit_0/in0_6" "mux_8bit_0/mux_one_6/GND!" 1.181
cap "mux_8bit_0/mux_one_6/2mux_nr_0/a_n17_n11#" "mux_8bit_0/in1_6" 36.092
cap "mux_8bit_0/mux_one_6/Vdd!" "mux_8bit_0/in1_6" 98.617
cap "reg_3/reg_one_1/w_n11_n27#" "reg_3/reg_one_1/w" 1.42109e-14
cap "reg_3/port60" "reg_3/reg_one_1/w_n11_n27#" -3.379
cap "mux_8bit_0/in0_6" "mux_8bit_0/mux_one_6/Vdd!" 78.896
cap "reg_3/port60" "reg_3/reg_one_1/Vdd!" -2.898
cap "mux_8bit_0/mux_one_6/2mux_nr_0/in1" "mux_8bit_0/mux_one_6/GND!" 1.42109e-14
cap "mux_8bit_0/in0_6" "mux_8bit_0/mux_one_6/inv2_2/GND!" 11.098
cap "mux_8bit_0/mux_one_6/inv2_1/a_1_8#" "mux_8bit_0/in0_6" 19.462
cap "reg_3/reg_one_1/Vdd!" "mux_8bit_0/in1_6" -2.948
cap "reg_3/reg_one_1/w_n11_n27#" "mux_8bit_0/in1_6" -2.948
cap "mux_8bit_0/out6" "mux_8bit_0/in0_6" 30.603
cap "mux_8bit_0/mux_one_6/sel" "mux_8bit_0/in1_6" 63.256
cap "reg_3/port60" "reg_3/reg_one_1/w_n11_n27#" 122.877
cap "reg_3/reg_one_1/a_33_32#" "mux_8bit_0/in1_6" -4.455
cap "mux_8bit_0/mux_one_6/sel" "mux_8bit_0/in0_6" 58.7
cap "mux_8bit_0/mux_one_6/2mux_nr_0/in1" "mux_8bit_0/in1_6" 18.535
cap "reg_4/reg_one_1/a_33_32#" "wz6" 7.959
cap "wz6" "reg_4/r0" 19.78
cap "reg_4/reg_one_1/tmp" "wz_addrL6" 4.68
cap "reg_4/reg_one_1/port1" "wz_addrL6" 4.95
cap "wz6" "reg_4/reg_one_1/Vdd!" 58.7
cap "reg_4/in6" "reg_4/r0" 190.251
cap "reg_4/in6" "reg_4/reg_one_1/Vdd!" 56.544
cap "mux_8bit_0/mux_one_6/GND!" "mux_8bit_0/mux_one_6/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "reg_4/reg_one_1/a_16_27#" "wz6" 8.022
cap "wz_addrL6" "reg_4/port60" 9.229
cap "wz6" "reg_4/reg_one_1/w" 5.064
cap "wz_addrL6" "reg_4/GND!" 58.7
cap "reg_4/reg_one_1/tmp" "wz6" 6.507
cap "reg_4/reg_one_1/Vdd!" "reg_4/r0" -9.768
cap "wz_addrL6" "mux_8bit_0/mux_one_6/GND!" 65.42
cap "wz_addrL6" "reg_4/reg_one_1/r0" 1.248
cap "wz_addrL6" "reg_4/reg_one_1/w_n11_n27#" 17.864
cap "reg_4/reg_one_1/w_n11_n27#" "wz6" 133.528
cap "wz6" "reg_4/GND!" 58.7
cap "reg_4/reg_one_1/a_4_n13#" "wz_addrL6" 47.175
cap "wz6" "mux_8bit_0/mux_one_6/GND!" 67.786
cap "mux_8bit_0/mux_one_6/2mux_nr_0/s" "wz6" 4.948
cap "wz_addrL6" "reg_4/reg_one_1/r1" 59.948
cap "reg_4/in6" "wz_addrL6" -6.325
cap "mux_8bit_0/mux_one_6/2mux_nr_0/a_n17_n11#" "wz6" -5.178
cap "reg_4/in6" "mux_8bit_0/mux_one_6/GND!" 331.401
cap "wz_addrL6" "mux_8bit_0/mux_one_6/inv2_1/a_1_8#" -1.132
cap "wz_addrL6" "reg_4/r0" 19.78
cap "reg_4/in6" "mux_8bit_0/mux_one_6/2mux_nr_0/out" 85.4219
cap "mux_8bit_0/mux_one_6/GND!" "reg_4/r0" 165.587
cap "wz6" "reg_4/reg_one_1/r1" 58.7
cap "reg_4/in6" "wz6" 2.844
cap "wz_addrL6" "reg_4/reg_one_1/Vdd!" 73.616
subcap "rx_PCL6" -293.223
cap "wz6" "addsub_1/addsub_one_6/b" 97.913
cap "addsub_1/addsub_one_6/Vdd!" "wz6" 15.72
cap "addsub_1/b6" "addsub_1/a6" 27.728
cap "wz6" "reg_4/reg_one_1/a_33_32#" -12.339
cap "wz6" "reg_4/reg_one_1/w" 58.7
cap "reg_4/reg_one_1/w_n11_n27#" "wz_addrL6" 8.24
cap "addsub_1/xor_6/a_61_n1#" "addsub_1/a6" 174.249
cap "addsub_1/xor_6/a_89_n31#" "addsub_1/a6" 2.424
cap "addsub_1/xor_6/b" "wz_addrL6" 7.975
cap "addsub_1/b6" "addsub_1/xor_6/a_61_n31#" -9.50351e-14
cap "wz_addrL6" "reg_4/reg_one_1/Vdd!" -2.948
cap "wz6" "addsub_1/b6" 26.517
cap "wz_addrL6" "addsub_1/addsub_one_6/Vdd!" 11.825
cap "addsub_1/xor_6/a_61_n1#" "wz6" 5.568
cap "addsub_1/a6" "addsub_1/xor_6/a_61_n31#" 2.424
cap "addsub_1/xor_6/b" "addsub_1/b6" 11.5435
cap "addsub_1/xor_6/a_89_n31#" "wz6" 17.316
cap "reg_4/reg_one_1/w_n11_n27#" "addsub_1/a6" 50.95
cap "wz_addrL6" "reg_4/reg_one_1/w" 58.7
cap "wz_addrL6" "reg_4/reg_one_1/w_n11_n27#" -3.379
cap "addsub_1/xor_6/b" "addsub_1/a6" 89.2933
cap "wz6" "addsub_1/xor_6/a_61_n31#" 19.78
cap "wz_addrL6" "addsub_1/b6" 7.975
cap "addsub_1/a6" "addsub_1/addsub_one_6/b" 36.877
cap "reg_4/reg_one_1/w_n11_n27#" "wz6" -8.24
cap "addsub_1/addsub_one_6/Vdd!" "addsub_1/a6" 127.516
cap "reg_4/reg_one_1/w_n11_n27#" "wz6" -2.417
cap "wz_addrL6" "addsub_1/a6" -7.348
cap "addsub_1/xor_6/b" "wz6" 11.825
subcap "a_1716_745#" -30.357
cap "addsub_1/addsub_one_6/a_72_n41#" "a_2510_1893#" 2.1
cap "addsub_1/addsub_one_6/cin" "a_2510_1893#" 8.408
cap "addsub_1/addsub_one_6/b" "a_2510_1893#" 12.612
cap "addsub_1/addsub_one_6/GND!" "addsub_1/addsub_one_6/a_35_n41#" -1.13687e-13
cap "wz_addrL6" "addsub_1/addsub_one_6/Vdd!" 32.72
cap "addsub_1/addsub_one_6/GND!" "a_2510_1893#" 44.7
cap "addsub_1/a6" "a_2510_1893#" 8.408
cap "wz_addrL6" "addsub_1/addsub_one_6/GND!" 43.659
cap "addsub_1/GND!" "wz_addrL6" 11.825
cap "latch_5/latch_one_6/a_n5_n54#" "addsub_1/s6" 19.2392
cap "addsub_1/addsub_one_6/a_11_n41#" "a_2510_1893#" 6.99
cap "addsub_1/addsub_one_6/a_78_n41#" "a_2510_1893#" 15.064
cap "addsub_1/addsub_one_6/b" "wz6" 95.736
cap "wz6" "addsub_1/addsub_one_6/cin" 1.56
cap "addsub_1/addsub_one_6/GND!" "a_2510_1893#" 30.928
cap "wz_addrL6" "addsub_1/addsub_one_6/a_35_n41#" 24.622
cap "addsub_1/s6" "a_2510_1893#" 41.11
cap "wz6" "addsub_1/addsub_one_6/GND!" 11.825
cap "addsub_1/addsub_one_6/b" "addsub_1/addsub_one_6/GND!" -2.27374e-13
cap "addsub_1/addsub_one_6/a_78_n41#" "wz6" 35.835
cap "latch_5/latch_one_6/Vdd!" "addsub_1/s6" -12.402
cap "addsub_1/addsub_one_6/Vdd!" "wz6" 3.171
cap "addsub_1/addsub_one_6/a_35_n41#" "a_2510_1893#" 7.536
cap "addsub_1/addsub_one_6/a_89_n41#" "a_2510_1893#" 22.875
cap "addsub_1/addsub_one_6/GND!" "wz6" 14.639
cap "addsub_1/GND!" "wz6" 11.825
cap "addsub_1/addsub_one_6/a_66_n41#" "a_2510_1893#" 2.1
cap "addsub_1/GND!" "addsub_1/s6" 76.9567
cap "wz_addrL6" "addsub_1/addsub_one_6/GND!" 10.505
cap "addsub_1/addsub_one_6/a_35_n41#" "wz6" 51.712
subcap "a_1716_745#" -103.553
cap "latch_5/out6" "latch_5/latch_one_6/c" 8.532
cap "latch_5/c" "latch_5/latch_one_6/Vdd!" 1071.03
cap "addsub_1/s6" "latch_5/latch_one_6/Vdd!" 19.399
cap "latch_5/latch_one_6/GND!" "latch_5/latch_one_6/Vdd!" -0.984
cap "latch_5/latch_one_6/a_12_n54#" "latch_5/latch_one_6/Vdd!" 1.13687e-13
cap "latch_5/out6" "latch_5/latch_one_6/a_30_n54#" 1.524
cap "latch_5/out6" "staticizer_2/staticizer_one_6/a_60_n45#" 212.283
cap "latch_5/out6" "staticizer_2/c" 58.7
cap "latch_5/out6" "staticizer_2/staticizer_one_6/a_77_n45#" 9.998
cap "staticizer_2/c" "wz6" 58.7
cap "addsub_1/s6" "addsub_1/GND!" 19.2392
cap "latch_5/out6" "latch_5/latch_one_6/a_n5_n54#" 59.375
cap "latch_5/out6" "latch_5/GND!" 58.7
cap "latch_5/out6" "latch_5/latch_one_6/Vdd!" 231.426
cap "latch_5/GND!" "wz6" 58.7
cap "latch_5/latch_one_6/Vdd!" "wz6" 117.4
cap "latch_5/out6" "latch_5/c" 66.65
cap "latch_5/out6" "addsub_1/s6" 4.324
cap "latch_5/out6" "latch_5/latch_one_6/GND!" 108.547
cap "latch_5/out6" "latch_5/latch_one_6/a_12_n54#" 9.731
cap "latch_5/c" "wz6" 58.7
cap "latch_5/latch_one_6/GND!" "wz6" 58.7
cap "latch_5/latch_one_6/GND!" "staticizer_2/staticizer_one_6/a_60_n45#" 8.52651e-14
cap "latch_5/out6" "staticizer_2/staticizer_one_6/c" 4.948
cap "latch_5/latch_one_6/a_n5_n54#" "addsub_1/s6" 57.7175
subcap "wz_addrH6" -931.891
cap "mux_8bit_1/in1_6" "mux_8bit_1/mux_one_6/GND!" 15.908
cap "mux_8bit_1/in1_6" "mux_8bit_1/mux_one_6/2mux_nr_0/in1" 18.535
cap "staticizer_2/staticizer_one_6/Vdd!" "staticizer_2/staticizer_one_6/out" 11.587
cap "staticizer_2/staticizer_one_6/a_77_n45#" "staticizer_2/staticizer_one_6/out" 19.052
cap "staticizer_2/staticizer_one_6/w_54_n57#" "staticizer_2/staticizer_one_6/out" 2.59
cap "staticizer_2/staticizer_one_6/a_60_n45#" "staticizer_2/staticizer_one_6/out" -5.616
cap "mux_8bit_1/in0_6" "mux_8bit_1/mux_one_6/GND!" 16.402
cap "mux_8bit_1/in1_6" "mux_8bit_1/mux_one_6/Vdd!" 96.331
cap "mux_8bit_1/in0_6" "mux_8bit_1/mux_one_6/inv2_2/GND!" 2.035
cap "staticizer_2/staticizer_one_6/a_95_n45#" "staticizer_2/staticizer_one_6/out" 4.212
cap "mux_8bit_1/in0_6" "mux_8bit_1/mux_one_6/inv2_1/a_1_8#" 4.95
cap "mux_8bit_1/in0_6" "mux_8bit_1/mux_one_6/2mux_nr_0/in0" 34.083
cap "staticizer_2/staticizer_one_6/c" "staticizer_2/staticizer_one_6/out" 3.996
cap "mux_8bit_1/in1_6" "mux_8bit_1/mux_one_6/sel" 63.256
cap "mux_8bit_1/in1_6" "mux_8bit_1/mux_one_6/2mux_nr_0/a_n17_n11#" 36.092
cap "mux_8bit_1/in0_6" "mux_8bit_1/mux_one_6/Vdd!" 149.982
cap "staticizer_2/staticizer_one_6/a_95_n27#" "staticizer_2/staticizer_one_6/out" 5.61
cap "mux_8bit_1/mux_one_6/2mux_nr_0/in0" "mux_8bit_1/mux_one_6/inv2_2/GND!" -3.55271e-15
cap "mux_8bit_1/in0_6" "mux_8bit_1/mux_one_6/sel" 58.7
cap "reg_5/r0" "wz6" 19.78
cap "reg_5/reg_one_1/Vdd!" "wz6" 58.7
cap "wz_addrH6" "mux_8bit_1/mux_one_6/GND!" 67.654
cap "mux_8bit_1/mux_one_6/GND!" "wz6" 67.786
cap "reg_5/reg_one_1/tmp" "wz_addrH6" 4.948
cap "reg_5/reg_one_1/r1" "wz_addrH6" 58.7
cap "reg_5/reg_one_1/r0" "wz_addrH6" 4.948
cap "reg_5/reg_one_1/a_54_5#" "wz_addrH6" 4.828
cap "mux_8bit_1/mux_one_6/2mux_nr_0/a_n17_n11#" "wz6" -5.178
cap "reg_5/r0" "reg_5/in6" 190.251
cap "reg_5/port60" "wz_addrH6" 6.6
cap "reg_5/reg_one_1/tmp" "wz6" 6.507
cap "reg_5/reg_one_1/r1" "wz6" 58.7
cap "reg_5/in6" "reg_5/reg_one_1/Vdd!" 56.544
cap "reg_5/r0" "reg_5/reg_one_1/Vdd!" -9.768
cap "mux_8bit_1/mux_one_6/2mux_nr_0/s" "wz6" 4.948
cap "mux_8bit_1/mux_one_6/GND!" "reg_5/in6" 331.401
cap "reg_5/reg_one_1/w_n11_n27#" "wz6" 133.528
cap "reg_5/in6" "mux_8bit_1/mux_one_6/2mux_nr_0/out" 85.4219
cap "reg_5/r0" "mux_8bit_1/mux_one_6/GND!" 165.587
cap "reg_5/reg_one_1/a_16_27#" "wz6" 8.022
cap "reg_5/reg_one_1/a_33_32#" "wz6" 7.959
cap "wz_addrH6" "reg_5/in6" -6.325
cap "reg_5/reg_one_1/a_4_n13#" "wz_addrH6" 27.497
cap "reg_5/GND!" "wz_addrH6" 58.7
cap "reg_5/r0" "wz_addrH6" 19.78
cap "reg_5/in6" "wz6" 2.844
cap "wz_addrH6" "reg_5/reg_one_1/Vdd!" 162.612
cap "reg_5/reg_one_1/w" "wz6" 5.064
cap "reg_5/GND!" "wz6" 58.7
cap "mux_8bit_1/mux_one_6/2mux_nr_0/a_n17_n11#" "mux_8bit_1/mux_one_6/GND!" 3.55271e-15
cap "reg_6/in6" "reg_5/w" 58.7
cap "reg_6/reg_one_1/tmp" "wz_addrH6" 4.948
cap "wz_addrH6" "reg_6/reg_one_1/r0" 4.948
cap "reg_6/reg_one_1/w_n11_n27#" "reg_5/port60" 37.942
cap "reg_6/in6" "reg_6/reg_one_1/tmp" 4.461
cap "reg_6/reg_one_1/r1" "wz_addrH6" 58.7
cap "reg_6/reg_one_1/r1" "reg_6/reg_one_1/Vdd!" 2.27374e-13
cap "reg_6/in6" "reg_6/reg_one_1/r1" 58.7
cap "wz_addrH6" "reg_6/reg_one_1/a_4_n13#" 17.113
cap "reg_6/in6" "reg_6/reg_one_1/w" 2.22
cap "reg_6/GND!" "wz_addrH6" 58.7
cap "reg_6/GND!" "reg_6/in6" 58.7
cap "wz_addrH6" "reg_5/reg_one_1/w_n11_n27#" 8.24
cap "reg_6/reg_one_1/w_n11_n27#" "reg_6/reg_one_1/r1" 7.10543e-15
cap "reg_6/in6" "reg_5/reg_one_1/w_n11_n27#" -8.24
cap "reg_6/r0" "reg_5/port60" 13.352
cap "reg_5/reg_one_1/Vdd!" "wz_addrH6" -2.417
cap "reg_5/port60" "reg_6/reg_one_1/a_21_n13#" 2.97
cap "reg_6/in6" "reg_6/reg_one_1/a_33_32#" 2.844
cap "reg_6/in6" "reg_5/reg_one_1/w_n11_n27#" -2.417
cap "reg_6/reg_one_1/Vdd!" "wz_addrH6" 160.588
cap "reg_5/port60" "reg_6/reg_one_1/r0" 2.104
cap "reg_6/in6" "reg_6/reg_one_1/Vdd!" 58.7
cap "reg_5/port60" "reg_5/w" 67.0625
cap "reg_6/reg_one_1/tmp" "reg_5/port60" 4.44
cap "reg_5/port60" "reg_6/reg_one_1/r0" 2.22
cap "reg_6/in6" "reg_6/reg_one_1/a_16_27#" 8.022
cap "reg_6/in6" "reg_6/reg_one_1/w_n11_n27#" 123.733
cap "reg_6/reg_one_1/r1" "reg_5/port60" 56.054
cap "reg_6/in6" "reg_6/reg_one_1/w" 2.844
cap "reg_5/port60" "reg_6/reg_one_1/a_4_n13#" 86.301
cap "reg_6/GND!" "reg_5/port60" 51.73
cap "reg_6/r0" "wz_addrH6" 19.78
cap "reg_6/in6" "reg_6/r0" 128.02
cap "reg_5/port60" "reg_5/reg_one_1/w_n11_n27#" 114.637
cap "reg_5/reg_one_1/a_33_32#" "reg_6/in6" -12.339
cap "reg_6/reg_one_1/port1" "reg_5/port60" 4.125
cap "reg_6/reg_one_1/a_54_5#" "wz_addrH6" 4.828
cap "reg_5/port60" "reg_6/reg_one_1/Vdd!" 51.73
cap "wz_addrH6" "reg_5/w" 58.7
subcap "m1_2132_731#" -14.804
cap "mux_8bit_2/mux_one_6/Vdd!" "mux_8bit_2/in0_6" 139.939
cap "rx_addrH6" "reg_6/reg_one_1/a_4_n13#" -10.448
cap "rx_addrH6" "mux_8bit_2/mux_one_6/Vdd!" 70.953
cap "reg_6/reg_one_1/Vdd!" "mux_8bit_2/in0_6" -0.393
cap "mux_8bit_2/in1_6" "reg_6/reg_one_1/w_n11_n27#" -1.886
cap "rx_addrH6" "mux_8bit_2/out6" 17.067
cap "rx_addrH6" "reg_6/reg_one_1/w_n11_n27#" 2.667
cap "reg_6/reg_one_1/w_n11_n27#" "mux_8bit_2/in0_6" 8.24
cap "mux_8bit_2/in1_6" "mux_8bit_2/mux_one_6/Vdd!" 2.035
cap "mux_8bit_2/mux_one_6/sel" "mux_8bit_2/in0_6" 58.7
cap "rx_addrH6" "reg_6/reg_one_1/w_n11_n27#" 6.592
cap "mux_8bit_2/in1_6" "reg_6/reg_one_1/a_33_32#" 5.115
cap "rx_addrH6" "mux_8bit_2/mux_one_6/sel" 51.73
cap "reg_6/reg_one_1/w_n11_n27#" "mux_8bit_2/in1_6" 48.9529
cap "mux_8bit_2/in0_6" "mux_8bit_2/mux_one_6/2mux_nr_0/in0" 34.083
cap "reg_6/reg_one_1/Vdd!" "reg_6/reg_one_1/a_4_n13#" -7.10543e-15
cap "rx_addrH6" "mux_8bit_2/mux_one_6/2mux_nr_0/in0" 25.266
cap "mux_8bit_2/in0_6" "reg_6/reg_one_1/w" 58.7
cap "mux_8bit_2/in0_6" "mux_8bit_2/mux_one_6/GND!" 16.402
cap "reg_6/port60" "mux_8bit_2/in0_6" 3.171
cap "reg_6/reg_one_1/Vdd!" "reg_6/reg_one_1/a_33_32#" -7.10543e-15
cap "mux_8bit_2/mux_one_6/2mux_nr_0/in1" "mux_8bit_2/mux_one_6/GND!" 1.42109e-14
cap "rx_addrH6" "reg_6/reg_one_1/w" 51.73
cap "rx_addrH6" "reg_6/port60" 3.3
cap "rx_addrH6" "mux_8bit_2/mux_one_6/GND!" 6.677
cap "mux_8bit_2/mux_one_6/inv2_1/a_1_8#" "mux_8bit_2/in0_6" 4.95
cap "mux_8bit_2/mux_one_6/inv2_2/GND!" "mux_8bit_2/in0_6" 2.035
cap "mux_8bit_2/in1_6" "reg_6/reg_one_1/w" 97.0214
cap "mux_8bit_2/mux_one_6/Vdd!" "mux_8bit_2/mux_one_6/2mux_nr_0/in0" -2.27374e-13
cap "mux_8bit_2/in1_6" "mux_8bit_2/mux_one_6/GND!" 2.035
cap "rx_addrH6" "mux_8bit_2/mux_one_6/inv2_2/GND!" 16.173
cap "reg_6/reg_one_1/tmp" "mux_8bit_2/in1_6" -4.818
cap "reg_6/reg_one_1/tmp" "reg_6/reg_one_1/w_n11_n27#" -7.10543e-15
cap "rx_addrH6" "mux_8bit_2/in0_6" 15.205
cap "reg_6/reg_one_1/Vdd!" "reg_6/reg_one_1/w" 3.55271e-15
cap "reg_6/reg_one_1/Vdd!" "reg_6/port60" -7.10543e-15
cap "reg_6/reg_one_1/a_4_n13#" "mux_8bit_2/in0_6" -1.152
cap "reg_6/reg_one_1/w_n11_n27#" "reg_6/port60" 3.55271e-15
cap "mux_8bit_2/mux_one_6/GND!" "reg_7/r0" 165.587
cap "rx_addrH6" "reg_7/r0" 13.352
cap "rx_addrH6" "reg_7/port60" 4.972
cap "wz_addrH6" "mux_8bit_2/mux_one_6/GND!" 67.654
cap "reg_7/reg_one_1/Vdd!" "reg_7/in6" 56.544
cap "wz_addrH6" "reg_7/reg_one_1/a_54_5#" 4.828
cap "wz_addrH6" "reg_7/r0" 19.78
cap "wz_addrH6" "reg_7/port60" 6.6
cap "mux_8bit_2/mux_one_6/2mux_nr_0/a_n17_n11#" "mux_8bit_2/mux_one_6/GND!" 3.55271e-15
cap "reg_7/reg_one_1/r0" "rx_addrH6" 2.22
cap "reg_7/reg_one_1/port1" "rx_addrH6" 4.125
cap "rx_addrH6" "reg_7/reg_one_1/a_4_n13#" 92.333
cap "wz_addrH6" "reg_7/reg_one_1/r0" 4.948
cap "wz_addrH6" "reg_7/reg_one_1/a_4_n13#" 27.497
cap "rx_addrH6" "reg_7/GND!" 51.73
cap "reg_7/reg_one_1/Vdd!" "rx_addrH6" 51.73
cap "rx_addrH6" "reg_7/reg_one_1/r1" 56.054
cap "reg_7/in6" "mux_8bit_2/mux_one_6/GND!" 331.401
cap "rx_addrH6" "reg_7/reg_one_1/tmp" 4.44
cap "reg_7/in6" "rx_addrH6" -7.238
cap "wz_addrH6" "reg_7/GND!" 58.7
cap "reg_7/reg_one_1/Vdd!" "reg_7/r0" -9.768
cap "reg_7/in6" "reg_7/r0" 190.251
cap "reg_7/reg_one_1/Vdd!" "wz_addrH6" 162.612
cap "wz_addrH6" "reg_7/reg_one_1/r1" 58.7
cap "wz_addrH6" "reg_7/reg_one_1/tmp" 4.948
cap "wz_addrH6" "reg_7/in6" -6.325
cap "rx_addrH6" "reg_7/reg_one_1/a_21_n13#" 2.97
cap "reg_7/reg_one_1/w_n11_n27#" "rx_addrH6" 41.371
cap "rx_addrH6" "reg_7/reg_one_1/r0" 2.104
cap "mux_8bit_2/mux_one_6/2mux_nr_0/out" "reg_7/in6" 85.4219
cap "rx_addrH6" "mux_8bit_2/mux_one_6/GND!" 59.427
subcap "rx_addrH6" -651.935
cap "addsub_2/xor_6/a_89_n31#" "reg_7/port60" 2.424
cap "wz_addrH6" "reg_7/reg_one_1/Vdd!" -2.417
cap "reg_7/port60" "addsub_2/xor_6/b" 89.2933
cap "wz_addrH6" "addsub_2/addsub_one_6/Vdd!" 11.825
cap "reg_7/port60" "addsub_2/b6" 27.728
cap "reg_7/port60" "reg_7/reg_one_1/w" 118.792
cap "reg_7/port60" "addsub_2/xor_6/a_61_n31#" 2.424
cap "reg_7/port60" "addsub_2/addsub_one_6/b" 36.877
cap "wz_addrH6" "addsub_2/xor_6/b" 11.825
cap "reg_7/port60" "reg_7/reg_one_1/w_n11_n27#" 121.23
cap "wz_addrH6" "addsub_2/b6" 5.939
cap "wz_addrH6" "reg_7/reg_one_1/w" 58.7
cap "reg_7/port60" "addsub_2/xor_6/a_61_n1#" 174.249
cap "addsub_2/xor_6/a_61_n31#" "addsub_2/b6" -1.13687e-13
cap "reg_7/port60" "addsub_2/addsub_one_6/Vdd!" 127.516
cap "reg_7/port60" "reg_7/reg_one_1/w_n11_n27#" -0.762
cap "wz_addrH6" "reg_7/reg_one_1/w_n11_n27#" 8.24
subcap "a_2516_745#" -30.357
cap "latch_6/latch_one_6/a_n5_n54#" "addsub_2/s6" 19.2392
cap "addsub_2/GND!" "addsub_2/s6" 76.9567
cap "wz_addrH6" "addsub_2/addsub_one_6/Vdd!" 22.705
cap "wz_addrH6" "addsub_2/addsub_one_6/GND!" 34.459
cap "addsub_2/addsub_one_6/b" "addsub_2/addsub_one_6/GND!" -2.27374e-13
cap "wz_addrH6" "addsub_2/s6" 50.259
cap "wz_addrH6" "addsub_2/addsub_one_6/GND!" 4.95
cap "latch_6/latch_one_6/Vdd!" "addsub_2/s6" -12.402
cap "wz_addrH6" "addsub_2/addsub_one_6/a_35_n41#" 19.78
cap "wz_addrH6" "addsub_2/GND!" 4.95
cap "addsub_2/addsub_one_6/GND!" "addsub_2/addsub_one_6/a_35_n41#" -1.13687e-13
subcap "a_2516_745#" -103.553
cap "staticizer_3/staticizer_one_6/out" "latch_6/latch_one_6/a_30_n35#" 1.88
cap "latch_6/latch_one_6/GND!" "staticizer_3/staticizer_one_6/out" 58.7
cap "staticizer_3/staticizer_one_6/out" "latch_6/c" 58.7
cap "staticizer_3/staticizer_one_6/out" "latch_6/latch_one_6/Vdd!" 169.606
cap "staticizer_3/staticizer_one_6/out" "latch_6/latch_one_6/c" 2.96
cap "staticizer_3/staticizer_one_6/out" "staticizer_3/staticizer_one_6/a_77_n45#" 5.115
cap "addsub_2/s6" "addsub_2/GND!" 19.2392
cap "latch_6/GND!" "staticizer_3/staticizer_one_6/out" 58.7
cap "latch_6/c" "latch_6/out6" 9.252
cap "latch_6/latch_one_6/a_n5_n54#" "addsub_2/s6" 57.7175
cap "latch_6/latch_one_6/GND!" "latch_6/out6" 10.156
cap "latch_6/latch_one_6/Vdd!" "latch_6/out6" 107.428
cap "staticizer_3/staticizer_one_6/out" "staticizer_3/staticizer_one_6/a_60_n45#" 75.3524
cap "latch_6/latch_one_6/Vdd!" "addsub_2/s6" 19.399
cap "staticizer_3/staticizer_one_6/out" "staticizer_3/c" 58.7
cap "staticizer_3/staticizer_one_6/a_60_n45#" "latch_6/out6" 150.065
cap "staticizer_3/staticizer_one_6/out" "latch_6/latch_one_6/a_12_n54#" 9.708
cap "latch_6/c" "latch_6/latch_one_6/Vdd!" 1070.42
cap "latch_6/latch_one_6/GND!" "latch_6/latch_one_6/Vdd!" 5.50671e-14
cap "staticizer_3/staticizer_one_6/out" "staticizer_3/staticizer_one_6/c" 2.844
cap "latch_6/latch_one_6/GND!" "staticizer_3/staticizer_one_6/a_60_n45#" 8.52651e-14
cap "staticizer_3/staticizer_one_6/out" "latch_6/out6" 7.047
cap "staticizer_3/staticizer_one_6/c" "latch_6/out6" -7.10543e-15
cap "latch_6/latch_one_6/Vdd!" "latch_6/latch_one_6/a_12_n54#" 1.13687e-13
cap "staticizer_3/staticizer_one_6/out" "addsub_2/s6" 6.404
cap "latch_6/latch_one_6/a_n5_n54#" "staticizer_3/staticizer_one_6/out" 59.464
subcap "addr_out6" -79.48
cap "staticizer_3/staticizer_one_6/out" "latch_7/in6" 23.087
cap "staticizer_3/staticizer_one_6/out" "staticizer_3/staticizer_one_6/a_60_n45#" 0.709429
cap "staticizer_3/staticizer_one_6/out" "staticizer_3/staticizer_one_6/a_77_n45#" 2.728
cap "latch_7/latch_one_6/a_n5_n54#" "latch_7/latch_one_6/Vdd!" -1.13687e-13
cap "staticizer_4/staticizer_one_6/a_60_n45#" "latch_7/latch_one_6/GND!" -7.10543e-15
cap "latch_7/latch_one_6/a_12_n54#" "latch_7/latch_one_6/Vdd!" 1.13687e-13
cap "latch_7/in6" "staticizer_3/staticizer_one_6/Vdd!" 11.463
cap "latch_7/out6" "latch_7/latch_one_6/Vdd!" 107.428
cap "latch_7/latch_one_6/a_n5_n54#" "latch_7/in6" 57.7175
cap "staticizer_3/staticizer_one_6/a_77_n45#" "staticizer_3/staticizer_one_6/Vdd!" 2.84217e-14
cap "latch_7/latch_one_6/GND!" "latch_7/latch_one_6/a_n5_n54#" 2.84217e-14
cap "staticizer_3/staticizer_one_6/out" "staticizer_3/staticizer_one_6/Vdd!" 6.001
cap "latch_7/out6" "latch_7/c" 9.252
cap "latch_7/c" "latch_7/latch_one_6/Vdd!" 1070.42
cap "latch_7/out6" "latch_7/latch_one_6/GND!" 10.156
cap "latch_7/in6" "latch_7/latch_one_6/Vdd!" 152.661
cap "latch_7/in6" "staticizer_3/staticizer_one_6/w_54_n57#" 10.127
cap "staticizer_3/staticizer_one_6/out" "staticizer_3/staticizer_one_6/w_54_n57#" 8.272
cap "staticizer_4/staticizer_one_6/a_60_n45#" "latch_7/out6" 150.065
cap "latch_7/latch_one_6/GND!" "latch_7/in6" 6.956
subcap "ry_addrH6" -898.053
subcap "addr_out14" -310.522
cap "latch_8/latch_one_6/Vdd!" "staticizer_5/in6" -1.162
cap "staticizer_4/staticizer_one_6/Vdd!" "staticizer_4/staticizer_one_6/out" -5.68434e-14
cap "staticizer_4/staticizer_one_6/out" "latch_8/in6" 57.7175
cap "latch_8/in6" "latch_8/latch_one_6/a_n5_n54#" 57.7175
cap "latch_8/latch_one_6/GND!" "latch_8/in6" 6.956
cap "latch_8/latch_one_6/Vdd!" "latch_8/latch_one_6/a_12_n54#" 1.13687e-13
cap "staticizer_4/staticizer_one_6/Vdd!" "latch_8/in6" 11.463
cap "latch_8/c" "staticizer_5/in6" -0.42
cap "latch_8/latch_one_6/Vdd!" "latch_8/latch_one_6/a_n5_n54#" -1.13687e-13
cap "staticizer_4/staticizer_one_6/Vdd!" "staticizer_4/staticizer_one_6/a_77_n45#" 1.13687e-13
cap "staticizer_4/staticizer_one_6/a_60_n45#" "staticizer_4/staticizer_one_6/w_54_n57#" 5.68434e-14
cap "latch_8/latch_one_6/Vdd!" "latch_8/in6" 152.661
cap "staticizer_4/staticizer_one_6/w_54_n57#" "latch_8/in6" 10.127
cap "latch_8/latch_one_6/GND!" "latch_8/latch_one_6/a_n5_n54#" 2.84217e-14
subcap "addr_out14" -37.648
cap "latch_8/latch_one_6/Vdd!" "latch_8/c" 1070.42
cap "staticizer_5/staticizer_one_6/a_60_n45#" "latch_8/latch_one_6/GND!" -7.10543e-15
cap "staticizer_5/in6" "latch_8/latch_one_6/Vdd!" 107.428
cap "staticizer_5/in6" "latch_8/latch_one_6/GND!" 10.156
cap "staticizer_5/in6" "latch_8/c" 9.252
cap "staticizer_5/staticizer_one_6/a_60_n45#" "staticizer_5/in6" 150.065
subcap "a_n24_920#" -96.28
cap "staticizer_1/staticizer_one_5/a_60_n45#" "staticizer_1/staticizer_one_5/Vdd!" -1.13687e-13
cap "staticizer_1/in5" "staticizer_1/staticizer_one_5/w_54_n57#" 18.828
cap "latch_4/latch_one_5/c" "staticizer_1/staticizer_one_5/w_54_n57#" 18.4696
cap "staticizer_1/staticizer_one_5/Vdd!" "staticizer_1/staticizer_one_5/c" -1.42109e-14
cap "staticizer_1/in5" "latch_4/latch_one_5/c" 0.492
cap "staticizer_1/staticizer_one_5/a_77_n45#" "staticizer_1/staticizer_one_5/Vdd!" -5.68434e-14
cap "staticizer_1/staticizer_one_5/Vdd!" "staticizer_1/staticizer_one_5/out" -7.10543e-15
cap "staticizer_1/staticizer_one_5/Vdd!" "staticizer_1/staticizer_one_5/w_54_n57#" 1.13687e-13
cap "staticizer_1/in5" "staticizer_1/staticizer_one_5/Vdd!" 36.89
cap "latch_4/latch_one_5/c" "staticizer_1/staticizer_one_5/Vdd!" 1073
cap "staticizer_1/in5" "staticizer_1/staticizer_one_5/a_60_n45#" 57.7175
subcap "a_109_920#" -139.568
subcap "data_in5" -33.471
subcap "rx5" -1770.33
cap "latch_0/latch_one_5/a_n5_n54#" "latch_0/latch_one_5/GND!" 5.68434e-14
cap "latch_0/in5" "latch_0/Vdd!" 26.825
cap "latch_4/latch_one_5/Vdd!" "latch_4/Vdd!" 4.44089e-16
cap "latch_0/latch_one_5/c" "latch_0/latch_one_5/GND!" 18.4696
cap "latch_0/latch_one_5/c" "latch_0/out5" 0.492
cap "latch_0/latch_one_5/c" "latch_4/in5" 58.7
cap "latch_0/out5" "latch_0/latch_one_5/GND!" 18.828
cap "latch_0/latch_one_5/GND!" "latch_4/in5" 59.993
cap "latch_0/latch_one_5/c" "staticizer_0/staticizer_one_5/Vdd!" 1073
cap "latch_0/in5" "latch_0/latch_one_5/a_n5_n54#" 32.9814
cap "latch_4/in5" "latch_4/Vdd!" 469.438
cap "latch_0/Vdd!" "latch_4/in5" 58.7
cap "latch_0/latch_one_5/GND!" "staticizer_0/staticizer_one_5/Vdd!" -0.246
cap "latch_0/out5" "staticizer_0/staticizer_one_5/Vdd!" 36.89
cap "latch_4/in5" "staticizer_0/staticizer_one_5/Vdd!" 37.42
cap "latch_0/out5" "staticizer_0/staticizer_one_5/a_60_n45#" 57.7175
cap "latch_4/latch_one_5/a_n5_n54#" "latch_4/in5" 69.3743
cap "latch_0/Vdd!" "staticizer_0/staticizer_one_5/Vdd!" 4.44089e-16
cap "staticizer_0/staticizer_one_5/a_60_n45#" "staticizer_0/staticizer_one_5/Vdd!" -4.648
cap "staticizer_0/staticizer_one_5/Vdd!" "staticizer_0/staticizer_one_5/c" 1.42109e-14
cap "staticizer_0/staticizer_one_5/Vdd!" "staticizer_0/staticizer_one_5/w_54_n57#" -0.984
cap "staticizer_0/staticizer_one_5/Vdd!" "staticizer_0/staticizer_one_5/a_60_n45#" -2.744
cap "staticizer_0/staticizer_one_5/a_77_n45#" "staticizer_0/staticizer_one_5/Vdd!" -5.68434e-14
cap "shift_0/a5" "wz5" 58.7
cap "shift_0/a5" "shift_0/shift_one_5/ad" 125.762
cap "staticizer_0/staticizer_one_5/out" "wz5" 21.255
cap "shift_0/shift_one_5/ad" "wz5" 58.7
cap "shift_0/a5" "staticizer_0/staticizer_one_5/Vdd!" -12.11
cap "staticizer_0/staticizer_one_5/Vdd!" "staticizer_0/staticizer_one_5/out" -7.10543e-15
cap "shift_0/a5" "staticizer_0/staticizer_one_5/c" 76.935
cap "shift_0/a5" "staticizer_0/staticizer_one_5/w_54_n57#" 73.425
cap "staticizer_0/staticizer_one_5/Vdd!" "wz5" 8.005
cap "staticizer_0/staticizer_one_5/Vdd!" "latch_0/out5" 17.934
cap "staticizer_0/staticizer_one_5/w_54_n57#" "wz5" 6.22
cap "shift_0/shift_one_5/Vdd!" "wz5" 8.24
cap "latch_0/out5" "staticizer_0/staticizer_one_5/a_60_n45#" 31.249
cap "shift_0/u" "rx5" 58.7
cap "wz5" "shift_0/shift_one_5/Vdd!" 91.858
cap "shift_0/shift_one_5/inv_2/GND!" "rx5" 11.43
cap "wz5" "shift_0/Vdd!" 58.7
cap "rx5" "shift_0/shift_one_5/Vdd!" 7.239
cap "shift_0/shift_one_5/inv_2/in" "rx5" 14.74
cap "shift_0/GND!" "wz5" 58.7
cap "shift_0/shift_one_5/m1_n60_n65#" "wz5" 11.825
cap "shift_0/Vdd!" "rx5" 58.7
cap "shift_0/u" "wz5" 58.7
cap "shift_0/GND!" "rx5" 58.7
cap "shift_0/shift_one_5/inv_2/GND!" "wz5" 21.418
cap "shift_0/shift_one_5/inv_2/out" "wz5" 25.522
cap "shift_0/shift_one_5/inv_3/in" "wz5" 8.599
cap "shift_0/o5" "latch_3/latch_one_5/GND!" 30.043
cap "shift_0/shift_one_5/inv_3/Vdd!" "shift_0/o5" 1.162
cap "latch_3/latch_one_5/a_n5_n54#" "wz5" 30.853
cap "shift_0/o5" "wz5" 2.184
cap "wz5" "latch_3/latch_one_5/GND!" 66.689
cap "shift_0/shift_one_5/inv_3/Vdd!" "wz5" 72.651
cap "latch_3/latch_one_5/a_n5_n54#" "latch_3/latch_one_5/Vdd!" -1.13687e-13
cap "rx5" "shift_0/o5" 20.945
cap "latch_3/latch_one_5/Vdd!" "shift_0/o5" 9.594
cap "rx5" "latch_3/latch_one_5/GND!" 107.383
cap "wz5" "latch_3/latch_one_5/a_12_n54#" 4.95
cap "latch_3/latch_one_5/c" "wz5" 1.248
cap "rx5" "shift_0/shift_one_5/inv_3/Vdd!" 7.239
cap "latch_3/latch_one_5/Vdd!" "wz5" 64.715
cap "rx5" "latch_3/latch_one_5/c" 3.12
cap "shift_0/shift_one_5/inv_3/GND!" "wz5" 3.152
cap "rx5" "latch_3/latch_one_5/Vdd!" 58.7
cap "wz5" "shift_0/shift_one_6/s" 58.7
cap "shift_0/o5" "shift_0/shift_one_5/inv_3/in" 57.7175
cap "rx5" "shift_0/shift_one_5/inv_3/GND!" 6.096
cap "latch_3/latch_one_5/a_n5_n54#" "shift_0/o5" 57.7175
cap "rx5" "shift_0/shift_one_6/s" 58.7
cap "fblock_0/fblock_one_5/2mux_nr_2/in1" "latch_3/out5" 9.35
cap "latch_3/latch_one_5/c" "latch_3/latch_one_5/GND!" 2.84217e-14
cap "fblock_0/fblock_one_5/2mux_nr_2/in0" "fblock_0/a5" 4.389
cap "fblock_0/a5" "latch_3/out5" 4.948
cap "fblock_0/a5" "fblock_0/fblock_one_5/2mux_nr_2/a_n17_n11#" 11.004
cap "latch_3/out5" "fblock_0/fblock_one_5/inv_0/in" 19.302
cap "fblock_0/g3" "latch_3/out5" 58.7
cap "fblock_0/fblock_one_5/2mux_nr_2/s" "fblock_0/a5" 0.486
cap "latch_3/latch_one_5/c" "fblock_0/a5" 78.258
cap "fblock_0/a5" "fblock_0/fblock_one_5/inv_0/Vdd!" 82.685
cap "fblock_0/fblock_one_5/2mux_nr_2/in0" "latch_3/out5" 7.975
cap "latch_3/out5" "fblock_0/fblock_one_5/2mux_nr_2/a_n17_n11#" 14.683
cap "fblock_0/fblock_one_5/inv_0/GND!" "fblock_0/a5" 56.9869
cap "fblock_0/a5" "fblock_0/GND!" 58.7
cap "fblock_0/a5" "latch_3/latch_one_5/GND!" 0.083
cap "fblock_0/a5" "fblock_0/g2" 58.7
cap "latch_3/latch_one_5/c" "latch_3/out5" 140.424
cap "latch_3/latch_one_5/Vdd!" "latch_3/latch_one_5/a_12_n54#" -3.55271e-15
cap "fblock_0/fblock_one_5/2mux_nr_2/in1" "fblock_0/a5" 5.115
cap "latch_3/latch_one_5/Vdd!" "latch_3/out5" 0.959
cap "fblock_0/a5" "fblock_0/fblock_one_5/inv_0/in" 9.081
cap "fblock_0/fblock_one_5/inv_0/GND!" "latch_3/out5" 38.323
cap "fblock_0/GND!" "latch_3/out5" 58.7
cap "latch_3/latch_one_5/c" "latch_3/latch_one_5/Vdd!" -8.88178e-16
cap "fblock_0/g3" "fblock_0/a5" 542.798
cap "fblock_0/g2" "latch_3/out5" 58.7
cap "latch_3/out5" "latch_3/latch_one_5/GND!" 1.209
cap "rx5" "fblock_0/fblock_one_5/f" 85.724
cap "rx5" "fblock_0/fblock_one_6/inv_3/Vdd!" 58.7
cap "fblock_0/f5" "latch_1/latch_one_5/GND!" 12.326
cap "fblock_0/f5" "latch_1/latch_one_5/Vdd!" 6.108
cap "fblock_0/f5" "wz5" 18.093
cap "wz5" "latch_1/latch_one_5/c" 4.324
cap "latch_1/latch_one_5/Vdd!" "fblock_0/fblock_one_6/inv_3/Vdd!" 1341.25
cap "rx5" "fblock_0/fblock_one_5/inv_0/in" 2.844
cap "wz5" "fblock_0/fblock_one_6/inv_3/Vdd!" 58.7
cap "rx5" "fblock_0/fblock_one_6/g0" 58.7
cap "rx5" "latch_1/latch_one_5/a_n5_n54#" 7.807
cap "fblock_0/fblock_one_5/inv_0/in" "fblock_0/fblock_one_5/inv_0/GND!" 5.68434e-14
cap "rx5" "fblock_0/fblock_one_6/g1" 58.7
cap "wz5" "latch_1/latch_one_5/a_12_n54#" 9.731
cap "fblock_0/f5" "fblock_0/fblock_one_6/inv_3/Vdd!" 12.684
cap "wz5" "fblock_0/fblock_one_5/inv_0/in" 4.123
cap "fblock_0/fblock_one_6/g0" "wz5" 58.7
cap "wz5" "latch_1/latch_one_5/a_n5_n54#" 43.4
cap "rx5" "latch_1/latch_one_5/GND!" 58.7
cap "wz5" "fblock_0/fblock_one_6/g1" 58.7
cap "rx5" "latch_1/latch_one_5/Vdd!" 103.828
cap "fblock_0/f5" "latch_1/latch_one_5/a_n5_n54#" 57.7175
cap "wz5" "fblock_0/fblock_one_5/inv_0/GND!" 20.977
cap "fblock_0/fblock_one_5/f" "fblock_0/fblock_one_5/inv_0/in" 2.84217e-14
cap "rx5" "fblock_0/f5" 13.492
cap "wz5" "latch_1/latch_one_5/GND!" 69.742
cap "wz5" "latch_1/latch_one_5/Vdd!" 58.7
subcap "ry5" -2610.32
cap "rx5" "addsub_0/xor_5/GND!" 12.213
cap "latch_1/latch_one_5/a_30_n54#" "latch_1/out5" 1.524
cap "latch_1/latch_one_5/c" "latch_1/out5" 144.632
cap "rx5" "latch_1/latch_one_5/a_12_n54#" 4.948
cap "latch_1/out5" "addsub_0/xor_5/GND!" 11.825
cap "rx5" "latch_1/out5" 9.182
cap "latch_1/latch_one_5/a_n5_n54#" "latch_1/out5" 15.975
cap "rx5" "addsub_0/sub" 11.825
cap "latch_1/out5" "latch_1/latch_one_5/GND!" 3.821
cap "addsub_0/sub" "latch_1/out5" 11.825
cap "latch_1/latch_one_5/GND!" "latch_1/out5" 2.361
cap "addsub_0/b5" "addsub_0/xor_5/GND!" 93.4474
cap "rx5" "addsub_0/b5" 2.764
cap "rx5" "addsub_0/xor_5/Vdd!" 8.496
cap "addsub_0/b5" "addsub_0/xor_5/GND!" 4.36
cap "rx5" "latch_1/latch_one_5/Vdd!" -1.405
cap "rx5" "latch_1/latch_one_5/Vdd!" -4.367
cap "rx5" "latch_1/latch_one_5/a_30_n35#" 4.828
cap "rx5" "latch_1/latch_one_5/c" 58.7
cap "rx5" "addsub_0/xor_5/GND!" 11.825
cap "latch_1/out5" "latch_1/latch_one_5/Vdd!" 1.221
cap "rx5" "latch_1/latch_one_5/a_n5_n54#" 4.948
cap "ry5" "addsub_0/addsub_one_6/GND!" 24.188
cap "as_cout" "addsub_0/addsub_one_6/a_11_n41#" 19.14
cap "wz5" "addsub_0/addsub_one_5/a_35_n41#" 65.763
cap "as_cout" "addsub_0/addsub_one_5/a_78_n41#" 4.204
cap "addsub_0/addsub_one_5/cout" "as_cout" 14.329
cap "as_cout" "addsub_0/addsub_one_6/a" 8.408
cap "as_cout" "addsub_0/addsub_one_5/a_35_n41#" 4.204
cap "as_cout" "addsub_0/addsub_one_6/a_35_n41#" 10.65
cap "wz5" "addsub_0/addsub_one_6/Vdd!" 11.825
cap "ry5" "addsub_0/addsub_one_5/Vdd!" 16.992
cap "as_cout" "addsub_0/addsub_one_6/b" 4.204
cap "addsub_0/addsub_one_5/cout" "ry5" 11.138
cap "addsub_0/addsub_one_5/GND!" "wz5" 0.308
cap "addsub_0/addsub_one_6/GND!" "wz5" 18.211
cap "as_cout" "addsub_0/addsub_one_6/GND!" 56.288
cap "as_cout" "addsub_0/addsub_one_5/GND!" 16.98
cap "ry5" "addsub_0/addsub_one_6/Vdd!" 11.825
cap "as_cout" "addsub_0/addsub_one_6/cin" 4.204
cap "as_cout" "addsub_0/addsub_one_6/a_29_n41#" 2.1
cap "addsub_0/addsub_one_5/Vdd!" "rx5" 9.22
cap "addsub_0/addsub_one_5/s" "as_cout" 41.11
cap "addsub_0/addsub_one_5/Vdd!" "wz5" 38.922
subcap "a_841_921#" -44.126
cap "latch_2/latch_one_5/a_30_n54#" "latch_2/out5" 2.592
cap "addsub_0/addsub_one_5/a_35_n41#" "latch_2/out5" -1.814
cap "ry5" "latch_2/latch_one_5/Vdd!" 58.7
cap "reg_0/reg_one_2/r0" "latch_2/out5" 63.6875
cap "ry5" "latch_2/latch_one_5/c" 81.378
cap "addsub_0/addsub_one_6/GND!" "addsub_0/s5" 76.9567
cap "latch_2/latch_one_5/a_n5_n54#" "addsub_0/s5" 57.7175
cap "ry5" "addsub_0/addsub_one_6/cin" 1.486
cap "addsub_0/addsub_one_6/GND!" "latch_2/out5" 19.247
cap "latch_2/latch_one_5/a_n5_n54#" "latch_2/out5" 12.196
cap "ry5" "latch_2/latch_one_5/GND!" 110.895
cap "addsub_0/s5" "latch_2/out5" 4.948
cap "addsub_0/s5" "latch_2/latch_one_5/Vdd!" 19.399
cap "addsub_0/addsub_one_5/GND!" "latch_2/out5" 3.399
cap "latch_2/latch_one_5/Vdd!" "latch_2/out5" 59.921
cap "latch_2/latch_one_5/c" "latch_2/out5" 297.857
cap "ry5" "reg_0/reg_one_2/r0" 17.308
cap "latch_2/latch_one_5/a_12_n54#" "latch_2/out5" 12.473
cap "ry5" "addsub_0/addsub_one_6/GND!" 20.633
cap "latch_2/latch_one_5/GND!" "latch_2/out5" 90.233
cap "reg_0/port51" "reg_0/w" 127.744
cap "reg_0/port50" "reg_0/w" 268.25
cap "reg_0/reg_one_2/w_n11_n27#" "reg_0/port50" 127.375
cap "reg_0/port51" "reg_0/reg_one_2/w_n11_n27#" 121.694
cap "reg_0/reg_one_2/Vdd!" "reg_0/port51" 58.7
cap "reg_0/port51" "reg_0/reg_one_2/r1" 64.004
cap "reg_0/port51" "reg_0/reg_one_2/r0" 23.94
cap "reg_1/port51" "reg_1/reg_one_2/w_n11_n27#" 121.694
cap "reg_1/port50" "reg_1/reg_one_2/tmp" 4.694
cap "reg_1/reg_one_2/a_21_n13#" "reg_1/port50" 2.238
cap "reg_1/reg_one_2/Vdd!" "reg_1/port50" 75.185
cap "reg_1/port51" "reg_1/reg_one_2/Vdd!" 58.7
cap "reg_1/port51" "reg_1/port50" 3.85
cap "reg_1/reg_one_2/a_4_n13#" "reg_1/port50" 118.494
cap "reg_1/port50" "reg_1/reg_one_2/r1" 60.064
cap "reg_1/port50" "reg_1/w" 125.763
cap "reg_1/port51" "reg_1/reg_one_2/r1" 64.004
cap "reg_1/port51" "reg_1/w" 127.744
cap "reg_1/reg_one_2/r0" "reg_1/port50" 21.144
cap "reg_1/reg_one_2/r0" "reg_1/port51" 48.664
cap "reg_1/port50" "reg_1/reg_one_2/w_n11_n27#" 198.775
cap "reg_1/port50" "reg_2/reg_one_2/Vdd!" 16.485
cap "reg_2/r1" "reg_2/port51" 58.7
cap "reg_2/reg_one_2/w_n11_n27#" "reg_2/port51" 121.694
cap "reg_2/port51" "reg_2/reg_one_2/r1" 5.304
cap "reg_2/Vdd!" "reg_1/port50" 58.7
cap "reg_1/port50" "reg_2/reg_one_2/a_21_n13#" 1.248
cap "reg_2/reg_one_2/r0" "reg_1/port50" 21.144
cap "reg_2/r1" "reg_2/reg_one_2/w_n11_n27#" 3.55271e-15
cap "reg_1/port50" "reg_2/w" 92.2312
cap "reg_1/port50" "reg_2/port51" 3.85
cap "reg_2/Vdd!" "reg_2/port51" 58.7
cap "reg_2/reg_one_2/a_21_n13#" "reg_1/port50" 0.99
cap "reg_2/reg_one_2/r0" "reg_2/port51" 48.664
cap "reg_2/r1" "reg_2/reg_one_2/Vdd!" 1.77636e-15
cap "reg_1/port50" "reg_2/reg_one_2/a_4_n13#" 118.494
cap "reg_1/port50" "reg_2/reg_one_2/tmp" 4.694
cap "reg_2/r1" "reg_1/port50" 58.7
cap "reg_2/reg_one_2/w_n11_n27#" "reg_1/port50" 135.088
cap "reg_1/port50" "reg_2/reg_one_2/r1" 1.364
cap "reg_2/w" "reg_2/port51" 94.2122
cap "reg_2/port50" "reg_3/reg_one_2/Vdd!" 15.954
cap "reg_2/port50" "reg_2/w" 33.5312
cap "reg_3/r1" "reg_3/reg_one_2/Vdd!" 1.77636e-15
cap "reg_3/Vdd!" "reg_2/port51" 58.7
cap "reg_2/port50" "reg_3/reg_one_2/a_4_n13#" 118.494
cap "reg_3/r1" "reg_2/port51" 58.7
cap "reg_3/w" "reg_3/port51" 5.072
cap "reg_2/port50" "reg_3/reg_one_2/a_21_n13#" 0.99
cap "reg_3/reg_one_2/r0" "reg_2/port50" 21.144
cap "reg_2/w" "reg_2/port51" 33.5312
cap "reg_2/port50" "reg_3/reg_one_2/w_n11_n27#" 63.11
cap "reg_2/port50" "reg_3/reg_one_2/r1" 1.364
cap "reg_2/port50" "reg_3/port51" 3.85
cap "reg_3/reg_one_2/w_n11_n27#" "reg_3/r1" 3.55271e-15
cap "reg_3/reg_one_2/r0" "reg_2/port51" 48.664
cap "reg_2/port50" "reg_2/reg_one_2/w_n11_n27#" 63.6875
cap "reg_3/reg_one_2/w_n11_n27#" "reg_2/port51" 106.567
cap "reg_2/port50" "reg_3/port50" 8.58
cap "reg_3/reg_one_2/r1" "reg_2/port51" 5.304
cap "reg_2/port50" "reg_3/reg_one_2/a_21_n13#" 1.248
cap "reg_3/port51" "reg_2/port51" 73.199
cap "reg_3/reg_one_2/w_n11_n27#" "reg_3/port51" 1.628
cap "reg_3/reg_one_2/tmp" "reg_2/port50" 4.694
cap "reg_2/port50" "reg_3/Vdd!" 58.7
cap "reg_2/port50" "reg_3/r1" 58.7
subcap "wz_addrL5" -535.598
subcap "PCL_w_muxout5" -380.236
cap "mux_8bit_0/Vdd!" "mux_8bit_0/in0_5" 58.7
cap "mux_8bit_0/Vdd!" "reg_3/port51" 58.7
cap "mux_8bit_0/out5" "mux_8bit_0/sel" 0.84
cap "reg_3/reg_one_2/w_n11_n27#" "reg_3/port50" 135.615
cap "reg_3/reg_one_2/w_n11_n27#" "reg_3/port51" -1.039
cap "reg_3/w" "reg_3/port50" 125.763
cap "mux_8bit_0/sel" "mux_8bit_0/in0_5" 58.7
cap "mux_8bit_0/sel" "reg_3/port51" 58.7
cap "mux_8bit_0/out5" "mux_8bit_0/mux_one_5/inv2_2/GND!" 37.928
cap "reg_3/reg_one_2/w_n11_n27#" "reg_3/port51" 12.7375
cap "reg_3/w" "reg_3/port51" 127.744
cap "mux_8bit_0/mux_one_5/2mux_nr_0/in0" "mux_8bit_0/in0_5" 29.025
cap "mux_8bit_0/mux_one_5/inv2_1/a_1_8#" "mux_8bit_0/in0_5" 19.462
cap "reg_3/port50" "reg_3/reg_one_2/Vdd!" -2.898
cap "mux_8bit_0/in0_5" "mux_8bit_0/mux_one_5/inv2_2/GND!" 12.279
cap "reg_3/port51" "mux_8bit_0/mux_one_5/inv2_2/GND!" 63.013
cap "mux_8bit_0/out5" "mux_8bit_0/in0_5" 30.603
cap "reg_3/reg_one_2/w_n11_n27#" "reg_3/port50" -3.379
cap "mux_8bit_0/out5" "reg_3/port51" -10.01
cap "mux_8bit_0/mux_one_5/inv2_2/Vdd!" "mux_8bit_0/in0_5" 20.196
cap "reg_4/reg_one_2/Vdd!" "wz_addrL5" 73.616
cap "reg_4/reg_one_2/w_n11_n27#" "ry5" 106.567
cap "reg_4/reg_one_2/Vdd!" "ry5" 58.7
cap "mux_8bit_0/mux_one_5/inv2_1/GND!" "mux_8bit_0/out5" 366.202
cap "mux_8bit_0/GND!" "wz_addrL5" 58.7
cap "reg_4/port51" "reg_4/reg_one_2/w_n11_n27#" 1.628
cap "reg_4/w" "reg_4/port51" 5.072
cap "wz_addrL5" "reg_4/reg_one_2/r0" 21.028
cap "reg_4/reg_one_2/tmp" "wz_addrL5" 4.68
cap "mux_8bit_0/GND!" "ry5" 58.7
cap "reg_4/port50" "wz_addrL5" 9.229
cap "reg_4/port51" "wz_addrL5" 4.95
cap "reg_4/reg_one_2/r0" "ry5" 48.664
cap "mux_8bit_0/out5" "wz_addrL5" -6.325
cap "wz_addrL5" "mux_8bit_0/mux_one_5/inv2_1/a_1_8#" -1.132
cap "reg_4/port51" "ry5" 73.199
cap "mux_8bit_0/out5" "ry5" -17.369
cap "mux_8bit_0/GND!" "mux_8bit_0/out5" 35.82
cap "reg_4/reg_one_2/r1" "wz_addrL5" 59.948
cap "mux_8bit_0/out5" "reg_4/reg_one_2/r0" 195.199
cap "mux_8bit_0/mux_one_5/inv2_1/GND!" "wz_addrL5" 6.72
cap "reg_4/reg_one_2/a_4_n13#" "wz_addrL5" 47.175
cap "reg_4/reg_one_2/r1" "ry5" 64.004
cap "wz_addrL5" "reg_4/reg_one_2/w_n11_n27#" 76.564
cap "mux_8bit_0/mux_one_5/inv2_1/GND!" "ry5" -6.916
cap "mux_8bit_0/mux_one_5/inv2_1/GND!" "mux_8bit_0/GND!" -0.246
cap "addsub_1/Vdd!" "wz_addrL5" 11.825
cap "addsub_1/sub" "wz_addrL5" 7.975
cap "reg_4/reg_one_2/Vdd!" "wz_addrL5" -2.948
cap "addsub_1/b5" "addsub_1/sub" 9.2348
cap "reg_4/port50" "addsub_1/sub" 113.342
cap "addsub_1/xor_5/GND!" "addsub_1/b5" 43.698
cap "reg_4/w" "wz_addrL5" 58.7
cap "reg_4/port50" "addsub_1/addsub_one_5/Vdd!" 4.36
cap "reg_4/reg_one_2/w_n11_n27#" "wz_addrL5" -3.379
cap "addsub_1/Vdd!" "reg_4/port51" 11.825
cap "reg_4/port51" "addsub_1/sub" 11.825
cap "reg_4/reg_one_2/w_n11_n27#" "wz_addrL5" 8.24
cap "addsub_1/b5" "wz_addrL5" 7.975
cap "reg_4/port50" "wz_addrL5" -7.348
cap "reg_4/port50" "reg_4/reg_one_2/w_n11_n27#" 63.6875
cap "reg_4/port50" "addsub_1/b5" 36.385
cap "reg_4/w" "reg_4/port51" 127.744
cap "reg_4/port51" "reg_4/reg_one_2/w_n11_n27#" -1.039
cap "reg_4/reg_one_2/w_n11_n27#" "reg_4/port51" 12.7375
cap "reg_4/port51" "addsub_1/b5" 11.825
subcap "a_1716_921#" -30.357
cap "ry5" "addsub_1/addsub_one_6/GND!" 48.25
cap "addsub_1/s5" "latch_5/latch_one_5/a_n5_n54#" 19.2392
cap "addsub_1/addsub_one_5/a_78_n41#" "a_2510_1893#" 4.204
cap "a_2510_1893#" "addsub_1/addsub_one_6/a_29_n41#" 2.1
cap "a_2510_1893#" "addsub_1/addsub_one_6/cin" 18.533
cap "addsub_1/addsub_one_5/GND!" "a_2510_1893#" 16.98
cap "addsub_1/addsub_one_5/GND!" "wz_addrL5" 10.505
cap "addsub_1/addsub_one_6/GND!" "addsub_1/addsub_one_5/a_35_n41#" 5.68434e-14
cap "addsub_1/addsub_one_6/a" "a_2510_1893#" 8.408
cap "ry5" "addsub_1/addsub_one_6/Vdd!" -4.455
cap "addsub_1/s5" "addsub_1/addsub_one_6/GND!" 76.9567
cap "wz_addrL5" "addsub_1/addsub_one_5/Vdd!" 37.175
cap "a_2510_1893#" "addsub_1/addsub_one_6/a_35_n41#" 10.65
cap "a_2510_1893#" "addsub_1/addsub_one_6/a_11_n41#" 19.14
cap "addsub_1/s5" "latch_5/latch_one_5/Vdd!" -12.402
cap "a_2510_1893#" "addsub_1/addsub_one_6/GND!" 56.288
cap "addsub_1/addsub_one_6/GND!" "wz_addrL5" 55.484
cap "a_2510_1893#" "addsub_1/addsub_one_5/a_35_n41#" 4.204
cap "wz_addrL5" "addsub_1/addsub_one_5/a_35_n41#" 24.622
cap "a_2510_1893#" "addsub_1/addsub_one_6/b" 4.204
cap "ry5" "addsub_1/addsub_one_6/cin" 18.24
cap "addsub_1/s5" "a_2510_1893#" 41.11
cap "addsub_1/addsub_one_6/Vdd!" "wz_addrL5" -4.455
cap "ry5" "addsub_1/addsub_one_5/Vdd!" 13.563
subcap "a_1776_924#" -134.112
subcap "a_1716_921#" -105.445
cap "wz_addrL5" "staticizer_2/Vdd!" 58.7
cap "latch_5/latch_one_5/GND!" "latch_5/out5" 12.91
cap "latch_5/latch_one_5/Vdd!" "ry5" 58.7
cap "latch_5/latch_one_5/Vdd!" "staticizer_2/Vdd!" -1.476
cap "latch_5/latch_one_5/c" "ry5" 81.378
cap "wz_addrL5" "latch_5/out5" 13.304
cap "latch_5/latch_one_5/c" "staticizer_2/Vdd!" 1073
cap "latch_5/latch_one_5/Vdd!" "latch_5/out5" 65.558
cap "wz_addrL5" "staticizer_2/staticizer_one_5/a_77_n45#" 9.998
cap "latch_5/latch_one_5/c" "latch_5/out5" 7.95
cap "wz_addrL5" "addsub_1/s5" 4.324
cap "latch_5/latch_one_5/a_n5_n54#" "addsub_1/s5" 57.7175
cap "staticizer_2/Vdd!" "ry5" 58.7
cap "latch_5/latch_one_5/a_30_n54#" "wz_addrL5" 1.524
cap "staticizer_2/staticizer_one_5/a_60_n45#" "latch_5/out5" 200.087
cap "latch_5/latch_one_5/Vdd!" "addsub_1/s5" 19.399
cap "addsub_1/GND!" "addsub_1/s5" 19.2392
cap "latch_5/latch_one_5/a_12_n54#" "wz_addrL5" 9.731
cap "staticizer_2/staticizer_one_5/c" "latch_5/latch_one_5/GND!" -5.68434e-14
cap "wz_addrL5" "latch_5/latch_one_5/GND!" 154.337
cap "staticizer_2/Vdd!" "latch_5/out5" 11.412
cap "wz_addrL5" "staticizer_2/staticizer_one_5/c" 63.648
cap "wz_addrL5" "latch_5/latch_one_5/a_n5_n54#" 59.375
cap "latch_5/latch_one_5/c" "latch_5/latch_one_5/GND!" 13.8522
cap "latch_5/latch_one_5/Vdd!" "wz_addrL5" 58.7
cap "wz_addrL5" "latch_5/latch_one_5/c" 67.232
cap "ry5" "latch_5/latch_one_5/GND!" 181.284
cap "latch_5/latch_one_5/Vdd!" "latch_5/latch_one_5/c" -1.968
cap "staticizer_2/staticizer_one_5/c" "ry5" 76.935
cap "staticizer_2/Vdd!" "latch_5/latch_one_5/GND!" -0.984
cap "wz_addrL5" "staticizer_2/staticizer_one_5/a_60_n45#" 12.196
subcap "wz_addrH5" -920.539
subcap "m1_1909_894#" -380.236
cap "wz_addrL5" "staticizer_2/staticizer_one_5/a_77_n45#" 3.676
cap "mux_8bit_1/out5" "mux_8bit_1/sel" 0.84
cap "mux_8bit_1/mux_one_5/2mux_nr_0/in0" "mux_8bit_1/mux_one_5/inv2_2/Vdd!" -2.84217e-14
cap "mux_8bit_1/sel" "mux_8bit_1/in0_5" 58.7
cap "mux_8bit_1/mux_one_5/inv2_2/GND!" "mux_8bit_1/out5" 37.928
cap "wz_addrL5" "staticizer_2/staticizer_one_5/a_95_n45#" 4.212
cap "wz_addrL5" "staticizer_2/staticizer_one_5/Vdd!" 4.776
cap "mux_8bit_1/Vdd!" "mux_8bit_1/in0_5" 58.7
cap "mux_8bit_1/mux_one_5/inv2_2/GND!" "mux_8bit_1/in0_5" 18.437
cap "mux_8bit_1/out5" "ry5" -10.01
cap "mux_8bit_1/mux_one_5/2mux_nr_0/in0" "mux_8bit_1/in0_5" 34.083
cap "staticizer_2/staticizer_one_5/w_54_n57#" "ry5" 4.329
cap "wz_addrL5" "staticizer_2/staticizer_one_5/a_95_n27#" 2.805
cap "mux_8bit_1/mux_one_5/inv2_1/a_1_8#" "mux_8bit_1/in0_5" 4.95
cap "wz_addrL5" "staticizer_2/staticizer_one_5/a_60_n45#" -5.616
cap "wz_addrL5" "staticizer_2/staticizer_one_5/out" 3.111
cap "staticizer_2/staticizer_one_5/w_54_n57#" "wz_addrL5" 2.59
cap "mux_8bit_1/sel" "ry5" 58.7
cap "mux_8bit_1/mux_one_5/inv2_2/GND!" "mux_8bit_1/mux_one_5/2mux_nr_0/in0" -1.42109e-14
cap "wz_addrL5" "staticizer_2/staticizer_one_5/c" 3.996
cap "mux_8bit_1/Vdd!" "ry5" 58.7
cap "mux_8bit_1/mux_one_5/inv2_2/GND!" "ry5" 63.013
cap "mux_8bit_1/in0_5" "mux_8bit_1/mux_one_5/inv2_2/Vdd!" 91.282
cap "ry5" "reg_5/port51" 73.199
cap "reg_5/reg_one_2/w_n11_n27#" "reg_5/port51" 1.628
cap "ry5" "reg_5/reg_one_2/Vdd!" 58.7
cap "wz_addrH5" "reg_5/reg_one_2/r0" 24.728
cap "mux_8bit_1/mux_one_5/inv2_1/GND!" "ry5" -6.916
cap "mux_8bit_1/out5" "mux_8bit_1/mux_one_5/inv2_1/GND!" 366.202
cap "reg_5/reg_one_2/r1" "wz_addrH5" 58.7
cap "mux_8bit_1/GND!" "wz_addrH5" 58.7
cap "ry5" "reg_5/reg_one_2/r0" 48.664
cap "mux_8bit_1/out5" "reg_5/reg_one_2/r0" 195.199
cap "reg_5/reg_one_2/a_54_5#" "wz_addrH5" 4.828
cap "reg_5/reg_one_2/a_4_n13#" "wz_addrH5" 27.497
cap "reg_5/reg_one_2/r1" "ry5" 64.004
cap "wz_addrH5" "reg_5/reg_one_2/tmp" 4.948
cap "mux_8bit_1/GND!" "ry5" 58.7
cap "mux_8bit_1/GND!" "mux_8bit_1/out5" 35.82
cap "reg_5/port50" "wz_addrH5" 6.6
cap "wz_addrH5" "reg_5/reg_one_2/w_n11_n27#" 58.7
cap "mux_8bit_1/out5" "wz_addrH5" -6.325
cap "mux_8bit_1/GND!" "mux_8bit_1/mux_one_5/inv2_1/GND!" -0.246
cap "reg_5/port51" "reg_5/w" 5.072
cap "wz_addrH5" "reg_5/reg_one_2/Vdd!" 162.612
cap "reg_5/reg_one_2/w_n11_n27#" "ry5" 106.567
cap "mux_8bit_1/out5" "ry5" -17.369
cap "mux_8bit_1/mux_one_5/inv2_1/GND!" "wz_addrH5" 8.954
cap "reg_6/reg_one_2/tmp" "wz_addrH5" 4.948
cap "reg_5/w" "reg_5/port50" 67.0625
cap "reg_5/reg_one_2/w_n11_n27#" "wz_addrH5" 8.24
cap "reg_6/reg_one_2/r1" "reg_6/reg_one_2/w_n11_n27#" 3.55271e-15
cap "reg_5/port51" "ry5" -17.146
cap "reg_6/reg_one_2/a_4_n13#" "reg_5/port50" 87.672
cap "ry5" "reg_6/reg_one_2/r1" 5.304
cap "reg_5/reg_one_2/w_n11_n27#" "ry5" -2.667
cap "wz_addrH5" "reg_6/reg_one_2/Vdd!" 150.468
cap "reg_6/reg_one_2/r1" "reg_5/port50" 5.804
cap "reg_5/port51" "reg_6/reg_one_2/r0" 19.78
cap "wz_addrH5" "reg_5/w" 58.7
cap "ry5" "reg_6/reg_one_2/r1" 58.7
cap "reg_6/reg_one_2/a_21_n13#" "reg_5/port50" 3.96
cap "ry5" "reg_6/reg_one_2/w_n11_n27#" 101.233
cap "reg_6/reg_one_2/r1" "reg_5/port50" 58.7
cap "reg_5/reg_one_2/w_n11_n27#" "reg_5/port51" 12.7375
cap "reg_6/reg_one_2/w_n11_n27#" "reg_5/port50" 151.215
cap "reg_6/reg_one_2/a_4_n13#" "wz_addrH5" 17.113
cap "reg_6/reg_one_2/w_n11_n27#" "reg_6/reg_one_2/r0" 1.13687e-13
cap "reg_6/reg_one_2/port1" "ry5" 68.579
cap "reg_6/reg_one_2/port1" "reg_5/port50" 5.5
cap "reg_5/port51" "reg_6/reg_one_2/Vdd!" 58.7
cap "reg_5/reg_one_2/Vdd!" "wz_addrH5" -2.417
cap "reg_5/w" "reg_5/port51" 69.0435
cap "wz_addrH5" "reg_6/reg_one_2/r1" 58.7
cap "wz_addrH5" "reg_6/reg_one_2/a_54_5#" 4.828
cap "wz_addrH5" "reg_6/reg_one_2/w_n11_n27#" 58.7
cap "ry5" "reg_6/reg_one_2/r0" 48.664
cap "reg_6/reg_one_2/r0" "reg_5/port50" 26.208
cap "reg_6/reg_one_2/tmp" "reg_5/port50" 5.92
cap "reg_5/reg_one_2/w_n11_n27#" "reg_5/port50" 127.375
cap "reg_5/reg_one_2/w_n11_n27#" "reg_5/port51" 1.628
cap "reg_5/port51" "reg_6/reg_one_2/r1" 58.7
cap "ry5" "reg_6/reg_one_2/Vdd!" 58.7
cap "reg_5/port51" "reg_6/reg_one_2/w_n11_n27#" 83.267
cap "reg_6/reg_one_2/Vdd!" "reg_5/port50" 58.7
cap "wz_addrH5" "reg_6/reg_one_2/r0" 24.728
cap "reg_5/w" "ry5" 58.7
cap "reg_6/reg_one_2/Vdd!" "wz_addrH5" 10.12
subcap "m1_2209_894#" -380.236
cap "rx_addrH5" "mux_8bit_2/mux_one_5/2mux_nr_0/in0" 30.259
cap "mux_8bit_2/mux_one_5/inv2_2/GND!" "rx_addrH5" 22.523
cap "mux_8bit_2/in0_5" "mux_8bit_2/sel" 58.7
cap "mux_8bit_2/out5" "mux_8bit_2/sel" 0.84
cap "ry_addrH5" "reg_6/w" 58.7
cap "rx_addrH5" "reg_6/w" 58.7
cap "mux_8bit_2/mux_one_5/inv2_2/GND!" "reg_6/port51" 63.013
cap "mux_8bit_2/mux_one_5/inv2_2/Vdd!" "rx_addrH5" 17.542
cap "mux_8bit_2/in0_5" "mux_8bit_2/mux_one_5/inv2_1/a_1_8#" 4.95
cap "ry_addrH5" "mux_8bit_2/Vdd!" 58.7
cap "reg_6/w" "reg_6/reg_one_2/Vdd!" 1.77636e-15
cap "rx_addrH5" "reg_6/reg_one_2/w_n11_n27#" 19.776
cap "mux_8bit_2/in0_5" "reg_6/reg_one_2/a_4_n13#" -1.152
cap "rx_addrH5" "mux_8bit_2/Vdd!" 58.7
cap "rx_addrH5" "reg_6/port50" 4.411
cap "mux_8bit_2/in0_5" "mux_8bit_2/mux_one_5/2mux_nr_0/in0" 34.083
cap "mux_8bit_2/mux_one_5/inv2_2/GND!" "mux_8bit_2/out5" 37.928
cap "mux_8bit_2/mux_one_5/inv2_2/GND!" "mux_8bit_2/in0_5" 18.437
cap "reg_6/port51" "reg_6/w" 127.744
cap "mux_8bit_2/out5" "rx_addrH5" 19.905
cap "rx_addrH5" "mux_8bit_2/in0_5" 16.569
cap "reg_6/port50" "reg_6/reg_one_2/Vdd!" -7.10543e-15
cap "mux_8bit_2/in0_5" "reg_6/reg_one_2/Vdd!" -0.393
cap "reg_6/port51" "reg_6/reg_one_2/w_n11_n27#" 12.7375
cap "ry_addrH5" "reg_6/reg_one_2/w_n11_n27#" 0.019
cap "reg_6/port51" "mux_8bit_2/Vdd!" 58.7
cap "mux_8bit_2/in0_5" "reg_6/w" 58.7
cap "rx_addrH5" "reg_6/reg_one_2/w_n11_n27#" -2.286
cap "mux_8bit_2/mux_one_5/inv2_2/Vdd!" "mux_8bit_2/in0_5" 81.239
cap "mux_8bit_2/out5" "reg_6/port51" -10.01
cap "mux_8bit_2/sel" "ry_addrH5" 58.7
cap "mux_8bit_2/in0_5" "reg_6/reg_one_2/w_n11_n27#" 8.24
cap "mux_8bit_2/in0_5" "mux_8bit_2/Vdd!" 58.7
cap "rx_addrH5" "mux_8bit_2/sel" 58.7
cap "mux_8bit_2/in0_5" "reg_6/port50" 3.171
cap "reg_6/port51" "reg_6/reg_one_2/w_n11_n27#" 4.295
cap "rx_addrH5" "reg_6/reg_one_2/a_4_n13#" -10.448
cap "mux_8bit_2/sel" "reg_6/port51" 58.7
cap "reg_7/port51" "reg_7/w" 5.072
cap "reg_7/reg_one_2/Vdd!" "rx_addrH5" 58.7
cap "ry5" "mux_8bit_2/out5" -17.369
cap "rx_addrH5" "reg_7/reg_one_2/r0" 26.208
cap "rx_addrH5" "reg_7/reg_one_2/a_21_n13#" 3.96
cap "reg_7/reg_one_2/r0" "mux_8bit_2/out5" 195.199
cap "reg_7/port51" "reg_7/reg_one_2/w_n11_n27#" 1.628
cap "reg_7/reg_one_2/a_4_n13#" "wz_addrH5" 27.497
cap "wz_addrH5" "reg_7/reg_one_2/w_n11_n27#" 58.7
cap "rx_addrH5" "reg_7/reg_one_2/a_4_n13#" 93.704
cap "rx_addrH5" "reg_7/port51" 5.5
cap "ry5" "reg_7/reg_one_2/r1" 64.004
cap "mux_8bit_2/GND!" "ry_addrH5" 58.7
cap "rx_addrH5" "reg_7/reg_one_2/w_n11_n27#" 163.513
cap "reg_7/reg_one_2/Vdd!" "ry_addrH5" 58.7
cap "mux_8bit_2/GND!" "mux_8bit_2/mux_one_5/inv2_1/GND!" -0.246
cap "reg_7/reg_one_2/r0" "ry_addrH5" 19.78
cap "wz_addrH5" "mux_8bit_2/out5" -6.325
cap "wz_addrH5" "reg_7/reg_one_2/a_54_5#" 4.828
cap "ry5" "mux_8bit_2/mux_one_5/inv2_1/GND!" -6.916
cap "rx_addrH5" "mux_8bit_2/out5" -6.325
cap "ry_addrH5" "reg_7/reg_one_2/w_n11_n27#" 86.284
cap "mux_8bit_2/GND!" "ry5" 58.7
cap "wz_addrH5" "reg_7/reg_one_2/r1" 58.7
cap "reg_7/reg_one_2/Vdd!" "ry5" 58.7
cap "reg_7/reg_one_2/r0" "ry5" 48.664
cap "wz_addrH5" "mux_8bit_2/mux_one_5/inv2_1/GND!" 8.954
cap "rx_addrH5" "reg_7/reg_one_2/r1" 64.504
cap "wz_addrH5" "reg_7/port50" 6.6
cap "wz_addrH5" "reg_7/reg_one_2/tmp" 4.948
cap "rx_addrH5" "mux_8bit_2/mux_one_5/inv2_1/GND!" 12.194
cap "mux_8bit_2/mux_one_5/inv2_1/GND!" "mux_8bit_2/out5" 366.202
cap "reg_7/port51" "ry5" 73.199
cap "rx_addrH5" "reg_7/port50" 6.006
cap "mux_8bit_2/GND!" "wz_addrH5" 58.7
cap "ry5" "reg_7/reg_one_2/w_n11_n27#" 106.567
cap "rx_addrH5" "reg_7/reg_one_2/tmp" 5.92
cap "reg_7/reg_one_2/Vdd!" "wz_addrH5" 162.612
cap "ry_addrH5" "reg_7/reg_one_2/r1" 58.7
cap "rx_addrH5" "mux_8bit_2/GND!" 58.7
cap "reg_7/reg_one_2/r0" "wz_addrH5" 24.728
cap "mux_8bit_2/GND!" "mux_8bit_2/out5" 35.82
cap "wz_addrH5" "reg_7/w" 58.7
cap "addsub_2/b5" "addsub_2/xor_5/GND!" 3.55271e-15
cap "addsub_2/sub" "wz_addrH5" 11.825
cap "wz_addrH5" "addsub_2/Vdd!" 11.825
cap "ry5" "reg_7/port51" -17.146
cap "reg_7/reg_one_2/w_n11_n27#" "reg_7/port50" -3.048
cap "reg_7/reg_one_2/w_n11_n27#" "ry5" -2.667
cap "wz_addrH5" "addsub_2/b5" 5.939
cap "wz_addrH5" "reg_7/reg_one_2/w_n11_n27#" 8.24
cap "wz_addrH5" "reg_7/reg_one_2/Vdd!" -2.417
cap "reg_7/w" "reg_7/port51" 127.744
cap "addsub_2/sub" "reg_7/port51" 11.825
cap "addsub_2/Vdd!" "reg_7/port51" 11.825
cap "addsub_2/b5" "reg_7/port51" 11.825
cap "reg_7/port51" "reg_7/reg_one_2/w_n11_n27#" 12.7375
cap "reg_7/w" "reg_7/port50" 125.763
cap "reg_7/w" "ry5" 58.7
cap "addsub_2/sub" "reg_7/port50" 113.342
cap "addsub_2/sub" "ry5" 11.825
cap "ry5" "addsub_2/Vdd!" 11.825
cap "addsub_2/addsub_one_5/Vdd!" "reg_7/port50" 4.36
cap "addsub_2/b5" "ry5" 11.825
cap "addsub_2/b5" "reg_7/port50" 36.385
cap "reg_7/reg_one_2/w_n11_n27#" "reg_7/port51" -1.37
cap "reg_7/port50" "reg_7/reg_one_2/w_n11_n27#" 135.615
subcap "a_2516_921#" -30.357
cap "wz_addrH5" "addsub_2/addsub_one_6/Vdd!" -4.455
cap "ry5" "addsub_2/addsub_one_5/Vdd!" 13.563
cap "addsub_2/addsub_one_6/GND!" "wz_addrH5" 39.409
cap "addsub_2/s5" "latch_6/latch_one_5/a_n5_n54#" 19.2392
cap "addsub_2/addsub_one_6/GND!" "addsub_2/s5" 76.9567
cap "wz_addrH5" "addsub_2/s5" 50.259
cap "addsub_2/addsub_one_5/GND!" "wz_addrH5" 4.95
cap "ry_addrH5" "addsub_2/addsub_one_6/Vdd!" -4.455
cap "addsub_2/addsub_one_6/GND!" "ry_addrH5" 45.221
cap "ry5" "addsub_2/addsub_one_6/Vdd!" -4.455
cap "ry5" "addsub_2/addsub_one_6/GND!" 52.81
cap "wz_addrH5" "addsub_2/addsub_one_5/a_35_n41#" 19.78
cap "addsub_2/addsub_one_6/GND!" "addsub_2/addsub_one_5/a_35_n41#" 5.68434e-14
cap "addsub_2/addsub_one_5/Vdd!" "wz_addrH5" 27.16
cap "ry_addrH5" "addsub_2/addsub_one_6/cin" 2.474
cap "ry5" "addsub_2/addsub_one_6/cin" 20.38
cap "latch_6/latch_one_5/Vdd!" "addsub_2/s5" -12.402
subcap "a_2575_924#" -134.51
subcap "a_2516_921#" -105.445
cap "staticizer_3/staticizer_one_5/c" "ry5" 76.935
cap "staticizer_3/staticizer_one_5/c" "ry_addrH5" 58.7
cap "latch_6/out5" "staticizer_3/staticizer_one_5/out" 7.047
cap "latch_6/out5" "latch_6/latch_one_5/GND!" 10.156
cap "staticizer_3/staticizer_one_5/out" "latch_6/latch_one_5/Vdd!" 110.906
cap "latch_6/latch_one_5/c" "latch_6/out5" 9.252
cap "staticizer_3/staticizer_one_5/out" "staticizer_3/Vdd!" 58.7
cap "latch_6/latch_one_5/Vdd!" "ry5" 58.7
cap "ry_addrH5" "latch_6/latch_one_5/Vdd!" 58.7
cap "addsub_2/s5" "latch_6/latch_one_5/Vdd!" 19.399
cap "addsub_2/s5" "addsub_2/GND!" 19.2392
cap "staticizer_3/staticizer_one_5/a_60_n45#" "latch_6/out5" 150.065
cap "latch_6/latch_one_5/c" "latch_6/latch_one_5/Vdd!" -2.576
cap "ry5" "staticizer_3/Vdd!" 58.7
cap "staticizer_3/staticizer_one_5/out" "latch_6/latch_one_5/GND!" 117.4
cap "staticizer_3/staticizer_one_5/out" "latch_6/latch_one_5/a_12_n54#" 9.708
cap "ry_addrH5" "staticizer_3/Vdd!" 58.7
cap "staticizer_3/staticizer_one_5/out" "latch_6/latch_one_5/a_n5_n54#" 59.464
cap "latch_6/latch_one_5/c" "staticizer_3/Vdd!" 1073
cap "latch_6/latch_one_5/GND!" "ry5" 181.284
cap "ry_addrH5" "latch_6/latch_one_5/GND!" 117.4
cap "staticizer_3/staticizer_one_5/out" "addsub_2/s5" 6.404
cap "latch_6/latch_one_5/c" "staticizer_3/staticizer_one_5/out" 61.66
cap "addsub_2/s5" "latch_6/latch_one_5/a_n5_n54#" 57.7175
cap "latch_6/latch_one_5/c" "latch_6/latch_one_5/GND!" 13.8522
cap "staticizer_3/staticizer_one_5/out" "staticizer_3/staticizer_one_5/a_77_n45#" 5.115
cap "latch_6/latch_one_5/c" "ry5" 81.378
cap "latch_6/latch_one_5/c" "ry_addrH5" 58.7
cap "staticizer_3/staticizer_one_5/a_60_n45#" "staticizer_3/staticizer_one_5/out" 75.3524
cap "staticizer_3/staticizer_one_5/out" "staticizer_3/staticizer_one_5/c" 61.544
cap "latch_6/latch_one_5/a_30_n35#" "staticizer_3/staticizer_one_5/out" 1.88
cap "staticizer_3/staticizer_one_5/c" "latch_6/latch_one_5/GND!" 5.68434e-14
cap "latch_6/out5" "latch_6/latch_one_5/Vdd!" 70.372
subcap "addr_out5" -134.51
cap "staticizer_3/staticizer_one_5/w_54_n57#" "latch_7/in5" 17.972
cap "staticizer_3/staticizer_one_5/c" "staticizer_3/staticizer_one_5/w_54_n57#" -1.42109e-14
cap "latch_7/latch_one_5/Vdd!" "latch_7/latch_one_5/GND!" -1.13687e-13
cap "latch_7/out5" "latch_7/latch_one_5/GND!" 10.156
cap "ry_addrH5" "latch_7/latch_one_5/GND!" 77.41
cap "staticizer_3/staticizer_one_5/out" "staticizer_3/staticizer_one_5/Vdd!" 6.001
cap "latch_7/latch_one_5/Vdd!" "latch_7/out5" 70.372
cap "staticizer_3/staticizer_one_5/a_77_n45#" "staticizer_3/staticizer_one_5/Vdd!" -3.55271e-15
cap "latch_7/latch_one_5/Vdd!" "ry_addrH5" 58.7
cap "latch_7/latch_one_5/GND!" "latch_7/latch_one_5/c" 13.8522
cap "staticizer_3/staticizer_one_5/a_60_n45#" "staticizer_3/staticizer_one_5/out" 0.709429
cap "latch_7/in5" "staticizer_3/staticizer_one_5/Vdd!" 11.463
cap "latch_7/in5" "latch_7/latch_one_5/GND!" 6.956
cap "latch_7/out5" "latch_7/latch_one_5/c" 9.252
cap "latch_7/latch_one_5/Vdd!" "latch_7/latch_one_5/c" -2.576
cap "ry_addrH5" "latch_7/latch_one_5/c" 58.7
cap "staticizer_4/Vdd!" "ry_addrH5" 58.7
cap "staticizer_3/staticizer_one_5/a_77_n45#" "staticizer_3/staticizer_one_5/out" 2.728
cap "latch_7/latch_one_5/Vdd!" "latch_7/in5" 286.786
cap "staticizer_4/staticizer_one_5/a_60_n45#" "latch_7/latch_one_5/GND!" 5.68434e-14
cap "staticizer_3/staticizer_one_5/out" "latch_7/in5" 23.087
cap "staticizer_4/Vdd!" "latch_7/latch_one_5/c" 1073
cap "staticizer_4/staticizer_one_5/a_60_n45#" "latch_7/latch_one_5/Vdd!" 7.10543e-15
cap "staticizer_3/staticizer_one_5/w_54_n57#" "staticizer_3/staticizer_one_5/out" 8.272
cap "staticizer_4/staticizer_one_5/a_60_n45#" "latch_7/out5" 150.065
cap "latch_7/latch_one_5/a_n5_n54#" "latch_7/in5" 57.7175
subcap "ry_addrH5" -842.542
subcap "addr_out13" -184.704
cap "latch_8/in5" "latch_8/latch_one_5/a_n5_n54#" 57.7175
cap "latch_8/in5" "latch_8/latch_one_5/Vdd!" 367.261
cap "staticizer_5/in5" "latch_8/latch_one_5/c" -0.42
cap "staticizer_5/staticizer_one_5/w_54_n57#" "latch_8/in5" 6.956
cap "staticizer_4/staticizer_one_5/Vdd!" "latch_8/in5" 11.463
cap "latch_8/in5" "staticizer_4/staticizer_one_5/out" 57.7175
cap "latch_8/in5" "staticizer_4/staticizer_one_5/c" 58.7
cap "latch_8/in5" "staticizer_4/staticizer_one_5/w_54_n57#" 21.105
cap "staticizer_5/in5" "latch_8/latch_one_5/Vdd!" -1.162
cap "staticizer_4/staticizer_one_5/w_54_n57#" "staticizer_4/staticizer_one_5/a_60_n45#" 2.84217e-14
subcap "addr_out13" -85.11
cap "latch_8/latch_one_5/Vdd!" "latch_8/latch_one_5/c" -2.576
cap "staticizer_5/in5" "latch_8/latch_one_5/c" 9.252
cap "latch_8/latch_one_5/c" "staticizer_5/staticizer_one_5/w_54_n57#" 13.8522
cap "latch_8/latch_one_5/c" "staticizer_5/Vdd!" 1073
cap "latch_8/latch_one_5/Vdd!" "staticizer_5/staticizer_one_5/a_60_n45#" 7.10543e-15
cap "staticizer_5/in5" "staticizer_5/staticizer_one_5/a_60_n45#" 150.065
cap "staticizer_5/in5" "latch_8/latch_one_5/Vdd!" 70.372
cap "staticizer_5/in5" "staticizer_5/staticizer_one_5/w_54_n57#" 10.156
cap "staticizer_1/staticizer_one_5/Vdd!" "latch_4/c" 1073
cap "latch_4/latch_one_5/a_12_n54#" "staticizer_1/staticizer_one_5/Vdd!" -7.10543e-15
cap "staticizer_1/staticizer_one_5/out" "staticizer_1/staticizer_one_5/Vdd!" 37.056
subcap "data_in5" -223.416
subcap "rx5" -2049.89
cap "latch_0/c" "latch_0/latch_one_5/Vdd!" 1073
cap "latch_0/latch_one_5/Vdd!" "latch_0/latch_one_5/a_12_n54#" -1.13687e-13
cap "latch_0/latch_one_5/Vdd!" "latch_0/GND!" 2.27374e-13
cap "latch_0/in5" "latch_0/latch_one_5/Vdd!" 40.2375
cap "latch_0/out5" "latch_0/latch_one_5/Vdd!" 37.056
subcap "wz5" -2594.69
cap "staticizer_0/staticizer_one_5/Vdd!" "latch_0/out5" 9.661
cap "shift_0/shift_one_5/2mux_nr_1/out" "latch_3/latch_one_5/Vdd!" 46.174
cap "fblock_0/b5" "fblock_0/fblock_one_5/2mux_nr_1/Vdd!" 11.239
cap "fblock_0/b5" "fblock_0/g2" 58.7
cap "fblock_0/b5" "fblock_0/g3" 140.424
cap "fblock_0/fblock_one_5/2mux_nr_0/in0" "fblock_0/b5" 7.975
cap "latch_3/latch_one_5/a_12_n54#" "latch_3/latch_one_5/Vdd!" 1.42109e-14
cap "fblock_0/b5" "fblock_0/fblock_one_5/2mux_nr_0/a_n17_n11#" 33.597
cap "fblock_0/fblock_one_5/2mux_nr_2/Vdd!" "fblock_0/g3" -3.55271e-15
cap "fblock_0/fblock_one_5/2mux_nr_1/GND!" "fblock_0/b5" 68.584
cap "fblock_0/fblock_one_5/2mux_nr_2/Vdd!" "fblock_0/fblock_one_5/2mux_nr_2/s" -5.68434e-14
cap "fblock_0/b5" "fblock_0/fblock_one_5/2mux_nr_0/out" 11.825
cap "fblock_0/b5" "fblock_0/fblock_one_5/2mux_nr_0/in1" 4.95
cap "fblock_0/fblock_one_5/g0" "ry5" 58.7
cap "fblock_0/fblock_one_5/inv_4/out" "ry5" 2.75
cap "fblock_0/fblock_one_5/f" "ry5" 25.152
cap "fblock_0/fblock_one_5/g1" "ry5" 58.7
cap "fblock_0/Vdd!" "latch_1/latch_one_5/Vdd!" 1341.25
cap "fblock_0/fblock_one_5/2mux_nr_1/out" "ry5" 11.825
cap "ry5" "latch_1/GND!" 58.7
cap "latch_1/latch_one_5/Vdd!" "ry5" 58.7
cap "fblock_0/Vdd!" "ry5" 58.7
cap "fblock_0/fblock_one_5/inv_3/out" "ry5" 4.95
cap "fblock_0/fblock_one_5/inv_3/GND!" "ry5" 24.128
cap "ry5" "fblock_0/fblock_one_5/2mux_nr_1/a_n17_n11#" 31.949
cap "fblock_0/fblock_one_5/2mux_nr_1/s" "ry5" 16.386
subcap "ry5" -2690.98
cap "addsub_0/b5" "latch_1/c" 58.7
cap "addsub_0/b5" "addsub_0/xor_5/a_69_n42#" 2.457
cap "addsub_0/xor_5/a_100_n42#" "addsub_0/b5" 0.707
cap "addsub_0/xor_5/b" "addsub_0/b5" 15.993
cap "addsub_0/b5" "addsub_0/xor_5/a_61_n31#" 7.218
cap "addsub_0/b5" "addsub_0/xor_5/GND!" 75.6667
cap "addsub_0/b5" "addsub_0/xor_5/out" 31.486
cap "addsub_0/xor_5/a_89_n31#" "addsub_0/b5" 3.068
cap "addsub_0/addsub_one_5/a_78_n41#" "as_cout" 10.86
cap "addsub_0/a5" "addsub_0/addsub_one_5/a_89_9#" 4.7
cap "addsub_0/addsub_one_5/a_35_n41#" "addsub_0/addsub_one_5/GND!" 2.27374e-13
cap "addsub_0/addsub_one_5/a_29_n41#" "as_cout" 2.1
cap "addsub_0/a5" "addsub_0/xor_5/a_61_n1#" 141.539
cap "addsub_0/addsub_one_5/a_66_n41#" "as_cout" 2.1
cap "addsub_0/a5" "addsub_0/xor_5/a_89_n31#" 2.424
cap "addsub_0/a5" "addsub_0/addsub_one_5/b" 94.487
cap "as_cout" "addsub_0/addsub_one_5/b" 16.816
cap "addsub_0/a5" "addsub_0/xor_5/a_61_n31#" 2.424
cap "addsub_0/a5" "addsub_0/addsub_one_5/GND!" 19.773
cap "addsub_0/addsub_one_5/GND!" "as_cout" 66.999
cap "addsub_0/a5" "addsub_0/xor_5/b" 2.424
cap "addsub_0/addsub_one_5/cin" "as_cout" 12.612
cap "addsub_0/addsub_one_5/a_89_n41#" "as_cout" 22.875
cap "addsub_0/addsub_one_5/a_72_n41#" "as_cout" 2.1
cap "addsub_0/a5" "addsub_0/xor_5/Vdd!" 182.581
cap "addsub_0/addsub_one_5/a_11_n41#" "as_cout" 11.28
cap "addsub_0/a5" "addsub_0/addsub_one_5/a_35_n41#" 19.78
cap "addsub_0/a5" "addsub_0/xor_5/a" 2.424
cap "addsub_0/addsub_one_5/a_35_n41#" "as_cout" 14.854
cap "addsub_0/a5" "as_cout" 12.612
cap "addsub_0/a5" "addsub_0/addsub_one_5/a_78_n41#" 11.825
cap "latch_2/latch_one_5/out" "rx5" 4.341
cap "latch_2/latch_one_5/a_n5_n54#" "rx5" 3.351
cap "latch_2/c" "rx5" 58.7
cap "addsub_0/addsub_one_5/b" "rx5" -2.068
cap "latch_2/latch_one_5/in" "rx5" 3.468
cap "latch_2/GND!" "rx5" 58.7
cap "rx5" "addsub_0/addsub_one_5/GND!" 24.915
cap "latch_2/latch_one_5/a_n5_n54#" "rx5" 2.844
cap "rx5" "latch_2/latch_one_5/Vdd!" 116.636
cap "reg_0/in5" "reg_0/r0" 153.495
cap "rx5" "latch_2/latch_one_5/a_30_n35#" 1.524
cap "rx5" "reg_0/r0" 19.78
cap "latch_2/latch_one_5/a_12_n54#" "rx5" 37.778
cap "latch_2/c" "reg_0/in5" 429.2
cap "latch_2/latch_one_5/c" "rx5" 2.844
cap "rx5" "reg_0/reg_one_2/Vdd!" 134.044
cap "reg_0/reg_one_2/tmp" "rx5" 4.948
cap "reg_0/r0" "reg_0/in5" -5.072
cap "reg_0/w" "wz5" 58.7
cap "reg_0/reg_one_2/r1" "wz5" 58.7
cap "reg_0/r0" "rx5" -7.416
cap "wz5" "reg_0/reg_one_2/w" 4.382
cap "reg_0/w" "reg_0/reg_one_2/Vdd!" -1.77636e-15
cap "wz5" "reg_1/r0" 63.6875
cap "reg_0/reg_one_2/w_n11_n27#" "wz5" 8.24
cap "reg_0/w" "rx5" 166
cap "wz5" "reg_0/GND!" 58.7
cap "reg_0/reg_one_2/r1" "rx5" 70.642
cap "wz5" "reg_0/in5" 14.786
cap "wz5" "reg_0/reg_one_2/Vdd!" 165.083
cap "reg_0/reg_one_2/tmp" "wz5" 4.324
cap "reg_0/reg_one_2/w_n11_n27#" "reg_0/reg_one_2/Vdd!" -1.42109e-14
cap "reg_0/reg_one_2/a_33_32#" "wz5" 65.474
cap "rx5" "reg_0/reg_one_2/a_4_n13#" 20.417
cap "reg_0/reg_one_2/w_n11_n27#" "rx5" 8.24
cap "reg_0/reg_one_2/a_16_27#" "wz5" 8.264
cap "rx5" "reg_0/GND!" 58.7
cap "reg_0/reg_one_2/a_21_n13#" "rx5" 20.118
cap "reg_0/r0" "wz5" -7.416
cap "reg_0/reg_one_2/tmp" "wz5" 4.389
cap "reg_1/in5" "reg_1/reg_one_2/Vdd!" 165.083
cap "reg_1/r0" "reg_1/in5" 89.8075
cap "reg_1/reg_one_2/tmp" "reg_1/in5" 4.324
cap "reg_1/reg_one_2/r1" "reg_1/in5" 58.7
cap "reg_1/w" "reg_1/in5" 58.7
cap "reg_1/in5" "reg_1/reg_one_2/w" 4.382
cap "reg_1/reg_one_2/w_n11_n27#" "reg_1/in5" 8.24
cap "reg_1/w" "reg_1/reg_one_2/Vdd!" -1.77636e-15
cap "reg_1/in5" "reg_1/GND!" 58.7
cap "reg_1/reg_one_2/w_n11_n27#" "reg_1/reg_one_2/Vdd!" -1.42109e-14
cap "reg_1/reg_one_2/a_16_27#" "reg_1/in5" 8.264
cap "reg_1/in5" "reg_1/reg_one_2/tmp" 4.389
cap "reg_1/in5" "reg_1/reg_one_2/a_33_32#" 65.474
cap "reg_2/in5" "reg_2/w" 58.7
cap "reg_2/reg_one_2/tmp" "reg_2/in5" 4.324
cap "reg_2/reg_one_2/w_n11_n27#" "reg_2/in5" 8.24
cap "reg_2/reg_one_2/Vdd!" "reg_2/w" -1.77636e-15
cap "reg_2/reg_one_2/w_n11_n27#" "reg_2/reg_one_2/Vdd!" -1.42109e-14
cap "reg_2/reg_one_2/r1" "reg_2/in5" 58.7
cap "reg_2/in5" "reg_2/reg_one_2/a_16_27#" 8.264
cap "reg_2/reg_one_2/r1" "reg_2/reg_one_2/Vdd!" 1.13687e-13
cap "reg_2/in5" "reg_2/reg_one_2/Vdd!" 165.083
cap "reg_2/in5" "reg_2/r0" 153.495
cap "reg_2/reg_one_2/a_33_32#" "reg_2/in5" 65.474
cap "reg_2/reg_one_2/tmp" "reg_2/in5" 4.389
cap "reg_2/GND!" "reg_2/in5" 58.7
cap "reg_2/reg_one_2/w" "reg_2/in5" 4.382
cap "reg_3/in5" "reg_3/reg_one_2/r1" 58.7
cap "reg_3/reg_one_2/w_n11_n27#" "reg_3/in5" 17.302
cap "reg_3/reg_one_2/w" "reg_3/in5" 1.248
cap "reg_3/in5" "reg_3/reg_one_2/tmp" 1.248
cap "reg_3/reg_one_2/tmp" "reg_3/in5" 6.6
cap "reg_3/reg_one_2/a_33_32#" "reg_3/in5" 39.098
cap "reg_3/reg_one_2/Vdd!" "reg_3/reg_one_2/r1" 1.13687e-13
cap "reg_3/in5" "reg_3/GND!" 58.7
cap "reg_3/reg_one_2/a_16_27#" "reg_3/in5" 7.446
cap "reg_3/in5" "reg_3/r0" 153.495
cap "reg_3/reg_one_2/Vdd!" "reg_3/in5" 75.24
cap "reg_3/reg_one_2/w_n11_n27#" "mux_8bit_0/in1_5" -2.948
cap "reg_3/reg_one_2/w_n11_n27#" "reg_3/reg_one_2/w" 1.42109e-14
cap "mux_8bit_0/in1_5" "reg_3/reg_one_2/w" 58.7
cap "mux_8bit_0/in1_5" "mux_8bit_0/mux_one_5/Vdd!" 98.617
cap "mux_8bit_0/in1_5" "mux_8bit_0/mux_one_5/2mux_nr_0/in1" 18.535
cap "reg_3/reg_one_2/w_n11_n27#" "mux_8bit_0/in1_5" 8.24
cap "mux_8bit_0/in1_5" "mux_8bit_0/mux_one_5/sel" 63.256
cap "mux_8bit_0/in1_5" "mux_8bit_0/mux_one_5/GND!" 15.908
cap "mux_8bit_0/in1_5" "reg_3/reg_one_2/Vdd!" -2.948
cap "mux_8bit_0/in1_5" "mux_8bit_0/mux_one_5/2mux_nr_0/a_n17_n11#" 36.092
cap "mux_8bit_0/mux_one_5/GND!" "mux_8bit_0/mux_one_5/2mux_nr_0/in1" 1.42109e-14
cap "mux_8bit_0/in1_5" "reg_3/reg_one_2/a_33_32#" -4.455
cap "reg_4/reg_one_2/w" "wz5" 5.064
cap "wz5" "reg_4/r0" 19.78
cap "reg_4/in5" "mux_8bit_0/mux_one_5/2mux_nr_0/out" 85.4219
cap "reg_4/reg_one_2/r1" "wz5" 58.7
cap "reg_4/reg_one_2/Vdd!" "reg_4/r0" -9.768
cap "reg_4/reg_one_2/w_n11_n27#" "wz5" 133.528
cap "mux_8bit_0/mux_one_5/2mux_nr_0/a_n17_n11#" "mux_8bit_0/mux_one_5/GND!" 3.55271e-15
cap "mux_8bit_0/mux_one_5/GND!" "reg_4/r0" 165.587
cap "mux_8bit_0/mux_one_5/2mux_nr_0/a_n17_n11#" "wz5" -5.178
cap "reg_4/in5" "wz5" 2.844
cap "reg_4/reg_one_2/a_33_32#" "wz5" 7.959
cap "reg_4/in5" "reg_4/reg_one_2/Vdd!" 56.544
cap "wz5" "reg_4/reg_one_2/a_16_27#" 8.022
cap "reg_4/in5" "mux_8bit_0/mux_one_5/GND!" 106.874
cap "reg_4/GND!" "wz5" 58.7
cap "mux_8bit_0/mux_one_5/2mux_nr_0/s" "wz5" 4.948
cap "reg_4/reg_one_2/Vdd!" "wz5" 58.7
cap "reg_4/reg_one_2/tmp" "wz5" 6.507
cap "reg_4/in5" "reg_4/r0" 118.803
cap "mux_8bit_0/mux_one_5/GND!" "wz5" 67.786
subcap "a_1545_928#" -73.342
subcap "rx_PCL5" -388.317
cap "wz5" "addsub_1/xor_5/Vdd!" 15.72
cap "wz5" "addsub_1/b5" 26.517
cap "wz5" "addsub_1/xor_5/a_61_n31#" 19.78
cap "wz5" "addsub_1/xor_5/a_61_n1#" 5.568
cap "addsub_1/a5" "addsub_1/xor_5/out" 36.877
cap "wz5" "reg_4/reg_one_2/w_n11_n27#" -2.417
cap "wz5" "addsub_1/xor_5/b" 11.825
cap "addsub_1/a5" "addsub_1/xor_5/Vdd!" 123.156
cap "reg_4/reg_one_2/w_n11_n27#" "reg_4/reg_one_2/Vdd!" -7.10543e-15
cap "addsub_1/a5" "addsub_1/b5" 2.424
cap "addsub_1/a5" "addsub_1/xor_5/a_61_n31#" 2.424
cap "addsub_1/a5" "addsub_1/xor_5/a_61_n1#" 174.249
cap "addsub_1/xor_5/b" "addsub_1/a5" 2.424
cap "addsub_1/xor_5/a_61_n31#" "addsub_1/b5" -9.50351e-14
cap "reg_4/reg_one_2/a_33_32#" "wz5" -12.339
cap "addsub_1/xor_5/b" "addsub_1/b5" 2.3087
cap "reg_4/reg_one_2/w_n11_n27#" "wz5" -8.24
cap "wz5" "addsub_1/xor_5/a_89_n31#" 17.316
cap "reg_4/reg_one_2/w" "wz5" 58.7
cap "addsub_1/a5" "addsub_1/xor_5/a_89_n31#" 2.424
cap "wz5" "addsub_1/xor_5/out" 97.913
cap "a_2510_1893#" "addsub_1/addsub_one_5/a_78_n41#" 10.86
cap "a_2510_1893#" "addsub_1/addsub_one_5/GND!" 66.999
cap "addsub_1/addsub_one_5/a_66_n41#" "a_2510_1893#" 2.1
cap "addsub_1/addsub_one_5/a_35_n41#" "wz5" 51.712
cap "addsub_1/addsub_one_5/b" "a_2510_1893#" 16.816
cap "addsub_1/addsub_one_5/cin" "wz5" 1.56
cap "a_2510_1893#" "addsub_1/addsub_one_5/a_72_n41#" 2.1
cap "addsub_1/addsub_one_5/a_78_n41#" "wz5" 35.835
cap "addsub_1/xor_5/Vdd!" "wz5" 3.171
cap "addsub_1/addsub_one_5/a_11_n41#" "a_2510_1893#" 11.28
cap "addsub_1/addsub_one_5/GND!" "wz5" 38.289
cap "a_2510_1893#" "addsub_1/addsub_one_5/a_35_n41#" 14.854
cap "a_2510_1893#" "addsub_1/a5" 12.612
cap "a_2510_1893#" "addsub_1/addsub_one_5/a_89_n41#" 22.875
cap "addsub_1/addsub_one_5/b" "addsub_1/addsub_one_5/GND!" -2.27374e-13
cap "addsub_1/addsub_one_5/b" "wz5" 95.736
cap "addsub_1/addsub_one_5/cin" "a_2510_1893#" 12.612
cap "a_2510_1893#" "addsub_1/addsub_one_5/a_29_n41#" 2.1
subcap "a_1776_924#" -201.977
cap "wz5" "staticizer_2/GND!" 58.7
cap "latch_5/c" "latch_5/latch_one_5/Vdd!" 1073
cap "latch_5/latch_one_5/Vdd!" "staticizer_2/c" -1.42109e-14
cap "wz5" "latch_5/GND!" 58.7
cap "latch_5/latch_one_5/Vdd!" "staticizer_2/in5" 37.056
cap "latch_5/c" "wz5" 58.7
cap "wz5" "latch_5/latch_one_5/Vdd!" 117.4
cap "wz5" "staticizer_2/c" 58.7
cap "mux_8bit_1/in1_5" "mux_8bit_1/mux_one_5/sel" 63.256
cap "mux_8bit_1/in1_5" "mux_8bit_1/mux_one_5/2mux_nr_0/a_n17_n11#" 36.092
cap "mux_8bit_1/in1_5" "mux_8bit_1/mux_one_5/GND!" 15.908
cap "staticizer_2/staticizer_one_5/Vdd!" "staticizer_2/staticizer_one_5/out" 6.811
cap "staticizer_2/staticizer_one_5/a_77_n45#" "staticizer_2/staticizer_one_5/out" 15.376
cap "staticizer_2/staticizer_one_5/a_95_n27#" "staticizer_2/staticizer_one_5/out" 2.805
cap "mux_8bit_1/in1_5" "mux_8bit_1/mux_one_5/2mux_nr_0/in1" 18.535
cap "mux_8bit_1/mux_one_5/Vdd!" "mux_8bit_1/in1_5" 96.331
cap "reg_5/reg_one_2/Vdd!" "reg_5/in5" 56.544
cap "wz5" "reg_5/r0" 19.78
cap "mux_8bit_1/mux_one_5/GND!" "reg_5/in5" 106.874
cap "wz5" "reg_5/reg_one_2/tmp" 6.507
cap "wz5" "reg_5/reg_one_2/w_n11_n27#" 133.528
cap "wz5" "reg_5/reg_one_2/a_16_27#" 8.022
cap "mux_8bit_1/mux_one_5/2mux_nr_0/out" "reg_5/in5" 85.4219
cap "wz5" "mux_8bit_1/mux_one_5/2mux_nr_0/s" 4.948
cap "wz5" "reg_5/reg_one_2/r1" 58.7
cap "wz5" "reg_5/in5" 2.844
cap "reg_5/r0" "reg_5/in5" 118.803
cap "mux_8bit_1/mux_one_5/GND!" "mux_8bit_1/mux_one_5/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "wz5" "reg_5/reg_one_2/Vdd!" 58.7
cap "wz5" "reg_5/reg_one_2/w" 5.064
cap "reg_5/r0" "reg_5/reg_one_2/Vdd!" -9.768
cap "wz5" "mux_8bit_1/mux_one_5/GND!" 67.786
cap "reg_5/GND!" "wz5" 58.7
cap "reg_5/r0" "mux_8bit_1/mux_one_5/GND!" 165.587
cap "wz5" "mux_8bit_1/mux_one_5/2mux_nr_0/a_n17_n11#" -5.178
cap "wz5" "reg_5/reg_one_2/a_33_32#" 7.959
cap "reg_5/w" "reg_6/in5" 58.7
cap "reg_6/reg_one_2/a_16_27#" "reg_6/in5" 8.022
cap "reg_6/in5" "reg_6/reg_one_2/a_33_32#" 2.844
cap "reg_5/reg_one_2/Vdd!" "reg_5/w" -1.77636e-15
cap "reg_6/GND!" "reg_6/in5" 58.7
cap "reg_5/reg_one_2/a_33_32#" "reg_6/in5" -12.339
cap "reg_6/reg_one_2/w_n11_n27#" "reg_6/in5" 123.733
cap "reg_6/reg_one_2/r1" "reg_6/in5" 58.7
cap "reg_5/reg_one_2/w_n11_n27#" "reg_6/in5" -2.417
cap "reg_6/reg_one_2/Vdd!" "reg_6/in5" 58.7
cap "reg_6/reg_one_2/tmp" "reg_6/in5" 4.461
cap "reg_5/reg_one_2/w_n11_n27#" "reg_6/in5" -8.24
cap "reg_6/r0" "reg_6/in5" 128.02
cap "reg_6/reg_one_2/w" "reg_6/in5" 2.22
cap "reg_6/reg_one_2/w" "reg_6/in5" 2.844
cap "mux_8bit_2/in1_5" "reg_6/reg_one_2/a_33_32#" 5.115
cap "mux_8bit_2/in1_5" "reg_6/reg_one_2/w_n11_n27#" -1.886
cap "reg_6/reg_one_2/tmp" "mux_8bit_2/in1_5" -4.818
cap "reg_6/reg_one_2/tmp" "reg_6/reg_one_2/w_n11_n27#" -7.10543e-15
cap "reg_6/reg_one_2/a_4_n13#" "reg_6/reg_one_2/Vdd!" -7.10543e-15
cap "mux_8bit_2/in1_5" "mux_8bit_2/mux_one_5/GND!" 2.035
cap "reg_6/reg_one_2/w_n11_n27#" "mux_8bit_2/in1_5" 48.9529
cap "reg_6/reg_one_2/Vdd!" "reg_6/reg_one_2/a_33_32#" -7.10543e-15
cap "mux_8bit_2/mux_one_5/Vdd!" "mux_8bit_2/in1_5" 2.035
cap "mux_8bit_2/in1_5" "reg_6/reg_one_2/w" 97.0214
cap "mux_8bit_2/mux_one_5/2mux_nr_0/in1" "mux_8bit_2/mux_one_5/GND!" 1.42109e-14
cap "reg_7/r0" "mux_8bit_2/mux_one_5/GND!" 165.587
cap "mux_8bit_2/mux_one_5/2mux_nr_0/a_n17_n11#" "mux_8bit_2/mux_one_5/GND!" 3.55271e-15
cap "reg_7/r0" "reg_7/in5" 118.803
cap "reg_7/in5" "mux_8bit_2/mux_one_5/2mux_nr_0/out" 85.4219
cap "reg_7/reg_one_2/Vdd!" "reg_7/in5" 56.544
cap "reg_7/in5" "mux_8bit_2/mux_one_5/GND!" 106.874
cap "reg_7/r0" "reg_7/reg_one_2/Vdd!" -9.768
subcap "rx_addrH5" -767.489
cap "addsub_2/a5" "addsub_2/xor_5/b" 2.424
cap "addsub_2/b5" "addsub_2/a5" 2.424
cap "addsub_2/a5" "addsub_2/xor_5/a_61_n1#" 174.249
cap "addsub_2/xor_5/a_89_n31#" "addsub_2/a5" 2.424
cap "addsub_2/xor_5/out" "addsub_2/a5" 36.877
cap "addsub_2/a5" "addsub_2/xor_5/Vdd!" 123.156
cap "addsub_2/b5" "addsub_2/xor_5/a_61_n31#" -9.50351e-14
cap "reg_7/reg_one_2/Vdd!" "reg_7/reg_one_2/w_n11_n27#" -7.10543e-15
cap "addsub_2/a5" "addsub_2/xor_5/a_61_n31#" 2.424
cap "addsub_2/addsub_one_5/b" "addsub_2/addsub_one_5/GND!" -2.27374e-13
subcap "a_2575_924#" -192.438
cap "latch_6/latch_one_5/Vdd!" "staticizer_3/in5" 37.056
cap "latch_6/latch_one_5/Vdd!" "staticizer_3/c" -1.42109e-14
cap "latch_6/latch_one_5/Vdd!" "latch_6/c" 1073
subcap "addr_out5" -259.186
cap "staticizer_3/staticizer_one_5/Vdd!" "staticizer_3/staticizer_one_5/out" 2.84217e-14
cap "staticizer_4/staticizer_one_5/a_60_n45#" "latch_7/latch_one_5/Vdd!" 1.42109e-14
cap "latch_7/c" "latch_7/latch_one_5/Vdd!" 1073
cap "staticizer_4/in5" "latch_7/latch_one_5/Vdd!" 37.056
cap "staticizer_3/staticizer_one_5/a_77_n45#" "staticizer_3/staticizer_one_5/Vdd!" 2.84217e-14
subcap "addr_out13" -171.7
cap "staticizer_4/staticizer_one_5/out" "staticizer_4/staticizer_one_5/Vdd!" -2.84217e-14
subcap "addr_out13" -259.186
cap "latch_8/c" "latch_8/latch_one_5/Vdd!" 1073
cap "staticizer_5/in5" "latch_8/latch_one_5/Vdd!" 37.056
cap "latch_8/latch_one_5/Vdd!" "staticizer_5/staticizer_one_5/a_60_n45#" 1.42109e-14
cap "staticizer_1/staticizer_one_4/Vdd!" "staticizer_1/staticizer_one_4/w_54_n57#" 1.13687e-13
cap "staticizer_1/staticizer_one_4/Vdd!" "latch_4/latch_one_4/c" 1073
cap "staticizer_1/staticizer_one_4/w_54_n57#" "latch_4/latch_one_4/c" 18.4696
cap "staticizer_1/staticizer_one_4/a_60_n45#" "staticizer_1/staticizer_one_4/Vdd!" -2.27374e-13
cap "staticizer_1/in4" "latch_4/latch_one_4/c" 0.492
cap "staticizer_1/staticizer_one_4/a_60_n45#" "staticizer_1/in4" 57.7175
cap "staticizer_1/in4" "staticizer_1/staticizer_one_4/w_54_n57#" 18.828
cap "staticizer_1/staticizer_one_4/Vdd!" "staticizer_1/in4" 73.946
cap "staticizer_1/staticizer_one_4/Vdd!" "latch_4/latch_one_4/a_12_n54#" -7.10543e-15
cap "staticizer_1/staticizer_one_4/c" "staticizer_1/in4" 1.42109e-14
subcap "a_109_1096#" -134.574
subcap "data_in4" -6.948
subcap "rx4" -1770.33
cap "latch_0/latch_one_4/a_12_n54#" "latch_0/latch_one_4/Vdd!" -1.13687e-13
cap "latch_0/latch_one_4/Vdd!" "latch_0/in4" 67.0625
cap "latch_0/latch_one_4/GND!" "latch_4/in4" 59.993
cap "staticizer_0/staticizer_one_4/a_60_n45#" "latch_0/latch_one_4/Vdd!" -4.648
cap "latch_0/latch_one_4/GND!" "latch_0/out4" 18.828
cap "latch_4/in4" "latch_0/latch_one_4/c" 58.7
cap "latch_0/out4" "latch_0/latch_one_4/c" 0.492
cap "latch_4/in4" "latch_4/latch_one_4/a_n5_n54#" 69.3743
cap "latch_4/in4" "latch_0/latch_one_4/Vdd!" 96.12
cap "latch_0/out4" "latch_0/latch_one_4/Vdd!" 73.946
cap "staticizer_0/staticizer_one_4/a_60_n45#" "latch_0/out4" 57.7175
cap "latch_0/latch_one_4/GND!" "latch_0/latch_one_4/a_n5_n54#" 5.68434e-14
cap "latch_0/latch_one_4/GND!" "latch_0/latch_one_4/c" 18.4696
cap "latch_0/latch_one_4/GND!" "latch_0/latch_one_4/Vdd!" -0.246
cap "latch_4/latch_one_4/Vdd!" "latch_4/in4" 469.437
cap "latch_0/latch_one_4/Vdd!" "latch_0/latch_one_4/a_n5_n54#" 1.13687e-13
cap "latch_0/latch_one_4/a_n5_n54#" "latch_0/in4" 32.9814
cap "latch_0/latch_one_4/Vdd!" "latch_0/latch_one_4/c" 1073
subcap "wz4" -2636.74
cap "staticizer_0/staticizer_one_4/w_54_n57#" "shift_0/a4" 73.425
cap "latch_0/out4" "shift_0/a4" 58.7
cap "staticizer_0/staticizer_one_4/w_54_n57#" "staticizer_0/staticizer_one_4/Vdd!" -0.984
cap "staticizer_0/staticizer_one_4/a_60_n45#" "staticizer_0/staticizer_one_4/Vdd!" -2.744
cap "shift_0/shift_one_4/ad" "shift_0/a4" 125.762
cap "latch_0/out4" "staticizer_0/staticizer_one_4/Vdd!" 35.6
cap "latch_0/out4" "staticizer_0/staticizer_one_4/a_60_n45#" 31.249
cap "staticizer_0/staticizer_one_4/w_54_n57#" "latch_0/out4" 6.22
cap "staticizer_0/staticizer_one_4/a_77_n45#" "staticizer_0/staticizer_one_4/Vdd!" 1.13687e-13
cap "shift_0/shift_one_4/Vdd!" "shift_0/a4" 2.84217e-14
cap "latch_0/out4" "shift_0/shift_one_4/ad" 58.7
cap "staticizer_0/staticizer_one_4/c" "shift_0/a4" 76.935
cap "latch_0/out4" "shift_0/shift_one_4/Vdd!" 8.24
cap "staticizer_0/staticizer_one_4/Vdd!" "shift_0/a4" -12.11
cap "shift_0/shift_one_4/Vdd!" "wz4" 91.858
cap "shift_0/Vdd!" "rx4" 58.7
cap "shift_0/GND!" "wz4" 58.7
cap "shift_0/Vdd!" "wz4" 58.7
cap "shift_0/u" "rx4" 58.7
cap "shift_0/shift_one_4/inv_2/GND!" "rx4" 11.43
cap "shift_0/u" "wz4" 58.7
cap "shift_0/shift_one_4/inv_2/GND!" "wz4" 21.418
cap "rx4" "shift_0/shift_one_4/inv_2/in" 14.74
cap "shift_0/shift_one_4/m1_n60_n65#" "wz4" 11.825
cap "shift_0/shift_one_4/Vdd!" "rx4" 7.239
cap "wz4" "shift_0/shift_one_4/inv_2/out" 25.522
cap "shift_0/GND!" "rx4" 58.7
cap "latch_3/latch_one_4/GND!" "wz4" 66.689
cap "shift_0/o4" "rx4" 20.945
cap "latch_3/latch_one_4/a_12_n54#" "wz4" 4.95
cap "latch_3/latch_one_4/Vdd!" "shift_0/o4" 9.594
cap "shift_0/o4" "wz4" 2.184
cap "rx4" "shift_0/s" 58.7
cap "shift_0/shift_one_4/2mux_nr_1/out" "shift_0/o4" 57.7175
cap "latch_3/latch_one_4/Vdd!" "latch_3/latch_one_4/a_n5_n54#" -1.13687e-13
cap "shift_0/shift_one_4/inv_3/Vdd!" "shift_0/o4" 1.162
cap "latch_3/latch_one_4/a_n5_n54#" "wz4" 30.853
cap "shift_0/o4" "latch_3/latch_one_4/GND!" 30.043
cap "wz4" "shift_0/s" 58.7
cap "latch_3/latch_one_4/Vdd!" "rx4" 58.7
cap "rx4" "shift_0/shift_one_4/inv_3/GND!" 6.096
cap "rx4" "latch_3/latch_one_4/c" 3.12
cap "latch_3/latch_one_4/Vdd!" "wz4" 64.715
cap "shift_0/shift_one_4/inv_3/GND!" "wz4" 3.152
cap "shift_0/shift_one_4/inv_3/Vdd!" "rx4" 7.239
cap "latch_3/latch_one_4/c" "wz4" 1.248
cap "latch_3/latch_one_4/a_n5_n54#" "shift_0/o4" 57.7175
cap "rx4" "latch_3/latch_one_4/GND!" 107.383
cap "latch_3/latch_one_4/Vdd!" "shift_0/shift_one_4/2mux_nr_1/out" 46.174
cap "shift_0/shift_one_4/2mux_nr_1/out" "wz4" 8.599
cap "shift_0/shift_one_4/inv_3/Vdd!" "wz4" 72.651
cap "fblock_0/fblock_one_4/2mux_nr_2/in1" "latch_3/out4" 9.35
cap "latch_3/out4" "fblock_0/g3" 58.7
cap "fblock_0/a4" "fblock_0/fblock_one_4/2mux_nr_2/a_n17_n11#" 11.004
cap "latch_3/latch_one_4/GND!" "latch_3/latch_one_4/c" 2.84217e-14
cap "latch_3/latch_one_4/GND!" "fblock_0/a4" 0.083
cap "fblock_0/fblock_one_4/2mux_nr_2/in0" "fblock_0/a4" 4.389
cap "latch_3/latch_one_4/Vdd!" "latch_3/latch_one_4/a_12_n54#" 2.84217e-14
cap "latch_3/latch_one_4/c" "fblock_0/a4" 78.258
cap "fblock_0/fblock_one_4/inv_0/Vdd!" "fblock_0/a4" 82.685
cap "fblock_0/fblock_one_4/inv_0/GND!" "fblock_0/a4" 56.9869
cap "fblock_0/a4" "fblock_0/fblock_one_4/inv_0/in" 9.081
cap "latch_3/out4" "latch_3/latch_one_4/Vdd!" 0.959
cap "fblock_0/g2" "fblock_0/a4" 58.7
cap "fblock_0/GND!" "fblock_0/a4" 58.7
cap "latch_3/out4" "fblock_0/fblock_one_4/2mux_nr_2/a_n17_n11#" 14.683
cap "fblock_0/fblock_one_4/2mux_nr_2/in1" "fblock_0/a4" 5.115
cap "fblock_0/a4" "fblock_0/g3" 542.798
cap "fblock_0/fblock_one_4/2mux_nr_2/in0" "latch_3/out4" 7.975
cap "latch_3/latch_one_4/GND!" "latch_3/out4" 1.209
cap "latch_3/out4" "latch_3/latch_one_4/c" 140.424
cap "fblock_0/fblock_one_4/inv_0/GND!" "latch_3/out4" 38.323
cap "fblock_0/g2" "latch_3/out4" 58.7
cap "latch_3/out4" "fblock_0/fblock_one_4/inv_0/in" 19.302
cap "latch_3/out4" "fblock_0/a4" 4.948
cap "latch_3/out4" "fblock_0/GND!" 58.7
cap "fblock_0/a4" "fblock_0/fblock_one_4/2mux_nr_2/s" 0.486
cap "wz4" "fblock_0/fblock_one_5/inv_3/Vdd!" 58.7
cap "latch_1/latch_one_4/GND!" "rx4" 58.7
cap "fblock_0/f4" "latch_1/latch_one_4/GND!" 12.326
cap "rx4" "fblock_0/fblock_one_5/g1" 58.7
cap "fblock_0/f4" "rx4" 13.492
cap "latch_1/latch_one_4/Vdd!" "fblock_0/fblock_one_5/inv_3/Vdd!" 1341.25
cap "rx4" "fblock_0/fblock_one_4/inv_0/in" 2.844
cap "wz4" "latch_1/latch_one_4/Vdd!" 58.7
cap "fblock_0/fblock_one_4/inv_0/GND!" "fblock_0/fblock_one_4/inv_0/in" 5.68434e-14
cap "fblock_0/fblock_one_5/g0" "rx4" 58.7
cap "latch_1/latch_one_4/a_n5_n54#" "rx4" 7.807
cap "fblock_0/f4" "latch_1/latch_one_4/a_n5_n54#" 57.7175
cap "wz4" "latch_1/latch_one_4/GND!" 69.742
cap "rx4" "fblock_0/fblock_one_5/inv_3/Vdd!" 58.7
cap "wz4" "latch_1/latch_one_4/c" 4.324
cap "fblock_0/f4" "fblock_0/fblock_one_5/inv_3/Vdd!" 12.684
cap "wz4" "fblock_0/fblock_one_5/g1" 58.7
cap "wz4" "latch_1/latch_one_4/a_12_n54#" 9.731
cap "wz4" "fblock_0/f4" 18.093
cap "rx4" "fblock_0/fblock_one_4/f" 85.724
cap "wz4" "fblock_0/fblock_one_4/inv_0/in" 4.123
cap "wz4" "fblock_0/fblock_one_4/inv_0/GND!" 20.977
cap "wz4" "fblock_0/fblock_one_5/g0" 58.7
cap "wz4" "latch_1/latch_one_4/a_n5_n54#" 43.4
cap "latch_1/latch_one_4/Vdd!" "rx4" 103.828
cap "fblock_0/f4" "latch_1/latch_one_4/Vdd!" 6.108
subcap "ry4" -2473.35
cap "addsub_0/xor_4/a_69_n42#" "addsub_0/b4" 2.457
cap "rx4" "latch_1/latch_one_4/a_n5_n54#" 4.948
cap "latch_1/latch_one_4/GND!" "latch_1/out4" 3.821
cap "rx4" "latch_1/latch_one_4/a_30_n35#" 4.828
cap "rx4" "addsub_0/xor_4/GND!" 24.038
cap "rx4" "latch_1/out4" 9.182
cap "latch_1/latch_one_4/Vdd!" "rx4" -4.367
cap "rx4" "addsub_0/b4" 2.764
cap "latch_1/out4" "latch_1/latch_one_4/Vdd!" 1.221
cap "rx4" "addsub_0/xor_4/Vdd!" 8.496
cap "rx4" "latch_1/latch_one_4/c" 58.7
cap "latch_1/latch_one_4/a_30_n54#" "latch_1/out4" 1.524
cap "addsub_0/xor_4/b" "latch_1/out4" 11.825
cap "addsub_0/xor_4/b" "addsub_0/b4" 1.194
cap "rx4" "latch_1/latch_one_4/Vdd!" -1.405
cap "latch_1/out4" "latch_1/latch_one_4/a_n5_n54#" 15.975
cap "latch_1/out4" "latch_1/latch_one_4/GND!" 2.361
cap "addsub_0/xor_4/GND!" "latch_1/out4" 11.825
cap "rx4" "addsub_0/xor_4/b" 11.825
cap "rx4" "latch_1/latch_one_4/a_12_n54#" 4.948
cap "addsub_0/xor_4/GND!" "addsub_0/b4" 141.265
cap "addsub_0/xor_4/out" "addsub_0/b4" 1.053
cap "latch_1/latch_one_4/c" "latch_1/out4" 144.632
cap "addsub_0/addsub_one_4/GND!" "rx4" -0.341
cap "addsub_0/addsub_one_4/a_78_n41#" "as_cout" 4.204
cap "addsub_0/addsub_one_4/cout" "ry4" 10.71
cap "addsub_0/addsub_one_4/a_89_n41#" "as_cout" 11.175
cap "addsub_0/addsub_one_5/a" "as_cout" 4.204
cap "addsub_0/xor_4/b" "rx4" 2.424
cap "rx4" "addsub_0/addsub_one_4/b" 57.61
cap "addsub_0/addsub_one_4/s" "as_cout" 41.11
cap "rx4" "addsub_0/addsub_one_4/a_89_9#" 4.7
cap "wz4" "addsub_0/xor_4/Vdd!" 50.747
cap "addsub_0/addsub_one_4/a_78_n41#" "rx4" 11.825
cap "addsub_0/xor_4/Vdd!" "ry4" 28.817
cap "rx4" "addsub_0/xor_4/Vdd!" 90.279
cap "rx4" "addsub_0/xor_4/a_61_n1#" 72.796
cap "addsub_0/addsub_one_4/a" "as_cout" 4.204
cap "as_cout" "addsub_0/addsub_one_5/GND!" 54.437
cap "addsub_0/addsub_one_4/a_35_n41#" "as_cout" 4.204
cap "addsub_0/addsub_one_4/GND!" "as_cout" 32.475
cap "as_cout" "addsub_0/addsub_one_4/cout" 14.329
cap "wz4" "addsub_0/addsub_one_5/GND!" 18.211
cap "addsub_0/addsub_one_5/a_11_n41#" "as_cout" 10.65
cap "wz4" "addsub_0/addsub_one_4/a_35_n41#" 65.763
cap "as_cout" "addsub_0/addsub_one_4/b" 4.204
cap "addsub_0/xor_4/a" "rx4" 2.424
cap "addsub_0/addsub_one_4/GND!" "wz4" 0.308
cap "ry4" "addsub_0/addsub_one_5/GND!" 24.288
cap "rx4" "addsub_0/addsub_one_5/GND!" 20.114
cap "addsub_0/addsub_one_4/a_35_n41#" "rx4" 19.78
subcap "a_841_1097#" -38.45
cap "ry4" "latch_2/latch_one_4/c" 81.378
cap "latch_2/latch_one_4/Vdd!" "addsub_0/s4" 19.399
cap "latch_2/latch_one_4/a_30_n54#" "latch_2/out4" 2.592
cap "reg_0/reg_one_3/r0" "latch_2/out4" 63.6875
cap "addsub_0/addsub_one_5/GND!" "addsub_0/s4" 76.9567
cap "rx4" "reg_0/reg_one_3/r0" 19.78
cap "latch_2/latch_one_4/Vdd!" "latch_2/out4" 59.921
cap "addsub_0/addsub_one_5/GND!" "latch_2/out4" 19.247
cap "latch_2/latch_one_4/Vdd!" "rx4" 116.636
cap "rx4" "addsub_0/addsub_one_5/GND!" 16.973
cap "latch_2/out4" "addsub_0/addsub_one_4/GND!" 3.399
cap "latch_2/latch_one_4/GND!" "ry4" 110.895
cap "latch_2/latch_one_4/c" "latch_2/out4" 619.757
cap "rx4" "addsub_0/addsub_one_4/GND!" 7.942
cap "rx4" "latch_2/latch_one_4/c" 61.544
cap "addsub_0/addsub_one_4/a_35_n41#" "latch_2/out4" -1.814
cap "latch_2/latch_one_4/a_n5_n54#" "addsub_0/s4" 57.7175
cap "latch_2/latch_one_4/a_n5_n54#" "latch_2/out4" 12.196
cap "rx4" "latch_2/latch_one_4/a_n5_n54#" 6.195
cap "latch_2/latch_one_4/a_30_n35#" "rx4" 1.524
cap "latch_2/latch_one_4/GND!" "latch_2/out4" 90.233
cap "addsub_0/addsub_one_4/b" "rx4" -2.068
cap "latch_2/latch_one_4/GND!" "rx4" 58.7
cap "addsub_0/s4" "latch_2/out4" 4.948
cap "rx4" "addsub_0/s4" 3.468
cap "ry4" "reg_0/reg_one_3/r0" 17.308
cap "rx4" "latch_2/out4" 4.341
cap "latch_2/latch_one_4/Vdd!" "ry4" 58.7
cap "latch_2/latch_one_4/a_12_n54#" "latch_2/out4" 12.473
cap "addsub_0/a_127_360#" "ry4" 1.486
cap "addsub_0/addsub_one_5/GND!" "ry4" 20.633
cap "latch_2/latch_one_4/a_12_n54#" "rx4" 37.778
cap "reg_0/port40" "reg_0/reg_one_3/Vdd!" 134.044
cap "reg_0/reg_one_3/r1" "reg_0/port40" 70.642
cap "reg_0/w" "reg_0/port41" 127.744
cap "reg_0/port40" "reg_0/reg_one_3/r0" -7.416
cap "reg_0/port41" "reg_0/reg_one_3/w_n11_n27#" 121.694
cap "reg_0/reg_one_3/Vdd!" "reg_0/port41" 58.7
cap "reg_0/port40" "reg_0/w" 434.25
cap "reg_0/reg_one_3/a_4_n13#" "reg_0/port40" 20.417
cap "reg_0/w" "reg_0/reg_one_3/Vdd!" -3.55271e-15
cap "reg_0/port40" "reg_0/reg_one_3/w_n11_n27#" 194.315
cap "reg_0/port40" "reg_0/reg_one_3/tmp" 4.948
cap "reg_0/reg_one_3/r1" "reg_0/port41" 64.004
cap "reg_0/port40" "reg_0/reg_one_3/a_21_n13#" 20.118
cap "reg_0/reg_one_3/r0" "reg_0/port41" 23.94
cap "reg_1/reg_one_3/a_21_n13#" "reg_1/port40" 2.238
cap "reg_1/port40" "reg_1/reg_one_3/a_4_n13#" 118.494
cap "reg_1/port40" "reg_1/w" 125.763
cap "reg_1/port40" "reg_1/reg_one_3/tmp" 4.694
cap "reg_1/port40" "reg_1/port41" 3.85
cap "reg_1/reg_one_3/r0" "reg_1/port41" 48.664
cap "reg_1/port40" "reg_1/reg_one_3/Vdd!" 75.185
cap "reg_1/reg_one_3/w_n11_n27#" "reg_1/port41" 121.694
cap "reg_1/port40" "reg_1/reg_one_3/r1" 60.064
cap "reg_1/w" "reg_1/port41" 127.744
cap "reg_1/reg_one_3/Vdd!" "reg_1/w" -3.55271e-15
cap "reg_1/port40" "reg_1/reg_one_3/r0" 21.144
cap "reg_1/reg_one_3/Vdd!" "reg_1/port41" 58.7
cap "reg_1/port40" "reg_1/reg_one_3/w_n11_n27#" 198.775
cap "reg_1/reg_one_3/r1" "reg_1/port41" 64.004
cap "reg_2/reg_one_3/Vdd!" "reg_1/port40" 75.185
cap "reg_2/reg_one_3/a_4_n13#" "reg_1/port40" 118.494
cap "reg_2/w" "reg_1/port40" 92.2312
cap "reg_2/port41" "reg_2/reg_one_3/w_n11_n27#" 121.694
cap "reg_2/reg_one_3/Vdd!" "reg_2/w" -3.55271e-15
cap "reg_2/reg_one_3/r0" "reg_1/port40" 21.144
cap "reg_2/reg_one_3/tmp" "reg_1/port40" 4.694
cap "reg_2/reg_one_3/r1" "reg_1/port40" 60.064
cap "reg_2/port41" "reg_1/port40" 3.85
cap "reg_2/reg_one_3/Vdd!" "reg_2/reg_one_3/r1" 2.27374e-13
cap "reg_2/reg_one_3/Vdd!" "reg_2/port41" 58.7
cap "reg_2/w" "reg_2/port41" 94.2122
cap "reg_2/reg_one_3/w_n11_n27#" "reg_1/port40" 135.088
cap "reg_2/port41" "reg_2/reg_one_3/r0" 48.664
cap "reg_2/reg_one_3/a_21_n13#" "reg_1/port40" 2.238
cap "reg_2/port41" "reg_2/reg_one_3/r1" 64.004
cap "reg_2/port40" "reg_3/reg_one_3/Vdd!" 74.654
cap "reg_2/w" "reg_2/port41" 33.5312
cap "reg_3/port41" "reg_3/w" 5.072
cap "reg_2/w" "reg_2/port40" 33.5312
cap "reg_2/port41" "reg_3/reg_one_3/r1" 64.004
cap "reg_3/reg_one_3/a_21_n13#" "reg_2/port40" 2.238
cap "reg_3/port41" "reg_2/port41" 73.199
cap "reg_2/port40" "reg_3/reg_one_3/a_4_n13#" 118.494
cap "reg_3/reg_one_3/r1" "reg_2/port40" 60.064
cap "reg_3/port41" "reg_2/port40" 3.85
cap "reg_2/port40" "reg_3/reg_one_3/tmp" 4.694
cap "reg_3/port40" "reg_2/port40" 8.58
cap "reg_3/port41" "reg_3/reg_one_3/w_n11_n27#" 1.628
cap "reg_3/reg_one_3/w_n11_n27#" "reg_2/port41" 106.567
cap "reg_3/reg_one_3/r1" "reg_3/reg_one_3/Vdd!" 2.27374e-13
cap "reg_3/reg_one_3/w_n11_n27#" "reg_2/port40" 63.11
cap "reg_2/port41" "reg_3/reg_one_3/r0" 48.664
cap "reg_2/reg_one_3/w_n11_n27#" "reg_2/port40" 63.6875
cap "reg_2/port40" "reg_3/reg_one_3/r0" 21.144
cap "reg_2/port41" "reg_3/reg_one_3/Vdd!" 58.7
subcap "wz_addrL4" -530.966
subcap "PCL_w_muxout4" -380.236
cap "mux_8bit_0/sel" "mux_8bit_0/in0_4" 58.7
cap "reg_3/port41" "mux_8bit_0/mux_one_4/inv2_2/GND!" 63.013
cap "reg_3/port41" "reg_3/reg_one_3/w_n11_n27#" -1.039
cap "mux_8bit_0/out4" "mux_8bit_0/mux_one_4/inv2_2/GND!" 37.928
cap "mux_8bit_0/Vdd!" "mux_8bit_0/in0_4" 58.7
cap "reg_3/reg_one_3/Vdd!" "reg_3/port40" -2.898
cap "reg_3/reg_one_3/Vdd!" "reg_3/w" -3.55271e-15
cap "reg_3/reg_one_3/Vdd!" "reg_3/reg_one_3/w_n11_n27#" -1.42109e-14
cap "mux_8bit_0/mux_one_4/inv2_2/GND!" "mux_8bit_0/in0_4" 12.279
cap "reg_3/port40" "reg_3/w" 125.763
cap "reg_3/reg_one_3/w_n11_n27#" "reg_3/port40" 135.615
cap "reg_3/reg_one_3/w_n11_n27#" "reg_3/port40" -3.379
cap "reg_3/port41" "mux_8bit_0/out4" -10.01
cap "reg_3/port41" "mux_8bit_0/sel" 58.7
cap "mux_8bit_0/in0_4" "mux_8bit_0/mux_one_4/2mux_nr_0/in0" 29.025
cap "mux_8bit_0/mux_one_4/inv2_2/Vdd!" "mux_8bit_0/in0_4" 20.196
cap "mux_8bit_0/out4" "mux_8bit_0/sel" 0.84
cap "mux_8bit_0/out4" "mux_8bit_0/in0_4" 30.603
cap "mux_8bit_0/mux_one_4/inv2_1/a_1_8#" "mux_8bit_0/in0_4" 19.462
cap "reg_3/port41" "mux_8bit_0/Vdd!" 58.7
cap "mux_8bit_0/mux_one_4/inv2_2/Vdd!" "mux_8bit_0/Vdd!" 2.84217e-14
cap "reg_3/port41" "reg_3/reg_one_3/w_n11_n27#" 12.7375
cap "reg_3/port41" "reg_3/w" 127.744
subcap "PCL4" -150.146
cap "ry4" "reg_4/port41" 73.199
cap "ry4" "mux_8bit_0/out4" -17.369
cap "ry4" "mux_8bit_0/GND!" 58.7
cap "reg_4/reg_one_3/a_4_n13#" "wz_addrL4" 47.175
cap "ry4" "reg_4/reg_one_3/r0" 48.664
cap "reg_4/reg_one_3/r1" "wz_addrL4" 59.948
cap "reg_4/reg_one_3/Vdd!" "wz_addrL4" 73.616
cap "reg_4/reg_one_3/Vdd!" "mux_8bit_0/out4" 41.182
cap "reg_4/reg_one_3/r0" "reg_4/reg_one_3/Vdd!" -6.512
cap "reg_4/reg_one_3/tmp" "wz_addrL4" 4.68
cap "mux_8bit_0/mux_one_4/inv2_1/GND!" "wz_addrL4" 6.72
cap "reg_4/reg_one_3/w_n11_n27#" "wz_addrL4" 76.564
cap "reg_4/reg_one_3/w_n11_n27#" "reg_4/port41" 1.628
cap "ry4" "reg_4/reg_one_3/r1" 64.004
cap "ry4" "reg_4/reg_one_3/Vdd!" 58.7
cap "mux_8bit_0/out4" "mux_8bit_0/mux_one_4/inv2_1/GND!" 400.316
cap "wz_addrL4" "reg_4/port41" 4.95
cap "mux_8bit_0/out4" "wz_addrL4" -6.325
cap "mux_8bit_0/GND!" "mux_8bit_0/mux_one_4/inv2_1/GND!" -3.444
cap "mux_8bit_0/GND!" "wz_addrL4" 58.7
cap "mux_8bit_0/out4" "mux_8bit_0/GND!" 46.74
cap "reg_4/reg_one_3/r0" "wz_addrL4" 21.028
cap "reg_4/reg_one_3/r0" "mux_8bit_0/out4" 289.193
cap "reg_4/port41" "reg_4/w" 5.072
cap "mux_8bit_0/out4" "mux_8bit_0/mux_one_4/2mux_nr_0/out" 85.4219
cap "mux_8bit_0/mux_one_4/inv2_1/GND!" "mux_8bit_0/mux_one_4/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "mux_8bit_0/mux_one_4/inv2_1/a_1_8#" "wz_addrL4" -1.132
cap "ry4" "mux_8bit_0/mux_one_4/inv2_1/GND!" -6.916
cap "ry4" "reg_4/reg_one_3/w_n11_n27#" 106.567
cap "reg_4/port40" "wz_addrL4" 9.229
cap "reg_4/reg_one_3/Vdd!" "wz_addrL4" -2.948
cap "wz_addrL4" "addsub_1/xor_4/b" 7.975
cap "reg_4/port40" "wz_addrL4" -7.348
cap "addsub_1/b4" "addsub_1/xor_4/b" 11.5435
cap "reg_4/port41" "addsub_1/xor_4/b" 11.825
cap "addsub_1/b4" "reg_4/port40" 38.809
cap "wz_addrL4" "reg_4/reg_one_3/w_n11_n27#" -3.379
cap "addsub_1/b4" "wz_addrL4" 7.975
cap "addsub_1/b4" "addsub_1/xor_4/a_61_n31#" 2.84217e-14
cap "reg_4/reg_one_3/Vdd!" "reg_4/reg_one_3/w_n11_n27#" -7.10543e-15
cap "reg_4/port40" "reg_4/reg_one_3/w_n11_n27#" 63.6875
cap "reg_4/port41" "reg_4/reg_one_3/w_n11_n27#" -1.039
cap "wz_addrL4" "reg_4/w" 58.7
cap "addsub_1/xor_4/Vdd!" "reg_4/port40" 23.31
cap "reg_4/port41" "addsub_1/b4" 11.825
cap "reg_4/reg_one_3/w_n11_n27#" "wz_addrL4" 8.24
cap "addsub_1/xor_4/Vdd!" "wz_addrL4" 11.825
cap "reg_4/port41" "reg_4/w" 127.744
cap "reg_4/port41" "reg_4/reg_one_3/w_n11_n27#" 12.7375
cap "reg_4/port41" "addsub_1/xor_4/Vdd!" 11.825
cap "addsub_1/xor_4/a_61_n1#" "reg_4/port40" 67.028
cap "reg_4/port40" "addsub_1/xor_4/b" 115.766
subcap "a_1716_1097#" -30.357
cap "addsub_1/addsub_one_4/Vdd!" "ry4" 9.108
cap "addsub_1/addsub_one_5/GND!" "addsub_1/addsub_one_4/a_35_n41#" 5.68434e-14
cap "wz_addrL4" "addsub_1/addsub_one_4/GND!" 10.505
cap "addsub_1/addsub_one_4/a_35_n41#" "wz_addrL4" 24.622
cap "a_2510_1893#" "addsub_1/addsub_one_4/b" 4.204
cap "addsub_1/addsub_one_5/GND!" "addsub_1/addsub_one_4/b" -5.68434e-14
cap "addsub_1/s4" "latch_5/latch_one_4/Vdd!" -12.402
cap "wz_addrL4" "addsub_1/addsub_one_4/Vdd!" 32.72
cap "a_2510_1893#" "addsub_1/addsub_one_4/a_78_n41#" 4.204
cap "addsub_1/addsub_one_4/a" "a_2510_1893#" 4.204
cap "addsub_1/addsub_one_5/GND!" "ry4" 48.35
cap "addsub_1/addsub_one_5/a" "a_2510_1893#" 4.204
cap "ry4" "addsub_1/addsub_one_4/cout" 17.812
cap "addsub_1/s4" "latch_5/latch_one_4/a_n5_n54#" 19.2392
cap "addsub_1/s4" "a_2510_1893#" 41.11
cap "a_2510_1893#" "addsub_1/addsub_one_4/a_89_n41#" 11.175
cap "addsub_1/addsub_one_5/GND!" "addsub_1/s4" 76.9567
cap "addsub_1/addsub_one_5/GND!" "a_2510_1893#" 54.437
cap "a_2510_1893#" "addsub_1/addsub_one_4/cout" 14.329
cap "addsub_1/addsub_one_5/GND!" "wz_addrL4" 55.484
cap "addsub_1/addsub_one_5/a_11_n41#" "a_2510_1893#" 10.65
cap "a_2510_1893#" "addsub_1/addsub_one_4/GND!" 32.475
cap "addsub_1/addsub_one_4/a_35_n41#" "a_2510_1893#" 4.204
subcap "a_1716_1097#" -99.769
cap "latch_5/latch_one_4/a_12_n54#" "latch_5/latch_one_4/Vdd!" 1.13687e-13
cap "ry4" "latch_5/latch_one_4/c" 81.378
cap "staticizer_2/staticizer_one_4/a_77_n45#" "latch_5/out4" 9.998
cap "staticizer_2/staticizer_one_4/a_60_n45#" "latch_5/out4" 212.283
cap "latch_5/latch_one_4/GND!" "latch_5/latch_one_4/Vdd!" -0.984
cap "latch_5/latch_one_4/Vdd!" "latch_5/out4" 231.426
cap "latch_5/latch_one_4/GND!" "staticizer_2/staticizer_one_4/c" -5.68434e-14
cap "ry4" "latch_5/latch_one_4/Vdd!" 117.4
cap "latch_5/latch_one_4/a_n5_n54#" "latch_5/out4" 59.375
cap "latch_5/out4" "addsub_1/s4" 4.324
cap "staticizer_2/staticizer_one_4/c" "latch_5/out4" 63.648
cap "addsub_1/GND!" "addsub_1/s4" 19.2392
cap "latch_5/latch_one_4/a_30_n54#" "latch_5/out4" 1.524
cap "latch_5/latch_one_4/Vdd!" "latch_5/latch_one_4/c" 1071.03
cap "latch_5/latch_one_4/a_12_n54#" "latch_5/out4" 9.731
cap "ry4" "staticizer_2/staticizer_one_4/c" 76.935
cap "latch_5/latch_one_4/GND!" "latch_5/out4" 167.247
cap "ry4" "latch_5/latch_one_4/GND!" 181.284
cap "latch_5/latch_one_4/GND!" "latch_5/latch_one_4/c" 13.8522
cap "latch_5/latch_one_4/Vdd!" "addsub_1/s4" 19.399
cap "latch_5/latch_one_4/c" "latch_5/out4" 75.182
cap "latch_5/latch_one_4/a_n5_n54#" "addsub_1/s4" 57.7175
subcap "wz_addrH4" -915.907
subcap "m1_1909_1070#" -380.236
cap "staticizer_2/staticizer_one_4/out" "staticizer_2/staticizer_one_4/a_95_n27#" 5.61
cap "mux_8bit_1/mux_one_4/inv2_2/GND!" "mux_8bit_1/out4" 37.928
cap "mux_8bit_1/mux_one_4/inv2_2/GND!" "ry4" 63.013
cap "staticizer_2/staticizer_one_4/w_54_n57#" "ry4" 4.329
cap "mux_8bit_1/mux_one_4/inv2_2/GND!" "mux_8bit_1/in0_4" 18.437
cap "mux_8bit_1/mux_one_4/inv2_2/Vdd!" "mux_8bit_1/Vdd!" 2.84217e-14
cap "staticizer_2/staticizer_one_4/out" "staticizer_2/staticizer_one_4/a_95_n45#" 4.212
cap "ry4" "mux_8bit_1/Vdd!" 58.7
cap "staticizer_2/staticizer_one_4/out" "staticizer_2/staticizer_one_4/a_60_n45#" -5.616
cap "mux_8bit_1/in0_4" "mux_8bit_1/mux_one_4/inv2_2/Vdd!" 91.282
cap "mux_8bit_1/in0_4" "mux_8bit_1/Vdd!" 58.7
cap "ry4" "mux_8bit_1/out4" -10.01
cap "mux_8bit_1/in0_4" "mux_8bit_1/mux_one_4/2mux_nr_0/in0" 34.083
cap "staticizer_2/staticizer_one_4/Vdd!" "staticizer_2/staticizer_one_4/out" 11.587
cap "staticizer_2/staticizer_one_4/out" "staticizer_2/staticizer_one_4/c" 3.996
cap "mux_8bit_1/sel" "mux_8bit_1/out4" 0.84
cap "mux_8bit_1/sel" "ry4" 58.7
cap "mux_8bit_1/in0_4" "mux_8bit_1/mux_one_4/inv2_1/a_1_8#" 4.95
cap "mux_8bit_1/in0_4" "mux_8bit_1/sel" 58.7
cap "staticizer_2/staticizer_one_4/w_54_n57#" "staticizer_2/staticizer_one_4/out" 2.59
cap "staticizer_2/staticizer_one_4/out" "staticizer_2/staticizer_one_4/a_77_n45#" 19.052
cap "reg_5/port41" "reg_5/reg_one_3/w_n11_n27#" 1.628
cap "reg_5/port41" "ry4" 73.199
cap "wz_addrH4" "reg_5/reg_one_3/r1" 58.7
cap "reg_5/port40" "wz_addrH4" 6.6
cap "mux_8bit_1/out4" "reg_5/reg_one_3/Vdd!" 41.182
cap "ry4" "reg_5/reg_one_3/r0" 48.664
cap "reg_5/reg_one_3/w_n11_n27#" "ry4" 106.567
cap "wz_addrH4" "reg_5/reg_one_3/Vdd!" 162.612
cap "ry4" "reg_5/reg_one_3/r1" 64.004
cap "wz_addrH4" "reg_5/reg_one_3/tmp" 4.948
cap "mux_8bit_1/mux_one_4/inv2_1/GND!" "mux_8bit_1/mux_one_4/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "mux_8bit_1/out4" "mux_8bit_1/GND!" 46.74
cap "reg_5/reg_one_3/a_54_5#" "wz_addrH4" 4.828
cap "mux_8bit_1/out4" "mux_8bit_1/mux_one_4/2mux_nr_0/out" 85.4219
cap "reg_5/reg_one_3/Vdd!" "reg_5/reg_one_3/r0" -6.512
cap "reg_5/port41" "reg_5/w" 5.072
cap "mux_8bit_1/mux_one_4/inv2_1/GND!" "mux_8bit_1/GND!" -3.444
cap "mux_8bit_1/mux_one_4/inv2_1/GND!" "mux_8bit_1/out4" 400.316
cap "ry4" "reg_5/reg_one_3/Vdd!" 58.7
cap "wz_addrH4" "mux_8bit_1/GND!" 58.7
cap "wz_addrH4" "reg_5/reg_one_3/a_4_n13#" 27.497
cap "wz_addrH4" "mux_8bit_1/out4" -6.325
cap "mux_8bit_1/mux_one_4/inv2_1/GND!" "wz_addrH4" 8.954
cap "mux_8bit_1/out4" "reg_5/reg_one_3/r0" 289.193
cap "ry4" "mux_8bit_1/GND!" 58.7
cap "ry4" "mux_8bit_1/out4" -17.369
cap "reg_5/reg_one_3/w_n11_n27#" "wz_addrH4" 58.7
cap "ry4" "mux_8bit_1/mux_one_4/inv2_1/GND!" -6.916
cap "wz_addrH4" "reg_5/reg_one_3/r0" 24.728
cap "reg_6/reg_one_3/a_21_n13#" "reg_5/port40" 3.96
cap "reg_5/port40" "reg_6/reg_one_3/r0" 26.208
cap "reg_5/port40" "reg_6/reg_one_3/tmp" 5.92
cap "reg_5/w" "reg_5/port40" 67.0625
cap "reg_5/reg_one_3/w_n11_n27#" "reg_5/port41" 1.628
cap "reg_6/reg_one_3/r0" "reg_6/reg_one_3/w_n11_n27#" 1.13687e-13
cap "reg_5/port40" "reg_6/reg_one_3/Vdd!" 58.7
cap "ry4" "reg_6/reg_one_3/w_n11_n27#" 101.233
cap "reg_5/reg_one_3/w_n11_n27#" "reg_5/port40" 127.375
cap "reg_6/reg_one_3/a_4_n13#" "reg_5/port40" 87.672
cap "reg_5/w" "reg_5/port41" 69.0435
cap "reg_5/port41" "reg_6/reg_one_3/r0" 19.78
cap "ry4" "reg_6/reg_one_3/port1" 68.579
cap "ry4" "reg_5/port41" -17.146
cap "wz_addrH4" "reg_6/reg_one_3/w_n11_n27#" 58.7
cap "reg_5/port41" "reg_6/reg_one_3/Vdd!" 58.7
cap "reg_5/reg_one_3/w_n11_n27#" "ry4" -2.667
cap "reg_5/port40" "reg_6/reg_one_3/r1" 64.504
cap "reg_6/reg_one_3/w_n11_n27#" "reg_6/reg_one_3/r1" -5.68434e-14
cap "reg_5/reg_one_3/w_n11_n27#" "reg_5/port41" 12.7375
cap "reg_5/reg_one_3/Vdd!" "reg_5/w" -3.55271e-15
cap "ry4" "reg_6/reg_one_3/r0" 48.664
cap "reg_5/w" "ry4" 58.7
cap "reg_5/port41" "reg_6/reg_one_3/r1" 58.7
cap "reg_6/reg_one_3/a_54_5#" "wz_addrH4" 4.828
cap "ry4" "reg_6/reg_one_3/Vdd!" 58.7
cap "reg_5/reg_one_3/Vdd!" "reg_5/reg_one_3/w_n11_n27#" -7.10543e-15
cap "wz_addrH4" "reg_6/reg_one_3/r0" 24.728
cap "wz_addrH4" "reg_6/reg_one_3/tmp" 4.948
cap "reg_5/port40" "reg_6/reg_one_3/w_n11_n27#" 151.215
cap "reg_5/w" "wz_addrH4" 58.7
cap "reg_5/reg_one_3/Vdd!" "wz_addrH4" -2.417
cap "wz_addrH4" "reg_6/reg_one_3/Vdd!" 160.588
cap "reg_5/port40" "reg_6/reg_one_3/port1" 5.5
cap "ry4" "reg_6/reg_one_3/r1" 64.004
cap "reg_5/reg_one_3/w_n11_n27#" "wz_addrH4" 8.24
cap "reg_6/reg_one_3/a_4_n13#" "wz_addrH4" 17.113
cap "reg_5/port41" "reg_6/reg_one_3/w_n11_n27#" 83.267
cap "wz_addrH4" "reg_6/reg_one_3/r1" 58.7
subcap "m1_2209_1070#" -380.236
cap "reg_6/port41" "mux_8bit_2/Vdd!" 58.7
cap "rx_addrH4" "reg_6/w" 58.7
cap "mux_8bit_2/mux_one_4/inv2_2/GND!" "reg_6/port41" 63.013
cap "mux_8bit_2/sel" "reg_6/port41" 58.7
cap "reg_6/reg_one_3/w_n11_n27#" "rx_addrH4" 19.776
cap "reg_6/reg_one_3/a_4_n13#" "rx_addrH4" -10.448
cap "mux_8bit_2/out4" "reg_6/port41" -10.01
cap "mux_8bit_2/in0_4" "reg_6/port40" 3.171
cap "mux_8bit_2/in0_4" "reg_6/reg_one_3/Vdd!" -0.393
cap "reg_6/reg_one_3/w_n11_n27#" "reg_6/port41" 4.295
cap "reg_6/port41" "reg_6/w" 127.744
cap "mux_8bit_2/in0_4" "mux_8bit_2/mux_one_4/inv2_1/a_1_8#" 4.95
cap "ry_addrH4" "mux_8bit_2/Vdd!" 58.7
cap "ry_addrH4" "mux_8bit_2/sel" 58.7
cap "reg_6/port41" "reg_6/reg_one_3/w_n11_n27#" 12.7375
cap "reg_6/reg_one_3/tmp" "reg_6/reg_one_3/Vdd!" -3.55271e-15
cap "ry_addrH4" "reg_6/reg_one_3/w_n11_n27#" 0.019
cap "mux_8bit_2/mux_one_4/2mux_nr_0/in0" "mux_8bit_2/in0_4" 34.083
cap "ry_addrH4" "reg_6/w" 58.7
cap "mux_8bit_2/in0_4" "mux_8bit_2/mux_one_4/inv2_2/Vdd!" 81.239
cap "reg_6/port40" "rx_addrH4" 4.411
cap "mux_8bit_2/in0_4" "mux_8bit_2/Vdd!" 58.7
cap "mux_8bit_2/in0_4" "mux_8bit_2/mux_one_4/inv2_2/GND!" 18.437
cap "mux_8bit_2/in0_4" "mux_8bit_2/sel" 58.7
cap "reg_6/reg_one_3/Vdd!" "reg_6/reg_one_3/w_n11_n27#" -1.42109e-14
cap "reg_6/reg_one_3/Vdd!" "reg_6/reg_one_3/a_4_n13#" -7.10543e-15
cap "mux_8bit_2/mux_one_4/inv2_2/Vdd!" "mux_8bit_2/Vdd!" 2.84217e-14
cap "mux_8bit_2/in0_4" "rx_addrH4" 16.569
cap "mux_8bit_2/in0_4" "reg_6/w" 58.7
cap "mux_8bit_2/mux_one_4/2mux_nr_0/in0" "rx_addrH4" 30.259
cap "mux_8bit_2/in0_4" "reg_6/reg_one_3/w_n11_n27#" 8.24
cap "mux_8bit_2/in0_4" "reg_6/reg_one_3/a_4_n13#" -1.152
cap "mux_8bit_2/mux_one_4/inv2_2/Vdd!" "rx_addrH4" 17.542
cap "mux_8bit_2/mux_one_4/inv2_2/GND!" "mux_8bit_2/out4" 37.928
cap "mux_8bit_2/mux_one_4/inv2_2/GND!" "rx_addrH4" 22.523
cap "mux_8bit_2/Vdd!" "rx_addrH4" 58.7
cap "mux_8bit_2/sel" "mux_8bit_2/out4" 0.84
cap "mux_8bit_2/sel" "rx_addrH4" 58.7
cap "mux_8bit_2/out4" "rx_addrH4" 19.905
cap "reg_6/reg_one_3/w_n11_n27#" "rx_addrH4" -2.286
cap "reg_6/port40" "reg_6/reg_one_3/Vdd!" -7.10543e-15
cap "reg_7/reg_one_3/a_4_n13#" "rx_addrH4" 93.704
cap "ry4" "reg_7/reg_one_3/Vdd!" 58.7
cap "ry_addrH4" "reg_7/reg_one_3/Vdd!" 58.7
cap "reg_7/reg_one_3/tmp" "wz_addrH4" 4.948
cap "wz_addrH4" "mux_8bit_2/GND!" 58.7
cap "rx_addrH4" "reg_7/reg_one_3/r0" 26.208
cap "reg_7/reg_one_3/Vdd!" "wz_addrH4" 162.612
cap "reg_7/port40" "wz_addrH4" 6.6
cap "reg_7/reg_one_3/a_21_n13#" "rx_addrH4" 3.96
cap "rx_addrH4" "mux_8bit_2/out4" -6.325
cap "mux_8bit_2/mux_one_4/inv2_1/GND!" "rx_addrH4" 12.194
cap "rx_addrH4" "reg_7/reg_one_3/r1" 64.504
cap "reg_7/port41" "rx_addrH4" 5.5
cap "mux_8bit_2/out4" "reg_7/reg_one_3/r0" 289.193
cap "mux_8bit_2/mux_one_4/2mux_nr_0/a_n17_n11#" "mux_8bit_2/mux_one_4/inv2_1/GND!" 3.55271e-15
cap "reg_7/reg_one_3/a_4_n13#" "wz_addrH4" 27.497
cap "rx_addrH4" "reg_7/reg_one_3/w_n11_n27#" 163.513
cap "ry4" "reg_7/reg_one_3/r0" 48.664
cap "mux_8bit_2/mux_one_4/inv2_1/GND!" "mux_8bit_2/out4" 400.316
cap "ry_addrH4" "reg_7/reg_one_3/r0" 19.78
cap "ry4" "mux_8bit_2/out4" -17.369
cap "ry4" "mux_8bit_2/mux_one_4/inv2_1/GND!" -6.916
cap "ry4" "reg_7/reg_one_3/r1" 64.004
cap "ry_addrH4" "reg_7/reg_one_3/r1" 58.7
cap "ry4" "reg_7/port41" 73.199
cap "mux_8bit_2/out4" "mux_8bit_2/mux_one_4/2mux_nr_0/out" 85.4219
cap "reg_7/port41" "reg_7/reg_one_3/w_n11_n27#" 1.628
cap "ry4" "reg_7/reg_one_3/w_n11_n27#" 106.567
cap "wz_addrH4" "reg_7/reg_one_3/r0" 24.728
cap "ry_addrH4" "reg_7/reg_one_3/w_n11_n27#" 86.284
cap "mux_8bit_2/out4" "wz_addrH4" -6.325
cap "wz_addrH4" "reg_7/reg_one_3/r1" 58.7
cap "mux_8bit_2/mux_one_4/inv2_1/GND!" "wz_addrH4" 8.954
cap "rx_addrH4" "reg_7/reg_one_3/tmp" 5.92
cap "rx_addrH4" "mux_8bit_2/GND!" 58.7
cap "wz_addrH4" "reg_7/reg_one_3/a_54_5#" 4.828
cap "wz_addrH4" "reg_7/reg_one_3/w_n11_n27#" 58.7
cap "mux_8bit_2/out4" "mux_8bit_2/GND!" 46.74
cap "mux_8bit_2/mux_one_4/inv2_1/GND!" "mux_8bit_2/GND!" -3.444
cap "reg_7/reg_one_3/Vdd!" "rx_addrH4" 58.7
cap "ry4" "mux_8bit_2/GND!" 58.7
cap "rx_addrH4" "reg_7/port40" 6.006
cap "ry_addrH4" "mux_8bit_2/GND!" 58.7
cap "reg_7/reg_one_3/Vdd!" "reg_7/reg_one_3/r0" -6.512
cap "reg_7/reg_one_3/Vdd!" "mux_8bit_2/out4" 41.182
cap "reg_7/port41" "reg_7/w" 5.072
cap "reg_7/reg_one_3/w_n11_n27#" "ry4" -2.667
cap "ry4" "reg_7/port41" -17.146
cap "addsub_2/xor_4/Vdd!" "ry4" 11.825
cap "addsub_2/xor_4/Vdd!" "wz_addrH4" 11.825
cap "reg_7/reg_one_3/w_n11_n27#" "reg_7/port41" 12.7375
cap "addsub_2/b4" "reg_7/port41" 11.825
cap "reg_7/port40" "addsub_2/xor_4/a_61_n1#" 67.028
cap "reg_7/w" "reg_7/port41" 127.744
cap "addsub_2/xor_4/b" "ry4" 11.825
cap "reg_7/port40" "reg_7/reg_one_3/w_n11_n27#" -3.048
cap "addsub_2/b4" "addsub_2/xor_4/a_61_n31#" 1.86517e-14
cap "reg_7/port40" "addsub_2/xor_4/Vdd!" 23.31
cap "addsub_2/xor_4/b" "wz_addrH4" 11.825
cap "reg_7/reg_one_3/Vdd!" "wz_addrH4" -2.417
cap "reg_7/reg_one_3/w_n11_n27#" "reg_7/port41" -1.37
cap "reg_7/port40" "addsub_2/xor_4/b" 115.766
cap "reg_7/w" "ry4" 58.7
cap "reg_7/reg_one_3/Vdd!" "reg_7/w" -3.55271e-15
cap "reg_7/reg_one_3/w_n11_n27#" "reg_7/reg_one_3/Vdd!" -7.10543e-15
cap "addsub_2/xor_4/Vdd!" "reg_7/port41" 11.825
cap "addsub_2/b4" "ry4" 11.825
cap "reg_7/w" "wz_addrH4" 58.7
cap "reg_7/reg_one_3/w_n11_n27#" "wz_addrH4" 8.24
cap "addsub_2/b4" "wz_addrH4" 5.939
cap "addsub_2/xor_4/b" "reg_7/port41" 11.825
cap "reg_7/port40" "reg_7/reg_one_3/w_n11_n27#" 135.615
cap "reg_7/port40" "reg_7/w" 125.763
cap "reg_7/port40" "addsub_2/b4" 38.809
subcap "a_2516_1097#" -30.357
cap "addsub_2/addsub_one_4/GND!" "wz_addrH4" 4.95
cap "addsub_2/addsub_one_4/Vdd!" "wz_addrH4" 22.705
cap "ry_addrH4" "addsub_2/addsub_one_5/GND!" 45.221
cap "addsub_2/s4" "addsub_2/addsub_one_5/GND!" 76.9567
cap "ry4" "addsub_2/addsub_one_4/cout" 19.952
cap "addsub_2/s4" "latch_6/latch_one_4/Vdd!" -12.402
cap "ry4" "addsub_2/addsub_one_5/GND!" 52.91
cap "ry_addrH4" "addsub_2/addsub_one_4/Vdd!" -4.455
cap "addsub_2/addsub_one_4/a_35_n41#" "wz_addrH4" 19.78
cap "addsub_2/addsub_one_5/GND!" "addsub_2/addsub_one_4/b" -5.68434e-14
cap "addsub_2/addsub_one_5/GND!" "wz_addrH4" 39.409
cap "addsub_2/addsub_one_4/a_35_n41#" "addsub_2/addsub_one_5/GND!" 5.68434e-14
cap "ry4" "addsub_2/addsub_one_4/Vdd!" 9.108
cap "ry_addrH4" "addsub_2/addsub_one_4/cout" 2.474
cap "addsub_2/s4" "latch_6/latch_one_4/a_n5_n54#" 19.2392
cap "addsub_2/s4" "wz_addrH4" 50.259
subcap "a_2516_1097#" -99.769
cap "latch_6/latch_one_4/a_n5_n54#" "addsub_2/s4" 57.7175
cap "staticizer_3/staticizer_one_4/out" "latch_6/latch_one_4/a_12_n54#" 9.708
cap "ry4" "latch_6/latch_one_4/c" 81.378
cap "latch_6/latch_one_4/GND!" "latch_6/out4" 10.156
cap "staticizer_3/staticizer_one_4/c" "latch_6/latch_one_4/GND!" 5.68434e-14
cap "latch_6/latch_one_4/GND!" "latch_6/latch_one_4/Vdd!" 2.27374e-13
cap "latch_6/latch_one_4/Vdd!" "latch_6/out4" 107.428
cap "staticizer_3/staticizer_one_4/a_60_n45#" "latch_6/out4" 150.065
cap "ry_addrH4" "latch_6/latch_one_4/GND!" 117.4
cap "addsub_2/s4" "latch_6/latch_one_4/Vdd!" 19.399
cap "staticizer_3/staticizer_one_4/out" "latch_6/latch_one_4/c" 61.66
cap "staticizer_3/staticizer_one_4/c" "ry_addrH4" 58.7
cap "ry_addrH4" "latch_6/latch_one_4/Vdd!" 117.4
cap "latch_6/latch_one_4/a_12_n54#" "latch_6/latch_one_4/Vdd!" 1.13687e-13
cap "ry4" "latch_6/latch_one_4/GND!" 181.284
cap "staticizer_3/staticizer_one_4/c" "ry4" 76.935
cap "staticizer_3/staticizer_one_4/out" "latch_6/latch_one_4/a_n5_n54#" 59.464
cap "ry4" "latch_6/latch_one_4/Vdd!" 117.4
cap "latch_6/latch_one_4/c" "latch_6/out4" 9.252
cap "latch_6/latch_one_4/GND!" "latch_6/latch_one_4/c" 13.8522
cap "staticizer_3/staticizer_one_4/out" "staticizer_3/staticizer_one_4/a_77_n45#" 5.115
cap "latch_6/latch_one_4/Vdd!" "latch_6/latch_one_4/c" 1070.42
cap "staticizer_3/staticizer_one_4/out" "latch_6/out4" 7.047
cap "staticizer_3/staticizer_one_4/out" "latch_6/latch_one_4/GND!" 117.4
cap "staticizer_3/staticizer_one_4/out" "latch_6/latch_one_4/a_30_n35#" 1.88
cap "ry_addrH4" "latch_6/latch_one_4/c" 58.7
cap "staticizer_3/staticizer_one_4/out" "staticizer_3/staticizer_one_4/c" 61.544
cap "staticizer_3/staticizer_one_4/out" "latch_6/latch_one_4/Vdd!" 169.606
cap "addsub_2/GND!" "addsub_2/s4" 19.2392
cap "staticizer_3/staticizer_one_4/out" "addsub_2/s4" 6.404
cap "staticizer_3/staticizer_one_4/out" "staticizer_3/staticizer_one_4/a_60_n45#" 75.3524
subcap "addr_out4" -56.838
cap "latch_7/out4" "latch_7/latch_one_4/c" 9.252
cap "staticizer_3/staticizer_one_4/c" "staticizer_3/staticizer_one_4/w_54_n57#" -1.42109e-14
cap "staticizer_3/staticizer_one_4/out" "staticizer_3/staticizer_one_4/a_60_n45#" 0.709429
cap "staticizer_3/staticizer_one_4/w_54_n57#" "latch_7/in4" 17.972
cap "ry_addrH4" "latch_7/latch_one_4/c" 58.7
cap "staticizer_3/staticizer_one_4/out" "staticizer_3/staticizer_one_4/a_77_n45#" 2.728
cap "latch_7/latch_one_4/GND!" "latch_7/latch_one_4/c" 13.8522
cap "latch_7/in4" "latch_7/latch_one_4/a_n5_n54#" 57.7175
cap "latch_7/latch_one_4/Vdd!" "latch_7/out4" 107.428
cap "staticizer_3/staticizer_one_4/out" "staticizer_3/staticizer_one_4/Vdd!" 6.001
cap "ry_addrH4" "latch_7/latch_one_4/Vdd!" 117.4
cap "latch_7/in4" "latch_7/latch_one_4/GND!" 6.956
cap "latch_7/in4" "staticizer_3/staticizer_one_4/Vdd!" 11.463
cap "latch_7/latch_one_4/a_n5_n54#" "latch_7/latch_one_4/Vdd!" -1.13687e-13
cap "latch_7/latch_one_4/Vdd!" "latch_7/latch_one_4/GND!" -0.738
cap "latch_7/out4" "staticizer_4/staticizer_one_4/a_60_n45#" 150.065
cap "latch_7/in4" "staticizer_3/staticizer_one_4/out" 23.087
cap "latch_7/latch_one_4/GND!" "latch_7/out4" 10.156
cap "latch_7/latch_one_4/Vdd!" "latch_7/latch_one_4/c" 1070.42
cap "ry_addrH4" "latch_7/latch_one_4/GND!" 77.41
cap "staticizer_3/staticizer_one_4/a_77_n45#" "staticizer_3/staticizer_one_4/Vdd!" 2.84217e-14
cap "latch_7/latch_one_4/a_12_n54#" "latch_7/latch_one_4/Vdd!" 1.13687e-13
cap "latch_7/latch_one_4/GND!" "staticizer_4/staticizer_one_4/a_60_n45#" 5.68434e-14
cap "staticizer_3/staticizer_one_4/w_54_n57#" "staticizer_3/staticizer_one_4/out" 8.272
cap "latch_7/in4" "latch_7/latch_one_4/Vdd!" 286.786
subcap "ry_addrH4" -836.866
subcap "addr_out12" -305.874
cap "staticizer_4/staticizer_one_4/a_60_n45#" "staticizer_4/staticizer_one_4/w_54_n57#" 2.84217e-14
cap "latch_8/latch_one_4/c" "staticizer_5/in4" -0.42
cap "staticizer_4/staticizer_one_4/out" "staticizer_4/staticizer_one_4/Vdd!" -5.68434e-14
cap "latch_8/latch_one_4/a_n5_n54#" "latch_8/latch_one_4/Vdd!" -1.13687e-13
cap "staticizer_4/staticizer_one_4/w_54_n57#" "latch_8/in4" 21.105
cap "staticizer_4/staticizer_one_4/out" "latch_8/in4" 57.7175
cap "latch_8/latch_one_4/a_n5_n54#" "latch_8/in4" 57.7175
cap "latch_8/latch_one_4/a_12_n54#" "latch_8/latch_one_4/Vdd!" 1.13687e-13
cap "latch_8/latch_one_4/Vdd!" "staticizer_5/in4" -1.162
cap "latch_8/in4" "staticizer_4/staticizer_one_4/Vdd!" 11.463
cap "latch_8/in4" "staticizer_5/staticizer_one_4/w_54_n57#" 6.956
cap "latch_8/in4" "latch_8/latch_one_4/Vdd!" 367.261
cap "staticizer_4/staticizer_one_4/Vdd!" "staticizer_4/staticizer_one_4/a_77_n45#" 1.13687e-13
cap "staticizer_4/staticizer_one_4/c" "latch_8/in4" 58.7
subcap "addr_out12" -36.486
cap "staticizer_5/staticizer_one_4/a_60_n45#" "staticizer_5/in4" 150.065
cap "latch_8/latch_one_4/Vdd!" "staticizer_5/in4" 107.428
cap "latch_8/latch_one_4/Vdd!" "latch_8/latch_one_4/c" 1070.42
cap "latch_8/latch_one_4/c" "staticizer_5/in4" 9.252
cap "staticizer_5/staticizer_one_4/w_54_n57#" "staticizer_5/in4" 10.156
cap "staticizer_5/staticizer_one_4/w_54_n57#" "latch_8/latch_one_4/c" 13.8522
cap "latch_4/c" "staticizer_1/Vdd!" 1073
cap "staticizer_0/Vdd!" "latch_0/c" 1073
cap "fblock_0/fblock_one_4/2mux_nr_0/out" "fblock_0/b4" 11.825
cap "fblock_0/b4" "fblock_0/fblock_one_4/inv_2/out" 7.975
cap "fblock_0/GND!" "fblock_0/b4" 58.7
cap "fblock_0/fblock_one_4/2mux_nr_1/Vdd!" "fblock_0/b4" 11.239
cap "fblock_0/fblock_one_4/g2" "fblock_0/b4" 58.7
cap "fblock_0/b4" "fblock_0/fblock_one_4/inv_1/out" 4.95
cap "fblock_0/b4" "fblock_0/fblock_one_4/2mux_nr_1/GND!" 9.884
cap "fblock_0/fblock_one_4/2mux_nr_0/a_n17_n11#" "fblock_0/b4" 33.597
cap "fblock_0/fblock_one_4/g3" "fblock_0/b4" 140.424
cap "latch_1/GND!" "ry4" 58.7
cap "fblock_0/fblock_one_4/2mux_nr_1/out" "ry4" 11.825
cap "ry4" "fblock_0/fblock_one_4/g1" 58.7
cap "ry4" "fblock_0/fblock_one_4/g0" 58.7
cap "fblock_0/fblock_one_4/inv_3/Vdd!" "latch_1/Vdd!" 1341.25
cap "ry4" "fblock_0/fblock_one_4/2mux_nr_1/s" 16.386
cap "ry4" "fblock_0/fblock_one_4/inv_3/out" 4.95
cap "fblock_0/fblock_one_4/inv_3/Vdd!" "ry4" 83.852
cap "ry4" "fblock_0/fblock_one_4/2mux_nr_1/a_n17_n11#" 31.949
cap "ry4" "latch_1/Vdd!" 58.7
cap "ry4" "fblock_0/fblock_one_4/inv_4/out" 2.75
cap "ry4" "fblock_0/fblock_one_4/inv_3/GND!" 24.128
cap "addsub_0/xor_4/b" "ry4" 14.799
cap "addsub_0/xor_4/a_61_n31#" "ry4" 7.218
cap "ry4" "addsub_0/xor_4/a_100_n42#" 0.707
cap "latch_1/c" "ry4" 58.7
cap "ry4" "addsub_0/xor_4/out" 30.433
cap "ry4" "addsub_0/xor_4/a_89_n31#" 3.068
cap "addsub_0/xor_4/GND!" "ry4" 32.209
cap "addsub_0/addsub_one_4/cin" "as_cout" 12.612
cap "addsub_0/addsub_one_4/Vdd!" "addsub_0/a4" 76.9567
cap "addsub_0/a4" "addsub_0/xor_4/a_61_n1#" 72.103
cap "addsub_0/a4" "as_cout" 12.612
cap "as_cout" "addsub_0/addsub_one_4/a_72_n41#" 2.1
cap "as_cout" "addsub_0/addsub_one_4/a_29_n41#" 2.1
cap "addsub_0/a4" "addsub_0/addsub_one_4/b" 36.877
cap "as_cout" "addsub_0/addsub_one_4/a_78_n41#" 10.86
cap "addsub_0/addsub_one_4/GND!" "as_cout" 58.163
cap "addsub_0/a4" "addsub_0/xor_4/a_61_n31#" 2.424
cap "as_cout" "addsub_0/addsub_one_4/a_89_n41#" 11.7
cap "addsub_0/addsub_one_4/GND!" "addsub_0/addsub_one_4/a_35_n41#" 2.27374e-13
cap "as_cout" "addsub_0/addsub_one_4/a_11_n41#" 21.93
cap "as_cout" "addsub_0/addsub_one_4/a_66_n41#" 2.1
cap "as_cout" "addsub_0/addsub_one_4/a_35_n41#" 14.854
cap "addsub_0/xor_4/a_89_n31#" "addsub_0/a4" 2.424
cap "addsub_0/addsub_one_4/b" "as_cout" 12.612
cap "addsub_0/a4" "addsub_0/xor_4/Vdd!" 22.66
cap "reg_0/in4" "latch_2/c" 107.3
cap "reg_0/r0" "reg_0/in4" 153.495
cap "wz4" "reg_0/reg_one_3/a_16_27#" 2.764
cap "reg_0/reg_one_3/Vdd!" "reg_0/reg_one_3/w" -7.10543e-15
cap "reg_0/reg_one_3/w" "wz4" 61.66
cap "reg_0/reg_one_3/Vdd!" "wz4" 18.225
cap "reg_0/Vdd!" "wz4" 58.7
cap "reg_0/in4" "wz4" 14.786
cap "reg_0/reg_one_3/w_n11_n27#" "wz4" 8.24
cap "reg_0/reg_one_3/w_n11_n27#" "reg_0/reg_one_3/Vdd!" 1.77636e-15
cap "reg_0/GND!" "wz4" 58.7
cap "wz4" "reg_0/reg_one_3/tmp" 8.713
cap "reg_0/r1" "wz4" 58.7
cap "reg_0/reg_one_3/a_33_32#" "wz4" 65.474
cap "reg_0/reg_one_3/Vdd!" "wz4" 88.158
cap "wz4" "reg_0/reg_one_3/w" 1.422
cap "reg_0/r0" "wz4" -7.416
cap "wz4" "reg_0/reg_one_3/a_16_27#" 5.5
cap "reg_0/in4" "reg_0/r0" -5.072
cap "wz4" "reg_1/r0" 63.6875
cap "reg_1/reg_one_3/Vdd!" "reg_1/reg_one_3/w" -7.10543e-15
cap "reg_1/reg_one_3/a_16_27#" "reg_1/in4" 5.5
cap "reg_1/in4" "reg_1/reg_one_3/w" 61.66
cap "reg_1/in4" "reg_1/r1" 58.7
cap "reg_1/in4" "reg_1/reg_one_3/tmp" 8.713
cap "reg_1/in4" "reg_1/reg_one_3/a_33_32#" 65.474
cap "reg_1/reg_one_3/Vdd!" "reg_1/in4" 18.225
cap "reg_1/r0" "reg_1/in4" 89.8075
cap "reg_1/reg_one_3/a_16_27#" "reg_1/in4" 2.764
cap "reg_1/Vdd!" "reg_1/in4" 58.7
cap "reg_1/reg_one_3/Vdd!" "reg_1/in4" 88.158
cap "reg_1/in4" "reg_1/GND!" 58.7
cap "reg_1/in4" "reg_1/reg_one_3/w" 1.422
cap "reg_1/reg_one_3/Vdd!" "reg_1/reg_one_3/w_n11_n27#" 1.77636e-15
cap "reg_1/in4" "reg_1/reg_one_3/w_n11_n27#" 8.24
cap "reg_2/reg_one_3/a_33_32#" "reg_2/in4" 65.474
cap "reg_2/reg_one_3/w" "reg_2/in4" 1.422
cap "reg_2/r0" "reg_2/in4" 153.495
cap "reg_2/reg_one_3/a_16_27#" "reg_2/in4" 2.764
cap "reg_2/reg_one_3/Vdd!" "reg_2/in4" 18.225
cap "reg_2/reg_one_3/Vdd!" "reg_2/in4" 88.158
cap "reg_2/reg_one_3/w" "reg_2/in4" 61.66
cap "reg_2/r1" "reg_2/in4" 58.7
cap "reg_2/reg_one_3/w_n11_n27#" "reg_2/in4" 8.24
cap "reg_2/reg_one_3/w" "reg_2/reg_one_3/Vdd!" -7.10543e-15
cap "reg_2/reg_one_3/Vdd!" "reg_2/reg_one_3/w_n11_n27#" 1.77636e-15
cap "reg_2/GND!" "reg_2/in4" 58.7
cap "reg_2/Vdd!" "reg_2/in4" 58.7
cap "reg_2/reg_one_3/a_16_27#" "reg_2/in4" 5.5
cap "reg_2/reg_one_3/tmp" "reg_2/in4" 8.713
cap "reg_3/in4" "reg_3/reg_one_3/a_33_32#" 39.098
cap "reg_3/in4" "reg_3/reg_one_3/Vdd!" 16.54
cap "reg_3/in4" "reg_3/r1" 58.7
cap "reg_3/in4" "reg_3/r0" 153.495
cap "reg_3/in4" "reg_3/reg_one_3/w" 1.248
cap "reg_3/in4" "reg_3/Vdd!" 58.7
cap "reg_3/in4" "reg_3/reg_one_3/a_16_27#" 2.496
cap "reg_3/GND!" "reg_3/in4" 58.7
cap "reg_3/in4" "reg_3/reg_one_3/a_16_27#" 4.95
cap "reg_3/in4" "reg_3/reg_one_3/w_n11_n27#" 17.302
cap "reg_3/in4" "reg_3/reg_one_3/tmp" 7.848
cap "mux_8bit_0/in1_4" "mux_8bit_0/mux_one_4/Vdd!" 98.617
cap "mux_8bit_0/in1_4" "mux_8bit_0/mux_one_4/GND!" 15.908
cap "mux_8bit_0/in1_4" "mux_8bit_0/mux_one_4/sel" 63.256
cap "reg_3/reg_one_3/w" "mux_8bit_0/in1_4" 58.7
cap "reg_3/reg_one_3/w_n11_n27#" "mux_8bit_0/in1_4" -2.948
cap "mux_8bit_0/in1_4" "mux_8bit_0/mux_one_4/2mux_nr_0/in1" 18.535
cap "reg_3/reg_one_3/Vdd!" "mux_8bit_0/in1_4" -2.948
cap "mux_8bit_0/in1_4" "mux_8bit_0/mux_one_4/2mux_nr_0/a_n17_n11#" 36.092
cap "reg_3/reg_one_3/w_n11_n27#" "reg_3/reg_one_3/w" 1.42109e-14
cap "reg_3/reg_one_3/a_33_32#" "mux_8bit_0/in1_4" -4.455
cap "mux_8bit_0/mux_one_4/GND!" "mux_8bit_0/mux_one_4/2mux_nr_0/in1" 1.42109e-14
cap "reg_3/reg_one_3/w_n11_n27#" "mux_8bit_0/in1_4" 8.24
subcap "PCL4" -6.692
cap "wz4" "reg_4/GND!" 58.7
cap "wz4" "mux_8bit_0/mux_one_4/2mux_nr_0/s" 4.948
cap "mux_8bit_0/mux_one_4/GND!" "wz4" 67.786
cap "wz4" "reg_4/reg_one_3/tmp" 6.507
cap "mux_8bit_0/mux_one_4/GND!" "reg_4/in4" 61.8402
cap "mux_8bit_0/mux_one_4/GND!" "reg_4/r0" 165.587
cap "wz4" "reg_4/in4" 2.844
cap "wz4" "reg_4/r0" 19.78
cap "reg_4/r0" "reg_4/in4" 24.808
cap "reg_4/reg_one_3/a_16_27#" "wz4" 6.6
cap "reg_4/r1" "wz4" 58.7
cap "reg_4/reg_one_3/a_33_32#" "wz4" 7.959
cap "reg_4/reg_one_3/Vdd!" "reg_4/in4" 15.362
cap "wz4" "reg_4/reg_one_3/w_n11_n27#" 133.528
cap "reg_4/reg_one_3/Vdd!" "reg_4/r0" -3.256
cap "wz4" "reg_4/reg_one_3/a_16_27#" 1.422
cap "reg_4/reg_one_3/w" "wz4" 5.064
cap "wz4" "reg_4/Vdd!" 58.7
cap "mux_8bit_0/mux_one_4/2mux_nr_0/a_n17_n11#" "wz4" -5.178
subcap "rx_PCL4" -261.685
cap "addsub_1/xor_4/out" "wz4" 97.913
cap "addsub_1/Vdd!" "wz4" 6.6
cap "addsub_1/xor_4/a_89_n31#" "wz4" 17.316
cap "addsub_1/a4" "addsub_1/xor_4/Vdd!" 27.249
cap "reg_4/reg_one_3/w" "wz4" 58.7
cap "wz4" "reg_4/reg_one_3/w_n11_n27#" -2.417
cap "addsub_1/xor_4/Vdd!" "wz4" 9.12
cap "wz4" "reg_4/reg_one_3/a_33_32#" -12.339
cap "wz4" "addsub_1/xor_4/GND!" 26.517
cap "addsub_1/xor_4/a_61_n1#" "addsub_1/a4" 110.581
cap "addsub_1/xor_4/a_61_n31#" "addsub_1/a4" 2.424
cap "addsub_1/xor_4/a_61_n1#" "wz4" 5.568
cap "wz4" "reg_4/reg_one_3/w_n11_n27#" -8.24
cap "addsub_1/a4" "addsub_1/xor_4/out" 36.877
cap "addsub_1/xor_4/a_61_n31#" "wz4" 19.78
cap "addsub_1/a4" "addsub_1/Vdd!" 76.9567
cap "addsub_1/xor_4/b" "wz4" 11.825
cap "addsub_1/xor_4/a_89_n31#" "addsub_1/a4" 2.424
cap "addsub_1/addsub_one_4/b" "a_2510_1893#" 12.612
cap "addsub_1/a4" "a_2510_1893#" 12.612
cap "wz4" "addsub_1/addsub_one_4/Vdd!" 2.145
cap "a_2510_1893#" "addsub_1/addsub_one_4/a_11_n41#" 21.93
cap "wz4" "addsub_1/addsub_one_4/GND!" 38.289
cap "wz4" "addsub_1/addsub_one_4/cin" 1.56
cap "wz4" "addsub_1/addsub_one_4/a_35_n41#" 51.712
cap "addsub_1/addsub_one_4/a_78_n41#" "wz4" 35.835
cap "a_2510_1893#" "addsub_1/addsub_one_4/GND!" 58.163
cap "addsub_1/addsub_one_4/cin" "a_2510_1893#" 12.612
cap "a_2510_1893#" "addsub_1/addsub_one_4/a_35_n41#" 14.854
cap "addsub_1/addsub_one_4/a_78_n41#" "a_2510_1893#" 10.86
cap "wz4" "addsub_1/xor_4/Vdd!" 1.026
cap "a_2510_1893#" "addsub_1/addsub_one_4/a_89_n41#" 11.7
cap "a_2510_1893#" "addsub_1/addsub_one_4/a_72_n41#" 2.1
cap "a_2510_1893#" "addsub_1/addsub_one_4/a_29_n41#" 2.1
cap "a_2510_1893#" "addsub_1/addsub_one_4/a_66_n41#" 2.1
cap "wz4" "addsub_1/addsub_one_4/b" 95.736
cap "staticizer_2/Vdd!" "wz4" 58.7
cap "wz4" "latch_5/c" 58.7
cap "staticizer_2/c" "wz4" 58.7
cap "wz4" "latch_5/GND!" 58.7
cap "staticizer_2/GND!" "wz4" 58.7
cap "staticizer_2/Vdd!" "latch_5/c" 1073
cap "latch_5/Vdd!" "wz4" 58.7
cap "mux_8bit_1/mux_one_4/sel" "mux_8bit_1/in1_4" 63.256
cap "mux_8bit_1/mux_one_4/Vdd!" "mux_8bit_1/in1_4" 96.331
cap "mux_8bit_1/mux_one_4/GND!" "mux_8bit_1/in1_4" 15.908
cap "mux_8bit_1/mux_one_4/2mux_nr_0/a_n17_n11#" "mux_8bit_1/in1_4" 36.092
cap "mux_8bit_1/mux_one_4/2mux_nr_0/in1" "mux_8bit_1/in1_4" 18.535
cap "wz4" "reg_5/r0" 19.78
cap "wz4" "reg_5/reg_one_3/a_33_32#" 7.959
cap "wz4" "reg_5/Vdd!" 58.7
cap "wz4" "mux_8bit_1/mux_one_4/2mux_nr_0/s" 4.948
cap "reg_5/in4" "mux_8bit_1/mux_one_4/GND!" 61.8402
cap "reg_5/r1" "wz4" 58.7
cap "mux_8bit_1/mux_one_4/GND!" "reg_5/r0" 165.587
cap "wz4" "reg_5/reg_one_3/a_16_27#" 1.422
cap "wz4" "reg_5/reg_one_3/w" 5.064
cap "wz4" "reg_5/reg_one_3/w_n11_n27#" 133.528
cap "reg_5/in4" "reg_5/reg_one_3/Vdd!" 15.362
cap "reg_5/in4" "reg_5/r0" 24.808
cap "wz4" "mux_8bit_1/mux_one_4/2mux_nr_0/a_n17_n11#" -5.178
cap "wz4" "reg_5/reg_one_3/tmp" 6.507
cap "wz4" "mux_8bit_1/mux_one_4/GND!" 67.786
cap "reg_5/reg_one_3/Vdd!" "reg_5/r0" -3.256
cap "wz4" "reg_5/reg_one_3/a_16_27#" 6.6
cap "reg_5/GND!" "wz4" 58.7
cap "reg_5/in4" "wz4" 2.844
cap "reg_6/reg_one_3/w" "reg_6/in4" 5.064
cap "reg_6/in4" "reg_6/reg_one_3/w_n11_n27#" 123.733
cap "reg_6/in4" "reg_6/reg_one_3/a_33_32#" 2.844
cap "reg_5/reg_one_3/w" "reg_5/reg_one_3/w_n11_n27#" 2.84217e-14
cap "reg_6/in4" "reg_5/reg_one_3/w_n11_n27#" -2.417
cap "reg_6/in4" "reg_5/reg_one_3/w_n11_n27#" -8.24
cap "reg_5/reg_one_3/Vdd!" "reg_5/reg_one_3/w_n11_n27#" 1.77636e-15
cap "reg_6/in4" "reg_6/r1" 58.7
cap "reg_6/reg_one_3/a_16_27#" "reg_6/in4" 6.6
cap "reg_6/in4" "reg_5/reg_one_3/a_33_32#" -12.339
cap "reg_6/in4" "reg_6/reg_one_3/tmp" 4.461
cap "reg_5/reg_one_3/w" "reg_6/in4" 58.7
cap "reg_6/in4" "reg_6/GND!" 58.7
cap "reg_6/in4" "reg_6/r0" 128.02
cap "reg_6/in4" "reg_6/reg_one_3/a_16_27#" 1.422
cap "reg_6/in4" "reg_6/Vdd!" 58.7
cap "mux_8bit_2/in1_4" "reg_6/reg_one_3/a_33_32#" 5.115
cap "mux_8bit_2/in1_4" "mux_8bit_2/mux_one_4/Vdd!" 2.035
cap "mux_8bit_2/in1_4" "reg_6/reg_one_3/w" 97.0214
cap "mux_8bit_2/in1_4" "reg_6/reg_one_3/w_n11_n27#" -1.886
cap "mux_8bit_2/in1_4" "mux_8bit_2/mux_one_4/GND!" 2.035
cap "mux_8bit_2/in1_4" "reg_6/reg_one_3/tmp" -4.818
cap "reg_6/reg_one_3/tmp" "reg_6/reg_one_3/w_n11_n27#" -7.10543e-15
cap "mux_8bit_2/in1_4" "reg_6/reg_one_3/w_n11_n27#" 48.9529
cap "mux_8bit_2/mux_one_4/2mux_nr_0/in1" "mux_8bit_2/mux_one_4/GND!" 1.42109e-14
cap "reg_7/reg_one_3/Vdd!" "reg_7/in4" 15.362
cap "reg_7/r0" "reg_7/in4" 24.808
cap "reg_7/in4" "mux_8bit_2/mux_one_4/GND!" 61.8402
cap "reg_7/r0" "reg_7/reg_one_3/Vdd!" -3.256
cap "reg_7/r0" "mux_8bit_2/mux_one_4/GND!" 165.587
subcap "rx_addrH4" -640.857
cap "addsub_2/xor_4/a_61_n1#" "addsub_2/a4" 110.581
cap "addsub_2/xor_4/a_61_n31#" "addsub_2/a4" 2.424
cap "addsub_2/xor_4/Vdd!" "addsub_2/a4" 27.249
cap "addsub_2/Vdd!" "addsub_2/a4" 76.9567
cap "addsub_2/xor_4/out" "addsub_2/a4" 36.877
cap "addsub_2/xor_4/a_89_n31#" "addsub_2/a4" 2.424
cap "staticizer_3/Vdd!" "latch_6/c" 1073
cap "staticizer_4/Vdd!" "latch_7/c" 1073
cap "latch_8/c" "staticizer_5/Vdd!" 1073
cap "latch_4/latch_one_3/c" "staticizer_1/staticizer_one_3/w_54_n57#" 18.4696
cap "staticizer_1/in3" "staticizer_1/staticizer_one_3/w_54_n57#" 18.828
cap "staticizer_1/staticizer_one_3/Vdd!" "staticizer_1/staticizer_one_3/w_54_n57#" 1.13687e-13
cap "latch_4/latch_one_3/c" "staticizer_1/in3" 0.492
cap "staticizer_1/staticizer_one_3/Vdd!" "latch_4/latch_one_3/a_12_n54#" -7.10543e-15
cap "latch_4/latch_one_3/c" "staticizer_1/staticizer_one_3/Vdd!" 1073
cap "staticizer_1/in3" "staticizer_1/staticizer_one_3/a_60_n45#" 57.7175
cap "staticizer_1/in3" "staticizer_1/staticizer_one_3/Vdd!" 73.946
cap "staticizer_1/staticizer_one_3/Vdd!" "staticizer_1/staticizer_one_3/a_60_n45#" -2.27374e-13
cap "staticizer_1/staticizer_one_3/c" "staticizer_1/in3" 1.42109e-14
subcap "a_109_1272#" -134.574
subcap "data_in3" -6.948
subcap "rx3" -1770.33
cap "latch_4/in3" "latch_4/latch_one_3/a_n5_n54#" 69.3743
cap "latch_0/latch_one_3/a_12_n54#" "latch_0/latch_one_3/Vdd!" -1.13687e-13
cap "latch_0/out3" "staticizer_0/staticizer_one_3/a_60_n45#" 57.7175
cap "latch_4/in3" "latch_0/latch_one_3/GND!" 59.993
cap "latch_0/latch_one_3/GND!" "latch_0/latch_one_3/a_n5_n54#" 5.68434e-14
cap "latch_0/in3" "latch_0/latch_one_3/a_n5_n54#" 32.9814
cap "staticizer_0/staticizer_one_3/a_60_n45#" "latch_0/latch_one_3/Vdd!" -4.648
cap "latch_4/in3" "latch_4/latch_one_3/Vdd!" 469.437
cap "latch_0/out3" "latch_0/latch_one_3/GND!" 18.828
cap "latch_0/latch_one_3/c" "latch_4/in3" 58.7
cap "latch_4/in3" "latch_0/latch_one_3/Vdd!" 96.12
cap "latch_0/latch_one_3/Vdd!" "latch_0/latch_one_3/a_n5_n54#" 1.13687e-13
cap "latch_0/latch_one_3/GND!" "latch_0/latch_one_3/Vdd!" -0.246
cap "latch_0/latch_one_3/c" "latch_0/latch_one_3/GND!" 18.4696
cap "latch_0/in3" "latch_0/latch_one_3/Vdd!" 67.0625
cap "latch_0/out3" "latch_0/latch_one_3/c" 0.492
cap "latch_0/out3" "latch_0/latch_one_3/Vdd!" 73.946
cap "latch_0/latch_one_3/c" "latch_0/latch_one_3/Vdd!" 1073
subcap "wz3" -2636.74
cap "staticizer_0/staticizer_one_3/w_54_n57#" "shift_0/a3" 73.425
cap "staticizer_0/staticizer_one_3/Vdd!" "staticizer_0/staticizer_one_3/w_54_n57#" -0.984
cap "shift_0/shift_one_3/ad" "shift_0/a3" 125.763
cap "latch_0/out3" "staticizer_0/staticizer_one_3/a_60_n45#" 31.249
cap "latch_0/out3" "shift_0/shift_one_3/Vdd!" 8.24
cap "latch_0/out3" "shift_0/a3" 58.7
cap "staticizer_0/staticizer_one_3/c" "shift_0/a3" 76.935
cap "staticizer_0/staticizer_one_3/Vdd!" "staticizer_0/staticizer_one_3/a_60_n45#" -2.744
cap "staticizer_0/staticizer_one_3/Vdd!" "latch_0/out3" 35.6
cap "latch_0/out3" "staticizer_0/staticizer_one_3/w_54_n57#" 6.22
cap "shift_0/shift_one_3/ad" "latch_0/out3" 58.7
cap "staticizer_0/staticizer_one_3/a_77_n45#" "staticizer_0/staticizer_one_3/Vdd!" 1.13687e-13
cap "staticizer_0/staticizer_one_3/Vdd!" "shift_0/a3" -12.11
cap "rx3" "shift_0/GND!" 58.7
cap "rx3" "shift_0/u" 58.7
cap "shift_0/shift_one_3/Vdd!" "rx3" 7.239
cap "shift_0/GND!" "wz3" 58.7
cap "wz3" "shift_0/shift_one_3/m1_n60_n65#" 11.825
cap "shift_0/u" "wz3" 58.7
cap "rx3" "shift_0/shift_one_3/inv_2/in" 14.74
cap "shift_0/shift_one_3/Vdd!" "wz3" 91.858
cap "rx3" "shift_0/shift_one_3/inv_2/GND!" 11.43
cap "shift_0/shift_one_3/inv_2/out" "wz3" 25.522
cap "shift_0/shift_one_3/inv_2/GND!" "wz3" 21.418
cap "shift_0/Vdd!" "rx3" 58.7
cap "shift_0/Vdd!" "wz3" 58.7
cap "shift_0/shift_one_3/inv_3/GND!" "rx3" 6.096
cap "wz3" "latch_3/latch_one_3/Vdd!" 64.715
cap "wz3" "shift_0/shift_one_3/inv_3/Vdd!" 72.651
cap "latch_3/latch_one_3/GND!" "wz3" 66.689
cap "rx3" "latch_3/latch_one_3/Vdd!" 58.7
cap "shift_0/shift_one_3/2mux_nr_1/out" "shift_0/o3" 57.7175
cap "rx3" "shift_0/shift_one_3/inv_3/Vdd!" 7.239
cap "latch_3/latch_one_3/a_n5_n54#" "wz3" 30.853
cap "latch_3/latch_one_3/GND!" "rx3" 107.383
cap "latch_3/latch_one_3/a_12_n54#" "wz3" 4.95
cap "shift_0/o3" "latch_3/latch_one_3/Vdd!" 9.594
cap "wz3" "latch_3/latch_one_3/c" 1.248
cap "shift_0/o3" "shift_0/shift_one_3/inv_3/Vdd!" 1.162
cap "shift_0/shift_one_3/2mux_nr_1/out" "latch_3/latch_one_3/Vdd!" 46.174
cap "latch_3/latch_one_3/GND!" "shift_0/o3" 30.043
cap "rx3" "latch_3/latch_one_3/c" 3.12
cap "shift_0/o3" "latch_3/latch_one_3/a_n5_n54#" 57.7175
cap "shift_0/s" "wz3" 58.7
cap "shift_0/o3" "wz3" 2.184
cap "shift_0/shift_one_3/inv_3/GND!" "wz3" 3.152
cap "shift_0/shift_one_3/2mux_nr_1/out" "wz3" 8.599
cap "latch_3/latch_one_3/a_n5_n54#" "latch_3/latch_one_3/Vdd!" -1.13687e-13
cap "shift_0/s" "rx3" 58.7
cap "shift_0/o3" "rx3" 20.945
cap "fblock_0/g3" "latch_3/out3" 58.7
cap "fblock_0/g3" "fblock_0/b3" 104.003
cap "latch_3/out3" "latch_3/latch_one_3/GND!" 1.209
cap "fblock_0/fblock_one_3/2mux_nr_2/a_n17_n11#" "latch_3/out3" 14.683
cap "fblock_0/b3" "fblock_0/fblock_one_3/2mux_nr_1/Vdd!" 25.648
cap "fblock_0/fblock_one_3/2mux_nr_2/a_n17_n11#" "fblock_0/fblock_one_3/inv_0/GND!" 5.68434e-14
cap "latch_3/latch_one_3/GND!" "latch_3/latch_one_3/c" 2.84217e-14
cap "fblock_0/g2" "latch_3/out3" 58.7
cap "fblock_0/fblock_one_3/2mux_nr_0/out" "fblock_0/a3" 5.115
cap "fblock_0/g2" "fblock_0/b3" 39.805
cap "fblock_0/g3" "fblock_0/a3" 542.798
cap "latch_3/latch_one_3/GND!" "fblock_0/a3" 0.083
cap "fblock_0/fblock_one_3/2mux_nr_2/a_n17_n11#" "fblock_0/a3" 11.004
cap "latch_3/latch_one_3/a_12_n54#" "latch_3/latch_one_3/Vdd!" 2.84217e-14
cap "latch_3/out3" "fblock_0/fblock_one_3/2mux_nr_2/in0" 7.975
cap "fblock_0/g2" "fblock_0/a3" 58.7
cap "fblock_0/b3" "fblock_0/fblock_one_3/2mux_nr_0/in0" 5.192
cap "fblock_0/fblock_one_3/2mux_nr_2/in0" "fblock_0/a3" 4.389
cap "latch_3/out3" "fblock_0/fblock_one_3/inv_0/in" 19.302
cap "fblock_0/fblock_one_3/2mux_nr_2/Vdd!" "fblock_0/a3" 82.685
cap "latch_3/out3" "fblock_0/fblock_one_3/inv_0/GND!" 97.023
cap "latch_3/out3" "latch_3/latch_one_3/c" 140.424
cap "fblock_0/fblock_one_3/inv_0/GND!" "fblock_0/fblock_one_3/inv_0/in" 5.68434e-14
cap "fblock_0/b3" "fblock_0/fblock_one_3/inv_0/GND!" 49.689
cap "fblock_0/b3" "fblock_0/fblock_one_3/2mux_nr_0/in1" 2.475
cap "fblock_0/fblock_one_3/2mux_nr_0/out" "latch_3/out3" 9.35
cap "latch_3/latch_one_3/Vdd!" "latch_3/out3" 0.959
cap "latch_3/out3" "fblock_0/a3" 4.948
cap "fblock_0/fblock_one_3/2mux_nr_0/out" "fblock_0/b3" 7.975
cap "fblock_0/a3" "fblock_0/fblock_one_3/inv_0/in" 9.081
cap "fblock_0/fblock_one_3/inv_0/GND!" "fblock_0/a3" 115.687
cap "latch_3/latch_one_3/c" "fblock_0/a3" 78.258
cap "fblock_0/b3" "fblock_0/fblock_one_3/2mux_nr_0/a_n17_n11#" 23.594
cap "fblock_0/fblock_one_3/2mux_nr_1/a_n17_n11#" "ry3" 23.594
cap "latch_1/latch_one_3/Vdd!" "wz3" 58.7
cap "ry3" "fblock_0/fblock_one_3/2mux_nr_1/Vdd!" 22.117
cap "fblock_0/f3" "latch_1/latch_one_3/Vdd!" 6.108
cap "fblock_0/fblock_one_3/inv_0/GND!" "fblock_0/fblock_one_3/inv_0/in" 5.68434e-14
cap "ry3" "fblock_0/fblock_one_3/2mux_nr_1/s" 13.064
cap "rx3" "latch_1/latch_one_3/Vdd!" 103.828
cap "latch_1/latch_one_3/a_n5_n54#" "wz3" 43.4
cap "fblock_0/fblock_one_4/inv_3/Vdd!" "ry3" 51.73
cap "fblock_0/fblock_one_3/f" "ry3" 13.352
cap "ry3" "latch_1/latch_one_3/GND!" 51.73
cap "fblock_0/fblock_one_3/inv_0/in" "wz3" 4.123
cap "latch_1/latch_one_3/a_n5_n54#" "fblock_0/f3" 57.7175
cap "ry3" "fblock_0/fblock_one_3/2mux_nr_1/GND!" 17.7
cap "rx3" "latch_1/latch_one_3/a_n5_n54#" 7.807
cap "fblock_0/g1" "ry3" 51.73
cap "fblock_0/fblock_one_3/inv_0/in" "rx3" 2.844
cap "fblock_0/fblock_one_4/inv_3/Vdd!" "wz3" 58.7
cap "wz3" "latch_1/latch_one_3/GND!" 69.742
cap "fblock_0/fblock_one_4/inv_3/Vdd!" "fblock_0/f3" 12.684
cap "fblock_0/fblock_one_3/inv_0/GND!" "wz3" 20.977
cap "fblock_0/f3" "latch_1/latch_one_3/GND!" 12.326
cap "fblock_0/fblock_one_4/inv_3/Vdd!" "rx3" 58.7
cap "ry3" "fblock_0/g0" 51.73
cap "fblock_0/g1" "wz3" 58.7
cap "fblock_0/fblock_one_3/f" "rx3" 85.724
cap "rx3" "latch_1/latch_one_3/GND!" 58.7
cap "fblock_0/g1" "rx3" 58.7
cap "fblock_0/g0" "wz3" 58.7
cap "fblock_0/fblock_one_4/inv_3/Vdd!" "latch_1/latch_one_3/Vdd!" 1341.25
cap "ry3" "fblock_0/fblock_one_3/2mux_nr_1/out" 7.975
cap "latch_1/latch_one_3/a_12_n54#" "wz3" 9.731
cap "fblock_0/f3" "wz3" 18.093
cap "ry3" "fblock_0/fblock_one_3/2mux_nr_1/in1" 2.475
cap "wz3" "latch_1/latch_one_3/c" 4.324
cap "ry3" "latch_1/latch_one_3/Vdd!" 51.73
cap "rx3" "fblock_0/g0" 58.7
cap "rx3" "fblock_0/f3" 13.492
cap "fblock_0/fblock_one_3/2mux_nr_1/in0" "ry3" 1.606
subcap "ry3" -2466.6
cap "rx3" "addsub_0/b3" 2.764
cap "addsub_0/xor_3/b" "addsub_0/b3" 14.618
cap "latch_1/out3" "latch_1/latch_one_3/GND!" 3.821
cap "rx3" "latch_1/latch_one_3/a_30_n35#" 4.828
cap "rx3" "latch_1/latch_one_3/a_12_n54#" 4.948
cap "addsub_0/b3" "addsub_0/xor_3/a_89_n31#" 3.068
cap "rx3" "latch_1/latch_one_3/c" 58.7
cap "addsub_0/xor_3/out" "addsub_0/b3" 31.486
cap "latch_1/out3" "latch_1/latch_one_3/a_n5_n54#" 15.975
cap "latch_1/out3" "addsub_0/xor_3/GND!" 11.825
cap "rx3" "addsub_0/xor_3/b" 11.825
cap "latch_1/out3" "latch_1/latch_one_3/Vdd!" 1.221
cap "addsub_0/xor_3/a_100_n42#" "addsub_0/b3" 0.707
cap "latch_1/out3" "latch_1/latch_one_3/GND!" 2.361
cap "latch_1/out3" "latch_1/latch_one_3/c" 144.632
cap "rx3" "latch_1/latch_one_3/Vdd!" -4.367
cap "addsub_0/xor_3/GND!" "addsub_0/b3" 173.754
cap "rx3" "addsub_0/xor_3/Vdd!" 8.496
cap "latch_1/out3" "addsub_0/xor_3/b" 11.825
cap "rx3" "latch_1/out3" 9.182
cap "addsub_0/xor_3/a_69_n42#" "addsub_0/b3" 2.457
cap "addsub_0/xor_3/a_61_n31#" "addsub_0/b3" 5.316
cap "latch_1/latch_one_3/c" "addsub_0/b3" 51.73
cap "latch_1/out3" "latch_1/latch_one_3/a_30_n54#" 1.524
cap "rx3" "latch_1/latch_one_3/a_n5_n54#" 4.948
cap "rx3" "latch_1/latch_one_3/Vdd!" -1.405
cap "rx3" "addsub_0/xor_3/GND!" 24.038
cap "addsub_0/addsub_one_3/GND!" "as_cout" 33
cap "addsub_0/addsub_one_3/GND!" "rx3" -0.341
cap "rx3" "addsub_0/addsub_one_3/a_35_n41#" 19.78
cap "as_cout" "addsub_0/addsub_one_3/a_35_n41#" 8.408
cap "addsub_0/addsub_one_4/GND!" "wz3" 18.211
cap "rx3" "addsub_0/xor_3/b" 2.424
cap "addsub_0/addsub_one_4/GND!" "as_cout" 40.362
cap "as_cout" "addsub_0/addsub_one_3/a_89_n41#" 22.875
cap "rx3" "addsub_0/addsub_one_4/GND!" 20.114
cap "addsub_0/addsub_one_3/a" "as_cout" 4.204
cap "as_cout" "addsub_0/addsub_one_3/a_78_n41#" 15.064
cap "rx3" "addsub_0/addsub_one_3/a_78_n41#" 11.825
cap "wz3" "addsub_0/addsub_one_3/Vdd!" 50.747
cap "addsub_0/addsub_one_4/GND!" "ry3" 24.188
cap "rx3" "addsub_0/xor_3/a_61_n31#" 1.95
cap "as_cout" "addsub_0/addsub_one_3/cout" 14.329
cap "rx3" "addsub_0/addsub_one_3/Vdd!" 93.561
cap "addsub_0/addsub_one_3/cin" "as_cout" 7.536
cap "rx3" "addsub_0/addsub_one_3/a_89_9#" 4.7
cap "rx3" "addsub_0/xor_3/a" 2.424
cap "addsub_0/addsub_one_3/cout" "ry3" 11.138
cap "addsub_0/xor_3/a_61_n1#" "rx3" 103.788
cap "addsub_0/addsub_one_3/Vdd!" "ry3" 28.817
cap "addsub_0/addsub_one_3/GND!" "wz3" 0.308
cap "rx3" "addsub_0/xor_3/a_89_n31#" 2.424
cap "as_cout" "addsub_0/addsub_one_3/s" 41.11
cap "wz3" "addsub_0/addsub_one_3/a_35_n41#" 65.763
cap "as_cout" "addsub_0/addsub_one_3/b" 4.204
cap "rx3" "addsub_0/addsub_one_3/b" 94.487
subcap "a_841_1273#" -38.45
cap "ry3" "latch_2/latch_one_3/Vdd!" 58.7
cap "rx3" "latch_2/latch_one_3/a_30_n35#" 1.524
cap "rx3" "latch_2/latch_one_3/Vdd!" 116.636
cap "addsub_0/addsub_one_3/GND!" "rx3" 7.942
cap "rx3" "latch_2/latch_one_3/c" 61.544
cap "addsub_0/addsub_one_3/b" "rx3" -2.068
cap "latch_2/out3" "addsub_0/addsub_one_4/GND!" 7.422
cap "ry3" "reg_0/reg_one_4/r0" 17.308
cap "latch_2/out3" "latch_2/latch_one_3/a_12_n54#" 12.473
cap "ry3" "addsub_0/a_126_536#" 1.486
cap "ry3" "addsub_0/GND!" 11.825
cap "latch_2/out3" "addsub_0/addsub_one_3/a_35_n41#" -1.814
cap "latch_2/latch_one_3/GND!" "latch_2/out3" 90.233
cap "latch_2/out3" "latch_2/latch_one_3/a_n5_n54#" 12.196
cap "addsub_0/s3" "latch_2/latch_one_3/a_n5_n54#" 57.7175
cap "rx3" "reg_0/reg_one_4/r0" 19.78
cap "rx3" "addsub_0/GND!" 11.825
cap "latch_2/out3" "latch_2/latch_one_3/a_30_n54#" 2.592
cap "addsub_0/s3" "rx3" 3.468
cap "latch_2/out3" "rx3" 4.341
cap "ry3" "addsub_0/addsub_one_4/GND!" 8.808
cap "latch_2/out3" "latch_2/latch_one_3/c" 727.057
cap "addsub_0/s3" "latch_2/latch_one_3/Vdd!" 19.399
cap "latch_2/latch_one_3/GND!" "ry3" 110.895
cap "addsub_0/addsub_one_3/GND!" "latch_2/out3" 3.399
cap "latch_2/out3" "latch_2/latch_one_3/Vdd!" 59.921
cap "rx3" "addsub_0/addsub_one_4/GND!" 5.148
cap "rx3" "latch_2/latch_one_3/a_12_n54#" 37.778
cap "latch_2/latch_one_3/GND!" "rx3" 58.7
cap "rx3" "latch_2/latch_one_3/a_n5_n54#" 6.195
cap "latch_2/out3" "reg_0/reg_one_4/r0" 217.183
cap "addsub_0/s3" "addsub_0/GND!" 76.9567
cap "latch_2/out3" "addsub_0/GND!" 11.825
cap "latch_2/out3" "addsub_0/s3" 4.948
cap "ry3" "latch_2/latch_one_3/c" 81.378
cap "reg_0/reg_one_4/r0" "reg_0/port31" 23.94
cap "reg_0/reg_one_4/a_16_27#" "wz3" 8.264
cap "reg_0/reg_one_4/tmp" "wz3" 4.324
cap "reg_0/reg_one_4/r0" "reg_0/in3" -5.072
cap "wz3" "reg_0/reg_one_4/w_n11_n27#" 66.94
cap "reg_0/port30" "reg_0/reg_one_4/a_4_n13#" 20.417
cap "reg_0/reg_one_4/Vdd!" "wz3" 165.083
cap "reg_0/reg_one_4/r1" "reg_0/port30" 70.642
cap "reg_0/w" "reg_0/port30" 434.25
cap "wz3" "reg_0/reg_one_4/w" 4.382
cap "wz3" "reg_0/reg_one_4/r0" -7.416
cap "reg_1/reg_one_4/r0" "wz3" 63.6875
cap "reg_0/reg_one_4/r1" "reg_0/port31" 64.004
cap "reg_0/w" "reg_0/port31" 127.744
cap "reg_0/port30" "reg_0/reg_one_4/a_21_n13#" 20.118
cap "reg_0/reg_one_4/tmp" "reg_0/port30" 4.948
cap "reg_0/reg_one_4/a_33_32#" "wz3" 65.474
cap "reg_0/port30" "reg_0/reg_one_4/w_n11_n27#" 194.315
cap "reg_0/reg_one_4/tmp" "wz3" 4.389
cap "reg_0/reg_one_4/Vdd!" "reg_0/port30" 134.044
cap "reg_0/reg_one_4/w_n11_n27#" "reg_0/port31" 121.694
cap "reg_0/reg_one_4/r1" "wz3" 58.7
cap "reg_0/w" "wz3" 58.7
cap "wz3" "reg_0/in3" 14.786
cap "reg_0/reg_one_4/Vdd!" "reg_0/port31" 58.7
cap "reg_0/port30" "reg_0/reg_one_4/r0" -7.416
cap "reg_1/port31" "reg_1/w" 127.744
cap "reg_1/reg_one_4/r0" "reg_1/in3" 89.8075
cap "reg_1/port30" "reg_1/reg_one_4/Vdd!" 75.185
cap "reg_1/port30" "reg_1/reg_one_4/r0" 21.144
cap "reg_1/in3" "reg_1/reg_one_4/Vdd!" 165.083
cap "reg_1/port30" "reg_1/port31" 3.85
cap "reg_1/port30" "reg_1/reg_one_4/a_21_n13#" 2.238
cap "reg_1/reg_one_4/r1" "reg_1/port31" 64.004
cap "reg_1/port31" "reg_1/reg_one_4/Vdd!" 58.7
cap "reg_1/port31" "reg_1/reg_one_4/r0" 48.664
cap "reg_1/in3" "reg_1/reg_one_4/tmp" 4.389
cap "reg_1/in3" "reg_1/reg_one_4/w" 4.382
cap "reg_1/port30" "reg_1/reg_one_4/a_4_n13#" 118.494
cap "reg_1/port30" "reg_1/reg_one_4/w_n11_n27#" 198.775
cap "reg_1/in3" "reg_1/reg_one_4/a_33_32#" 65.474
cap "reg_1/in3" "reg_1/reg_one_4/w_n11_n27#" 66.94
cap "reg_1/in3" "reg_1/w" 58.7
cap "reg_1/port30" "reg_1/w" 125.763
cap "reg_1/reg_one_4/r1" "reg_1/in3" 58.7
cap "reg_1/port30" "reg_1/reg_one_4/tmp" 4.694
cap "reg_1/reg_one_4/r1" "reg_1/port30" 60.064
cap "reg_1/reg_one_4/tmp" "reg_1/in3" 4.324
cap "reg_1/port31" "reg_1/reg_one_4/w_n11_n27#" 121.694
cap "reg_1/reg_one_4/a_16_27#" "reg_1/in3" 8.264
cap "reg_2/reg_one_4/r0" "reg_1/port30" 21.144
cap "reg_2/port31" "reg_2/w" 94.2122
cap "reg_2/reg_one_4/w_n11_n27#" "reg_2/in3" 66.94
cap "reg_2/reg_one_4/r0" "reg_2/port31" 48.664
cap "reg_2/reg_one_4/a_4_n13#" "reg_1/port30" 118.494
cap "reg_2/reg_one_4/a_16_27#" "reg_2/in3" 8.264
cap "reg_2/reg_one_4/Vdd!" "reg_2/in3" 165.083
cap "reg_1/port30" "reg_2/reg_one_4/a_21_n13#" 2.238
cap "reg_2/reg_one_4/tmp" "reg_2/in3" 4.324
cap "reg_2/reg_one_4/w_n11_n27#" "reg_1/port30" 135.088
cap "reg_2/in3" "reg_2/reg_one_4/r1" 58.7
cap "reg_2/reg_one_4/Vdd!" "reg_1/port30" 75.185
cap "reg_2/reg_one_4/w" "reg_2/in3" 4.382
cap "reg_2/port31" "reg_2/reg_one_4/w_n11_n27#" 121.694
cap "reg_2/reg_one_4/tmp" "reg_1/port30" 4.694
cap "reg_2/w" "reg_2/in3" 58.7
cap "reg_2/reg_one_4/Vdd!" "reg_2/port31" 58.7
cap "reg_2/port31" "reg_1/port30" 3.85
cap "reg_2/reg_one_4/r0" "reg_2/in3" 153.495
cap "reg_1/port30" "reg_2/reg_one_4/r1" 60.064
cap "reg_2/reg_one_4/tmp" "reg_2/in3" 4.389
cap "reg_2/port31" "reg_2/reg_one_4/r1" 64.004
cap "reg_2/w" "reg_1/port30" 92.2312
cap "reg_2/reg_one_4/a_33_32#" "reg_2/in3" 65.474
cap "reg_2/port31" "reg_3/reg_one_4/Vdd!" 58.7
cap "reg_3/port31" "reg_3/reg_one_4/w_n11_n27#" 1.628
cap "reg_3/reg_one_4/tmp" "reg_3/in3" 1.248
cap "reg_3/in3" "reg_3/reg_one_4/Vdd!" 75.24
cap "reg_3/port30" "reg_2/port30" 8.58
cap "reg_2/reg_one_4/w_n11_n27#" "reg_2/port30" 63.6875
cap "reg_2/port30" "reg_3/reg_one_4/r1" 60.064
cap "reg_3/reg_one_4/w_n11_n27#" "reg_2/port30" 63.11
cap "reg_3/in3" "reg_3/reg_one_4/a_16_27#" 7.446
cap "reg_2/w" "reg_2/port30" 33.5312
cap "reg_2/port31" "reg_3/reg_one_4/r1" 64.004
cap "reg_2/w" "reg_2/port31" 33.5312
cap "reg_2/port31" "reg_3/reg_one_4/w_n11_n27#" 106.567
cap "reg_3/reg_one_4/a_21_n13#" "reg_2/port30" 2.238
cap "reg_3/port31" "reg_2/port30" 3.85
cap "reg_3/in3" "reg_3/reg_one_4/r1" 58.7
cap "reg_2/port31" "reg_3/port31" 73.199
cap "reg_3/reg_one_4/r0" "reg_2/port30" 21.144
cap "reg_3/in3" "reg_3/reg_one_4/w_n11_n27#" 58.7
cap "reg_3/in3" "reg_3/reg_one_4/w_n11_n27#" 17.302
cap "reg_2/port31" "reg_3/reg_one_4/r0" 48.664
cap "reg_3/w" "reg_3/port31" 5.072
cap "reg_3/reg_one_4/tmp" "reg_2/port30" 4.694
cap "reg_3/reg_one_4/a_4_n13#" "reg_2/port30" 118.494
cap "reg_3/in3" "reg_3/reg_one_4/tmp" 6.6
cap "reg_3/reg_one_4/r0" "reg_3/in3" 153.495
cap "reg_3/reg_one_4/a_33_32#" "reg_3/in3" 39.098
cap "reg_3/reg_one_4/Vdd!" "reg_2/port30" 74.654
cap "reg_3/in3" "reg_3/reg_one_4/w" 1.248
subcap "wz_addrL3" -530.966
subcap "PCL_w_muxout3" -380.236
cap "mux_8bit_0/sel" "mux_8bit_0/out3" 0.84
cap "reg_3/port30" "reg_3/reg_one_4/w_n11_n27#" -3.379
cap "mux_8bit_0/in1_3" "mux_8bit_0/mux_one_3/inv2_2/GND!" 4.81
cap "mux_8bit_0/in0_3" "mux_8bit_0/out3" 30.603
cap "reg_3/port30" "reg_3/reg_one_4/w" 125.763
cap "mux_8bit_0/in0_3" "mux_8bit_0/mux_one_3/inv2_2/GND!" 12.279
cap "mux_8bit_0/in1_3" "mux_8bit_0/sel" 58.7
cap "reg_3/port31" "mux_8bit_0/out3" -10.01
cap "reg_3/port30" "reg_3/reg_one_4/w_n11_n27#" 135.615
cap "mux_8bit_0/in1_3" "reg_3/reg_one_4/w" 58.7
cap "mux_8bit_0/mux_one_3/inv2_2/GND!" "reg_3/port31" 63.013
cap "mux_8bit_0/in1_3" "mux_8bit_0/mux_one_3/Vdd!" 98.617
cap "mux_8bit_0/in1_3" "reg_3/reg_one_4/w_n11_n27#" -2.948
cap "mux_8bit_0/in0_3" "mux_8bit_0/sel" 58.7
cap "reg_3/reg_one_4/w_n11_n27#" "reg_3/port31" -1.039
cap "mux_8bit_0/in1_3" "reg_3/reg_one_4/w_n11_n27#" 8.24
cap "mux_8bit_0/mux_one_3/2mux_nr_0/in1" "mux_8bit_0/in1_3" 18.535
cap "mux_8bit_0/in0_3" "mux_8bit_0/mux_one_3/Vdd!" 78.896
cap "reg_3/port31" "mux_8bit_0/sel" 58.7
cap "mux_8bit_0/in0_3" "mux_8bit_0/mux_one_3/inv2_1/a_1_8#" 19.462
cap "reg_3/port30" "reg_3/reg_one_4/Vdd!" -2.898
cap "mux_8bit_0/in0_3" "mux_8bit_0/mux_one_3/2mux_nr_0/in0" 29.025
cap "reg_3/reg_one_4/w" "reg_3/port31" 127.744
cap "reg_3/port31" "mux_8bit_0/mux_one_3/Vdd!" 58.7
cap "mux_8bit_0/in1_3" "mux_8bit_0/mux_one_3/2mux_nr_0/a_n17_n11#" 36.092
cap "mux_8bit_0/in1_3" "reg_3/reg_one_4/Vdd!" -2.948
cap "mux_8bit_0/mux_one_3/inv2_2/GND!" "mux_8bit_0/out3" 37.928
cap "reg_3/port31" "reg_3/reg_one_4/w_n11_n27#" 12.7375
cap "mux_8bit_0/mux_one_3/2mux_nr_0/s" "mux_8bit_0/in1_3" 4.556
cap "reg_3/reg_one_4/a_33_32#" "mux_8bit_0/in1_3" -4.455
cap "mux_8bit_0/in1_3" "mux_8bit_0/mux_one_3/inv2_0/GND!" 11.098
cap "mux_8bit_0/mux_one_3/inv2_1/GND!" "wz_addrL3" 6.72
cap "wz3" "reg_4/reg_one_4/r1" 58.7
cap "reg_4/reg_one_4/r1" "ry3" 64.004
cap "reg_4/reg_one_4/a_16_27#" "wz3" 8.022
cap "reg_4/port31" "ry3" 73.199
cap "reg_4/reg_one_4/w_n11_n27#" "reg_4/port31" 1.628
cap "wz3" "reg_4/reg_one_4/w_n11_n27#" 192.228
cap "reg_4/reg_one_4/w_n11_n27#" "ry3" 106.567
cap "reg_4/reg_one_4/Vdd!" "wz3" 58.7
cap "reg_4/reg_one_4/Vdd!" "ry3" 58.7
cap "wz_addrL3" "reg_4/port30" 9.229
cap "reg_4/reg_one_4/r0" "wz3" 19.78
cap "reg_4/reg_one_4/r0" "ry3" 48.664
cap "wz3" "reg_4/reg_one_4/tmp" 6.507
cap "wz_addrL3" "reg_4/reg_one_4/r1" 59.948
cap "mux_8bit_0/GND!" "wz3" 58.7
cap "mux_8bit_0/GND!" "ry3" 58.7
cap "reg_4/reg_one_4/Vdd!" "reg_4/reg_one_4/r0" -9.768
cap "mux_8bit_0/mux_one_3/inv2_1/GND!" "mux_8bit_0/mux_one_3/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "reg_4/reg_one_4/a_33_32#" "wz3" 7.959
cap "wz_addrL3" "reg_4/port31" 4.95
cap "reg_4/reg_one_4/w" "reg_4/port31" 5.072
cap "mux_8bit_0/out3" "wz3" 2.844
cap "mux_8bit_0/out3" "ry3" -17.369
cap "mux_8bit_0/mux_one_3/2mux_nr_0/a_n17_n11#" "wz3" -5.178
cap "wz_addrL3" "reg_4/reg_one_4/w_n11_n27#" 76.564
cap "mux_8bit_0/mux_one_3/inv2_1/GND!" "wz3" 9.086
cap "mux_8bit_0/mux_one_3/inv2_1/GND!" "ry3" -6.916
cap "reg_4/reg_one_4/Vdd!" "mux_8bit_0/out3" 56.544
cap "mux_8bit_0/out3" "reg_4/reg_one_4/r0" 314.001
cap "reg_4/reg_one_4/Vdd!" "wz_addrL3" 73.616
cap "mux_8bit_0/mux_one_3/inv2_1/a_1_8#" "wz_addrL3" -1.132
cap "wz_addrL3" "reg_4/reg_one_4/r0" 21.028
cap "wz_addrL3" "reg_4/reg_one_4/tmp" 4.68
cap "mux_8bit_0/out3" "mux_8bit_0/GND!" 46.74
cap "mux_8bit_0/mux_one_3/inv2_1/GND!" "reg_4/reg_one_4/r0" 63.6875
cap "wz3" "mux_8bit_0/mux_one_3/2mux_nr_0/s" 4.948
cap "wz_addrL3" "mux_8bit_0/GND!" 58.7
cap "wz_addrL3" "reg_4/reg_one_4/a_4_n13#" 47.175
cap "mux_8bit_0/mux_one_3/inv2_1/GND!" "mux_8bit_0/GND!" -3.444
cap "mux_8bit_0/out3" "mux_8bit_0/mux_one_3/2mux_nr_0/out" 85.4219
cap "mux_8bit_0/out3" "wz_addrL3" -6.325
cap "reg_4/reg_one_4/w" "wz3" 5.064
cap "mux_8bit_0/out3" "mux_8bit_0/mux_one_3/inv2_1/GND!" 462.156
cap "addsub_1/addsub_one_3/Vdd!" "reg_4/port30" 26.592
cap "wz_addrL3" "addsub_1/xor_3/b" 7.975
cap "wz3" "addsub_1/xor_3/a_61_n1#" 5.568
cap "wz3" "addsub_1/b3" 26.517
cap "addsub_1/xor_3/a_89_n31#" "reg_4/port30" 2.424
cap "wz3" "addsub_1/xor_3/a_61_n31#" 19.78
cap "wz3" "addsub_1/addsub_one_3/Vdd!" 15.72
cap "reg_4/reg_one_4/w_n11_n27#" "reg_4/port30" 63.6875
cap "reg_4/port31" "addsub_1/b3" 11.825
cap "addsub_1/xor_3/b" "reg_4/port30" 115.766
cap "addsub_1/xor_3/b" "addsub_1/b3" 11.5435
cap "addsub_1/addsub_one_3/b" "reg_4/port30" 36.877
cap "reg_4/port31" "addsub_1/addsub_one_3/Vdd!" 11.825
cap "wz_addrL3" "reg_4/port30" -7.348
cap "addsub_1/xor_3/a_89_n31#" "wz3" 17.316
cap "wz_addrL3" "addsub_1/b3" 7.975
cap "wz3" "reg_4/reg_one_4/w" 58.7
cap "wz3" "reg_4/reg_one_4/w_n11_n27#" -8.24
cap "reg_4/port31" "reg_4/reg_one_4/w_n11_n27#" -1.039
cap "wz_addrL3" "addsub_1/addsub_one_3/Vdd!" 11.825
cap "wz3" "reg_4/reg_one_4/a_33_32#" -12.339
cap "wz3" "addsub_1/xor_3/b" 11.825
cap "wz3" "reg_4/reg_one_4/w_n11_n27#" -2.417
cap "wz_addrL3" "reg_4/reg_one_4/w_n11_n27#" -3.379
cap "reg_4/port31" "reg_4/reg_one_4/w_n11_n27#" 12.7375
cap "wz3" "addsub_1/addsub_one_3/b" 97.913
cap "reg_4/port31" "reg_4/reg_one_4/w" 127.744
cap "addsub_1/xor_3/a_61_n1#" "reg_4/port30" 98.02
cap "wz_addrL3" "reg_4/reg_one_4/Vdd!" -2.948
cap "reg_4/port31" "addsub_1/xor_3/b" 11.825
cap "addsub_1/b3" "reg_4/port30" 38.809
cap "wz_addrL3" "reg_4/reg_one_4/w" 58.7
cap "wz_addrL3" "reg_4/reg_one_4/w_n11_n27#" 8.24
cap "addsub_1/xor_3/a_61_n31#" "reg_4/port30" 1.95
cap "addsub_1/xor_3/a_61_n31#" "addsub_1/b3" 1.32339e-13
subcap "a_1716_1273#" -30.357
cap "a_2510_1893#" "addsub_1/addsub_one_4/GND!" 40.362
cap "ry3" "addsub_1/addsub_one_4/GND!" 36.425
cap "a_2510_1893#" "addsub_1/s3" 41.11
cap "addsub_1/GND!" "wz3" 11.825
cap "addsub_1/addsub_one_3/Vdd!" "wz_addrL3" 32.72
cap "addsub_1/addsub_one_3/Vdd!" "wz3" 3.171
cap "latch_5/latch_one_3/Vdd!" "addsub_1/s3" -12.402
cap "addsub_1/GND!" "wz_addrL3" 11.825
cap "wz3" "addsub_1/addsub_one_3/b" 95.736
cap "addsub_1/addsub_one_3/GND!" "wz3" 11.825
cap "addsub_1/addsub_one_3/GND!" "wz_addrL3" 10.505
cap "addsub_1/addsub_one_3/a_35_n41#" "wz3" 51.712
cap "addsub_1/addsub_one_3/a_35_n41#" "wz_addrL3" 24.622
cap "addsub_1/addsub_one_3/Vdd!" "ry3" 9.108
cap "a_2510_1893#" "addsub_1/addsub_one_3/GND!" 33
cap "addsub_1/GND!" "ry3" 11.825
cap "a_2510_1893#" "addsub_1/addsub_one_3/b" 4.204
cap "a_2510_1893#" "addsub_1/addsub_one_3/a_35_n41#" 8.408
cap "addsub_1/addsub_one_3/a_89_n41#" "a_2510_1893#" 22.875
cap "addsub_1/GND!" "addsub_1/s3" 76.9567
cap "addsub_1/addsub_one_3/a_35_n41#" "addsub_1/addsub_one_4/GND!" -1.13687e-13
cap "addsub_1/addsub_one_3/a_78_n41#" "wz3" 35.835
cap "wz3" "addsub_1/addsub_one_3/cin" 1.56
cap "latch_5/latch_one_3/a_n5_n54#" "addsub_1/s3" 19.2392
cap "addsub_1/addsub_one_4/GND!" "wz3" 14.639
cap "addsub_1/addsub_one_3/cout" "a_2510_1893#" 14.329
cap "a_2510_1893#" "addsub_1/addsub_one_3/a" 4.204
cap "addsub_1/addsub_one_4/GND!" "wz_addrL3" 43.659
cap "addsub_1/addsub_one_3/a_78_n41#" "a_2510_1893#" 15.064
cap "a_2510_1893#" "addsub_1/addsub_one_3/cin" 7.536
cap "addsub_1/addsub_one_3/cout" "ry3" 18.24
subcap "a_1716_1273#" -99.769
cap "latch_5/latch_one_3/Vdd!" "latch_5/latch_one_3/GND!" -0.984
cap "latch_5/latch_one_3/c" "latch_5/latch_one_3/GND!" 13.8522
cap "staticizer_2/staticizer_one_3/c" "wz3" 58.7
cap "wz3" "latch_5/latch_one_3/GND!" 117.4
cap "latch_5/latch_one_3/Vdd!" "latch_5/latch_one_3/c" 1071.03
cap "latch_5/latch_one_3/c" "wz3" 58.7
cap "latch_5/latch_one_3/Vdd!" "wz3" 117.4
cap "ry3" "staticizer_2/staticizer_one_3/c" 76.935
cap "latch_5/out3" "addsub_1/s3" 4.324
cap "ry3" "latch_5/latch_one_3/GND!" 181.284
cap "latch_5/out3" "staticizer_2/staticizer_one_3/a_77_n45#" 9.998
cap "latch_5/out3" "latch_5/latch_one_3/a_n5_n54#" 59.375
cap "addsub_1/s3" "latch_5/latch_one_3/a_n5_n54#" 57.7175
cap "latch_5/latch_one_3/a_12_n54#" "latch_5/latch_one_3/Vdd!" 1.13687e-13
cap "latch_5/out3" "latch_5/latch_one_3/a_30_n54#" 1.524
cap "latch_5/latch_one_3/Vdd!" "ry3" 117.4
cap "latch_5/latch_one_3/c" "ry3" 81.378
cap "staticizer_2/staticizer_one_3/c" "latch_5/out3" 63.648
cap "latch_5/out3" "latch_5/latch_one_3/GND!" 167.247
cap "latch_5/latch_one_3/c" "latch_5/out3" 75.182
cap "latch_5/latch_one_3/Vdd!" "addsub_1/s3" 19.399
cap "latch_5/latch_one_3/Vdd!" "latch_5/out3" 231.426
cap "staticizer_2/staticizer_one_3/c" "latch_5/latch_one_3/GND!" -5.68434e-14
cap "latch_5/latch_one_3/a_12_n54#" "latch_5/out3" 9.731
cap "addsub_1/s3" "addsub_1/GND!" 19.2392
cap "latch_5/out3" "staticizer_2/staticizer_one_3/a_60_n45#" 212.283
subcap "wz_addrH3" -915.907
subcap "m1_1909_1246#" -380.236
cap "mux_8bit_1/out3" "ry3" -10.01
cap "mux_8bit_1/mux_one_3/inv2_0/GND!" "mux_8bit_1/in1_3" 11.098
cap "staticizer_2/staticizer_one_3/c" "staticizer_2/staticizer_one_3/out" 3.996
cap "staticizer_2/staticizer_one_3/a_95_n27#" "staticizer_2/staticizer_one_3/out" 5.61
cap "mux_8bit_1/sel" "mux_8bit_1/in0_3" 58.7
cap "mux_8bit_1/sel" "ry3" 58.7
cap "mux_8bit_1/mux_one_3/2mux_nr_0/in1" "mux_8bit_1/in1_3" 18.535
cap "mux_8bit_1/mux_one_3/Vdd!" "mux_8bit_1/in0_3" 149.982
cap "mux_8bit_1/mux_one_3/Vdd!" "ry3" 58.7
cap "mux_8bit_1/out3" "mux_8bit_1/sel" 0.84
cap "staticizer_2/staticizer_one_3/a_60_n45#" "staticizer_2/staticizer_one_3/out" -5.616
cap "staticizer_2/staticizer_one_3/w_54_n57#" "staticizer_2/staticizer_one_3/out" 2.59
cap "mux_8bit_1/in1_3" "mux_8bit_1/mux_one_3/2mux_nr_0/s" 4.556
cap "mux_8bit_1/mux_one_3/inv2_2/GND!" "mux_8bit_1/in0_3" 18.437
cap "mux_8bit_1/mux_one_3/inv2_2/GND!" "ry3" 63.013
cap "staticizer_2/staticizer_one_3/w_54_n57#" "ry3" 4.329
cap "mux_8bit_1/sel" "mux_8bit_1/in1_3" 58.7
cap "staticizer_2/staticizer_one_3/a_95_n45#" "staticizer_2/staticizer_one_3/out" 4.212
cap "mux_8bit_1/out3" "mux_8bit_1/mux_one_3/inv2_2/GND!" 37.928
cap "staticizer_2/staticizer_one_3/a_77_n45#" "staticizer_2/staticizer_one_3/out" 19.052
cap "mux_8bit_1/mux_one_3/inv2_1/a_1_8#" "mux_8bit_1/in0_3" 4.95
cap "mux_8bit_1/mux_one_3/Vdd!" "mux_8bit_1/in1_3" 96.331
cap "mux_8bit_1/mux_one_3/2mux_nr_0/in0" "mux_8bit_1/in0_3" 34.083
cap "mux_8bit_1/in1_3" "mux_8bit_1/mux_one_3/2mux_nr_0/a_n17_n11#" 36.092
cap "mux_8bit_1/mux_one_3/inv2_2/GND!" "mux_8bit_1/in1_3" 4.81
cap "staticizer_2/staticizer_one_3/Vdd!" "staticizer_2/staticizer_one_3/out" 11.587
cap "wz_addrH3" "mux_8bit_1/out3" -6.325
cap "reg_5/reg_one_4/r0" "mux_8bit_1/mux_one_3/inv2_1/GND!" 63.6875
cap "wz_addrH3" "reg_5/reg_one_4/Vdd!" 162.612
cap "reg_5/reg_one_4/r0" "mux_8bit_1/out3" 314.001
cap "mux_8bit_1/mux_one_3/inv2_1/GND!" "mux_8bit_1/GND!" -3.444
cap "mux_8bit_1/out3" "mux_8bit_1/GND!" 46.74
cap "wz3" "reg_5/reg_one_4/w_n11_n27#" 192.228
cap "reg_5/reg_one_4/r0" "ry3" 48.664
cap "reg_5/reg_one_4/r0" "reg_5/reg_one_4/Vdd!" -9.768
cap "wz3" "reg_5/reg_one_4/tmp" 6.507
cap "wz3" "mux_8bit_1/mux_one_3/inv2_1/GND!" 9.086
cap "ry3" "mux_8bit_1/GND!" 58.7
cap "wz3" "reg_5/reg_one_4/w" 5.064
cap "wz3" "mux_8bit_1/out3" 2.844
cap "reg_5/reg_one_4/r1" "ry3" 64.004
cap "wz3" "reg_5/reg_one_4/Vdd!" 58.7
cap "mux_8bit_1/mux_one_3/inv2_1/GND!" "mux_8bit_1/mux_one_3/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "reg_5/reg_one_4/a_16_27#" "wz3" 8.022
cap "mux_8bit_1/mux_one_3/inv2_1/GND!" "mux_8bit_1/out3" 462.156
cap "ry3" "reg_5/reg_one_4/w_n11_n27#" 106.567
cap "reg_5/reg_one_4/r0" "wz_addrH3" 24.728
cap "ry3" "mux_8bit_1/mux_one_3/inv2_1/GND!" -6.916
cap "wz3" "reg_5/reg_one_4/a_33_32#" 7.959
cap "wz_addrH3" "mux_8bit_1/GND!" 58.7
cap "ry3" "mux_8bit_1/out3" -17.369
cap "reg_5/reg_one_4/Vdd!" "mux_8bit_1/out3" 56.544
cap "reg_5/port31" "reg_5/reg_one_4/w_n11_n27#" 1.628
cap "reg_5/port31" "reg_5/reg_one_4/w" 5.072
cap "wz3" "mux_8bit_1/mux_one_3/2mux_nr_0/s" 4.948
cap "reg_5/reg_one_4/r1" "wz_addrH3" 58.7
cap "mux_8bit_1/mux_one_3/2mux_nr_0/out" "mux_8bit_1/out3" 85.4219
cap "ry3" "reg_5/reg_one_4/Vdd!" 58.7
cap "reg_5/port31" "ry3" 73.199
cap "wz_addrH3" "reg_5/reg_one_4/a_4_n13#" 27.497
cap "reg_5/reg_one_4/r0" "wz3" 19.78
cap "wz3" "mux_8bit_1/mux_one_3/2mux_nr_0/a_n17_n11#" -5.178
cap "wz_addrH3" "reg_5/reg_one_4/a_54_5#" 4.828
cap "wz3" "mux_8bit_1/GND!" 58.7
cap "reg_5/reg_one_4/r1" "wz3" 58.7
cap "wz_addrH3" "reg_5/port30" 6.6
cap "wz_addrH3" "reg_5/reg_one_4/w_n11_n27#" 58.7
cap "wz_addrH3" "reg_5/reg_one_4/tmp" 4.948
cap "wz_addrH3" "mux_8bit_1/mux_one_3/inv2_1/GND!" 8.954
cap "reg_6/reg_one_4/tmp" "wz_addrH3" 4.948
cap "reg_6/in3" "reg_6/reg_one_4/a_16_27#" 8.022
cap "reg_5/port31" "reg_6/reg_one_4/r1" 58.7
cap "reg_6/reg_one_4/r0" "reg_6/reg_one_4/w_n11_n27#" 1.13687e-13
cap "reg_6/reg_one_4/Vdd!" "reg_5/port31" 58.7
cap "reg_5/port31" "ry3" -17.146
cap "reg_5/w" "reg_5/port30" 67.0625
cap "reg_6/reg_one_4/port1" "ry3" 68.579
cap "reg_6/in3" "reg_6/reg_one_4/r1" 58.7
cap "reg_6/in3" "reg_6/reg_one_4/Vdd!" 58.7
cap "reg_6/reg_one_4/tmp" "reg_5/port30" 5.92
cap "reg_5/port31" "reg_5/reg_one_4/w_n11_n27#" 12.7375
cap "reg_5/port31" "reg_6/reg_one_4/r0" 19.78
cap "reg_5/w" "ry3" 58.7
cap "reg_6/in3" "reg_5/reg_one_4/w_n11_n27#" -8.24
cap "reg_5/reg_one_4/w_n11_n27#" "ry3" -2.667
cap "wz_addrH3" "reg_6/reg_one_4/r1" 58.7
cap "reg_6/in3" "reg_6/reg_one_4/r0" 128.02
cap "reg_6/reg_one_4/Vdd!" "wz_addrH3" 160.588
cap "reg_6/in3" "reg_5/reg_one_4/w_n11_n27#" -2.417
cap "reg_6/reg_one_4/a_4_n13#" "wz_addrH3" 17.113
cap "reg_5/reg_one_4/w_n11_n27#" "wz_addrH3" 8.24
cap "reg_5/port30" "reg_6/reg_one_4/r1" 64.504
cap "reg_5/port31" "reg_6/reg_one_4/w_n11_n27#" 83.267
cap "reg_6/reg_one_4/Vdd!" "reg_5/port30" 58.7
cap "reg_6/reg_one_4/a_54_5#" "wz_addrH3" 4.828
cap "reg_6/reg_one_4/a_4_n13#" "reg_5/port30" 87.672
cap "reg_6/reg_one_4/r0" "wz_addrH3" 24.728
cap "reg_6/in3" "reg_6/reg_one_4/w" 2.844
cap "reg_6/in3" "reg_6/reg_one_4/w_n11_n27#" 182.433
cap "reg_5/reg_one_4/w_n11_n27#" "reg_5/port30" 127.375
cap "reg_6/in3" "reg_6/reg_one_4/w" 2.22
cap "ry3" "reg_6/reg_one_4/r1" 64.004
cap "reg_6/reg_one_4/Vdd!" "ry3" 58.7
cap "reg_6/reg_one_4/r0" "reg_5/port30" 26.208
cap "wz_addrH3" "reg_6/reg_one_4/w_n11_n27#" 58.7
cap "reg_6/in3" "reg_6/reg_one_4/a_33_32#" 2.844
cap "reg_6/reg_one_4/r0" "ry3" 48.664
cap "reg_5/port31" "reg_5/w" 69.0435
cap "reg_5/reg_one_4/w_n11_n27#" "reg_5/port31" 1.628
cap "reg_6/reg_one_4/w_n11_n27#" "reg_5/port30" 151.215
cap "reg_5/reg_one_4/Vdd!" "wz_addrH3" -2.417
cap "reg_6/in3" "reg_5/w" 58.7
cap "reg_6/in3" "reg_6/reg_one_4/tmp" 4.461
cap "reg_6/reg_one_4/a_21_n13#" "reg_5/port30" 3.96
cap "reg_6/reg_one_4/w_n11_n27#" "reg_6/reg_one_4/r1" -5.68434e-14
cap "ry3" "reg_6/reg_one_4/w_n11_n27#" 101.233
cap "reg_6/reg_one_4/port1" "reg_5/port30" 5.5
cap "reg_5/w" "wz_addrH3" 58.7
cap "reg_6/in3" "reg_5/reg_one_4/a_33_32#" -12.339
subcap "m1_2209_1246#" -380.236
cap "reg_6/reg_one_4/Vdd!" "mux_8bit_2/in0_3" -0.393
cap "mux_8bit_2/sel" "reg_6/port31" 58.7
cap "mux_8bit_2/out3" "mux_8bit_2/sel" 0.84
cap "mux_8bit_2/out3" "mux_8bit_2/mux_one_3/inv2_2/GND!" 37.928
cap "reg_6/reg_one_4/w_n11_n27#" "mux_8bit_2/in1_3" 48.9529
cap "mux_8bit_2/mux_one_3/inv2_2/GND!" "reg_6/port31" 63.013
cap "reg_6/reg_one_4/a_33_32#" "mux_8bit_2/in1_3" 5.115
cap "reg_6/reg_one_4/w" "ry_addrH3" 58.7
cap "mux_8bit_2/in1_3" "reg_6/reg_one_4/w_n11_n27#" -1.886
cap "reg_6/reg_one_4/w_n11_n27#" "reg_6/port31" 12.7375
cap "mux_8bit_2/mux_one_3/Vdd!" "mux_8bit_2/mux_one_3/2mux_nr_0/in0" -2.27374e-13
cap "ry_addrH3" "mux_8bit_2/mux_one_3/Vdd!" 58.7
cap "mux_8bit_2/in0_3" "rx_addrH3" 16.569
cap "ry_addrH3" "reg_6/reg_one_4/w_n11_n27#" 0.019
cap "reg_6/reg_one_4/a_4_n13#" "mux_8bit_2/in0_3" -1.152
cap "reg_6/reg_one_4/Vdd!" "reg_6/reg_one_4/a_4_n13#" -7.10543e-15
cap "ry_addrH3" "mux_8bit_2/sel" 58.7
cap "reg_6/reg_one_4/w" "mux_8bit_2/in0_3" 58.7
cap "reg_6/reg_one_4/w" "reg_6/reg_one_4/Vdd!" 3.55271e-15
cap "reg_6/reg_one_4/tmp" "mux_8bit_2/in1_3" -4.818
cap "mux_8bit_2/mux_one_3/Vdd!" "mux_8bit_2/in0_3" 139.939
cap "reg_6/reg_one_4/a_4_n13#" "rx_addrH3" -10.448
cap "reg_6/port30" "mux_8bit_2/in0_3" 3.171
cap "mux_8bit_2/in0_3" "mux_8bit_2/sel" 58.7
cap "mux_8bit_2/in0_3" "mux_8bit_2/mux_one_3/inv2_1/a_1_8#" 4.95
cap "reg_6/reg_one_4/Vdd!" "reg_6/port30" -7.10543e-15
cap "mux_8bit_2/mux_one_3/inv2_2/GND!" "mux_8bit_2/in0_3" 18.437
cap "reg_6/reg_one_4/w" "rx_addrH3" 58.7
cap "reg_6/reg_one_4/w" "mux_8bit_2/in1_3" 97.0214
cap "mux_8bit_2/out3" "rx_addrH3" 19.905
cap "mux_8bit_2/mux_one_3/inv2_0/GND!" "mux_8bit_2/in1_3" 2.035
cap "reg_6/reg_one_4/w_n11_n27#" "rx_addrH3" -2.286
cap "reg_6/reg_one_4/w_n11_n27#" "mux_8bit_2/in0_3" 8.24
cap "mux_8bit_2/mux_one_3/Vdd!" "rx_addrH3" 76.242
cap "mux_8bit_2/in0_3" "mux_8bit_2/mux_one_3/2mux_nr_0/in0" 34.083
cap "reg_6/port30" "rx_addrH3" 4.411
cap "reg_6/reg_one_4/a_33_32#" "reg_6/reg_one_4/Vdd!" -7.10543e-15
cap "mux_8bit_2/mux_one_3/Vdd!" "mux_8bit_2/in1_3" 2.035
cap "mux_8bit_2/sel" "rx_addrH3" 58.7
cap "reg_6/reg_one_4/w" "reg_6/port31" 127.744
cap "mux_8bit_2/mux_one_3/inv2_2/GND!" "rx_addrH3" 22.523
cap "mux_8bit_2/out3" "reg_6/port31" -10.01
cap "mux_8bit_2/mux_one_3/Vdd!" "reg_6/port31" 58.7
cap "reg_6/reg_one_4/w_n11_n27#" "reg_6/port31" 4.295
cap "reg_6/reg_one_4/w_n11_n27#" "rx_addrH3" 19.776
cap "rx_addrH3" "mux_8bit_2/mux_one_3/2mux_nr_0/in0" 30.259
cap "reg_6/reg_one_4/tmp" "reg_6/reg_one_4/w_n11_n27#" 3.55271e-15
cap "mux_8bit_2/mux_one_3/inv2_1/GND!" "mux_8bit_2/out3" 462.156
cap "wz_addrH3" "reg_7/reg_one_4/r1" 58.7
cap "mux_8bit_2/mux_one_3/inv2_1/GND!" "reg_7/reg_one_4/r0" 63.6875
cap "mux_8bit_2/mux_one_3/inv2_1/GND!" "mux_8bit_2/mux_one_3/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "reg_7/reg_one_4/tmp" "wz_addrH3" 4.948
cap "ry_addrH3" "reg_7/reg_one_4/Vdd!" 58.7
cap "ry3" "reg_7/port31" 73.199
cap "wz_addrH3" "reg_7/reg_one_4/a_4_n13#" 27.497
cap "rx_addrH3" "reg_7/reg_one_4/Vdd!" 58.7
cap "mux_8bit_2/GND!" "ry3" 58.7
cap "reg_7/port30" "rx_addrH3" 6.006
cap "reg_7/reg_one_4/w_n11_n27#" "ry3" 106.567
cap "mux_8bit_2/GND!" "wz_addrH3" 58.7
cap "reg_7/reg_one_4/w_n11_n27#" "wz_addrH3" 58.7
cap "rx_addrH3" "mux_8bit_2/out3" -6.325
cap "mux_8bit_2/GND!" "mux_8bit_2/out3" 46.74
cap "ry_addrH3" "reg_7/reg_one_4/r0" 19.78
cap "rx_addrH3" "reg_7/reg_one_4/r0" 26.208
cap "reg_7/reg_one_4/Vdd!" "ry3" 58.7
cap "reg_7/reg_one_4/Vdd!" "wz_addrH3" 162.612
cap "reg_7/reg_one_4/w" "reg_7/port31" 5.072
cap "reg_7/port30" "wz_addrH3" 6.6
cap "reg_7/reg_one_4/Vdd!" "mux_8bit_2/out3" 56.544
cap "rx_addrH3" "mux_8bit_2/mux_one_3/inv2_1/GND!" 12.194
cap "mux_8bit_2/out3" "ry3" -17.369
cap "mux_8bit_2/GND!" "mux_8bit_2/mux_one_3/inv2_1/GND!" -3.444
cap "reg_7/reg_one_4/Vdd!" "reg_7/reg_one_4/r0" -9.768
cap "reg_7/reg_one_4/r0" "ry3" 48.664
cap "wz_addrH3" "mux_8bit_2/out3" -6.325
cap "ry_addrH3" "reg_7/reg_one_4/r1" 58.7
cap "rx_addrH3" "reg_7/reg_one_4/r1" 64.504
cap "wz_addrH3" "reg_7/reg_one_4/r0" 24.728
cap "mux_8bit_2/mux_one_3/2mux_nr_0/out" "mux_8bit_2/out3" 85.4219
cap "reg_7/reg_one_4/a_54_5#" "wz_addrH3" 4.828
cap "mux_8bit_2/out3" "reg_7/reg_one_4/r0" 314.001
cap "reg_7/reg_one_4/tmp" "rx_addrH3" 5.92
cap "rx_addrH3" "reg_7/reg_one_4/a_21_n13#" 3.96
cap "rx_addrH3" "reg_7/reg_one_4/a_4_n13#" 93.704
cap "rx_addrH3" "reg_7/port31" 5.5
cap "mux_8bit_2/mux_one_3/inv2_1/GND!" "ry3" -6.916
cap "reg_7/reg_one_4/w_n11_n27#" "reg_7/port31" 1.628
cap "mux_8bit_2/GND!" "ry_addrH3" 58.7
cap "wz_addrH3" "mux_8bit_2/mux_one_3/inv2_1/GND!" 8.954
cap "mux_8bit_2/GND!" "rx_addrH3" 58.7
cap "ry_addrH3" "reg_7/reg_one_4/w_n11_n27#" 86.284
cap "rx_addrH3" "reg_7/reg_one_4/w_n11_n27#" 163.513
cap "reg_7/reg_one_4/r1" "ry3" 64.004
cap "reg_7/reg_one_4/w_n11_n27#" "reg_7/port30" -3.048
cap "addsub_2/xor_3/a_61_n31#" "reg_7/port30" 1.95
cap "wz_addrH3" "addsub_2/b3" 5.939
cap "ry3" "reg_7/reg_one_4/w_n11_n27#" -2.667
cap "reg_7/reg_one_4/Vdd!" "wz_addrH3" -2.417
cap "reg_7/port31" "addsub_2/addsub_one_3/Vdd!" 11.825
cap "reg_7/reg_one_4/w" "reg_7/port30" 125.763
cap "addsub_2/xor_3/a_89_n31#" "reg_7/port30" 2.424
cap "addsub_2/xor_3/b" "reg_7/port30" 115.766
cap "addsub_2/addsub_one_3/Vdd!" "wz_addrH3" 11.825
cap "reg_7/reg_one_4/w" "ry3" 58.7
cap "reg_7/port31" "reg_7/reg_one_4/w_n11_n27#" 12.7375
cap "addsub_2/xor_3/b" "ry3" 11.825
cap "reg_7/port31" "ry3" -17.146
cap "wz_addrH3" "reg_7/reg_one_4/w_n11_n27#" 8.24
cap "reg_7/port30" "addsub_2/b3" 38.809
cap "reg_7/port31" "reg_7/reg_one_4/w_n11_n27#" -1.37
cap "ry3" "addsub_2/b3" 11.825
cap "addsub_2/xor_3/a_61_n31#" "addsub_2/b3" 1.32339e-13
cap "addsub_2/addsub_one_3/Vdd!" "reg_7/port30" 26.592
cap "addsub_2/xor_3/a_61_n1#" "reg_7/port30" 98.02
cap "reg_7/reg_one_4/w" "reg_7/port31" 127.744
cap "reg_7/reg_one_4/w" "wz_addrH3" 58.7
cap "reg_7/port31" "addsub_2/xor_3/b" 11.825
cap "addsub_2/xor_3/b" "wz_addrH3" 11.825
cap "addsub_2/addsub_one_3/Vdd!" "ry3" 11.825
cap "reg_7/port30" "reg_7/reg_one_4/w_n11_n27#" 135.615
cap "reg_7/port31" "addsub_2/b3" 11.825
cap "addsub_2/addsub_one_3/b" "reg_7/port30" 36.877
subcap "a_2516_1273#" -30.357
cap "addsub_2/addsub_one_3/cout" "ry3" 20.38
cap "addsub_2/addsub_one_4/GND!" "addsub_2/addsub_one_3/a_35_n41#" -1.13687e-13
cap "ry_addrH3" "addsub_2/addsub_one_3/cout" 2.474
cap "wz_addrH3" "addsub_2/addsub_one_3/Vdd!" 22.705
cap "wz_addrH3" "addsub_2/addsub_one_4/GND!" 34.459
cap "addsub_2/s3" "addsub_2/GND!" 76.9567
cap "addsub_2/GND!" "ry3" 11.825
cap "addsub_2/s3" "wz_addrH3" 50.259
cap "ry_addrH3" "addsub_2/GND!" 11.825
cap "addsub_2/s3" "latch_6/latch_one_3/Vdd!" -12.402
cap "addsub_2/s3" "latch_6/latch_one_3/a_n5_n54#" 19.2392
cap "wz_addrH3" "addsub_2/addsub_one_3/a_35_n41#" 19.78
cap "addsub_2/addsub_one_3/GND!" "wz_addrH3" 4.95
cap "wz_addrH3" "addsub_2/GND!" 4.95
cap "addsub_2/addsub_one_3/Vdd!" "ry3" 9.108
cap "ry_addrH3" "addsub_2/addsub_one_3/Vdd!" -4.455
cap "addsub_2/addsub_one_4/GND!" "ry3" 40.985
cap "ry_addrH3" "addsub_2/addsub_one_4/GND!" 33.396
subcap "a_2516_1273#" -99.769
cap "ry_addrH3" "latch_6/latch_one_3/GND!" 117.4
cap "latch_6/out3" "latch_6/latch_one_3/c" 9.252
cap "latch_6/latch_one_3/Vdd!" "latch_6/latch_one_3/c" 1070.42
cap "staticizer_3/staticizer_one_3/out" "latch_6/latch_one_3/GND!" 117.4
cap "staticizer_3/staticizer_one_3/c" "latch_6/latch_one_3/GND!" 5.68434e-14
cap "ry_addrH3" "latch_6/latch_one_3/Vdd!" 117.4
cap "staticizer_3/staticizer_one_3/out" "staticizer_3/staticizer_one_3/a_60_n45#" 75.3524
cap "addsub_2/s3" "staticizer_3/staticizer_one_3/out" 6.404
cap "staticizer_3/staticizer_one_3/c" "ry3" 76.935
cap "staticizer_3/staticizer_one_3/out" "latch_6/latch_one_3/a_12_n54#" 9.708
cap "staticizer_3/staticizer_one_3/out" "latch_6/out3" 7.047
cap "staticizer_3/staticizer_one_3/a_77_n45#" "staticizer_3/staticizer_one_3/out" 5.115
cap "staticizer_3/staticizer_one_3/out" "latch_6/latch_one_3/Vdd!" 169.606
cap "staticizer_3/staticizer_one_3/out" "latch_6/latch_one_3/a_n5_n54#" 59.464
cap "ry3" "latch_6/latch_one_3/GND!" 181.284
cap "latch_6/out3" "latch_6/latch_one_3/GND!" 10.156
cap "latch_6/latch_one_3/GND!" "latch_6/latch_one_3/Vdd!" -3.41061e-13
cap "latch_6/out3" "staticizer_3/staticizer_one_3/a_60_n45#" 150.065
cap "ry3" "latch_6/latch_one_3/Vdd!" 117.4
cap "addsub_2/s3" "addsub_2/GND!" 19.2392
cap "ry_addrH3" "latch_6/latch_one_3/c" 58.7
cap "addsub_2/s3" "latch_6/latch_one_3/Vdd!" 19.399
cap "latch_6/latch_one_3/a_12_n54#" "latch_6/latch_one_3/Vdd!" 1.13687e-13
cap "latch_6/out3" "latch_6/latch_one_3/Vdd!" 107.428
cap "addsub_2/s3" "latch_6/latch_one_3/a_n5_n54#" 57.7175
cap "staticizer_3/staticizer_one_3/out" "latch_6/latch_one_3/c" 61.66
cap "ry_addrH3" "staticizer_3/staticizer_one_3/c" 58.7
cap "staticizer_3/staticizer_one_3/out" "latch_6/latch_one_3/a_30_n35#" 1.88
cap "staticizer_3/staticizer_one_3/out" "staticizer_3/staticizer_one_3/c" 61.544
cap "latch_6/latch_one_3/GND!" "latch_6/latch_one_3/c" 13.8522
cap "ry3" "latch_6/latch_one_3/c" 81.378
subcap "addr_out3" -56.838
cap "latch_7/latch_one_3/c" "latch_7/latch_one_3/GND!" 13.8522
cap "latch_7/out3" "latch_7/latch_one_3/Vdd!" 107.428
cap "latch_7/in3" "staticizer_3/staticizer_one_3/w_54_n57#" 17.972
cap "ry_addrH3" "latch_7/latch_one_3/GND!" 77.41
cap "staticizer_3/staticizer_one_3/c" "staticizer_3/staticizer_one_3/w_54_n57#" -1.42109e-14
cap "staticizer_3/staticizer_one_3/Vdd!" "latch_7/in3" 11.463
cap "staticizer_3/staticizer_one_3/out" "staticizer_3/staticizer_one_3/w_54_n57#" 8.272
cap "latch_7/in3" "latch_7/latch_one_3/Vdd!" 286.786
cap "latch_7/latch_one_3/c" "latch_7/out3" 9.252
cap "staticizer_4/staticizer_one_3/a_60_n45#" "latch_7/latch_one_3/GND!" 5.68434e-14
cap "staticizer_3/staticizer_one_3/Vdd!" "staticizer_3/staticizer_one_3/out" 6.001
cap "latch_7/in3" "latch_7/latch_one_3/a_n5_n54#" 57.7175
cap "latch_7/latch_one_3/Vdd!" "latch_7/latch_one_3/a_n5_n54#" -1.13687e-13
cap "staticizer_3/staticizer_one_3/out" "staticizer_3/staticizer_one_3/a_60_n45#" 0.709429
cap "latch_7/latch_one_3/Vdd!" "latch_7/latch_one_3/a_12_n54#" 1.13687e-13
cap "staticizer_3/staticizer_one_3/out" "latch_7/in3" 23.087
cap "latch_7/out3" "latch_7/latch_one_3/GND!" 10.156
cap "latch_7/latch_one_3/c" "latch_7/latch_one_3/Vdd!" 1070.42
cap "ry_addrH3" "latch_7/latch_one_3/Vdd!" 117.4
cap "latch_7/out3" "staticizer_4/staticizer_one_3/a_60_n45#" 150.065
cap "staticizer_3/staticizer_one_3/Vdd!" "staticizer_3/staticizer_one_3/a_77_n45#" 2.84217e-14
cap "latch_7/latch_one_3/Vdd!" "latch_7/latch_one_3/GND!" -0.738
cap "latch_7/in3" "latch_7/latch_one_3/GND!" 6.956
cap "ry_addrH3" "latch_7/latch_one_3/c" 58.7
cap "staticizer_3/staticizer_one_3/out" "staticizer_3/staticizer_one_3/a_77_n45#" 2.728
subcap "ry_addrH3" -836.866
subcap "addr_out11" -305.874
cap "staticizer_4/staticizer_one_3/c" "latch_8/in3" 58.7
cap "latch_8/latch_one_3/a_12_n54#" "latch_8/latch_one_3/Vdd!" 1.13687e-13
cap "staticizer_4/staticizer_one_3/Vdd!" "latch_8/in3" 11.463
cap "latch_8/latch_one_3/c" "staticizer_5/in3" -0.42
cap "latch_8/latch_one_3/a_n5_n54#" "latch_8/in3" 57.7175
cap "staticizer_5/staticizer_one_3/w_54_n57#" "latch_8/in3" 6.956
cap "staticizer_4/staticizer_one_3/w_54_n57#" "staticizer_4/staticizer_one_3/a_60_n45#" 2.84217e-14
cap "latch_8/in3" "staticizer_4/staticizer_one_3/out" 57.7175
cap "staticizer_5/in3" "latch_8/latch_one_3/Vdd!" -1.162
cap "staticizer_4/staticizer_one_3/Vdd!" "staticizer_4/staticizer_one_3/out" -5.68434e-14
cap "latch_8/in3" "staticizer_4/staticizer_one_3/w_54_n57#" 21.105
cap "latch_8/in3" "latch_8/latch_one_3/Vdd!" 367.261
cap "staticizer_4/staticizer_one_3/Vdd!" "staticizer_4/staticizer_one_3/a_77_n45#" 1.13687e-13
cap "latch_8/latch_one_3/a_n5_n54#" "latch_8/latch_one_3/Vdd!" -1.13687e-13
subcap "addr_out11" -36.486
cap "staticizer_5/in3" "staticizer_5/staticizer_one_3/a_60_n45#" 150.065
cap "staticizer_5/staticizer_one_3/w_54_n57#" "latch_8/latch_one_3/c" 13.8522
cap "staticizer_5/in3" "staticizer_5/staticizer_one_3/w_54_n57#" 10.156
cap "latch_8/latch_one_3/Vdd!" "latch_8/latch_one_3/c" 1070.42
cap "staticizer_5/in3" "latch_8/latch_one_3/Vdd!" 107.428
cap "staticizer_5/in3" "latch_8/latch_one_3/c" 9.252
cap "staticizer_1/Vdd!" "staticizer_1/staticizer_one_2/w_54_n57#" -3.55271e-15
cap "staticizer_1/staticizer_one_2/w_54_n57#" "latch_4/latch_one_2/c" 18.4696
cap "staticizer_1/Vdd!" "latch_4/latch_one_2/c" 1073
cap "latch_0/latch_one_2/c" "staticizer_0/Vdd!" 1073
cap "rx2" "latch_0/Vdd!" 58.7
cap "latch_4/Vdd!" "rx2" 187.775
cap "latch_0/latch_one_2/GND!" "rx2" 59.993
cap "rx2" "staticizer_0/Vdd!" 37.42
cap "latch_0/latch_one_2/GND!" "staticizer_0/Vdd!" -0.246
cap "latch_0/latch_one_2/c" "rx2" 58.7
cap "latch_0/latch_one_2/GND!" "latch_0/latch_one_2/c" 18.4696
cap "staticizer_0/staticizer_one_2/w_54_n57#" "staticizer_0/Vdd!" -0.984
cap "staticizer_0/staticizer_one_2/w_54_n57#" "shift_0/a2" 73.425
cap "shift_0/a3" "shift_0/a2" 125.762
cap "staticizer_0/staticizer_one_2/c" "shift_0/a2" 76.935
cap "staticizer_0/Vdd!" "shift_0/a2" -12.11
cap "rx2" "shift_0/GND!" 58.7
cap "rx2" "shift_0/shift_one_2/inv_2/in" 14.74
cap "rx2" "shift_0/shift_one_2/inv_2/GND!" 11.43
cap "rx2" "shift_0/shift_one_2/Vdd!" 7.239
cap "rx2" "shift_0/u" 58.7
cap "rx2" "shift_0/Vdd!" 58.7
cap "rx2" "latch_3/latch_one_2/GND!" 107.383
cap "rx2" "shift_0/shift_one_2/inv_3/Vdd!" 7.239
cap "rx2" "latch_3/latch_one_2/c" 3.12
cap "latch_3/Vdd!" "rx2" 58.7
cap "latch_3/latch_one_2/GND!" "shift_0/o2" 23.087
cap "rx2" "shift_0/shift_one_2/inv_2/GND!" 6.096
cap "rx2" "shift_0/o2" 20.945
cap "shift_0/shift_one_2/inv_3/Vdd!" "shift_0/o2" 1.162
cap "rx2" "shift_0/shift_one_3/s" 58.7
cap "fblock_0/b3" "fblock_0/fblock_one_3/2mux_nr_0/a_n17_n11#" 14.35
cap "fblock_0/fblock_one_3/inv_2/out" "fblock_0/b3" 2.783
cap "fblock_0/b3" "fblock_0/fblock_one_3/2mux_nr_0/out" 3.85
cap "rx2" "latch_3/latch_one_2/c" 78.258
cap "fblock_0/b3" "fblock_0/fblock_one_3/inv_1/out" 2.475
cap "fblock_0/fblock_one_3/g2" "fblock_0/b3" 18.895
cap "latch_3/latch_one_2/GND!" "rx2" 0.083
cap "fblock_0/fblock_one_3/g3" "rx2" 187.775
cap "fblock_0/fblock_one_2/inv_0/GND!" "fblock_0/fblock_one_2/2mux_nr_2/out" 5.68434e-14
cap "fblock_0/b3" "fblock_0/GND!" 18.895
cap "latch_3/latch_one_2/GND!" "latch_3/latch_one_2/c" 2.84217e-14
cap "fblock_0/b3" "fblock_0/fblock_one_3/2mux_nr_1/GND!" 27.522
cap "fblock_0/fblock_one_3/g3" "fblock_0/b3" 35.5805
cap "fblock_0/b3" "fblock_0/fblock_one_3/2mux_nr_1/Vdd!" 10.789
cap "fblock_0/fblock_one_3/inv_3/Vdd!" "ry3" 46.34
cap "fblock_0/fblock_one_3/2mux_nr_1/a_n17_n11#" "ry3" 12.702
cap "latch_1/latch_one_2/GND!" "ry3" 30.82
cap "fblock_0/fblock_one_3/inv_3/Vdd!" "latch_1/Vdd!" 1341.25
cap "fblock_0/fblock_one_3/g1" "ry3" 30.82
cap "latch_1/Vdd!" "ry3" 30.82
cap "fblock_0/fblock_one_3/inv_4/out" "ry3" 1.144
cap "fblock_0/fblock_one_3/inv_3/GND!" "ry3" 10.548
cap "fblock_0/fblock_one_3/2mux_nr_1/s" "ry3" 7.442
cap "fblock_0/fblock_one_3/g0" "ry3" 30.82
cap "fblock_0/fblock_one_3/2mux_nr_1/out" "ry3" 3.85
cap "fblock_0/fblock_one_3/inv_3/out" "ry3" 2.475
cap "addsub_0/xor_3/GND!" "ry3" 8.476
cap "ry3" "addsub_0/sub" 6.325
cap "ry3" "latch_1/latch_one_2/c" 30.82
cap "addsub_0/xor_3/a_61_n31#" "ry3" 6.876
cap "ry3" "addsub_0/xor_3/GND!" 14.188
cap "addsub_0/xor_3/out" "ry3" 1.98
cap "addsub_0/addsub_one_3/a_11_n41#" "as_cout" 21.93
cap "ry2" "addsub_0/addsub_one_3/Vdd!" 11.825
cap "addsub_0/addsub_one_3/a_35_n41#" "as_cout" 10.65
cap "as_cout" "addsub_0/addsub_one_3/a_66_n41#" 2.1
cap "addsub_0/addsub_one_2/Vdd!" "ry2" 16.992
cap "as_cout" "addsub_0/a3" 12.612
cap "ry2" "addsub_0/addsub_one_3/GND!" 24.288
cap "addsub_0/addsub_one_3/Vdd!" "addsub_0/a3" 19.378
cap "as_cout" "addsub_0/addsub_one_3/GND!" 67.564
cap "addsub_0/addsub_one_3/a_29_n41#" "as_cout" 2.1
cap "addsub_0/xor_3/a_61_n1#" "addsub_0/a3" 37.751
cap "addsub_0/addsub_one_3/Vdd!" "addsub_0/a3" 76.9567
cap "addsub_0/addsub_one_3/a_72_n41#" "as_cout" 2.1
cap "addsub_0/addsub_one_2/cout" "ry2" 10.71
cap "addsub_0/xor_3/a_61_n31#" "addsub_0/a3" 1.95
cap "as_cout" "addsub_0/addsub_one_3/b" 12.612
cap "addsub_0/addsub_one_2/cout" "as_cout" 11.644
cap "addsub_0/addsub_one_3/a_35_n41#" "addsub_0/addsub_one_3/GND!" -5.68434e-14
cap "addsub_0/addsub_one_3/cin" "as_cout" 7.536
cap "ry2" "addsub_0/addsub_one_3/GND!" 20.633
cap "ry2" "reg_0/reg_one_5/r0" 17.308
cap "ry2" "latch_2/Vdd!" 58.7
cap "ry2" "latch_2/latch_one_2/GND!" 110.895
cap "ry2" "addsub_0/addsub_one_3/cin" 1.486
cap "ry2" "latch_2/latch_one_2/c" 81.378
cap "reg_0/reg_one_4/w" "reg_0/port21" 127.744
cap "reg_0/port21" "reg_0/reg_one_5/r1" 5.304
cap "reg_0/port21" "reg_0/Vdd!" 58.7
cap "reg_0/port21" "reg_0/reg_one_5/w_n11_n27#" 121.694
cap "reg_0/reg_one_5/r0" "reg_0/port21" 23.94
cap "reg_0/r1" "reg_0/port21" 58.7
cap "reg_1/Vdd!" "reg_1/port21" 58.7
cap "reg_1/reg_one_5/w_n11_n27#" "reg_1/r1" 3.55271e-15
cap "reg_1/reg_one_5/r0" "reg_1/port21" 48.664
cap "reg_1/reg_one_5/w_n11_n27#" "reg_1/port21" 121.694
cap "reg_1/port21" "reg_1/r1" 58.7
cap "reg_1/reg_one_4/w" "reg_1/port21" 127.744
cap "reg_1/reg_one_5/r1" "reg_1/port21" 5.304
cap "reg_2/port21" "reg_2/r1" 58.7
cap "reg_2/port21" "reg_2/reg_one_5/r1" 5.304
cap "reg_2/port21" "reg_2/reg_one_4/w" 94.2122
cap "reg_2/port21" "reg_2/reg_one_5/w_n11_n27#" 121.694
cap "reg_2/port21" "reg_2/Vdd!" 58.7
cap "reg_2/reg_one_5/r0" "reg_2/port21" 48.664
cap "reg_2/r1" "reg_2/reg_one_5/w_n11_n27#" 3.55271e-15
cap "reg_3/port21" "reg_3/reg_one_5/w_n11_n27#" 1.628
cap "reg_3/r1" "reg_2/port21" 58.7
cap "reg_2/port21" "reg_3/port21" 73.199
cap "reg_2/port21" "reg_3/reg_one_5/r1" 5.304
cap "reg_2/port21" "reg_3/Vdd!" 58.7
cap "reg_2/port21" "reg_3/reg_one_5/r0" 48.664
cap "reg_3/port21" "reg_3/reg_one_4/w" 5.072
cap "reg_2/reg_one_4/w" "reg_2/port21" 33.5312
cap "reg_3/r1" "reg_3/reg_one_5/w_n11_n27#" 3.55271e-15
cap "reg_2/port21" "reg_3/reg_one_5/w_n11_n27#" 106.567
subcap "wz_addrL2" -695.199
subcap "PCL_w_muxout2" -419.208
cap "reg_3/port21" "reg_3/reg_one_5/w_n11_n27#" 12.7375
cap "reg_3/reg_one_5/w_n11_n27#" "reg_3/port21" -1.039
cap "mux_8bit_0/out2" "mux_8bit_0/mux_one_3/sel" 0.84
cap "mux_8bit_0/out2" "reg_3/port21" -10.01
cap "reg_3/port21" "mux_8bit_0/mux_one_3/Vdd!" 58.7
cap "reg_3/reg_one_4/w" "reg_3/port21" 127.744
cap "mux_8bit_0/out2" "mux_8bit_0/mux_one_2/inv2_2/GND!" 37.928
cap "reg_3/port21" "mux_8bit_0/mux_one_3/sel" 58.7
cap "reg_3/port21" "mux_8bit_0/mux_one_2/inv2_2/GND!" 63.013
cap "mux_8bit_0/out2" "mux_8bit_0/mux_one_2/inv2_1/GND!" 121.433
cap "mux_8bit_0/mux_one_3/GND!" "reg_4/reg_one_5/r0" 101.9
cap "ry2" "reg_4/Vdd!" 58.7
cap "mux_8bit_0/out2" "ry2" -17.369
cap "ry2" "reg_4/reg_one_5/w_n11_n27#" 106.567
cap "reg_4/port21" "reg_4/reg_one_4/w" 5.072
cap "reg_4/r1" "ry2" 58.7
cap "reg_4/port21" "ry2" 73.199
cap "mux_8bit_0/mux_one_3/GND!" "ry2" 58.7
cap "ry2" "reg_4/reg_one_5/r1" 5.304
cap "reg_4/reg_one_5/r0" "ry2" 48.664
cap "reg_4/port21" "reg_4/reg_one_5/w_n11_n27#" 1.628
cap "mux_8bit_0/out2" "mux_8bit_0/mux_one_3/GND!" 12.3
cap "mux_8bit_0/mux_one_2/inv2_1/GND!" "ry2" -6.916
cap "mux_8bit_0/out2" "reg_4/reg_one_5/r0" 111.843
subcap "rx_PCL3" -181.275
cap "addsub_1/addsub_one_3/Vdd!" "addsub_1/a3" 23.967
cap "reg_4/port21" "reg_4/reg_one_5/w_n11_n27#" -1.039
cap "addsub_1/xor_3/a_61_n1#" "addsub_1/a3" 76.2293
cap "reg_4/port21" "addsub_1/Vdd!" 11.825
cap "reg_4/port21" "addsub_1/xor_3/GND!" 11.825
cap "reg_4/port21" "addsub_1/sub" 11.825
cap "reg_4/reg_one_4/w" "reg_4/port21" 127.744
cap "addsub_1/Vdd!" "addsub_1/a3" 76.9567
cap "reg_4/port21" "reg_4/reg_one_5/w_n11_n27#" 12.7375
cap "addsub_1/xor_3/a_61_n31#" "addsub_1/a3" 1.95
cap "a_2510_1893#" "addsub_1/addsub_one_3/a_35_n41#" 10.65
cap "a_2510_1893#" "addsub_1/addsub_one_3/b" 12.612
cap "addsub_1/addsub_one_3/Vdd!" "ry2" -4.455
cap "ry2" "addsub_1/addsub_one_3/cin" 17.812
cap "a_2510_1893#" "addsub_1/addsub_one_3/a_72_n41#" 2.1
cap "a_2510_1893#" "addsub_1/addsub_one_3/GND!" 67.564
cap "a_2510_1893#" "addsub_1/a3" 12.612
cap "ry2" "addsub_1/addsub_one_2/Vdd!" 13.563
cap "a_2510_1893#" "addsub_1/addsub_one_3/a_66_n41#" 2.1
cap "ry2" "addsub_1/addsub_one_3/GND!" 48.35
cap "addsub_1/addsub_one_3/a_29_n41#" "a_2510_1893#" 2.1
cap "a_2510_1893#" "addsub_1/addsub_one_3/cin" 19.18
cap "a_2510_1893#" "addsub_1/addsub_one_3/a_11_n41#" 21.93
cap "staticizer_2/Vdd!" "latch_5/latch_one_2/c" 1073
cap "ry2" "staticizer_2/Vdd!" 58.7
cap "ry2" "latch_5/Vdd!" 58.7
cap "staticizer_2/staticizer_one_2/c" "ry2" 76.935
cap "latch_5/latch_one_2/GND!" "latch_5/latch_one_2/c" 13.8522
cap "ry2" "latch_5/latch_one_2/c" 81.378
cap "ry2" "latch_5/latch_one_2/GND!" 181.284
subcap "wz_addrH2" -1023.43
subcap "m1_1909_1422#" -419.208
cap "ry2" "staticizer_2/staticizer_one_2/w_54_n57#" 4.329
cap "ry2" "mux_8bit_1/mux_one_3/Vdd!" 58.7
cap "ry2" "mux_8bit_1/out2" -10.01
cap "ry2" "mux_8bit_1/mux_one_2/inv2_2/GND!" 63.013
cap "staticizer_2/staticizer_one_2/c" "staticizer_2/staticizer_one_2/w_54_n57#" -3.55271e-15
cap "ry2" "mux_8bit_1/mux_one_3/sel" 58.7
cap "mux_8bit_1/out2" "mux_8bit_1/mux_one_2/inv2_2/GND!" 37.928
cap "mux_8bit_1/mux_one_3/sel" "mux_8bit_1/out2" 0.84
cap "reg_5/reg_one_5/w_n11_n27#" "ry2" 106.567
cap "reg_5/Vdd!" "ry2" 58.7
cap "mux_8bit_1/out2" "ry2" -17.369
cap "ry2" "reg_5/r1" 58.7
cap "mux_8bit_1/out2" "mux_8bit_1/mux_one_2/inv2_1/GND!" 121.433
cap "reg_5/port21" "ry2" 73.199
cap "reg_5/reg_one_4/w" "reg_5/port21" 5.072
cap "mux_8bit_1/mux_one_2/inv2_1/GND!" "ry2" -6.916
cap "reg_5/reg_one_5/r0" "mux_8bit_1/mux_one_3/GND!" 101.9
cap "mux_8bit_1/out2" "reg_5/reg_one_5/r0" 111.843
cap "mux_8bit_1/out2" "mux_8bit_1/mux_one_3/GND!" 12.3
cap "reg_5/reg_one_5/r1" "ry2" 5.304
cap "reg_5/reg_one_5/w_n11_n27#" "reg_5/port21" 1.628
cap "ry2" "mux_8bit_1/mux_one_3/GND!" 58.7
cap "reg_5/reg_one_5/r0" "ry2" 48.664
cap "reg_5/port21" "reg_6/reg_one_5/r0" 19.78
cap "reg_5/port21" "ry2" -17.146
cap "reg_5/port21" "reg_6/Vdd!" 58.7
cap "reg_5/reg_one_5/w_n11_n27#" "ry2" -2.667
cap "reg_6/reg_one_5/port1" "ry2" 68.579
cap "reg_5/port21" "reg_6/r1" 58.7
cap "reg_5/port21" "reg_5/reg_one_5/w_n11_n27#" 12.7375
cap "reg_6/reg_one_5/w_n11_n27#" "ry2" 101.233
cap "reg_6/reg_one_5/r1" "ry2" 5.304
cap "reg_6/reg_one_5/r0" "ry2" 48.664
cap "reg_5/reg_one_4/w_n11_n27#" "reg_5/reg_one_4/w" 1.42109e-14
cap "reg_5/port21" "reg_5/reg_one_4/w" 69.0435
cap "ry2" "reg_6/Vdd!" 58.7
cap "reg_6/reg_one_5/w_n11_n27#" "reg_6/r1" 3.55271e-15
cap "reg_6/r1" "ry2" 58.7
cap "reg_5/reg_one_5/w_n11_n27#" "reg_5/port21" 1.628
cap "reg_5/reg_one_4/w" "ry2" 58.7
cap "reg_5/port21" "reg_6/reg_one_5/w_n11_n27#" 83.267
subcap "m1_2132_1435#" -57.262
subcap "m1_2209_1422#" -419.208
cap "reg_6/port21" "reg_6/reg_one_5/w_n11_n27#" 4.295
cap "mux_8bit_2/out2" "reg_6/port21" -10.01
cap "ry_addrH2" "reg_6/reg_one_5/w_n11_n27#" 0.019
cap "reg_6/reg_one_4/w" "reg_6/reg_one_4/w_n11_n27#" 2.84217e-14
cap "mux_8bit_2/mux_one_3/Vdd!" "reg_6/port21" 58.7
cap "reg_6/port21" "mux_8bit_2/mux_one_2/inv2_2/GND!" 63.013
cap "ry_addrH2" "mux_8bit_2/mux_one_3/Vdd!" 58.7
cap "mux_8bit_2/out2" "mux_8bit_2/mux_one_2/inv2_2/GND!" 37.928
cap "reg_6/reg_one_5/w_n11_n27#" "reg_6/port21" 12.7375
cap "reg_6/reg_one_4/w" "reg_6/port21" 127.744
cap "reg_6/port21" "mux_8bit_2/mux_one_3/sel" 58.7
cap "ry_addrH2" "reg_6/reg_one_4/w" 58.7
cap "ry_addrH2" "mux_8bit_2/mux_one_3/sel" 58.7
cap "mux_8bit_2/out2" "mux_8bit_2/mux_one_3/sel" 0.84
cap "reg_7/Vdd!" "ry_addrH2" 58.7
cap "mux_8bit_2/mux_one_3/GND!" "ry2" 58.7
cap "reg_7/port21" "reg_7/reg_one_5/w_n11_n27#" 1.628
cap "reg_7/reg_one_5/r0" "ry_addrH2" 19.78
cap "ry2" "reg_7/Vdd!" 58.7
cap "reg_7/reg_one_5/r0" "mux_8bit_2/out2" 111.843
cap "reg_7/reg_one_4/w" "reg_7/port21" 5.072
cap "ry2" "reg_7/reg_one_5/r0" 48.664
cap "reg_7/reg_one_5/w_n11_n27#" "ry_addrH2" 86.284
cap "reg_7/r1" "ry_addrH2" 58.7
cap "mux_8bit_2/mux_one_3/GND!" "reg_7/reg_one_5/r0" 101.9
cap "ry2" "reg_7/reg_one_5/w_n11_n27#" 106.567
cap "reg_7/r1" "ry2" 58.7
cap "mux_8bit_2/out2" "mux_8bit_2/mux_one_2/inv2_1/GND!" 121.433
cap "ry2" "mux_8bit_2/mux_one_2/inv2_1/GND!" -6.916
cap "ry2" "reg_7/port21" 73.199
cap "ry2" "mux_8bit_2/out2" -17.369
cap "ry2" "reg_7/reg_one_5/r1" 5.304
cap "mux_8bit_2/mux_one_3/GND!" "ry_addrH2" 58.7
cap "mux_8bit_2/mux_one_3/GND!" "mux_8bit_2/out2" 12.3
subcap "rx_addrH3" -560.447
cap "reg_7/reg_one_5/w_n11_n27#" "reg_7/port21" 12.7375
cap "ry2" "reg_7/port21" -17.146
cap "reg_7/reg_one_4/w" "reg_7/port21" 127.744
cap "addsub_2/xor_3/a_61_n31#" "addsub_2/a3" 1.95
cap "addsub_2/Vdd!" "reg_7/port21" 11.825
cap "addsub_2/xor_3/a_61_n1#" "addsub_2/a3" 76.2293
cap "addsub_2/a3" "addsub_2/addsub_one_3/Vdd!" 23.967
cap "addsub_2/xor_3/GND!" "reg_7/port21" 11.825
cap "reg_7/reg_one_4/w" "ry2" 58.7
cap "ry2" "addsub_2/Vdd!" 11.825
cap "reg_7/reg_one_5/w_n11_n27#" "reg_7/port21" -1.37
cap "addsub_2/a3" "addsub_2/Vdd!" 76.9567
cap "addsub_2/sub" "reg_7/port21" 11.825
cap "ry2" "addsub_2/xor_3/GND!" 11.825
cap "ry2" "reg_7/reg_one_5/w_n11_n27#" -2.667
cap "ry2" "addsub_2/sub" 11.825
cap "ry_addrH2" "addsub_2/addsub_one_3/cin" 2.474
cap "ry_addrH2" "addsub_2/addsub_one_3/GND!" 45.221
cap "addsub_2/addsub_one_3/cin" "ry2" 19.952
cap "ry2" "addsub_2/addsub_one_2/Vdd!" 13.563
cap "ry2" "addsub_2/addsub_one_3/GND!" 52.91
cap "ry_addrH2" "addsub_2/addsub_one_3/Vdd!" -4.455
cap "addsub_2/addsub_one_3/Vdd!" "ry2" -4.455
cap "latch_6/Vdd!" "ry_addrH2" 58.7
cap "latch_6/latch_one_2/c" "ry_addrH2" 58.7
cap "staticizer_3/Vdd!" "latch_6/latch_one_2/c" 1073
cap "staticizer_3/Vdd!" "ry2" 58.7
cap "staticizer_3/Vdd!" "ry_addrH2" 58.7
cap "staticizer_3/staticizer_one_2/c" "ry2" 76.935
cap "latch_6/latch_one_2/GND!" "latch_6/latch_one_2/c" 13.8522
cap "latch_6/latch_one_2/GND!" "ry2" 181.284
cap "latch_6/Vdd!" "ry2" 58.7
cap "staticizer_3/staticizer_one_2/c" "ry_addrH2" 58.7
cap "latch_6/latch_one_2/GND!" "ry_addrH2" 117.4
cap "ry2" "latch_6/latch_one_2/c" 81.378
cap "ry_addrH2" "latch_7/latch_one_2/c" 58.7
cap "latch_7/Vdd!" "ry2" 98.3583
cap "latch_7/Vdd!" "ry_addrH2" 58.7
cap "ry2" "staticizer_3/staticizer_one_2/w_54_n57#" 6.253
cap "staticizer_4/Vdd!" "ry_addrH2" 58.7
cap "latch_7/latch_one_2/GND!" "ry_addrH2" 77.41
cap "staticizer_4/Vdd!" "latch_7/latch_one_2/c" 1073
cap "latch_7/latch_one_2/GND!" "latch_7/latch_one_2/c" 13.8522
cap "latch_8/Vdd!" "ry_addrH2" 178.833
cap "staticizer_4/staticizer_one_2/c" "ry_addrH2" 58.7
cap "staticizer_4/staticizer_one_2/w_54_n57#" "ry_addrH2" 9.386
cap "latch_8/latch_one_2/c" "staticizer_5/Vdd!" 1073
cap "latch_8/latch_one_2/c" "staticizer_5/staticizer_one_2/w_54_n57#" 13.8522
cap "staticizer_1/staticizer_one_2/w_54_n57#" "latch_4/latch_one_2/c" -1.42109e-14
cap "staticizer_1/staticizer_one_2/Vdd!" "staticizer_1/in2" 73.946
cap "staticizer_1/staticizer_one_2/Vdd!" "latch_4/latch_one_2/c" 1073
cap "staticizer_1/staticizer_one_2/a_60_n45#" "staticizer_1/in2" 57.7175
cap "staticizer_1/staticizer_one_2/Vdd!" "latch_4/latch_one_2/a_12_n54#" -7.10543e-15
cap "latch_4/latch_one_2/c" "staticizer_1/in2" 0.492
cap "staticizer_1/staticizer_one_2/a_60_n45#" "staticizer_1/staticizer_one_2/Vdd!" -2.27374e-13
cap "staticizer_1/staticizer_one_2/w_54_n57#" "staticizer_1/in2" 18.828
subcap "a_109_1448#" -129.844
subcap "data_in2" -6.948
subcap "rx2" -1843.97
cap "latch_0/latch_one_2/GND!" "latch_0/latch_one_2/a_n5_n54#" 5.68434e-14
cap "latch_0/out2" "staticizer_0/staticizer_one_2/a_60_n45#" 57.7175
cap "latch_0/latch_one_2/GND!" "latch_0/latch_one_2/c" 1.13687e-13
cap "latch_0/in2" "latch_0/latch_one_2/a_n5_n54#" 32.9814
cap "latch_4/latch_one_2/a_n5_n54#" "latch_4/in2" 69.3743
cap "latch_0/latch_one_2/c" "latch_0/out2" 0.492
cap "latch_0/latch_one_2/Vdd!" "latch_0/latch_one_2/GND!" 2.27374e-13
cap "latch_0/latch_one_2/Vdd!" "latch_0/latch_one_2/a_12_n54#" -1.13687e-13
cap "latch_0/latch_one_2/Vdd!" "staticizer_0/staticizer_one_2/a_60_n45#" -4.648
cap "latch_0/latch_one_2/Vdd!" "latch_0/in2" 67.0625
cap "latch_0/latch_one_2/Vdd!" "latch_0/out2" 73.946
cap "latch_4/latch_one_2/Vdd!" "latch_4/in2" 281.662
cap "latch_0/latch_one_2/Vdd!" "latch_0/latch_one_2/a_n5_n54#" 1.13687e-13
cap "latch_0/latch_one_2/Vdd!" "latch_0/latch_one_2/c" 1073
cap "latch_0/latch_one_2/GND!" "latch_0/out2" 18.828
subcap "wz2" -2641.37
cap "shift_0/a2" "latch_0/out2" 58.7
cap "staticizer_0/staticizer_one_2/a_77_n45#" "staticizer_0/staticizer_one_2/Vdd!" 1.13687e-13
cap "staticizer_0/staticizer_one_2/w_54_n57#" "latch_0/out2" 6.22
cap "staticizer_0/staticizer_one_2/w_54_n57#" "staticizer_0/c" 1.77636e-15
cap "latch_0/out2" "staticizer_0/staticizer_one_2/Vdd!" 35.6
cap "latch_0/out2" "staticizer_0/staticizer_one_2/a_60_n45#" 31.249
cap "latch_0/out2" "shift_0/shift_one_2/ad" 58.7
cap "shift_0/shift_one_2/Vdd!" "latch_0/out2" 8.24
cap "staticizer_0/staticizer_one_2/Vdd!" "staticizer_0/staticizer_one_2/a_60_n45#" -2.744
cap "wz2" "shift_0/shift_one_2/inv_2/out" 25.522
cap "wz2" "shift_0/GND!" 58.7
cap "wz2" "shift_0/u" 58.7
cap "wz2" "shift_0/Vdd!" 58.7
cap "wz2" "shift_0/shift_one_2/Vdd!" 91.858
cap "wz2" "shift_0/shift_one_2/inv_2/GND!" 21.418
cap "wz2" "shift_0/shift_one_2/m1_n60_n65#" 11.825
subcap "a_373_1444#" -134.744
cap "latch_3/latch_one_2/GND!" "wz2" 7.989
cap "wz2" "shift_0/shift_one_2/inv_3/GND!" 3.152
cap "wz2" "shift_0/shift_one_2/s" 58.7
cap "wz2" "latch_3/latch_one_2/a_n5_n54#" 30.853
cap "latch_3/latch_one_2/GND!" "latch_3/in2" 6.956
cap "latch_3/latch_one_2/Vdd!" "latch_3/latch_one_2/a_n5_n54#" -2.27374e-13
cap "wz2" "latch_3/GND!" 58.7
cap "wz2" "latch_3/latch_one_2/a_12_n54#" 4.95
cap "shift_0/shift_one_2/2mux_nr_1/Vdd!" "wz2" 72.651
cap "wz2" "latch_3/latch_one_2/Vdd!" 64.715
cap "latch_3/in2" "latch_3/latch_one_2/a_n5_n54#" 57.7175
cap "wz2" "shift_0/shift_one_2/2mux_nr_1/out" 8.599
cap "shift_0/shift_one_2/2mux_nr_1/out" "latch_3/latch_one_2/Vdd!" 46.174
cap "wz2" "latch_3/in2" 2.184
cap "latch_3/in2" "latch_3/latch_one_2/Vdd!" 9.594
cap "wz2" "latch_3/latch_one_2/c" 1.248
cap "latch_3/in2" "shift_0/shift_one_2/2mux_nr_1/out" 57.7175
cap "fblock_0/g2" "latch_3/out2" 58.7
cap "fblock_0/fblock_one_2/2mux_nr_2/in0" "latch_3/out2" 7.975
cap "fblock_0/a2" "fblock_0/fblock_one_2/2mux_nr_2/a_n17_n11#" 11.004
cap "fblock_0/fblock_one_2/2mux_nr_0/out" "fblock_0/b2" 11.825
cap "latch_3/latch_one_2/Vdd!" "latch_3/out2" 0.959
cap "fblock_0/fblock_one_2/2mux_nr_2/a_n17_n11#" "latch_3/out2" 14.683
cap "fblock_0/g2" "fblock_0/b2" 58.7
cap "fblock_0/a2" "fblock_0/g3" 355.024
cap "latch_3/latch_one_2/GND!" "latch_3/out2" 1.209
cap "fblock_0/a2" "fblock_0/fblock_one_2/inv_0/in" 9.081
cap "fblock_0/g3" "latch_3/out2" 58.7
cap "fblock_0/fblock_one_2/inv_0/in" "latch_3/out2" 19.302
cap "fblock_0/fblock_one_2/2mux_nr_2/Vdd!" "fblock_0/a2" 82.685
cap "fblock_0/a2" "fblock_0/fblock_one_2/inv_0/GND!" 115.687
cap "latch_3/latch_one_2/a_12_n54#" "latch_3/latch_one_2/Vdd!" 2.84217e-14
cap "fblock_0/g3" "fblock_0/b2" 140.424
cap "fblock_0/b2" "fblock_0/fblock_one_2/2mux_nr_0/a_n17_n11#" 33.597
cap "fblock_0/fblock_one_2/inv_0/GND!" "latch_3/out2" 97.023
cap "fblock_0/fblock_one_2/2mux_nr_0/in0" "fblock_0/b2" 7.975
cap "fblock_0/b2" "fblock_0/fblock_one_2/2mux_nr_1/Vdd!" 11.239
cap "fblock_0/fblock_one_2/2mux_nr_0/in1" "fblock_0/b2" 4.95
cap "fblock_0/fblock_one_2/2mux_nr_0/out" "fblock_0/a2" 5.115
cap "fblock_0/a2" "fblock_0/fblock_one_2/2mux_nr_2/in0" 4.389
cap "fblock_0/a2" "latch_3/out2" 4.948
cap "fblock_0/a2" "fblock_0/g2" 58.7
cap "fblock_0/fblock_one_2/2mux_nr_0/out" "latch_3/out2" 9.35
cap "latch_3/out2" "latch_3/latch_one_2/c" 140.424
cap "fblock_0/fblock_one_2/inv_0/GND!" "fblock_0/b2" 68.584
cap "ry2" "fblock_0/Vdd!" 58.7
cap "ry2" "fblock_0/fblock_one_2/2mux_nr_1/GND!" 24.128
cap "wz2" "latch_1/latch_one_2/a_n5_n54#" 43.4
cap "ry2" "fblock_0/fblock_one_2/2mux_nr_1/out" 11.825
cap "wz2" "fblock_0/fblock_one_2/inv_0/in" 4.123
cap "latch_1/latch_one_2/Vdd!" "wz2" 58.7
cap "latch_1/latch_one_2/Vdd!" "rx2" 103.828
cap "latch_1/latch_one_2/a_n5_n54#" "rx2" 7.807
cap "wz2" "fblock_0/f2" 18.093
cap "fblock_0/fblock_one_2/inv_0/in" "rx2" 2.844
cap "latch_1/latch_one_2/GND!" "fblock_0/f2" 12.326
cap "wz2" "fblock_0/g1" 58.7
cap "fblock_0/fblock_one_2/f" "rx2" 85.724
cap "rx2" "fblock_0/f2" 13.492
cap "latch_1/latch_one_2/Vdd!" "ry2" 58.7
cap "fblock_0/g1" "rx2" 58.7
cap "ry2" "fblock_0/fblock_one_2/f" 25.152
cap "fblock_0/g1" "ry2" 58.7
cap "wz2" "latch_1/latch_one_2/c" 4.324
cap "wz2" "latch_1/latch_one_2/GND!" 11.042
cap "wz2" "fblock_0/fblock_one_2/inv_0/GND!" 20.977
cap "ry2" "fblock_0/fblock_one_2/2mux_nr_1/in1" 4.95
cap "wz2" "latch_1/latch_one_2/a_12_n54#" 9.731
cap "ry2" "fblock_0/fblock_one_2/2mux_nr_1/in0" 2.75
cap "ry2" "fblock_0/fblock_one_2/2mux_nr_1/a_n17_n11#" 31.949
cap "latch_1/latch_one_2/Vdd!" "fblock_0/Vdd!" 1341.25
cap "fblock_0/Vdd!" "fblock_0/f2" 12.684
cap "ry2" "fblock_0/fblock_one_2/2mux_nr_1/s" 16.386
cap "wz2" "fblock_0/g0" 58.7
cap "wz2" "latch_1/GND!" 58.7
cap "rx2" "fblock_0/g0" 58.7
cap "latch_1/latch_one_2/a_n5_n54#" "fblock_0/f2" 57.7175
cap "latch_1/GND!" "rx2" 58.7
cap "latch_1/latch_one_2/Vdd!" "fblock_0/f2" 6.108
cap "wz2" "fblock_0/Vdd!" 58.7
cap "ry2" "fblock_0/g0" 58.7
cap "ry2" "latch_1/GND!" 58.7
cap "fblock_0/Vdd!" "rx2" 58.7
subcap "ry2" -2492.66
cap "latch_1/latch_one_2/c" "addsub_0/b2" 58.7
cap "latch_1/out2" "latch_1/latch_one_2/a_30_n54#" 1.524
cap "latch_1/out2" "latch_1/latch_one_2/Vdd!" 1.221
cap "latch_1/latch_one_2/Vdd!" "rx2" -4.367
cap "latch_1/out2" "addsub_0/xor_2/b" 11.825
cap "addsub_0/b2" "addsub_0/xor_2/GND!" 173.474
cap "latch_1/latch_one_2/c" "latch_1/out2" 144.632
cap "addsub_0/xor_2/Vdd!" "rx2" 8.496
cap "latch_1/out2" "addsub_0/xor_2/GND!" 11.825
cap "addsub_0/xor_2/a_61_n31#" "addsub_0/b2" 7.218
cap "addsub_0/xor_2/a_89_n31#" "addsub_0/b2" 3.068
cap "latch_1/out2" "latch_1/latch_one_2/GND!" 3.821
cap "latch_1/latch_one_2/a_n5_n54#" "rx2" 4.948
cap "addsub_0/xor_2/out" "addsub_0/b2" 31.486
cap "latch_1/latch_one_2/Vdd!" "rx2" -1.405
cap "rx2" "addsub_0/xor_2/b" 11.825
cap "latch_1/latch_one_2/a_30_n35#" "rx2" 4.828
cap "addsub_0/b2" "rx2" 2.764
cap "latch_1/latch_one_2/c" "rx2" 58.7
cap "addsub_0/b2" "addsub_0/xor_2/a_69_n42#" 2.457
cap "rx2" "addsub_0/xor_2/GND!" 24.038
cap "latch_1/out2" "latch_1/latch_one_2/a_n5_n54#" 15.975
cap "addsub_0/b2" "addsub_0/xor_2/b" 15.993
cap "latch_1/latch_one_2/GND!" "latch_1/out2" 2.361
cap "rx2" "latch_1/latch_one_2/a_12_n54#" 4.948
cap "addsub_0/b2" "addsub_0/xor_2/a_100_n42#" 0.707
cap "latch_1/out2" "rx2" 9.182
cap "addsub_0/addsub_one_2/a_78_n41#" "as_cout" 15.064
cap "addsub_0/addsub_one_2/GND!" "as_cout" 44.7
cap "wz2" "addsub_0/addsub_one_2/Vdd!" 50.747
cap "addsub_0/addsub_one_2/a_72_n41#" "as_cout" 2.1
cap "addsub_0/addsub_one_2/cout" "as_cout" 6.885
cap "wz2" "addsub_0/addsub_one_2/a_35_n41#" 65.763
cap "wz2" "addsub_0/addsub_one_2/GND!" 18.211
cap "addsub_0/addsub_one_2/cin" "as_cout" 8.408
cap "addsub_0/xor_2/a_61_n31#" "addsub_0/a2" 2.424
cap "addsub_0/addsub_one_2/b" "as_cout" 12.612
cap "addsub_0/a2" "addsub_0/addsub_one_2/a_78_n41#" 11.825
cap "addsub_0/addsub_one_2/a_35_n41#" "as_cout" 8.408
cap "addsub_0/addsub_one_2/GND!" "addsub_0/a2" -0.341
cap "addsub_0/a2" "addsub_0/xor_2/a_61_n1#" 141.539
cap "addsub_0/addsub_one_2/GND!" "as_cout" 30.19
cap "addsub_0/a2" "as_cout" 8.408
cap "as_cout" "addsub_0/addsub_one_2/a_66_n41#" 2.1
cap "as_cout" "addsub_0/addsub_one_2/a_89_n41#" 22.875
cap "addsub_0/addsub_one_2/s" "as_cout" 41.11
cap "addsub_0/xor_2/b" "addsub_0/a2" 2.424
cap "addsub_0/addsub_one_2/b" "addsub_0/a2" 94.487
cap "addsub_0/a2" "addsub_0/addsub_one_2/Vdd!" 189.896
cap "addsub_0/addsub_one_2/GND!" "addsub_0/addsub_one_2/a_35_n41#" 2.27374e-13
cap "addsub_0/addsub_one_2/GND!" "wz2" 0.308
cap "addsub_0/a2" "addsub_0/addsub_one_2/a_35_n41#" 19.78
cap "addsub_0/xor_2/a" "addsub_0/a2" 2.424
cap "addsub_0/addsub_one_2/GND!" "addsub_0/a2" 20.114
cap "addsub_0/addsub_one_2/a_89_9#" "addsub_0/a2" 4.7
cap "addsub_0/a2" "addsub_0/xor_2/a_89_n31#" 2.424
subcap "a_841_1449#" -43.082
cap "latch_2/latch_one_2/a_n5_n54#" "addsub_0/s2" 57.7175
cap "addsub_0/s2" "rx2" 3.468
cap "latch_2/latch_one_2/a_12_n54#" "rx2" 37.778
cap "addsub_0/addsub_one_2/GND!" "rx2" 5.148
cap "rx2" "addsub_0/addsub_one_2/GND!" 7.942
cap "latch_2/latch_one_2/Vdd!" "latch_2/out2" 59.921
cap "latch_2/latch_one_2/GND!" "latch_2/out2" 90.233
cap "latch_2/out2" "latch_2/latch_one_2/c" 727.057
cap "addsub_0/GND!" "addsub_0/s2" 76.9567
cap "reg_0/reg_one_5/r0" "latch_2/out2" 217.183
cap "addsub_0/addsub_one_2/a_35_n41#" "latch_2/out2" -1.814
cap "latch_2/latch_one_2/a_n5_n54#" "latch_2/out2" 12.196
cap "rx2" "latch_2/out2" 4.341
cap "latch_2/latch_one_2/Vdd!" "rx2" 116.636
cap "latch_2/latch_one_2/GND!" "rx2" 58.7
cap "rx2" "latch_2/latch_one_2/c" 61.544
cap "reg_0/reg_one_5/r0" "rx2" 19.78
cap "latch_2/latch_one_2/a_30_n54#" "latch_2/out2" 2.592
cap "addsub_0/GND!" "latch_2/out2" 11.825
cap "latch_2/latch_one_2/a_n5_n54#" "rx2" 6.195
cap "addsub_0/addsub_one_2/b" "rx2" -2.068
cap "latch_2/latch_one_2/a_12_n54#" "latch_2/out2" 12.473
cap "addsub_0/s2" "latch_2/out2" 4.948
cap "latch_2/latch_one_2/Vdd!" "addsub_0/s2" 19.399
cap "addsub_0/addsub_one_2/GND!" "latch_2/out2" 7.422
cap "latch_2/out2" "addsub_0/addsub_one_2/GND!" 3.399
cap "addsub_0/GND!" "rx2" 11.825
cap "rx2" "latch_2/latch_one_2/a_30_n35#" 1.524
cap "reg_0/reg_one_5/w" "wz2" 4.382
cap "reg_0/w" "reg_0/port20" 434.25
cap "reg_0/w" "wz2" 58.7
cap "reg_0/port20" "reg_0/reg_one_5/a_4_n13#" 20.417
cap "reg_0/reg_one_5/r0" "reg_0/in2" -5.072
cap "reg_0/port20" "reg_0/reg_one_5/r1" 70.642
cap "wz2" "reg_0/reg_one_5/r1" 58.7
cap "wz2" "reg_1/reg_one_5/r0" 63.6875
cap "reg_0/reg_one_5/Vdd!" "reg_0/port20" 134.044
cap "reg_0/reg_one_5/Vdd!" "wz2" 165.083
cap "reg_0/port20" "reg_0/reg_one_5/tmp" 4.948
cap "wz2" "reg_0/reg_one_5/tmp" 4.324
cap "reg_0/port20" "reg_0/reg_one_5/w_n11_n27#" 194.315
cap "wz2" "reg_0/reg_one_5/w_n11_n27#" 66.94
cap "wz2" "reg_0/reg_one_5/a_33_32#" 65.474
cap "wz2" "reg_0/in2" 14.786
cap "reg_0/port20" "reg_0/reg_one_5/a_21_n13#" 20.118
cap "reg_0/reg_one_5/tmp" "wz2" 4.389
cap "reg_0/port21" "reg_0/reg_one_5/w_n11_n27#" 4.24583
cap "reg_0/reg_one_5/a_16_27#" "wz2" 8.264
cap "reg_0/reg_one_5/r0" "reg_0/port20" -7.416
cap "reg_0/reg_one_5/r0" "wz2" -7.416
cap "reg_1/reg_one_5/tmp" "reg_1/in2" 4.324
cap "reg_1/reg_one_5/a_16_27#" "reg_1/in2" 8.264
cap "reg_1/reg_one_5/tmp" "reg_1/in2" 4.389
cap "reg_1/reg_one_5/r0" "reg_1/in2" 89.8075
cap "reg_1/reg_one_5/w" "reg_1/in2" 4.382
cap "reg_1/reg_one_5/r1" "reg_1/port20" 60.064
cap "reg_1/w" "reg_1/port20" 125.763
cap "reg_1/reg_one_5/w_n11_n27#" "reg_1/port20" 198.775
cap "reg_1/reg_one_5/Vdd!" "reg_1/port20" 75.185
cap "reg_1/reg_one_5/tmp" "reg_1/port20" 4.694
cap "reg_1/port21" "reg_1/reg_one_5/w_n11_n27#" 4.24583
cap "reg_1/reg_one_5/a_21_n13#" "reg_1/port20" 2.238
cap "reg_1/port20" "reg_1/reg_one_5/port1" 3.85
cap "reg_1/reg_one_5/a_33_32#" "reg_1/in2" 65.474
cap "reg_1/reg_one_5/r0" "reg_1/port20" 21.144
cap "reg_1/reg_one_5/r1" "reg_1/in2" 58.7
cap "reg_1/reg_one_5/a_4_n13#" "reg_1/port20" 118.494
cap "reg_1/w" "reg_1/in2" 58.7
cap "reg_1/reg_one_5/w_n11_n27#" "reg_1/in2" 66.94
cap "reg_1/reg_one_5/Vdd!" "reg_1/in2" 165.083
cap "reg_1/port20" "reg_2/reg_one_5/w_n11_n27#" 135.088
cap "reg_1/port20" "reg_2/reg_one_5/port1" 3.85
cap "reg_2/in2" "reg_2/reg_one_5/r1" 58.7
cap "reg_1/port20" "reg_2/reg_one_5/a_4_n13#" 118.494
cap "reg_1/port20" "reg_2/reg_one_5/tmp" 4.694
cap "reg_2/in2" "reg_2/reg_one_5/Vdd!" 165.083
cap "reg_1/port20" "reg_2/reg_one_5/a_21_n13#" 2.238
cap "reg_1/port20" "reg_2/reg_one_5/r0" 21.144
cap "reg_2/in2" "reg_2/w" 58.7
cap "reg_2/in2" "reg_2/reg_one_5/tmp" 4.389
cap "reg_2/in2" "reg_2/reg_one_5/w_n11_n27#" 66.94
cap "reg_1/port20" "reg_2/reg_one_5/Vdd!" 75.185
cap "reg_1/port20" "reg_2/reg_one_5/r1" 60.064
cap "reg_2/in2" "reg_2/reg_one_5/tmp" 4.324
cap "reg_2/in2" "reg_2/reg_one_5/r0" 153.495
cap "reg_2/in2" "reg_2/reg_one_5/a_16_27#" 8.264
cap "reg_2/reg_one_5/w_n11_n27#" "reg_2/port21" 4.24583
cap "reg_2/in2" "reg_2/reg_one_5/a_33_32#" 65.474
cap "reg_1/port20" "reg_2/w" 92.2312
cap "reg_2/in2" "reg_2/reg_one_5/w" 4.382
cap "reg_3/reg_one_5/a_21_n13#" "reg_2/port20" 2.238
cap "reg_3/reg_one_5/r1" "reg_2/port20" 60.064
cap "reg_2/w" "reg_2/port20" 33.5312
cap "reg_3/in2" "reg_3/reg_one_5/w_n11_n27#" 17.302
cap "reg_3/in2" "reg_3/reg_one_5/a_16_27#" 7.446
cap "reg_3/reg_one_5/Vdd!" "reg_2/port20" 74.654
cap "reg_2/port20" "reg_3/reg_one_5/port1" 3.85
cap "reg_3/reg_one_5/r1" "reg_3/in2" 58.7
cap "reg_2/port20" "reg_3/reg_one_5/r0" 21.144
cap "reg_3/reg_one_5/a_4_n13#" "reg_2/port20" 118.494
cap "reg_3/in2" "reg_3/reg_one_5/r0" 153.495
cap "reg_3/in2" "reg_3/reg_one_5/Vdd!" 75.24
cap "reg_3/reg_one_5/tmp" "reg_2/port20" 4.694
cap "reg_3/reg_one_5/tmp" "reg_3/in2" 6.6
cap "reg_2/port20" "reg_3/reg_one_5/w_n11_n27#" 63.11
cap "reg_2/port20" "reg_2/reg_one_5/w_n11_n27#" 63.6875
cap "reg_3/in2" "reg_3/reg_one_5/w" 1.248
cap "reg_3/in2" "reg_3/reg_one_5/tmp" 1.248
cap "reg_3/in2" "reg_3/reg_one_5/a_33_32#" 39.098
cap "reg_3/in2" "reg_3/reg_one_5/w_n11_n27#" 58.7
cap "reg_3/port20" "reg_2/port20" 8.58
subcap "wz_addrL2" -534.75
cap "reg_3/reg_one_5/w_n11_n27#" "reg_3/port21" 4.24583
cap "mux_8bit_0/mux_one_2/inv2_1/a_1_8#" "mux_8bit_0/in0_2" 19.462
cap "reg_3/reg_one_5/w_n11_n27#" "reg_3/port20" 135.615
cap "mux_8bit_0/in1_2" "mux_8bit_0/mux_one_2/2mux_nr_0/a_n17_n11#" 36.092
cap "mux_8bit_0/in0_2" "mux_8bit_0/mux_one_2/Vdd!" 78.896
cap "reg_3/reg_one_5/w" "reg_3/port20" 125.763
cap "mux_8bit_0/in1_2" "reg_3/reg_one_5/w_n11_n27#" 8.24
cap "mux_8bit_0/mux_one_2/2mux_nr_0/in1" "mux_8bit_0/mux_one_2/GND!" 1.42109e-14
cap "reg_3/reg_one_5/Vdd!" "reg_3/port20" -2.898
cap "mux_8bit_0/in1_2" "reg_3/reg_one_5/w" 58.7
cap "mux_8bit_0/in1_2" "mux_8bit_0/mux_one_2/2mux_nr_0/in1" 18.535
cap "mux_8bit_0/in1_2" "reg_3/reg_one_5/Vdd!" -2.948
cap "mux_8bit_0/in1_2" "mux_8bit_0/mux_one_2/GND!" 15.908
cap "reg_3/reg_one_5/w_n11_n27#" "reg_3/reg_one_5/w" 1.42109e-14
cap "mux_8bit_0/in1_2" "mux_8bit_0/mux_one_2/sel" 63.256
cap "mux_8bit_0/in1_2" "reg_3/reg_one_5/w_n11_n27#" -2.948
cap "reg_3/reg_one_5/a_33_32#" "mux_8bit_0/in1_2" -4.455
cap "mux_8bit_0/in0_2" "mux_8bit_0/out2" 30.603
cap "reg_3/port20" "reg_3/reg_one_5/w_n11_n27#" -3.379
cap "mux_8bit_0/in0_2" "mux_8bit_0/mux_one_2/2mux_nr_0/in0" 29.025
cap "mux_8bit_0/in0_2" "mux_8bit_0/mux_one_2/GND!" 12.279
cap "mux_8bit_0/in1_2" "mux_8bit_0/mux_one_2/Vdd!" 98.617
cap "mux_8bit_0/in0_2" "mux_8bit_0/mux_one_2/sel" 58.7
cap "reg_4/reg_one_5/Vdd!" "mux_8bit_0/out2" 56.544
cap "wz_addrL2" "reg_4/reg_one_5/r0" 21.028
cap "reg_4/reg_one_5/w" "wz2" 5.064
cap "reg_4/reg_one_5/w_n11_n27#" "wz2" 192.228
cap "wz_addrL2" "reg_4/reg_one_5/r1" 59.948
cap "reg_4/reg_one_5/tmp" "wz_addrL2" 4.68
cap "reg_4/reg_one_5/a_33_32#" "wz2" 7.959
cap "wz_addrL2" "mux_8bit_0/out2" -6.325
cap "reg_4/reg_one_5/r0" "wz2" 19.78
cap "wz_addrL2" "mux_8bit_0/mux_one_2/GND!" 65.42
cap "mux_8bit_0/mux_one_2/2mux_nr_0/out" "mux_8bit_0/out2" 85.4219
cap "wz_addrL2" "reg_4/reg_one_5/port1" 4.95
cap "wz2" "reg_4/reg_one_5/r1" 58.7
cap "reg_4/reg_one_5/tmp" "wz2" 6.507
cap "reg_4/reg_one_5/r0" "mux_8bit_0/out2" 202.159
cap "wz2" "mux_8bit_0/mux_one_2/2mux_nr_0/a_n17_n11#" -5.178
cap "wz2" "reg_4/reg_one_5/a_16_27#" 8.022
cap "wz2" "mux_8bit_0/out2" 2.844
cap "mux_8bit_0/mux_one_2/GND!" "reg_4/reg_one_5/r0" 165.587
cap "wz_addrL2" "reg_4/reg_one_5/Vdd!" 73.616
cap "mux_8bit_0/mux_one_2/GND!" "wz2" 67.786
cap "mux_8bit_0/mux_one_2/inv2_1/a_1_8#" "wz_addrL2" -1.132
cap "wz_addrL2" "reg_4/reg_one_5/a_4_n13#" 47.175
cap "mux_8bit_0/mux_one_2/2mux_nr_0/a_n17_n11#" "mux_8bit_0/mux_one_2/GND!" 3.55271e-15
cap "mux_8bit_0/mux_one_2/2mux_nr_0/s" "wz2" 4.948
cap "reg_4/reg_one_5/r0" "reg_4/reg_one_5/Vdd!" -9.768
cap "mux_8bit_0/mux_one_2/GND!" "mux_8bit_0/out2" 398.251
cap "reg_4/reg_one_5/w_n11_n27#" "wz_addrL2" 76.564
cap "wz_addrL2" "reg_4/port20" 9.229
cap "wz2" "reg_4/reg_one_5/Vdd!" 58.7
subcap "rx_PCL2" -253.641
cap "wz2" "addsub_1/xor_2/b" 11.825
cap "wz2" "reg_4/reg_one_5/w_n11_n27#" -2.417
cap "wz_addrL2" "reg_4/reg_one_5/w" 58.7
cap "wz_addrL2" "addsub_1/a2" -7.348
cap "addsub_1/xor_2/a_61_n1#" "wz2" 5.568
cap "reg_4/reg_one_5/w_n11_n27#" "wz2" -8.24
cap "wz_addrL2" "addsub_1/xor_2/b" 7.975
cap "addsub_1/addsub_one_2/Vdd!" "wz2" 15.72
cap "addsub_1/xor_2/b" "addsub_1/a2" 115.766
cap "reg_4/reg_one_5/w_n11_n27#" "reg_4/port21" 4.24583
cap "wz_addrL2" "reg_4/reg_one_5/w_n11_n27#" 8.24
cap "addsub_1/xor_2/a_61_n1#" "addsub_1/a2" 174.249
cap "wz_addrL2" "addsub_1/addsub_one_2/Vdd!" 11.825
cap "reg_4/reg_one_5/w_n11_n27#" "addsub_1/a2" 63.6875
cap "addsub_1/addsub_one_2/Vdd!" "addsub_1/a2" 127.516
cap "addsub_1/xor_2/a_61_n31#" "addsub_1/b2" -1.13687e-13
cap "wz2" "reg_4/reg_one_5/a_33_32#" -12.339
cap "addsub_1/xor_2/a_61_n31#" "wz2" 19.78
cap "addsub_1/xor_2/a_61_n31#" "addsub_1/a2" 2.424
cap "reg_4/reg_one_5/Vdd!" "wz_addrL2" -2.948
cap "addsub_1/addsub_one_2/b" "wz2" 97.913
cap "addsub_1/addsub_one_2/b" "addsub_1/a2" 36.877
cap "wz2" "addsub_1/b2" 26.517
cap "addsub_1/xor_2/a_89_n31#" "wz2" 17.316
cap "wz_addrL2" "addsub_1/b2" 7.975
cap "addsub_1/b2" "addsub_1/a2" 38.809
cap "reg_4/reg_one_5/w_n11_n27#" "wz_addrL2" -3.379
cap "reg_4/reg_one_5/w" "wz2" 58.7
cap "addsub_1/xor_2/a_89_n31#" "addsub_1/a2" 2.424
cap "addsub_1/xor_2/b" "addsub_1/b2" 11.5435
subcap "a_1716_1449#" -30.357
cap "a_2510_1893#" "addsub_1/addsub_one_2/cout" 6.885
cap "addsub_1/addsub_one_2/b" "addsub_1/addsub_one_2/GND!" -2.27374e-13
cap "a_2510_1893#" "addsub_1/s2" 41.11
cap "addsub_1/addsub_one_2/cin" "a_2510_1893#" 8.408
cap "wz_addrL2" "addsub_1/GND!" 11.825
cap "addsub_1/addsub_one_2/GND!" "wz2" 11.825
cap "addsub_1/addsub_one_2/a_35_n41#" "wz2" 51.712
cap "latch_5/latch_one_2/Vdd!" "addsub_1/s2" -12.402
cap "addsub_1/addsub_one_2/b" "a_2510_1893#" 12.612
cap "addsub_1/addsub_one_2/GND!" "wz2" 14.639
cap "wz_addrL2" "addsub_1/addsub_one_2/Vdd!" 32.72
cap "a_2510_1893#" "addsub_1/addsub_one_2/a_72_n41#" 2.1
cap "addsub_1/addsub_one_2/a_35_n41#" "addsub_1/addsub_one_2/GND!" -1.13687e-13
cap "addsub_1/addsub_one_2/a_78_n41#" "wz2" 35.835
cap "wz_addrL2" "addsub_1/addsub_one_2/GND!" 10.505
cap "addsub_1/addsub_one_2/a_35_n41#" "wz_addrL2" 24.622
cap "addsub_1/addsub_one_2/a_35_n41#" "a_2510_1893#" 8.408
cap "a_2510_1893#" "addsub_1/addsub_one_2/GND!" 44.7
cap "a_2510_1893#" "addsub_1/a2" 8.408
cap "addsub_1/addsub_one_2/GND!" "wz_addrL2" 43.659
cap "a_2510_1893#" "addsub_1/addsub_one_2/a_89_n41#" 22.875
cap "addsub_1/addsub_one_2/a_66_n41#" "a_2510_1893#" 2.1
cap "a_2510_1893#" "addsub_1/addsub_one_2/GND!" 30.19
cap "addsub_1/s2" "addsub_1/GND!" 76.9567
cap "a_2510_1893#" "addsub_1/addsub_one_2/a_78_n41#" 15.064
cap "addsub_1/addsub_one_2/cin" "wz2" 1.56
cap "latch_5/latch_one_2/a_n5_n54#" "addsub_1/s2" 19.2392
cap "addsub_1/addsub_one_2/b" "wz2" 95.736
cap "addsub_1/GND!" "wz2" 11.825
cap "addsub_1/addsub_one_2/Vdd!" "wz2" 3.171
subcap "a_1716_1449#" -104.401
cap "latch_5/out2" "latch_5/latch_one_2/a_12_n54#" 9.731
cap "latch_5/out2" "staticizer_2/staticizer_one_2/a_60_n45#" 212.283
cap "latch_5/out2" "addsub_1/s2" 4.324
cap "latch_5/out2" "latch_5/latch_one_2/Vdd!" 231.426
cap "latch_5/latch_one_2/GND!" "latch_5/latch_one_2/Vdd!" -0.984
cap "latch_5/out2" "latch_5/latch_one_2/a_n5_n54#" 59.375
cap "latch_5/out2" "staticizer_2/staticizer_one_2/c" 63.648
cap "latch_5/latch_one_2/GND!" "staticizer_2/staticizer_one_2/c" 1.42109e-14
cap "latch_5/latch_one_2/Vdd!" "latch_5/latch_one_2/c" 1071.03
cap "latch_5/out2" "staticizer_2/staticizer_one_2/a_77_n45#" 9.998
cap "latch_5/out2" "latch_5/latch_one_2/a_30_n54#" 1.524
cap "latch_5/out2" "latch_5/latch_one_2/GND!" 167.247
cap "latch_5/out2" "latch_5/latch_one_2/c" 75.182
cap "wz2" "latch_5/latch_one_2/Vdd!" 117.4
cap "wz2" "staticizer_2/staticizer_one_2/c" 58.7
cap "latch_5/latch_one_2/Vdd!" "latch_5/latch_one_2/a_12_n54#" 1.13687e-13
cap "addsub_1/s2" "addsub_1/GND!" 19.2392
cap "wz2" "latch_5/latch_one_2/GND!" 117.4
cap "addsub_1/s2" "latch_5/latch_one_2/Vdd!" 19.399
cap "wz2" "latch_5/latch_one_2/c" 58.7
cap "addsub_1/s2" "latch_5/latch_one_2/a_n5_n54#" 57.7175
subcap "wz_addrH2" -919.691
cap "mux_8bit_1/in1_2" "mux_8bit_1/mux_one_2/sel" 63.256
cap "staticizer_2/staticizer_one_2/out" "staticizer_2/staticizer_one_2/c" 3.996
cap "mux_8bit_1/in1_2" "mux_8bit_1/mux_one_2/GND!" 15.908
cap "mux_8bit_1/mux_one_2/Vdd!" "mux_8bit_1/in1_2" 96.331
cap "staticizer_2/staticizer_one_2/a_60_n45#" "staticizer_2/staticizer_one_2/out" -5.616
cap "staticizer_2/staticizer_one_2/out" "staticizer_2/staticizer_one_2/a_77_n45#" 19.052
cap "mux_8bit_1/in0_2" "mux_8bit_1/mux_one_2/inv2_1/a_1_8#" 4.95
cap "staticizer_2/staticizer_one_2/out" "staticizer_2/staticizer_one_2/a_95_n27#" 5.61
cap "mux_8bit_1/mux_one_2/2mux_nr_0/in1" "mux_8bit_1/in1_2" 18.535
cap "staticizer_2/staticizer_one_2/out" "staticizer_2/staticizer_one_2/a_95_n45#" 4.212
cap "staticizer_2/staticizer_one_2/out" "staticizer_2/staticizer_one_2/w_54_n57#" 2.59
cap "mux_8bit_1/mux_one_2/sel" "mux_8bit_1/in0_2" 58.7
cap "mux_8bit_1/mux_one_2/2mux_nr_0/in0" "mux_8bit_1/in0_2" 34.083
cap "mux_8bit_1/mux_one_2/GND!" "mux_8bit_1/in0_2" 18.437
cap "mux_8bit_1/mux_one_2/2mux_nr_0/a_n17_n11#" "mux_8bit_1/in1_2" 36.092
cap "mux_8bit_1/mux_one_2/Vdd!" "mux_8bit_1/in0_2" 149.982
cap "staticizer_2/staticizer_one_2/out" "staticizer_2/staticizer_one_2/Vdd!" 11.587
cap "wz2" "reg_5/reg_one_5/tmp" 6.507
cap "reg_5/port20" "wz_addrH2" 6.6
cap "mux_8bit_1/out2" "mux_8bit_1/mux_one_2/GND!" 398.251
cap "wz2" "reg_5/reg_one_5/r0" 19.78
cap "wz2" "reg_5/reg_one_5/a_16_27#" 8.022
cap "wz2" "reg_5/reg_one_5/a_33_32#" 7.959
cap "wz2" "mux_8bit_1/mux_one_2/2mux_nr_0/s" 4.948
cap "reg_5/reg_one_5/Vdd!" "wz_addrH2" 162.612
cap "reg_5/reg_one_5/r1" "wz_addrH2" 58.7
cap "mux_8bit_1/mux_one_2/2mux_nr_0/a_n17_n11#" "mux_8bit_1/mux_one_2/GND!" 3.55271e-15
cap "wz2" "reg_5/reg_one_5/Vdd!" 58.7
cap "reg_5/reg_one_5/r0" "mux_8bit_1/mux_one_2/GND!" 165.587
cap "wz2" "reg_5/reg_one_5/r1" 58.7
cap "mux_8bit_1/out2" "reg_5/reg_one_5/r0" 202.159
cap "mux_8bit_1/out2" "mux_8bit_1/mux_one_2/2mux_nr_0/out" 85.4219
cap "reg_5/reg_one_5/w_n11_n27#" "wz_addrH2" 58.7
cap "reg_5/reg_one_5/a_4_n13#" "wz_addrH2" 27.497
cap "reg_5/reg_one_5/w_n11_n27#" "wz2" 192.228
cap "mux_8bit_1/out2" "reg_5/reg_one_5/Vdd!" 56.544
cap "reg_5/reg_one_5/a_54_5#" "wz_addrH2" 4.828
cap "wz2" "reg_5/reg_one_5/w" 5.064
cap "wz_addrH2" "mux_8bit_1/mux_one_2/GND!" 67.654
cap "mux_8bit_1/out2" "wz_addrH2" -6.325
cap "reg_5/reg_one_5/Vdd!" "reg_5/reg_one_5/r0" -9.768
cap "wz2" "mux_8bit_1/mux_one_2/GND!" 67.786
cap "wz2" "mux_8bit_1/out2" 2.844
cap "wz2" "mux_8bit_1/mux_one_2/2mux_nr_0/a_n17_n11#" -5.178
cap "reg_5/reg_one_5/tmp" "wz_addrH2" 4.948
cap "reg_5/reg_one_5/r0" "wz_addrH2" 24.728
cap "wz_addrH2" "reg_6/reg_one_5/a_4_n13#" 17.113
cap "reg_6/in2" "reg_6/reg_one_5/a_33_32#" 2.844
cap "reg_6/in2" "reg_6/reg_one_5/tmp" 4.461
cap "reg_6/reg_one_5/r0" "wz_addrH2" 24.728
cap "reg_6/in2" "reg_6/reg_one_5/w_n11_n27#" 182.433
cap "reg_5/port20" "reg_6/reg_one_5/tmp" 5.92
cap "reg_5/port20" "reg_6/reg_one_5/a_21_n13#" 3.96
cap "reg_6/reg_one_5/w_n11_n27#" "reg_5/port20" 151.215
cap "reg_6/reg_one_5/r1" "wz_addrH2" 58.7
cap "reg_6/reg_one_5/Vdd!" "reg_6/in2" 58.7
cap "wz_addrH2" "reg_5/reg_one_5/w_n11_n27#" 8.24
cap "reg_5/port21" "reg_5/reg_one_5/w_n11_n27#" 4.24583
cap "reg_6/reg_one_5/Vdd!" "reg_5/port20" 58.7
cap "reg_6/in2" "reg_5/reg_one_5/w_n11_n27#" -2.417
cap "reg_5/port20" "reg_6/reg_one_5/r0" 2.844
cap "reg_6/in2" "reg_6/reg_one_5/a_16_27#" 8.022
cap "reg_5/w" "reg_6/in2" 58.7
cap "reg_5/w" "reg_5/port20" 67.0625
cap "reg_6/reg_one_5/r1" "reg_6/reg_one_5/Vdd!" 2.27374e-13
cap "wz_addrH2" "reg_6/reg_one_5/tmp" 4.948
cap "reg_6/reg_one_5/a_54_5#" "wz_addrH2" 4.828
cap "reg_6/reg_one_5/w_n11_n27#" "wz_addrH2" 58.7
cap "reg_5/port20" "reg_6/reg_one_5/a_4_n13#" 87.672
cap "reg_6/reg_one_5/r0" "reg_6/in2" 128.02
cap "reg_5/port20" "reg_6/reg_one_5/port1" 5.5
cap "reg_6/reg_one_5/r0" "reg_5/port20" 23.364
cap "reg_6/reg_one_5/Vdd!" "wz_addrH2" 160.588
cap "reg_6/reg_one_5/r1" "reg_6/in2" 58.7
cap "reg_6/in2" "reg_5/reg_one_5/w_n11_n27#" -8.24
cap "reg_6/reg_one_5/r1" "reg_5/port20" 64.504
cap "reg_5/port20" "reg_5/reg_one_5/w_n11_n27#" 127.375
cap "wz_addrH2" "reg_5/reg_one_5/Vdd!" -2.417
cap "reg_6/in2" "reg_6/reg_one_5/w" 2.22
cap "reg_6/in2" "reg_5/reg_one_5/a_33_32#" -12.339
cap "reg_5/w" "wz_addrH2" 58.7
cap "reg_6/in2" "reg_6/reg_one_5/w" 2.844
subcap "m1_2132_1435#" -9.63
cap "rx_addrH2" "reg_6/reg_one_5/a_4_n13#" -10.448
cap "mux_8bit_2/in0_2" "mux_8bit_2/mux_one_2/Vdd!" 139.939
cap "mux_8bit_2/in1_2" "reg_6/reg_one_5/w_n11_n27#" 48.9529
cap "mux_8bit_2/mux_one_2/GND!" "mux_8bit_2/in0_2" 18.437
cap "mux_8bit_2/mux_one_2/GND!" "mux_8bit_2/mux_one_2/2mux_nr_0/in1" 1.42109e-14
cap "rx_addrH2" "reg_6/reg_one_5/w" 58.7
cap "mux_8bit_2/in0_2" "reg_6/reg_one_5/a_4_n13#" -1.152
cap "mux_8bit_2/in0_2" "reg_6/port20" 3.171
cap "mux_8bit_2/in1_2" "mux_8bit_2/mux_one_2/Vdd!" 2.035
cap "mux_8bit_2/mux_one_2/GND!" "mux_8bit_2/in1_2" 2.035
cap "rx_addrH2" "mux_8bit_2/mux_one_2/sel" 58.7
cap "mux_8bit_2/in0_2" "reg_6/reg_one_5/w" 58.7
cap "mux_8bit_2/mux_one_2/2mux_nr_0/in0" "rx_addrH2" 30.259
cap "mux_8bit_2/mux_one_2/2mux_nr_0/in0" "mux_8bit_2/mux_one_2/Vdd!" -2.27374e-13
cap "rx_addrH2" "reg_6/reg_one_5/w_n11_n27#" -2.286
cap "mux_8bit_2/in1_2" "reg_6/reg_one_5/w" 97.0214
cap "reg_6/reg_one_5/Vdd!" "reg_6/port20" -7.10543e-15
cap "mux_8bit_2/in1_2" "reg_6/reg_one_5/tmp" -4.818
cap "mux_8bit_2/in0_2" "reg_6/reg_one_5/Vdd!" -0.393
cap "reg_6/reg_one_5/Vdd!" "reg_6/reg_one_5/a_4_n13#" -7.10543e-15
cap "mux_8bit_2/in1_2" "reg_6/reg_one_5/w_n11_n27#" -1.886
cap "mux_8bit_2/in0_2" "mux_8bit_2/mux_one_2/sel" 58.7
cap "mux_8bit_2/mux_one_2/2mux_nr_0/in0" "mux_8bit_2/in0_2" 34.083
cap "mux_8bit_2/in1_2" "reg_6/reg_one_5/a_33_32#" 5.115
cap "reg_6/reg_one_5/tmp" "reg_6/reg_one_5/w_n11_n27#" -7.10543e-15
cap "mux_8bit_2/in0_2" "mux_8bit_2/mux_one_2/inv2_1/a_1_8#" 4.95
cap "reg_6/reg_one_5/Vdd!" "reg_6/reg_one_5/w" 3.55271e-15
cap "reg_6/reg_one_5/w_n11_n27#" "reg_6/port21" 4.24583
cap "reg_6/reg_one_5/Vdd!" "reg_6/reg_one_5/a_33_32#" -7.10543e-15
cap "rx_addrH2" "reg_6/reg_one_5/w_n11_n27#" 19.776
cap "mux_8bit_2/out2" "rx_addrH2" 19.905
cap "rx_addrH2" "mux_8bit_2/mux_one_2/Vdd!" 76.242
cap "mux_8bit_2/in0_2" "reg_6/reg_one_5/w_n11_n27#" 8.24
cap "mux_8bit_2/mux_one_2/GND!" "rx_addrH2" 22.523
cap "rx_addrH2" "reg_6/port20" 4.411
cap "mux_8bit_2/in0_2" "rx_addrH2" 16.569
cap "reg_7/reg_one_5/a_54_5#" "wz_addrH2" 4.828
cap "reg_7/reg_one_5/Vdd!" "wz_addrH2" 162.612
cap "rx_addrH2" "reg_7/reg_one_5/tmp" 5.92
cap "rx_addrH2" "reg_7/reg_one_5/r0" 23.364
cap "mux_8bit_2/mux_one_2/GND!" "reg_7/reg_one_5/r0" 165.587
cap "mux_8bit_2/out2" "reg_7/reg_one_5/r0" 202.159
cap "rx_addrH2" "reg_7/reg_one_5/r0" 2.844
cap "rx_addrH2" "reg_7/reg_one_5/port1" 5.5
cap "rx_addrH2" "mux_8bit_2/mux_one_2/GND!" 70.894
cap "rx_addrH2" "reg_7/reg_one_5/a_21_n13#" 3.96
cap "reg_7/reg_one_5/Vdd!" "reg_7/reg_one_5/r0" -9.768
cap "rx_addrH2" "mux_8bit_2/out2" -6.325
cap "mux_8bit_2/mux_one_2/GND!" "mux_8bit_2/out2" 398.251
cap "rx_addrH2" "reg_7/port20" 6.006
cap "reg_7/reg_one_5/r1" "wz_addrH2" 58.7
cap "mux_8bit_2/mux_one_2/GND!" "mux_8bit_2/mux_one_2/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "reg_7/reg_one_5/Vdd!" "rx_addrH2" 58.7
cap "reg_7/reg_one_5/Vdd!" "mux_8bit_2/out2" 56.544
cap "reg_7/reg_one_5/a_4_n13#" "wz_addrH2" 27.497
cap "reg_7/reg_one_5/w_n11_n27#" "wz_addrH2" 58.7
cap "reg_7/reg_one_5/tmp" "wz_addrH2" 4.948
cap "reg_7/reg_one_5/r1" "rx_addrH2" 64.504
cap "reg_7/reg_one_5/r0" "wz_addrH2" 24.728
cap "mux_8bit_2/out2" "mux_8bit_2/mux_one_2/2mux_nr_0/out" 85.4219
cap "rx_addrH2" "reg_7/reg_one_5/a_4_n13#" 93.704
cap "rx_addrH2" "reg_7/reg_one_5/w_n11_n27#" 163.513
cap "mux_8bit_2/mux_one_2/GND!" "wz_addrH2" 67.654
cap "mux_8bit_2/out2" "wz_addrH2" -6.325
cap "reg_7/port20" "wz_addrH2" 6.6
subcap "rx_addrH2" -605.114
cap "addsub_2/xor_2/a_61_n1#" "reg_7/port20" 174.249
cap "addsub_2/xor_2/a_61_n31#" "addsub_2/b2" -9.50351e-14
cap "reg_7/reg_one_5/w" "wz_addrH2" 58.7
cap "wz_addrH2" "reg_7/reg_one_5/w_n11_n27#" 8.24
cap "addsub_2/xor_2/a_89_n31#" "reg_7/port20" 2.424
cap "addsub_2/b2" "wz_addrH2" 5.939
cap "addsub_2/xor_2/a_61_n31#" "reg_7/port20" 2.424
cap "addsub_2/xor_2/b" "reg_7/port20" 115.766
cap "reg_7/port20" "addsub_2/addsub_one_2/Vdd!" 127.516
cap "reg_7/reg_one_5/w_n11_n27#" "reg_7/port20" -3.048
cap "reg_7/reg_one_5/w" "reg_7/port20" 125.763
cap "reg_7/port20" "reg_7/reg_one_5/w_n11_n27#" 135.615
cap "wz_addrH2" "reg_7/reg_one_5/Vdd!" -2.417
cap "addsub_2/addsub_one_2/b" "reg_7/port20" 36.877
cap "addsub_2/b2" "reg_7/port20" 38.809
cap "reg_7/reg_one_5/w_n11_n27#" "reg_7/port21" 4.24583
cap "wz_addrH2" "addsub_2/addsub_one_2/Vdd!" 11.825
cap "addsub_2/xor_2/b" "wz_addrH2" 11.825
subcap "a_2516_1449#" -30.357
cap "addsub_2/s2" "wz_addrH2" 50.259
cap "addsub_2/s2" "addsub_2/GND!" 76.9567
cap "addsub_2/addsub_one_2/GND!" "addsub_2/addsub_one_2/b" -2.27374e-13
cap "addsub_2/addsub_one_2/GND!" "wz_addrH2" 4.95
cap "latch_6/latch_one_2/Vdd!" "addsub_2/s2" -12.402
cap "addsub_2/addsub_one_2/a_35_n41#" "wz_addrH2" 19.78
cap "addsub_2/addsub_one_2/GND!" "addsub_2/addsub_one_2/a_35_n41#" -1.13687e-13
cap "addsub_2/s2" "latch_6/latch_one_2/a_n5_n54#" 19.2392
cap "addsub_2/GND!" "wz_addrH2" 4.95
cap "addsub_2/addsub_one_2/Vdd!" "wz_addrH2" 22.705
cap "addsub_2/addsub_one_2/GND!" "wz_addrH2" 34.459
subcap "a_2516_1449#" -104.401
cap "latch_6/latch_one_2/a_30_n35#" "staticizer_3/staticizer_one_2/out" 1.88
cap "latch_6/latch_one_2/Vdd!" "latch_6/latch_one_2/GND!" -1.13687e-13
cap "latch_6/latch_one_2/Vdd!" "latch_6/latch_one_2/a_12_n54#" 1.13687e-13
cap "staticizer_3/staticizer_one_2/out" "staticizer_3/staticizer_one_2/c" 61.544
cap "latch_6/latch_one_2/Vdd!" "addsub_2/s2" 19.399
cap "latch_6/latch_one_2/c" "staticizer_3/staticizer_one_2/out" 61.66
cap "staticizer_3/staticizer_one_2/out" "staticizer_3/staticizer_one_2/a_60_n45#" 75.3524
cap "staticizer_3/staticizer_one_2/out" "latch_6/out2" 7.047
cap "latch_6/latch_one_2/c" "latch_6/out2" 9.252
cap "addsub_2/s2" "addsub_2/GND!" 19.2392
cap "staticizer_3/staticizer_one_2/a_60_n45#" "latch_6/out2" 150.065
cap "staticizer_3/staticizer_one_2/out" "staticizer_3/staticizer_one_2/a_77_n45#" 5.115
cap "latch_6/latch_one_2/Vdd!" "staticizer_3/staticizer_one_2/out" 169.606
cap "latch_6/latch_one_2/a_n5_n54#" "addsub_2/s2" 57.7175
cap "latch_6/latch_one_2/c" "latch_6/latch_one_2/Vdd!" 1070.42
cap "staticizer_3/staticizer_one_2/out" "latch_6/latch_one_2/GND!" 117.4
cap "staticizer_3/staticizer_one_2/c" "latch_6/latch_one_2/GND!" 1.42109e-14
cap "latch_6/latch_one_2/a_12_n54#" "staticizer_3/staticizer_one_2/out" 9.708
cap "latch_6/latch_one_2/Vdd!" "latch_6/out2" 107.428
cap "addsub_2/s2" "staticizer_3/staticizer_one_2/out" 6.404
cap "latch_6/latch_one_2/GND!" "latch_6/out2" 10.156
cap "latch_6/latch_one_2/a_n5_n54#" "staticizer_3/staticizer_one_2/out" 59.464
subcap "addr_out2" -56.838
cap "staticizer_3/staticizer_one_2/a_77_n45#" "staticizer_3/staticizer_one_2/Vdd!" 2.84217e-14
cap "latch_7/latch_one_2/a_n5_n54#" "latch_7/latch_one_2/Vdd!" -1.13687e-13
cap "staticizer_3/staticizer_one_2/w_54_n57#" "staticizer_3/staticizer_one_2/out" 8.272
cap "staticizer_3/staticizer_one_2/a_77_n45#" "staticizer_3/staticizer_one_2/out" 2.728
cap "latch_7/latch_one_2/Vdd!" "latch_7/latch_one_2/c" 1070.42
cap "latch_7/latch_one_2/Vdd!" "latch_7/out2" 107.428
cap "staticizer_3/staticizer_one_2/a_60_n45#" "staticizer_3/staticizer_one_2/out" 0.709429
cap "staticizer_3/staticizer_one_2/Vdd!" "latch_7/in2" 11.463
cap "latch_7/latch_one_2/GND!" "latch_7/out2" 10.156
cap "latch_7/latch_one_2/Vdd!" "latch_7/in2" 188.427
cap "latch_7/latch_one_2/GND!" "staticizer_4/staticizer_one_2/a_60_n45#" 5.68434e-14
cap "staticizer_3/staticizer_one_2/out" "latch_7/in2" 23.087
cap "latch_7/latch_one_2/GND!" "latch_7/in2" 6.956
cap "latch_7/out2" "latch_7/latch_one_2/c" 9.252
cap "staticizer_3/staticizer_one_2/Vdd!" "staticizer_3/staticizer_one_2/out" 6.001
cap "latch_7/latch_one_2/Vdd!" "latch_7/latch_one_2/a_12_n54#" 1.13687e-13
cap "staticizer_3/staticizer_one_2/w_54_n57#" "latch_7/in2" 11.719
cap "latch_7/latch_one_2/a_n5_n54#" "latch_7/in2" 57.7175
cap "staticizer_4/staticizer_one_2/a_60_n45#" "latch_7/out2" 150.065
cap "latch_7/latch_one_2/GND!" "latch_7/latch_one_2/Vdd!" -0.738
subcap "ry_addrH2" -897.005
subcap "addr_out10" -305.874
cap "latch_8/latch_one_2/a_12_n54#" "latch_8/latch_one_2/Vdd!" 1.13687e-13
cap "staticizer_4/staticizer_one_2/a_77_n45#" "staticizer_4/staticizer_one_2/Vdd!" 1.13687e-13
cap "staticizer_5/in2" "latch_8/latch_one_2/Vdd!" -1.162
cap "staticizer_4/staticizer_one_2/out" "staticizer_4/staticizer_one_2/Vdd!" -5.68434e-14
cap "staticizer_4/staticizer_one_2/w_54_n57#" "staticizer_4/staticizer_one_2/c" 2.84217e-14
cap "latch_8/latch_one_2/a_n5_n54#" "latch_8/latch_one_2/Vdd!" -1.13687e-13
cap "latch_8/in2" "staticizer_4/staticizer_one_2/out" 57.7175
cap "latch_8/in2" "latch_8/latch_one_2/Vdd!" 188.427
cap "latch_8/in2" "staticizer_4/staticizer_one_2/Vdd!" 11.463
cap "staticizer_4/staticizer_one_2/w_54_n57#" "staticizer_4/staticizer_one_2/a_60_n45#" 2.84217e-14
cap "staticizer_4/staticizer_one_2/w_54_n57#" "latch_8/in2" 11.719
cap "latch_8/latch_one_2/a_n5_n54#" "latch_8/in2" 57.7175
cap "staticizer_5/in2" "latch_8/latch_one_2/c" -0.42
cap "staticizer_5/staticizer_one_2/w_54_n57#" "latch_8/in2" 6.956
subcap "addr_out10" -36.486
cap "staticizer_5/in2" "latch_8/latch_one_2/c" 9.252
cap "staticizer_5/in2" "staticizer_5/staticizer_one_2/w_54_n57#" 10.156
cap "latch_8/latch_one_2/Vdd!" "latch_8/latch_one_2/c" 1070.42
cap "staticizer_5/in2" "latch_8/latch_one_2/Vdd!" 107.428
cap "staticizer_5/staticizer_one_2/a_60_n45#" "staticizer_5/in2" 150.065
subcap "a_n24_1624#" -100.028
cap "staticizer_1/staticizer_one_1/a_60_n45#" "staticizer_1/in1" 57.7175
cap "staticizer_1/staticizer_one_1/Vdd!" "staticizer_1/staticizer_one_1/a_60_n45#" 5.68434e-14
cap "staticizer_1/staticizer_one_1/out" "staticizer_1/staticizer_one_1/Vdd!" -7.10543e-15
cap "staticizer_1/staticizer_one_1/Vdd!" "staticizer_1/in1" 27.626
cap "latch_4/latch_one_1/c" "staticizer_1/in1" 0.492
cap "staticizer_1/Vdd!" "latch_4/latch_one_1/c" 1073
cap "staticizer_1/staticizer_one_1/w_54_n57#" "staticizer_1/in1" 18.828
cap "staticizer_1/Vdd!" "staticizer_1/staticizer_one_1/w_54_n57#" 1.13687e-13
cap "staticizer_1/staticizer_one_1/w_54_n57#" "latch_4/latch_one_1/c" 18.4696
subcap "a_109_1624#" -116.828
subcap "data_in1" -75.185
subcap "rx1" -1814.76
cap "latch_0/Vdd!" "latch_4/in1" 58.7
cap "latch_4/in1" "latch_4/Vdd!" 469.438
cap "latch_0/out1" "staticizer_0/staticizer_one_1/a_60_n45#" 57.7175
cap "latch_4/in1" "latch_4/latch_one_1/a_n5_n54#" 56.1817
cap "latch_0/latch_one_1/GND!" "latch_0/latch_one_1/c" 18.4696
cap "latch_0/latch_one_1/GND!" "staticizer_0/Vdd!" -0.246
cap "staticizer_0/staticizer_one_1/Vdd!" "staticizer_0/Vdd!" -0.246
cap "latch_0/latch_one_1/a_n5_n54#" "latch_0/latch_one_1/GND!" 5.68434e-14
cap "latch_0/latch_one_1/a_n5_n54#" "latch_0/in1" 19.7889
cap "latch_0/latch_one_1/c" "staticizer_0/Vdd!" 1073
cap "latch_0/latch_one_1/GND!" "latch_4/in1" 59.993
cap "staticizer_0/staticizer_one_1/a_60_n45#" "staticizer_0/staticizer_one_1/Vdd!" -4.648
cap "latch_0/latch_one_1/c" "latch_4/in1" 58.7
cap "latch_4/in1" "staticizer_0/Vdd!" 37.42
cap "latch_0/out1" "latch_0/latch_one_1/GND!" 18.828
cap "latch_0/out1" "staticizer_0/staticizer_one_1/Vdd!" 27.626
cap "latch_0/out1" "latch_0/latch_one_1/c" 0.492
cap "staticizer_0/staticizer_one_1/Vdd!" "latch_0/out1" 16.212
cap "wz1" "shift_0/shift_one_1/Vdd!" 8.24
cap "staticizer_0/staticizer_one_1/w_54_n57#" "shift_0/a1" 73.425
cap "wz1" "staticizer_0/staticizer_one_1/out" 15.075
cap "staticizer_0/staticizer_one_1/w_54_n57#" "wz1" 6.22
cap "latch_0/out1" "staticizer_0/Vdd!" 1.722
cap "staticizer_0/staticizer_one_1/w_54_n57#" "staticizer_0/Vdd!" -0.984
cap "staticizer_0/staticizer_one_1/Vdd!" "staticizer_0/staticizer_one_1/a_60_n45#" -2.324
cap "shift_0/shift_one_1/ad" "shift_0/a1" 125.762
cap "staticizer_0/staticizer_one_1/Vdd!" "staticizer_0/staticizer_one_1/a_77_n45#" -7.10543e-15
cap "staticizer_0/staticizer_one_1/a_60_n45#" "staticizer_0/Vdd!" -0.42
cap "shift_0/shift_one_1/ad" "wz1" 58.7
cap "staticizer_0/staticizer_one_1/c" "shift_0/a1" 76.935
cap "staticizer_0/staticizer_one_1/a_60_n45#" "latch_0/out1" 31.249
cap "staticizer_0/staticizer_one_1/Vdd!" "staticizer_0/Vdd!" -0.984
cap "staticizer_0/staticizer_one_1/Vdd!" "wz1" 6.641
cap "wz1" "shift_0/a1" 58.7
cap "shift_0/a1" "staticizer_0/Vdd!" -12.11
cap "wz1" "shift_0/Vdd!" 58.7
cap "shift_0/shift_one_1/inv_2/GND!" "rx1" 11.43
cap "wz1" "shift_0/u" 58.7
cap "shift_0/shift_one_1/inv_2/out" "wz1" 25.522
cap "wz1" "shift_0/shift_one_1/Vdd!" 91.858
cap "wz1" "shift_0/GND!" 58.7
cap "wz1" "shift_0/shift_one_1/inv_2/GND!" 21.418
cap "wz1" "shift_0/shift_one_1/m1_n60_n65#" 11.825
cap "shift_0/shift_one_1/inv_2/in" "rx1" 14.74
cap "shift_0/Vdd!" "rx1" 58.7
cap "shift_0/u" "rx1" 58.7
cap "shift_0/shift_one_1/Vdd!" "rx1" 7.239
cap "shift_0/GND!" "rx1" 58.7
cap "shift_0/o1" "shift_0/shift_one_1/inv_3/Vdd!" 1.162
cap "latch_3/Vdd!" "rx1" 58.7
cap "wz1" "shift_0/shift_one_1/inv_3/GND!" 3.152
cap "wz1" "latch_3/latch_one_1/GND!" 66.689
cap "latch_3/latch_one_1/Vdd!" "shift_0/o1" 9.594
cap "wz1" "shift_0/shift_one_1/inv_3/Vdd!" 72.651
cap "shift_0/shift_one_1/inv_3/GND!" "rx1" 6.096
cap "wz1" "latch_3/latch_one_1/c" 1.248
cap "wz1" "shift_0/o1" 2.184
cap "wz1" "shift_0/shift_one_2/s" 58.7
cap "rx1" "latch_3/latch_one_1/GND!" 107.383
cap "shift_0/shift_one_1/inv_3/Vdd!" "rx1" 7.239
cap "wz1" "latch_3/latch_one_1/Vdd!" 6.015
cap "shift_0/o1" "rx1" 20.945
cap "wz1" "latch_3/latch_one_1/a_12_n54#" 4.95
cap "latch_3/latch_one_1/c" "rx1" 3.12
cap "shift_0/shift_one_2/s" "rx1" 58.7
cap "shift_0/o1" "shift_0/shift_one_1/inv_3/in" 57.7175
cap "latch_3/latch_one_1/a_n5_n54#" "shift_0/o1" 57.7175
cap "latch_3/latch_one_1/a_n5_n54#" "latch_3/latch_one_1/Vdd!" 2.84217e-14
cap "wz1" "latch_3/Vdd!" 58.7
cap "wz1" "shift_0/shift_one_1/inv_3/in" 8.599
cap "shift_0/o1" "latch_3/latch_one_1/GND!" 30.043
cap "latch_3/latch_one_1/a_n5_n54#" "wz1" 30.853
cap "fblock_0/g2" "latch_3/out1" 58.7
cap "latch_3/latch_one_1/GND!" "fblock_0/a1" 0.083
cap "fblock_0/fblock_one_1/2mux_nr_2/in0" "fblock_0/a1" 9.912
cap "fblock_0/fblock_one_1/f" "fblock_0/a1" 37.08
cap "latch_3/latch_one_1/c" "fblock_0/a1" 78.258
cap "latch_3/out1" "fblock_0/g3" 58.7
cap "fblock_0/fblock_one_1/inv_0/Vdd!" "fblock_0/a1" 35.38
cap "latch_3/latch_one_1/Vdd!" "latch_3/latch_one_1/a_12_n54#" -3.55271e-15
cap "latch_3/out1" "fblock_0/fblock_one_1/2mux_nr_2/in1" 9.35
cap "fblock_0/g2" "fblock_0/a1" 44.76
cap "latch_3/out1" "fblock_0/a1" 4.948
cap "fblock_0/a1" "fblock_0/fblock_one_1/2mux_nr_2/s" 1.11
cap "latch_3/out1" "fblock_0/GND!" 58.7
cap "fblock_0/fblock_one_1/2mux_nr_2/Vdd!" "fblock_0/a1" 6.216
cap "latch_3/out1" "fblock_0/fblock_one_1/inv_0/GND!" 38.323
cap "fblock_0/g3" "fblock_0/a1" 528.858
cap "fblock_0/fblock_one_1/2mux_nr_2/in1" "fblock_0/a1" 10.638
cap "fblock_0/GND!" "fblock_0/a1" 44.76
cap "latch_3/out1" "fblock_0/fblock_one_1/2mux_nr_2/a_n17_n11#" 14.683
cap "latch_3/out1" "fblock_0/fblock_one_1/inv_0/in" 19.302
cap "fblock_0/fblock_one_1/inv_0/GND!" "fblock_0/a1" 52.3709
cap "latch_3/latch_one_1/Vdd!" "latch_3/out1" 0.959
cap "fblock_0/fblock_one_1/2mux_nr_2/a_n17_n11#" "fblock_0/a1" 14.484
cap "fblock_0/fblock_one_1/inv_0/in" "fblock_0/a1" 17.232
cap "latch_3/latch_one_1/c" "latch_3/latch_one_1/GND!" 2.84217e-14
cap "latch_3/out1" "fblock_0/fblock_one_1/2mux_nr_2/in0" 7.975
cap "latch_3/out1" "latch_3/latch_one_1/GND!" 1.209
cap "latch_3/out1" "latch_3/latch_one_1/c" 140.424
subcap "a_580_1619#" -8.954
cap "fblock_0/f1" "wz1" 18.093
cap "fblock_0/fblock_one_2/g0" "wz1" 58.7
cap "latch_1/Vdd!" "wz1" 58.7
cap "latch_1/latch_one_1/a_12_n54#" "wz1" 9.731
cap "fblock_0/fblock_one_1/inv_0/in" "wz1" 4.123
cap "latch_1/latch_one_1/a_n5_n54#" "wz1" 43.4
cap "fblock_0/fblock_one_1/inv_0/in" "fblock_0/fblock_one_1/inv_0/GND!" 5.68434e-14
cap "rx1" "fblock_0/f1" 17.535
cap "fblock_0/fblock_one_2/g0" "rx1" 44.76
cap "rx1" "latch_1/Vdd!" 44.76
cap "rx1" "latch_1/latch_one_1/a_12_n54#" 4.761
cap "latch_1/latch_one_1/a_n5_n54#" "fblock_0/f1" 57.7175
cap "fblock_0/fblock_one_1/inv_0/in" "rx1" 3.468
cap "latch_1/latch_one_1/a_n5_n54#" "rx1" 9.072
cap "fblock_0/fblock_one_2/inv_3/Vdd!" "wz1" 58.7
cap "latch_1/latch_one_1/GND!" "wz1" 69.742
cap "fblock_0/fblock_one_2/g1" "wz1" 58.7
cap "latch_1/latch_one_1/c" "wz1" 4.324
cap "rx1" "latch_1/latch_one_1/Vdd!" 46.561
cap "fblock_0/fblock_one_2/inv_3/Vdd!" "fblock_0/f1" 12.684
cap "fblock_0/fblock_one_2/inv_3/Vdd!" "rx1" 44.76
cap "fblock_0/f1" "latch_1/latch_one_1/GND!" 12.326
cap "fblock_0/f1" "latch_1/latch_one_1/Vdd!" 6.108
cap "fblock_0/fblock_one_2/inv_3/Vdd!" "latch_1/Vdd!" 1341.25
cap "rx1" "latch_1/latch_one_1/Vdd!" 15.309
cap "rx1" "latch_1/latch_one_1/GND!" 44.76
cap "rx1" "fblock_0/fblock_one_1/f" 75.577
cap "rx1" "fblock_0/fblock_one_2/g1" 44.76
cap "fblock_0/fblock_one_1/inv_0/GND!" "wz1" 20.977
cap "latch_1/latch_one_1/c" "rx1" 0.624
cap "fblock_0/fblock_one_1/inv_0/in" "fblock_0/fblock_one_1/f" 2.84217e-14
subcap "ry1" -2471.26
cap "latch_1/out1" "latch_1/latch_one_1/GND!" 3.821
cap "rx1" "addsub_0/b1" 1.908
cap "latch_1/out1" "latch_1/latch_one_1/a_30_n54#" 1.524
cap "rx1" "latch_1/latch_one_1/a_30_n35#" 4.116
cap "latch_1/out1" "latch_1/latch_one_1/a_n5_n54#" 15.975
cap "addsub_0/xor_1/GND!" "addsub_0/b1" 0.872
cap "addsub_0/xor_1/GND!" "rx1" 14.485
cap "latch_1/latch_one_1/Vdd!" "rx1" 6.396
cap "rx1" "latch_1/latch_one_1/c" 44.76
cap "rx1" "latch_1/latch_one_1/a_12_n54#" 3.468
cap "latch_1/out1" "addsub_0/xor_1/GND!" 11.825
cap "latch_1/out1" "latch_1/latch_one_1/GND!" 2.361
cap "rx1" "addsub_0/xor_1/Vdd!" 6.896
cap "latch_1/latch_one_1/a_n5_n54#" "rx1" 3.468
cap "latch_1/out1" "addsub_0/sub" 11.825
cap "latch_1/out1" "rx1" 9.798
cap "addsub_0/xor_1/GND!" "addsub_0/b1" 93.4474
cap "rx1" "addsub_0/xor_1/GND!" 9.075
cap "latch_1/out1" "latch_1/latch_one_1/Vdd!" 1.221
cap "latch_1/out1" "latch_1/latch_one_1/c" 144.632
cap "latch_1/latch_one_1/Vdd!" "rx1" -5.959
cap "rx1" "addsub_0/sub" 9.075
cap "as_cout" "addsub_0/addsub_one_2/a_29_n41#" 2.1
cap "as_cout" "addsub_0/addsub_one_1/s" 41.11
cap "addsub_0/addsub_one_1/Vdd!" "rx1" 0.841
cap "wz1" "addsub_0/addsub_one_1/GND!" 0.308
cap "as_cout" "addsub_0/addsub_one_2/a_35_n41#" 10.65
cap "as_cout" "addsub_0/addsub_one_2/b" 4.204
cap "as_cout" "addsub_0/addsub_one_2/a" 8.408
cap "addsub_0/addsub_one_1/a_35_n41#" "wz1" 65.763
cap "wz1" "addsub_0/addsub_one_2/GND!" 18.211
cap "addsub_0/addsub_one_2/GND!" "ry1" 24.188
cap "addsub_0/addsub_one_1/GND!" "as_cout" 10.65
cap "addsub_0/addsub_one_1/cout" "ry1" 11.138
cap "addsub_0/addsub_one_1/a_35_n41#" "as_cout" 4.204
cap "as_cout" "addsub_0/addsub_one_2/GND!" 56.78
cap "wz1" "addsub_0/addsub_one_2/Vdd!" 11.825
cap "wz1" "addsub_0/addsub_one_1/Vdd!" 38.922
cap "addsub_0/addsub_one_2/Vdd!" "ry1" 11.825
cap "addsub_0/addsub_one_1/Vdd!" "ry1" 16.992
cap "as_cout" "addsub_0/addsub_one_1/cout" 14.329
cap "as_cout" "addsub_0/addsub_one_2/a_11_n41#" 21.93
cap "as_cout" "addsub_0/addsub_one_1/a_78_n41#" 3.332
cap "as_cout" "addsub_0/addsub_one_2/cin" 4.204
subcap "a_841_1625#" -51.694
cap "addsub_0/s1" "addsub_0/addsub_one_2/GND!" 76.9567
cap "latch_2/latch_one_1/GND!" "latch_2/out1" 90.233
cap "latch_2/latch_one_1/GND!" "ry1" 110.895
cap "latch_2/out1" "latch_2/latch_one_1/a_12_n54#" 12.473
cap "addsub_0/s1" "latch_2/out1" 4.948
cap "reg_0/reg_one_6/r0" "latch_2/out1" 63.6875
cap "latch_2/out1" "latch_2/latch_one_1/a_30_n54#" 2.592
cap "addsub_0/addsub_one_1/a_35_n41#" "latch_2/out1" -1.814
cap "latch_2/out1" "addsub_0/addsub_one_2/GND!" 19.247
cap "reg_0/reg_one_6/r0" "ry1" 17.308
cap "addsub_0/addsub_one_1/GND!" "latch_2/out1" 3.399
cap "addsub_0/s1" "latch_2/latch_one_1/a_n5_n54#" 57.7175
cap "addsub_0/s1" "latch_2/latch_one_1/Vdd!" 19.399
cap "latch_2/out1" "latch_2/Vdd!" 58.7
cap "addsub_0/addsub_one_2/GND!" "ry1" 20.633
cap "ry1" "latch_2/Vdd!" 58.7
cap "ry1" "addsub_0/addsub_one_2/cin" 1.486
cap "latch_2/out1" "latch_2/latch_one_1/c" 244.207
cap "latch_2/out1" "latch_2/latch_one_1/Vdd!" 1.221
cap "latch_2/latch_one_1/c" "ry1" 81.378
cap "latch_2/out1" "latch_2/latch_one_1/a_n5_n54#" 12.196
cap "reg_0/port11" "reg_0/reg_one_6/w_n11_n27#" 121.694
cap "reg_0/reg_one_6/w_n11_n27#" "reg_0/reg_one_6/Vdd!" -1.42109e-14
cap "reg_0/w" "reg_0/port10" 214.6
cap "reg_0/port10" "reg_0/reg_one_6/w_n11_n27#" 127.375
cap "reg_0/port11" "reg_0/reg_one_6/r1" 64.004
cap "reg_0/port11" "reg_0/reg_one_6/Vdd!" 58.7
cap "reg_0/reg_one_6/r0" "reg_0/port11" 23.94
cap "reg_0/w" "reg_0/port11" 127.744
cap "reg_1/port10" "reg_1/reg_one_6/a_21_n13#" 2.238
cap "reg_1/port11" "reg_1/reg_one_6/r1" 64.004
cap "reg_1/port11" "reg_1/reg_one_6/Vdd!" 58.7
cap "reg_1/port11" "reg_1/w" 127.744
cap "reg_1/port10" "reg_1/reg_one_6/a_4_n13#" 118.494
cap "reg_1/port10" "reg_1/reg_one_6/w_n11_n27#" 198.775
cap "reg_1/port10" "reg_1/reg_one_6/r0" 21.144
cap "reg_1/port10" "reg_1/port11" 3.85
cap "reg_1/port11" "reg_1/reg_one_6/w_n11_n27#" 121.694
cap "reg_1/reg_one_6/r0" "reg_1/port11" 48.664
cap "reg_1/reg_one_6/Vdd!" "reg_1/reg_one_6/w_n11_n27#" -1.42109e-14
cap "reg_1/port10" "reg_1/reg_one_6/Vdd!" 75.185
cap "reg_1/port10" "reg_1/reg_one_6/r1" 60.064
cap "reg_1/port10" "reg_1/w" 125.763
cap "reg_1/port10" "reg_1/reg_one_6/tmp" 4.694
cap "reg_2/r1" "reg_2/reg_one_6/Vdd!" 1.77636e-15
cap "reg_2/port11" "reg_2/reg_one_6/r0" 48.664
cap "reg_1/port10" "reg_2/reg_one_6/r0" 21.144
cap "reg_1/port10" "reg_2/r1" 58.7
cap "reg_2/port11" "reg_2/r1" 58.7
cap "reg_2/reg_one_6/w_n11_n27#" "reg_2/r1" 3.55271e-15
cap "reg_2/port11" "reg_2/reg_one_6/r1" 5.304
cap "reg_1/port10" "reg_2/reg_one_6/r1" 1.364
cap "reg_1/port10" "reg_2/reg_one_6/a_21_n13#" 0.99
cap "reg_1/port10" "reg_2/reg_one_6/Vdd!" 16.485
cap "reg_2/port11" "reg_2/w" 94.2122
cap "reg_1/port10" "reg_2/w" 92.2312
cap "reg_2/port11" "reg_1/port10" 3.85
cap "reg_2/reg_one_6/w_n11_n27#" "reg_1/port10" 135.088
cap "reg_2/port11" "reg_2/reg_one_6/w_n11_n27#" 121.694
cap "reg_1/port10" "reg_2/reg_one_6/a_21_n13#" 1.248
cap "reg_1/port10" "reg_2/reg_one_6/tmp" 4.694
cap "reg_2/port11" "reg_2/Vdd!" 58.7
cap "reg_1/port10" "reg_2/Vdd!" 58.7
cap "reg_1/port10" "reg_2/reg_one_6/a_4_n13#" 118.494
cap "reg_2/reg_one_6/w_n11_n27#" "reg_2/port10" 63.6875
cap "reg_3/reg_one_6/w_n11_n27#" "reg_3/port11" 1.628
cap "reg_3/reg_one_6/w_n11_n27#" "reg_2/port11" 106.567
cap "reg_2/port10" "reg_3/reg_one_6/a_21_n13#" 0.99
cap "reg_3/Vdd!" "reg_2/port10" 58.7
cap "reg_3/r1" "reg_2/port11" 58.7
cap "reg_3/reg_one_6/Vdd!" "reg_3/r1" 1.77636e-15
cap "reg_2/port10" "reg_3/reg_one_6/tmp" 4.694
cap "reg_3/reg_one_6/r1" "reg_2/port11" 5.304
cap "reg_3/port11" "reg_2/port11" 73.199
cap "reg_2/port10" "reg_3/reg_one_6/r0" 21.144
cap "reg_2/w" "reg_2/port10" 33.5312
cap "reg_2/port10" "reg_3/reg_one_6/a_21_n13#" 1.248
cap "reg_2/port10" "reg_3/port10" 8.58
cap "reg_3/Vdd!" "reg_2/port11" 58.7
cap "reg_2/port10" "reg_3/reg_one_6/a_4_n13#" 118.494
cap "reg_3/reg_one_6/w_n11_n27#" "reg_2/port10" 63.11
cap "reg_3/r1" "reg_2/port10" 58.7
cap "reg_2/port10" "reg_3/port11" 3.85
cap "reg_2/port11" "reg_3/reg_one_6/r0" 48.664
cap "reg_3/reg_one_6/r1" "reg_2/port10" 1.364
cap "reg_3/w" "reg_3/port11" 5.072
cap "reg_3/reg_one_6/Vdd!" "reg_2/port10" 15.954
cap "reg_2/w" "reg_2/port11" 33.5312
cap "reg_3/reg_one_6/w_n11_n27#" "reg_3/r1" 3.55271e-15
subcap "wz_addrL1" -536.642
subcap "PCL_w_muxout1" -380.236
cap "reg_3/w" "reg_3/port10" 125.763
cap "mux_8bit_0/mux_one_1/inv2_2/GND!" "mux_8bit_0/out1" 37.928
cap "mux_8bit_0/out1" "mux_8bit_0/in0_1" 30.603
cap "reg_3/port11" "mux_8bit_0/out1" -10.01
cap "mux_8bit_0/mux_one_2/2mux_nr_0/s" "mux_8bit_0/in0_1" 58.7
cap "mux_8bit_0/Vdd!" "mux_8bit_0/in0_1" 58.7
cap "mux_8bit_0/mux_one_1/inv2_2/GND!" "mux_8bit_0/in0_1" 12.279
cap "mux_8bit_0/mux_one_2/2mux_nr_0/s" "reg_3/port11" 58.7
cap "mux_8bit_0/Vdd!" "reg_3/port11" 58.7
cap "mux_8bit_0/mux_one_1/inv2_2/GND!" "reg_3/port11" 63.013
cap "reg_3/port11" "reg_3/reg_one_6/w_n11_n27#" -1.039
cap "mux_8bit_0/in0_1" "mux_8bit_0/mux_one_1/inv2_2/a_6_n1#" 29.025
cap "reg_3/port10" "reg_3/reg_one_6/w_n11_n27#" -3.379
cap "reg_3/port11" "reg_3/reg_one_6/w_n11_n27#" 12.7375
cap "reg_3/port10" "reg_3/reg_one_6/w_n11_n27#" 135.615
cap "reg_3/reg_one_6/Vdd!" "reg_3/port10" -2.898
cap "mux_8bit_0/mux_one_1/inv2_1/a_1_8#" "mux_8bit_0/in0_1" 19.462
cap "reg_3/w" "reg_3/port11" 127.744
cap "mux_8bit_0/mux_one_2/2mux_nr_0/s" "mux_8bit_0/out1" 0.84
cap "mux_8bit_0/mux_one_1/inv2_2/Vdd!" "mux_8bit_0/in0_1" 20.196
cap "reg_4/reg_one_6/tmp" "wz_addrL1" 4.68
cap "mux_8bit_0/out1" "ry1" -17.369
cap "reg_4/reg_one_6/r0" "mux_8bit_0/out1" 183.291
cap "reg_4/port10" "wz_addrL1" 9.229
cap "mux_8bit_0/mux_one_1/inv2_1/a_1_8#" "wz_addrL1" -1.132
cap "reg_4/reg_one_6/Vdd!" "wz_addrL1" 73.616
cap "reg_4/port11" "wz_addrL1" 4.95
cap "mux_8bit_0/mux_one_2/2mux_nr_0/GND!" "wz_addrL1" 58.7
cap "mux_8bit_0/mux_one_1/inv2_1/GND!" "wz_addrL1" 6.72
cap "reg_4/w" "reg_4/port11" 5.072
cap "reg_4/reg_one_6/w_n11_n27#" "wz_addrL1" 76.564
cap "reg_4/reg_one_6/r1" "wz_addrL1" 59.948
cap "reg_4/reg_one_6/Vdd!" "ry1" 58.7
cap "reg_4/port11" "reg_4/reg_one_6/w_n11_n27#" 1.628
cap "reg_4/reg_one_6/r0" "wz_addrL1" 21.028
cap "reg_4/port11" "ry1" 73.199
cap "reg_4/reg_one_6/r0" "reg_4/reg_one_6/Vdd!" 7.10543e-15
cap "mux_8bit_0/mux_one_2/2mux_nr_0/GND!" "ry1" 58.7
cap "reg_4/reg_one_6/a_4_n13#" "wz_addrL1" 47.175
cap "mux_8bit_0/mux_one_1/inv2_1/GND!" "ry1" -6.916
cap "mux_8bit_0/out1" "wz_addrL1" -6.325
cap "reg_4/reg_one_6/w_n11_n27#" "ry1" 106.567
cap "reg_4/reg_one_6/r1" "ry1" 64.004
cap "reg_4/reg_one_6/r0" "ry1" 48.664
cap "mux_8bit_0/out1" "mux_8bit_0/mux_one_2/2mux_nr_0/GND!" 32.46
cap "mux_8bit_0/out1" "mux_8bit_0/mux_one_1/inv2_1/GND!" 340.759
cap "addsub_1/Vdd!" "reg_4/port11" 11.825
cap "wz_addrL1" "addsub_1/Vdd!" 11.825
cap "reg_4/port10" "addsub_1/addsub_one_1/Vdd!" 0.872
cap "reg_4/port10" "reg_4/reg_one_6/w_n11_n27#" 63.6875
cap "wz_addrL1" "reg_4/reg_one_6/w_n11_n27#" -3.379
cap "reg_4/reg_one_6/w_n11_n27#" "reg_4/port11" -1.039
cap "wz_addrL1" "reg_4/port10" -7.348
cap "addsub_1/b1" "reg_4/port11" 11.825
cap "wz_addrL1" "addsub_1/b1" 7.975
cap "reg_4/port10" "addsub_1/sub" 113.342
cap "wz_addrL1" "reg_4/w" 58.7
cap "reg_4/w" "reg_4/port11" 127.744
cap "reg_4/reg_one_6/w_n11_n27#" "reg_4/port11" 12.7375
cap "wz_addrL1" "reg_4/reg_one_6/w_n11_n27#" 8.24
cap "wz_addrL1" "reg_4/reg_one_6/Vdd!" -2.948
cap "reg_4/port10" "addsub_1/b1" 36.385
cap "addsub_1/xor_1/GND!" "addsub_1/b1" -1.77636e-15
cap "addsub_1/sub" "reg_4/port11" 11.825
cap "wz_addrL1" "addsub_1/sub" 7.975
subcap "a_1716_1625#" -30.357
cap "addsub_1/addsub_one_2/a_11_n41#" "a_2510_1893#" 21.93
cap "wz_addrL1" "addsub_1/addsub_one_1/Vdd!" 37.175
cap "a_2510_1893#" "addsub_1/addsub_one_2/a_29_n41#" 2.1
cap "a_2510_1893#" "addsub_1/addsub_one_1/GND!" 10.65
cap "a_2510_1893#" "addsub_1/addsub_one_2/a" 8.408
cap "a_2510_1893#" "addsub_1/s1" 41.11
cap "a_2510_1893#" "addsub_1/addsub_one_2/a_35_n41#" 10.65
cap "ry1" "addsub_1/addsub_one_2/cin" 18.24
cap "addsub_1/s1" "addsub_1/addsub_one_2/GND!" 76.9567
cap "a_2510_1893#" "addsub_1/addsub_one_2/b" 4.204
cap "latch_5/latch_one_1/a_n5_n54#" "addsub_1/s1" 19.2392
cap "a_2510_1893#" "addsub_1/addsub_one_2/GND!" 56.78
cap "addsub_1/addsub_one_1/a_35_n41#" "a_2510_1893#" 4.204
cap "latch_5/latch_one_1/Vdd!" "addsub_1/s1" -12.402
cap "addsub_1/addsub_one_2/Vdd!" "ry1" -4.455
cap "wz_addrL1" "addsub_1/addsub_one_2/Vdd!" -4.455
cap "addsub_1/addsub_one_1/a_35_n41#" "addsub_1/addsub_one_2/GND!" 5.68434e-14
cap "wz_addrL1" "addsub_1/addsub_one_1/GND!" 10.505
cap "a_2510_1893#" "addsub_1/addsub_one_1/a_78_n41#" 3.332
cap "a_2510_1893#" "addsub_1/addsub_one_2/cin" 18.533
cap "addsub_1/addsub_one_2/GND!" "ry1" 48.25
cap "wz_addrL1" "addsub_1/addsub_one_2/GND!" 55.484
cap "addsub_1/addsub_one_1/a_35_n41#" "wz_addrL1" 24.622
cap "addsub_1/addsub_one_1/Vdd!" "ry1" 13.563
subcap "a_1776_1628#" -139.302
subcap "a_1716_1625#" -113.013
cap "addsub_1/s1" "wz_addrL1" 4.324
cap "addsub_1/s1" "latch_5/latch_one_1/Vdd!" 19.399
cap "addsub_1/s1" "addsub_1/GND!" 19.2392
cap "latch_5/latch_one_1/a_n5_n54#" "addsub_1/s1" 57.7175
cap "staticizer_2/staticizer_one_1/c" "latch_5/latch_one_1/GND!" -5.68434e-14
cap "wz_addrL1" "latch_5/latch_one_1/a_30_n54#" 1.524
cap "latch_5/out1" "staticizer_2/staticizer_one_1/a_60_n45#" 184.696
cap "wz_addrL1" "latch_5/latch_one_1/c" 67.232
cap "staticizer_2/Vdd!" "wz_addrL1" 58.7
cap "ry1" "latch_5/Vdd!" 58.7
cap "staticizer_2/Vdd!" "latch_5/latch_one_1/Vdd!" -1.23
cap "latch_5/latch_one_1/Vdd!" "latch_5/latch_one_1/c" -1.722
cap "ry1" "staticizer_2/staticizer_one_1/c" 76.935
cap "wz_addrL1" "latch_5/latch_one_1/a_12_n54#" 9.731
cap "latch_5/latch_one_1/a_n5_n54#" "wz_addrL1" 59.375
cap "latch_5/latch_one_1/a_12_n54#" "latch_5/latch_one_1/Vdd!" -3.55271e-15
cap "latch_5/latch_one_1/GND!" "latch_5/latch_one_1/c" 13.8522
cap "staticizer_2/Vdd!" "latch_5/latch_one_1/GND!" -0.984
cap "latch_5/out1" "latch_5/latch_one_1/c" 6.864
cap "wz_addrL1" "latch_5/latch_one_1/GND!" 154.337
cap "ry1" "latch_5/latch_one_1/c" 81.378
cap "latch_5/out1" "staticizer_2/Vdd!" 10.326
cap "ry1" "staticizer_2/Vdd!" 58.7
cap "latch_5/out1" "wz_addrL1" 13.304
cap "staticizer_2/staticizer_one_1/a_77_n45#" "wz_addrL1" 9.998
cap "latch_5/out1" "latch_5/latch_one_1/Vdd!" 53.456
cap "wz_addrL1" "latch_5/Vdd!" 58.7
cap "staticizer_2/staticizer_one_1/a_60_n45#" "wz_addrL1" 12.196
cap "staticizer_2/staticizer_one_1/c" "wz_addrL1" 63.648
cap "ry1" "latch_5/latch_one_1/GND!" 181.284
cap "latch_5/out1" "latch_5/latch_one_1/GND!" 12.91
cap "staticizer_2/Vdd!" "latch_5/latch_one_1/c" 1073
subcap "wz_addrH1" -921.583
subcap "m1_1909_1598#" -380.236
cap "mux_8bit_1/mux_one_2/2mux_nr_0/s" "mux_8bit_1/out1" 0.84
cap "mux_8bit_1/in0_1" "mux_8bit_1/mux_one_1/inv2_2/GND!" 18.437
cap "mux_8bit_1/mux_one_1/inv2_2/GND!" "ry1" 63.013
cap "staticizer_2/staticizer_one_1/out" "wz_addrL1" 2.127
cap "mux_8bit_1/in0_1" "mux_8bit_1/mux_one_1/inv2_2/a_6_n1#" 34.083
cap "staticizer_2/staticizer_one_1/w_54_n57#" "ry1" 4.329
cap "mux_8bit_1/mux_one_2/2mux_nr_0/s" "mux_8bit_1/in0_1" 58.7
cap "staticizer_2/staticizer_one_1/a_60_n45#" "wz_addrL1" -5.616
cap "mux_8bit_1/mux_one_2/2mux_nr_0/s" "ry1" 58.7
cap "ry1" "mux_8bit_1/out1" -10.01
cap "staticizer_2/staticizer_one_1/c" "wz_addrL1" 3.996
cap "staticizer_2/staticizer_one_1/a_95_n27#" "wz_addrL1" 0.561
cap "mux_8bit_1/mux_one_1/inv2_2/Vdd!" "mux_8bit_1/in0_1" 91.282
cap "mux_8bit_1/mux_one_1/inv2_2/a_6_n1#" "mux_8bit_1/mux_one_1/inv2_2/GND!" -1.42109e-14
cap "staticizer_2/staticizer_one_1/a_95_n45#" "wz_addrL1" 4.212
cap "mux_8bit_1/in0_1" "mux_8bit_1/Vdd!" 58.7
cap "mux_8bit_1/mux_one_1/inv2_1/a_1_8#" "mux_8bit_1/in0_1" 4.95
cap "mux_8bit_1/mux_one_1/inv2_2/GND!" "mux_8bit_1/out1" 37.928
cap "mux_8bit_1/Vdd!" "ry1" 58.7
cap "staticizer_2/staticizer_one_1/w_54_n57#" "wz_addrL1" 2.59
cap "staticizer_2/staticizer_one_1/a_77_n45#" "wz_addrL1" 2.084
cap "staticizer_2/staticizer_one_1/Vdd!" "wz_addrL1" 4.776
cap "mux_8bit_1/out1" "ry1" -17.369
cap "mux_8bit_1/out1" "mux_8bit_1/mux_one_1/inv2_1/GND!" 340.759
cap "reg_5/reg_one_6/Vdd!" "ry1" 58.7
cap "wz_addrH1" "mux_8bit_1/out1" -6.325
cap "wz_addrH1" "reg_5/reg_one_6/Vdd!" 162.612
cap "wz_addrH1" "reg_5/port10" 6.6
cap "mux_8bit_1/mux_one_1/inv2_1/GND!" "ry1" -6.916
cap "ry1" "reg_5/reg_one_6/w_n11_n27#" 106.567
cap "wz_addrH1" "reg_5/reg_one_6/w_n11_n27#" 58.7
cap "wz_addrH1" "mux_8bit_1/mux_one_1/inv2_1/GND!" 8.954
cap "wz_addrH1" "reg_5/reg_one_6/tmp" 4.948
cap "mux_8bit_1/out1" "mux_8bit_1/mux_one_2/2mux_nr_0/GND!" 32.46
cap "reg_5/reg_one_6/r1" "ry1" 64.004
cap "wz_addrH1" "reg_5/reg_one_6/a_54_5#" 4.828
cap "mux_8bit_1/out1" "reg_5/reg_one_6/r0" 183.291
cap "wz_addrH1" "reg_5/reg_one_6/r1" 58.7
cap "reg_5/reg_one_6/Vdd!" "reg_5/reg_one_6/r0" 7.10543e-15
cap "reg_5/w" "reg_5/port11" 5.072
cap "mux_8bit_1/mux_one_2/2mux_nr_0/GND!" "ry1" 58.7
cap "ry1" "reg_5/reg_one_6/r0" 48.664
cap "wz_addrH1" "mux_8bit_1/mux_one_2/2mux_nr_0/GND!" 58.7
cap "reg_5/port11" "ry1" 73.199
cap "reg_5/port11" "reg_5/reg_one_6/w_n11_n27#" 1.628
cap "wz_addrH1" "reg_5/reg_one_6/r0" 24.728
cap "wz_addrH1" "reg_5/reg_one_6/a_4_n13#" 27.497
cap "reg_5/port10" "reg_5/w" 67.0625
cap "reg_5/port11" "reg_6/reg_one_6/r1" 58.7
cap "reg_6/reg_one_6/r0" "reg_5/port10" 26.208
cap "reg_6/reg_one_6/w_n11_n27#" "reg_5/port10" 151.215
cap "wz_addrH1" "reg_6/reg_one_6/Vdd!" 10.12
cap "reg_5/w" "wz_addrH1" 58.7
cap "reg_6/reg_one_6/r1" "ry1" 5.304
cap "reg_5/port10" "reg_6/reg_one_6/Vdd!" 58.7
cap "reg_6/reg_one_6/r0" "wz_addrH1" 24.728
cap "ry1" "reg_6/reg_one_6/r1" 58.7
cap "reg_6/reg_one_6/w_n11_n27#" "wz_addrH1" 58.7
cap "reg_6/reg_one_6/port1" "reg_5/port10" 5.5
cap "reg_6/reg_one_6/Vdd!" "wz_addrH1" 150.468
cap "reg_6/reg_one_6/r0" "reg_6/reg_one_6/w_n11_n27#" 1.13687e-13
cap "reg_5/reg_one_6/Vdd!" "wz_addrH1" -2.417
cap "reg_5/port10" "reg_5/reg_one_6/w_n11_n27#" 127.375
cap "reg_6/reg_one_6/r1" "reg_5/port10" 5.804
cap "reg_5/port10" "reg_6/reg_one_6/r1" 58.7
cap "reg_6/reg_one_6/a_4_n13#" "reg_5/port10" 87.672
cap "reg_5/reg_one_6/w_n11_n27#" "wz_addrH1" 8.24
cap "reg_6/reg_one_6/r1" "wz_addrH1" 58.7
cap "reg_6/reg_one_6/tmp" "reg_5/port10" 5.92
cap "reg_6/reg_one_6/a_4_n13#" "wz_addrH1" 17.113
cap "reg_6/reg_one_6/w_n11_n27#" "reg_6/reg_one_6/r1" 3.55271e-15
cap "reg_6/reg_one_6/tmp" "wz_addrH1" 4.948
cap "reg_5/port11" "ry1" -17.146
cap "reg_6/reg_one_6/a_21_n13#" "reg_5/port10" 3.96
cap "reg_5/port11" "reg_5/reg_one_6/w_n11_n27#" 1.628
cap "wz_addrH1" "reg_6/reg_one_6/a_54_5#" 4.828
cap "reg_5/reg_one_6/w_n11_n27#" "ry1" -2.667
cap "reg_5/port11" "reg_5/w" 69.0435
cap "reg_5/port11" "reg_6/reg_one_6/r0" 19.78
cap "reg_5/port11" "reg_6/reg_one_6/w_n11_n27#" 83.267
cap "reg_5/port11" "reg_6/reg_one_6/Vdd!" 58.7
cap "ry1" "reg_5/w" 58.7
cap "reg_6/reg_one_6/r0" "ry1" 48.664
cap "reg_6/reg_one_6/w_n11_n27#" "ry1" 101.233
cap "reg_6/reg_one_6/Vdd!" "ry1" 58.7
cap "reg_5/port11" "reg_5/reg_one_6/w_n11_n27#" 12.7375
cap "reg_6/reg_one_6/port1" "ry1" 68.579
subcap "m1_2209_1598#" -380.236
cap "rx_addrH1" "reg_6/reg_one_6/w_n11_n27#" -2.286
cap "reg_6/w" "reg_6/reg_one_6/Vdd!" 8.88178e-16
cap "mux_8bit_2/in0_1" "reg_6/reg_one_6/w_n11_n27#" 8.24
cap "rx_addrH1" "reg_6/reg_one_6/w_n11_n27#" 19.776
cap "ry_addrH1" "reg_6/reg_one_6/w_n11_n27#" 0.019
cap "mux_8bit_2/in0_1" "mux_8bit_2/Vdd!" 58.7
cap "mux_8bit_2/in0_1" "reg_6/reg_one_6/a_4_n13#" -1.152
cap "mux_8bit_2/Vdd!" "rx_addrH1" 58.7
cap "reg_6/reg_one_6/a_4_n13#" "rx_addrH1" -10.448
cap "mux_8bit_2/mux_one_1/inv2_2/a_6_n1#" "mux_8bit_2/in0_1" 34.083
cap "mux_8bit_2/mux_one_1/inv2_2/a_6_n1#" "rx_addrH1" 30.259
cap "reg_6/w" "rx_addrH1" 58.7
cap "reg_6/w" "mux_8bit_2/in0_1" 58.7
cap "reg_6/port11" "reg_6/reg_one_6/w_n11_n27#" 4.295
cap "mux_8bit_2/mux_one_1/inv2_2/GND!" "mux_8bit_2/out1" 37.928
cap "mux_8bit_2/Vdd!" "ry_addrH1" 58.7
cap "mux_8bit_2/in0_1" "mux_8bit_2/mux_one_1/inv2_2/GND!" 18.437
cap "reg_6/port11" "reg_6/reg_one_6/w_n11_n27#" 12.7375
cap "mux_8bit_2/mux_one_1/inv2_2/GND!" "rx_addrH1" 22.523
cap "reg_6/w" "ry_addrH1" 58.7
cap "reg_6/port11" "mux_8bit_2/Vdd!" 58.7
cap "mux_8bit_2/in0_1" "mux_8bit_2/mux_one_1/inv2_1/a_1_8#" 4.95
cap "mux_8bit_2/in0_1" "mux_8bit_2/mux_one_1/inv2_2/Vdd!" 81.239
cap "mux_8bit_2/mux_one_1/inv2_2/Vdd!" "rx_addrH1" 17.542
cap "reg_6/port11" "reg_6/w" 127.744
cap "mux_8bit_2/mux_one_2/2mux_nr_0/s" "mux_8bit_2/out1" 0.84
cap "mux_8bit_2/in0_1" "reg_6/reg_one_6/Vdd!" -0.393
cap "rx_addrH1" "mux_8bit_2/mux_one_2/2mux_nr_0/s" 58.7
cap "mux_8bit_2/in0_1" "mux_8bit_2/mux_one_2/2mux_nr_0/s" 58.7
cap "reg_6/port11" "mux_8bit_2/mux_one_1/inv2_2/GND!" 63.013
cap "ry_addrH1" "mux_8bit_2/mux_one_2/2mux_nr_0/s" 58.7
cap "rx_addrH1" "mux_8bit_2/out1" 19.905
cap "reg_6/reg_one_6/Vdd!" "reg_6/port10" -7.10543e-15
cap "mux_8bit_2/in0_1" "rx_addrH1" 16.569
cap "reg_6/port11" "mux_8bit_2/mux_one_2/2mux_nr_0/s" 58.7
cap "rx_addrH1" "reg_6/port10" 4.411
cap "mux_8bit_2/in0_1" "reg_6/port10" 3.171
cap "reg_6/port11" "mux_8bit_2/out1" -10.01
cap "reg_7/reg_one_6/r0" "ry1" 48.664
cap "reg_7/reg_one_6/a_54_5#" "wz_addrH1" 4.828
cap "ry_addrH1" "reg_7/reg_one_6/Vdd!" 58.7
cap "mux_8bit_2/out1" "rx_addrH1" -6.325
cap "wz_addrH1" "reg_7/reg_one_6/r1" 58.7
cap "reg_7/port11" "rx_addrH1" 5.5
cap "reg_7/reg_one_6/a_4_n13#" "rx_addrH1" 93.704
cap "reg_7/reg_one_6/r0" "ry_addrH1" 19.78
cap "wz_addrH1" "reg_7/reg_one_6/Vdd!" 162.612
cap "mux_8bit_2/mux_one_2/2mux_nr_0/GND!" "ry1" 58.7
cap "reg_7/reg_one_6/w_n11_n27#" "rx_addrH1" 163.513
cap "reg_7/port10" "wz_addrH1" 6.6
cap "reg_7/reg_one_6/r0" "mux_8bit_2/out1" 183.291
cap "ry1" "mux_8bit_2/mux_one_1/inv2_1/GND!" -6.916
cap "reg_7/reg_one_6/r0" "wz_addrH1" 24.728
cap "mux_8bit_2/mux_one_2/2mux_nr_0/GND!" "ry_addrH1" 58.7
cap "reg_7/reg_one_6/a_21_n13#" "rx_addrH1" 3.96
cap "rx_addrH1" "reg_7/reg_one_6/r1" 64.504
cap "ry1" "mux_8bit_2/out1" -17.369
cap "ry1" "reg_7/port11" 73.199
cap "mux_8bit_2/mux_one_2/2mux_nr_0/GND!" "mux_8bit_2/out1" 32.46
cap "reg_7/reg_one_6/Vdd!" "rx_addrH1" 58.7
cap "reg_7/reg_one_6/tmp" "wz_addrH1" 4.948
cap "mux_8bit_2/mux_one_2/2mux_nr_0/GND!" "wz_addrH1" 58.7
cap "ry1" "reg_7/reg_one_6/w_n11_n27#" 106.567
cap "reg_7/port10" "rx_addrH1" 6.006
cap "mux_8bit_2/mux_one_1/inv2_1/GND!" "mux_8bit_2/out1" 340.759
cap "wz_addrH1" "mux_8bit_2/mux_one_1/inv2_1/GND!" 8.954
cap "reg_7/reg_one_6/r0" "rx_addrH1" 26.208
cap "ry1" "reg_7/reg_one_6/r1" 64.004
cap "reg_7/reg_one_6/r0" "reg_7/reg_one_6/Vdd!" 7.10543e-15
cap "ry_addrH1" "reg_7/reg_one_6/w_n11_n27#" 86.284
cap "wz_addrH1" "mux_8bit_2/out1" -6.325
cap "reg_7/reg_one_6/tmp" "rx_addrH1" 5.92
cap "reg_7/w" "reg_7/port11" 5.072
cap "ry1" "reg_7/reg_one_6/Vdd!" 58.7
cap "mux_8bit_2/mux_one_2/2mux_nr_0/GND!" "rx_addrH1" 58.7
cap "reg_7/reg_one_6/a_4_n13#" "wz_addrH1" 27.497
cap "wz_addrH1" "reg_7/reg_one_6/w_n11_n27#" 58.7
cap "ry_addrH1" "reg_7/reg_one_6/r1" 58.7
cap "reg_7/reg_one_6/w_n11_n27#" "reg_7/port11" 1.628
cap "mux_8bit_2/mux_one_1/inv2_1/GND!" "rx_addrH1" 12.194
cap "addsub_2/b1" "reg_7/port11" 11.825
cap "addsub_2/b1" "reg_7/port10" 36.385
cap "addsub_2/sub" "ry1" 11.825
cap "addsub_2/b1" "wz_addrH1" 5.939
cap "addsub_2/b1" "ry1" 11.825
cap "addsub_2/b1" "addsub_2/xor_1/GND!" -1.77636e-15
cap "reg_7/w" "reg_7/port11" 127.744
cap "reg_7/w" "reg_7/port10" 125.763
cap "reg_7/w" "wz_addrH1" 58.7
cap "reg_7/w" "ry1" 58.7
cap "addsub_2/Vdd!" "reg_7/port11" 11.825
cap "reg_7/port11" "ry1" -17.146
cap "addsub_2/Vdd!" "wz_addrH1" 11.825
cap "addsub_2/Vdd!" "ry1" 11.825
cap "reg_7/port10" "addsub_2/addsub_one_1/Vdd!" 0.872
cap "reg_7/port11" "reg_7/reg_one_6/w_n11_n27#" 12.7375
cap "reg_7/port10" "reg_7/reg_one_6/w_n11_n27#" 135.615
cap "reg_7/reg_one_6/Vdd!" "wz_addrH1" -2.417
cap "wz_addrH1" "reg_7/reg_one_6/w_n11_n27#" 8.24
cap "reg_7/reg_one_6/w_n11_n27#" "reg_7/port11" -1.37
cap "reg_7/port10" "reg_7/reg_one_6/w_n11_n27#" -3.048
cap "reg_7/reg_one_6/w_n11_n27#" "ry1" -2.667
cap "addsub_2/sub" "reg_7/port11" 11.825
cap "addsub_2/sub" "reg_7/port10" 113.342
cap "addsub_2/sub" "wz_addrH1" 11.825
subcap "a_2516_1625#" -30.357
cap "addsub_2/addsub_one_2/Vdd!" "wz_addrH1" -4.455
cap "addsub_2/addsub_one_1/a_35_n41#" "addsub_2/addsub_one_2/GND!" 5.68434e-14
cap "addsub_2/addsub_one_2/cin" "ry_addrH1" 2.474
cap "addsub_2/addsub_one_1/Vdd!" "wz_addrH1" 27.16
cap "wz_addrH1" "addsub_2/addsub_one_1/a_35_n41#" 19.78
cap "ry_addrH1" "addsub_2/addsub_one_2/GND!" 45.221
cap "addsub_2/addsub_one_2/Vdd!" "ry_addrH1" -4.455
cap "addsub_2/addsub_one_2/cin" "ry1" 20.38
cap "ry1" "addsub_2/addsub_one_2/GND!" 52.81
cap "addsub_2/s1" "latch_6/latch_one_1/Vdd!" -12.402
cap "addsub_2/addsub_one_2/Vdd!" "ry1" -4.455
cap "addsub_2/addsub_one_1/GND!" "wz_addrH1" 4.95
cap "wz_addrH1" "addsub_2/addsub_one_2/GND!" 39.409
cap "addsub_2/s1" "addsub_2/addsub_one_2/GND!" 76.9567
cap "ry1" "addsub_2/addsub_one_1/Vdd!" 13.563
cap "addsub_2/s1" "latch_6/latch_one_1/a_n5_n54#" 19.2392
cap "addsub_2/s1" "wz_addrH1" 50.259
subcap "a_2575_1628#" -139.7
subcap "a_2516_1625#" -113.013
cap "staticizer_3/Vdd!" "ry_addrH1" 58.7
cap "latch_6/out1" "latch_6/latch_one_1/GND!" 10.156
cap "staticizer_3/staticizer_one_1/c" "latch_6/latch_one_1/GND!" 5.68434e-14
cap "staticizer_3/staticizer_one_1/out" "latch_6/latch_one_1/GND!" 117.4
cap "latch_6/latch_one_1/Vdd!" "latch_6/latch_one_1/a_12_n54#" -3.55271e-15
cap "staticizer_3/staticizer_one_1/out" "latch_6/latch_one_1/a_30_n35#" 1.88
cap "latch_6/latch_one_1/c" "ry1" 81.378
cap "staticizer_3/staticizer_one_1/out" "latch_6/Vdd!" 58.7
cap "ry_addrH1" "latch_6/latch_one_1/GND!" 117.4
cap "staticizer_3/staticizer_one_1/out" "staticizer_3/staticizer_one_1/a_77_n45#" 5.115
cap "staticizer_3/staticizer_one_1/out" "addsub_2/s1" 6.404
cap "ry_addrH1" "latch_6/Vdd!" 58.7
cap "staticizer_3/staticizer_one_1/a_60_n45#" "latch_6/out1" 138.522
cap "staticizer_3/staticizer_one_1/out" "latch_6/latch_one_1/a_12_n54#" 4.208
cap "staticizer_3/staticizer_one_1/out" "latch_6/latch_one_1/a_n5_n54#" 59.464
cap "staticizer_3/staticizer_one_1/c" "ry1" 76.935
cap "addsub_2/GND!" "addsub_2/s1" 19.2392
cap "staticizer_3/staticizer_one_1/out" "staticizer_3/staticizer_one_1/a_60_n45#" 75.3524
cap "staticizer_3/Vdd!" "ry1" 58.7
cap "staticizer_3/staticizer_one_1/out" "latch_6/latch_one_1/a_12_n54#" 5.5
cap "latch_6/latch_one_1/Vdd!" "latch_6/latch_one_1/c" -2.254
cap "latch_6/out1" "latch_6/latch_one_1/Vdd!" 58.27
cap "ry1" "latch_6/latch_one_1/GND!" 181.284
cap "latch_6/out1" "latch_6/latch_one_1/c" 8.034
cap "staticizer_3/staticizer_one_1/out" "latch_6/latch_one_1/Vdd!" 38.093
cap "staticizer_3/staticizer_one_1/out" "latch_6/latch_one_1/Vdd!" 14.113
cap "latch_6/latch_one_1/a_n5_n54#" "addsub_2/s1" 57.7175
cap "staticizer_3/staticizer_one_1/out" "latch_6/latch_one_1/c" 61.66
cap "ry1" "latch_6/Vdd!" 58.7
cap "staticizer_3/Vdd!" "latch_6/latch_one_1/c" 1073
cap "latch_6/latch_one_1/c" "ry_addrH1" 58.7
cap "staticizer_3/staticizer_one_1/out" "latch_6/out1" 7.047
cap "staticizer_3/staticizer_one_1/out" "staticizer_3/staticizer_one_1/c" 61.544
cap "staticizer_3/staticizer_one_1/out" "staticizer_3/Vdd!" 58.7
cap "latch_6/latch_one_1/c" "latch_6/latch_one_1/GND!" 13.8522
cap "staticizer_3/staticizer_one_1/c" "ry_addrH1" 58.7
cap "latch_6/latch_one_1/Vdd!" "addsub_2/s1" 19.399
subcap "addr_out1" -139.7
cap "latch_7/in1" "staticizer_3/staticizer_one_1/w_54_n57#" 17.972
cap "staticizer_3/staticizer_one_1/w_54_n57#" "staticizer_3/staticizer_one_1/c" -1.42109e-14
cap "ry_addrH1" "latch_7/latch_one_1/c" 58.7
cap "staticizer_3/staticizer_one_1/out" "staticizer_3/staticizer_one_1/a_77_n45#" 2.728
cap "staticizer_3/staticizer_one_1/out" "staticizer_3/staticizer_one_1/Vdd!" 6.001
cap "latch_7/out1" "latch_7/latch_one_1/GND!" 10.156
cap "latch_7/out1" "latch_7/latch_one_1/Vdd!" 58.27
cap "latch_7/latch_one_1/GND!" "latch_7/latch_one_1/c" 13.8522
cap "latch_7/latch_one_1/Vdd!" "latch_7/latch_one_1/c" -2.254
cap "latch_7/in1" "staticizer_3/staticizer_one_1/Vdd!" 11.463
cap "latch_7/latch_one_1/a_n5_n54#" "latch_7/in1" 57.7175
cap "latch_7/out1" "staticizer_4/staticizer_one_1/a_60_n45#" 138.522
cap "latch_7/latch_one_1/GND!" "ry_addrH1" 77.41
cap "staticizer_3/staticizer_one_1/a_60_n45#" "staticizer_3/staticizer_one_1/out" 0.709429
cap "latch_7/latch_one_1/Vdd!" "latch_7/latch_one_1/a_12_n54#" -3.55271e-15
cap "staticizer_4/Vdd!" "latch_7/latch_one_1/c" 1073
cap "latch_7/latch_one_1/GND!" "latch_7/latch_one_1/Vdd!" 4.44089e-16
cap "ry_addrH1" "latch_7/Vdd!" 58.7
cap "latch_7/in1" "staticizer_3/staticizer_one_1/out" 23.087
cap "latch_7/latch_one_1/GND!" "latch_7/in1" 6.956
cap "latch_7/in1" "latch_7/latch_one_1/Vdd!" 9.594
cap "staticizer_3/staticizer_one_1/a_77_n45#" "staticizer_3/staticizer_one_1/Vdd!" -3.55271e-15
cap "latch_7/latch_one_1/GND!" "staticizer_4/staticizer_one_1/a_60_n45#" 5.68434e-14
cap "staticizer_4/Vdd!" "ry_addrH1" 58.7
cap "staticizer_3/staticizer_one_1/w_54_n57#" "staticizer_3/staticizer_one_1/out" 8.272
cap "latch_7/out1" "latch_7/latch_one_1/c" 8.034
cap "latch_7/in1" "latch_7/Vdd!" 277.192
subcap "ry_addrH1" -850.11
subcap "addr_out9" -154.002
cap "staticizer_4/staticizer_one_1/Vdd!" "staticizer_4/staticizer_one_1/a_77_n45#" -3.55271e-15
cap "latch_8/in1" "latch_8/latch_one_1/Vdd!" 9.594
cap "latch_8/in1" "staticizer_4/staticizer_one_1/c" 58.7
cap "staticizer_4/staticizer_one_1/Vdd!" "latch_8/in1" 11.463
cap "latch_8/in1" "latch_8/Vdd!" 357.667
cap "latch_8/latch_one_1/c" "latch_8/latch_one_1/Vdd!" -7.10543e-15
cap "staticizer_4/staticizer_one_1/a_60_n45#" "staticizer_4/staticizer_one_1/w_54_n57#" 2.84217e-14
cap "latch_8/latch_one_1/a_12_n54#" "latch_8/latch_one_1/Vdd!" -3.55271e-15
cap "latch_8/in1" "staticizer_4/staticizer_one_1/out" 57.7175
cap "latch_8/in1" "latch_8/latch_one_1/a_n5_n54#" 57.7175
cap "latch_8/in1" "staticizer_5/staticizer_one_1/w_54_n57#" 6.956
cap "latch_8/in1" "staticizer_4/staticizer_one_1/w_54_n57#" 21.105
subcap "addr_out9" -99.76
cap "staticizer_5/in1" "staticizer_5/staticizer_one_1/w_54_n57#" 10.156
cap "latch_8/latch_one_1/c" "latch_8/latch_one_1/Vdd!" -2.254
cap "latch_8/latch_one_1/c" "staticizer_5/in1" 8.034
cap "staticizer_5/staticizer_one_1/a_60_n45#" "staticizer_5/in1" 138.522
cap "latch_8/latch_one_1/c" "staticizer_5/staticizer_one_1/w_54_n57#" 13.8522
cap "latch_8/latch_one_1/Vdd!" "staticizer_5/in1" 58.27
cap "latch_8/latch_one_1/c" "staticizer_5/Vdd!" 1073
subcap "a_n24_1624#" -34.788
cap "staticizer_1/staticizer_one_1/Vdd!" "staticizer_1/GND!" 170.22
cap "staticizer_1/in1" "staticizer_1/staticizer_one_1/Vdd!" 46.32
cap "staticizer_1/staticizer_one_1/Vdd!" "latch_4/GND!" 70.212
cap "staticizer_1/staticizer_one_1/Vdd!" "staticizer_1/c" 170.22
cap "staticizer_1/staticizer_one_1/Vdd!" "latch_4/c" 1243.22
subcap "a_109_1624#" -101.818
subcap "data_in1" -72.606
subcap "rx1" -1944
cap "latch_0/out1" "latch_4/latch_one_1/Vdd!" 46.32
cap "latch_4/in1" "latch_4/latch_one_1/a_n5_n54#" 13.1926
cap "latch_0/in1" "latch_0/latch_one_1/a_n5_n54#" 13.1926
cap "latch_4/latch_one_1/Vdd!" "latch_0/in1" 67.0625
cap "latch_4/latch_one_1/Vdd!" "latch_0/latch_one_1/a_12_n54#" -1.13687e-13
cap "latch_0/c" "latch_4/latch_one_1/Vdd!" 1243.22
cap "latch_4/GND!" "latch_4/latch_one_1/Vdd!" 65.88
cap "latch_0/GND!" "latch_4/latch_one_1/Vdd!" 170.22
subcap "wz1" -2689.16
cap "latch_0/out1" "staticizer_0/staticizer_one_1/Vdd!" 11.025
cap "staticizer_0/staticizer_one_1/Vdd!" "shift_0/shift_one_1/au" 170.22
cap "staticizer_0/staticizer_one_1/Vdd!" "shift_0/a1" 170.22
cap "staticizer_0/staticizer_one_1/Vdd!" "staticizer_0/c" 170.22
cap "staticizer_0/staticizer_one_1/Vdd!" "staticizer_0/GND!" 170.22
cap "shift_0/shift_one_1/u" "shift_0/shift_one_1/2mux_nr_1/Vdd!" 170.22
cap "shift_0/shift_one_1/GND!" "shift_0/shift_one_1/2mux_nr_1/Vdd!" 170.22
cap "shift_0/shift_one_1/2mux_nr_1/out" "latch_3/in1" 16.4907
cap "latch_3/GND!" "latch_3/latch_one_1/Vdd!" 170.22
cap "shift_0/shift_one_1/2mux_nr_1/out" "latch_3/latch_one_1/Vdd!" 46.174
cap "shift_0/shift_one_1/s" "latch_3/latch_one_1/Vdd!" 170.22
cap "fblock_0/a1" "fblock_0/g2" 25.865
cap "fblock_0/g3" "fblock_0/b1" 140.424
cap "fblock_0/a1" "fblock_0/fblock_one_1/2mux_nr_2/a_n17_n11#" 2.667
cap "Vdd!" "fblock_0/g3" 170.22
cap "fblock_0/g2" "fblock_0/b1" 58.7
cap "fblock_0/a1" "fblock_0/fblock_one_1/2mux_nr_2/Vdd!" 95.38
cap "latch_3/latch_one_1/Vdd!" "latch_3/latch_one_1/a_12_n54#" 1.42109e-14
cap "fblock_0/b1" "fblock_0/fblock_one_1/2mux_nr_1/Vdd!" 11.239
cap "Vdd!" "fblock_0/fblock_one_1/inv_1/in" 4.948
cap "Vdd!" "fblock_0/fblock_one_1/2mux_nr_1/Vdd!" 25.24
cap "fblock_0/b1" "fblock_0/fblock_one_1/2mux_nr_0/out" 11.825
cap "Vdd!" "fblock_0/g2" 170.22
cap "fblock_0/fblock_one_1/2mux_nr_0/in1" "fblock_0/b1" 4.95
cap "Vdd!" "fblock_0/fblock_one_1/GND!" 90.345
cap "Vdd!" "fblock_0/fblock_one_1/inv_2/out" 1.549
cap "Vdd!" "fblock_0/fblock_one_1/2mux_nr_0/in1" 65.12
cap "Vdd!" "fblock_0/fblock_one_1/inv_2/in" 4.948
cap "fblock_0/fblock_one_1/2mux_nr_1/GND!" "fblock_0/fblock_one_1/2mux_nr_2/Vdd!" -2.536
cap "Vdd!" "fblock_0/fblock_one_1/inv_1/out" 3.657
cap "fblock_0/a1" "fblock_0/fblock_one_1/2mux_nr_1/GND!" 34.601
cap "fblock_0/a1" "fblock_0/fblock_one_1/2mux_nr_2/out" 1.485
cap "fblock_0/fblock_one_1/2mux_nr_0/in0" "fblock_0/b1" 7.975
cap "Vdd!" "fblock_0/fblock_one_1/2mux_nr_0/in0" 31.288
cap "fblock_0/b1" "fblock_0/fblock_one_1/2mux_nr_0/a_n17_n11#" 33.597
cap "fblock_0/fblock_one_1/2mux_nr_1/GND!" "fblock_0/b1" 68.584
cap "Vdd!" "fblock_0/fblock_one_1/2mux_nr_1/GND!" 170.22
cap "fblock_0/a1" "fblock_0/g3" 25.865
cap "Vdd!" "latch_3/c" 170.22
cap "ry1" "fblock_0/fblock_one_1/inv_3/GND!" 24.128
cap "fblock_0/fblock_one_1/inv_3/GND!" "latch_1/latch_one_1/Vdd!" 105.001
cap "rx1" "latch_1/latch_one_1/a_n5_n54#" 5.971
cap "ry1" "fblock_0/fblock_one_1/2mux_nr_1/out" 11.825
cap "fblock_0/fblock_one_1/inv_4/in" "latch_1/latch_one_1/Vdd!" 2.764
cap "ry1" "fblock_0/g1" 58.7
cap "ry1" "latch_1/latch_one_1/Vdd!" 117.4
cap "rx1" "fblock_0/g1" 37.79
cap "fblock_0/g1" "latch_1/latch_one_1/Vdd!" 170.22
cap "rx1" "latch_1/latch_one_1/Vdd!" 129.97
cap "fblock_0/fblock_one_1/2mux_nr_1/a_n17_n11#" "ry1" 31.949
cap "ry1" "fblock_0/fblock_one_1/f" 25.152
cap "latch_1/latch_one_1/Vdd!" "fblock_0/fblock_one_1/f" 86.807
cap "rx1" "fblock_0/fblock_one_1/f" 86.768
cap "rx1" "fblock_0/f1" 4.579
cap "fblock_0/fblock_one_1/inv_4/out" "latch_1/latch_one_1/Vdd!" 1.144
cap "fblock_0/fblock_one_1/inv_3/in" "latch_1/latch_one_1/Vdd!" 4.948
cap "rx1" "latch_1/latch_one_1/a_12_n54#" 2.475
cap "ry1" "fblock_0/fblock_one_1/2mux_nr_1/in1" 4.95
cap "fblock_0/fblock_one_1/2mux_nr_1/in1" "latch_1/latch_one_1/Vdd!" 72.864
cap "fblock_0/fblock_one_1/2mux_nr_1/in0" "ry1" 2.75
cap "fblock_0/fblock_one_1/2mux_nr_1/in0" "latch_1/latch_one_1/Vdd!" 36.993
cap "ry1" "fblock_0/fblock_one_1/2mux_nr_1/s" 16.386
cap "fblock_0/g0" "ry1" 58.7
cap "fblock_0/fblock_one_1/inv_3/out" "latch_1/latch_one_1/Vdd!" 3.657
cap "latch_1/GND!" "ry1" 58.7
cap "rx1" "fblock_0/g0" 37.79
cap "fblock_0/g0" "latch_1/latch_one_1/Vdd!" 170.22
cap "latch_1/GND!" "rx1" 37.79
cap "latch_1/GND!" "latch_1/latch_one_1/Vdd!" 170.22
subcap "ry1" -2648.81
cap "addsub_0/xor_1/b" "rx1" 7.7
cap "addsub_0/xor_1/GND!" "rx1" 18.763
cap "addsub_0/b1" "addsub_0/xor_1/a_100_n42#" 0.707
cap "latch_1/c" "rx1" 37.79
cap "addsub_0/b1" "addsub_0/xor_1/out" 31.486
cap "latch_1/latch_one_1/Vdd!" "rx1" 6.296
cap "addsub_0/xor_1/a_61_n31#" "addsub_0/b1" 7.218
cap "Vdd!" "addsub_0/xor_1/b" 33.825
cap "addsub_0/b1" "addsub_0/xor_1/a_69_n42#" 2.457
cap "latch_1/latch_one_1/out" "rx1" 8.906
cap "rx1" "latch_1/latch_one_1/a_n5_n54#" 2.728
cap "addsub_0/xor_1/GND!" "Vdd!" 33.825
cap "addsub_0/b1" "addsub_0/xor_1/b" 15.993
cap "latch_1/latch_one_1/a_12_n54#" "rx1" 2.728
cap "addsub_0/xor_1/GND!" "addsub_0/b1" 79.1547
cap "addsub_0/xor_1/Vdd!" "rx1" 7.696
cap "latch_1/c" "Vdd!" 170.22
cap "addsub_0/b1" "rx1" 14.691
cap "latch_1/c" "addsub_0/b1" 58.7
cap "latch_1/latch_one_1/a_30_n35#" "rx1" 3.76
cap "latch_1/latch_one_1/Vdd!" "rx1" -7.631
cap "addsub_0/b1" "addsub_0/xor_1/a_89_n31#" 3.068
subcap "Vdd!" -3273.94
cap "addsub_0/xor_1/Vdd!" "addsub_0/addsub_one_1/a_11_9#" 90.388
cap "addsub_0/addsub_one_1/b" "as_cout" 16.816
cap "addsub_0/addsub_one_1/a_29_n41#" "as_cout" 2.1
cap "as_cout" "addsub_0/addsub_one_1/a_66_n41#" 2.1
cap "addsub_0/addsub_one_1/a_89_9#" "addsub_0/a1" 4.7
cap "addsub_0/addsub_one_1/GND!" "addsub_0/a1" 19.773
cap "as_cout" "addsub_0/addsub_one_1/a_89_n41#" 22.875
cap "addsub_0/a1" "addsub_0/xor_1/a" 2.424
cap "addsub_0/xor_1/a_61_n1#" "addsub_0/a1" 141.539
cap "addsub_0/xor_1/Vdd!" "addsub_0/addsub_one_1/a_29_9#" 3.56
cap "addsub_0/addsub_one_1/GND!" "addsub_0/xor_1/Vdd!" 24.637
cap "as_cout" "addsub_0/addsub_one_1/a_78_n41#" 14.192
cap "addsub_0/xor_1/b" "addsub_0/a1" 2.424
cap "addsub_0/xor_1/a_89_n31#" "addsub_0/a1" 2.424
cap "addsub_0/addsub_one_1/a_35_n41#" "as_cout" 14.854
cap "addsub_0/xor_1/Vdd!" "addsub_0/a1" 223.633
cap "addsub_0/xor_1/Vdd!" "addsub_0/addsub_one_1/cin" 33.924
cap "addsub_0/addsub_one_1/a_11_n41#" "addsub_0/xor_1/Vdd!" 63.533
cap "addsub_0/addsub_one_1/b" "addsub_0/a1" 94.487
cap "addsub_0/addsub_one_1/b" "addsub_0/xor_1/Vdd!" 38.168
cap "addsub_0/addsub_one_1/GND!" "addsub_0/addsub_one_1/a_35_n41#" 2.27374e-13
cap "addsub_0/addsub_one_1/GND!" "as_cout" 63.816
cap "addsub_0/addsub_one_1/a_78_n41#" "addsub_0/a1" 11.825
cap "addsub_0/xor_1/a_61_n31#" "addsub_0/a1" 2.424
cap "as_cout" "addsub_0/addsub_one_1/a_72_n41#" 2.1
cap "addsub_0/addsub_one_1/a_35_n41#" "addsub_0/a1" 19.78
cap "as_cout" "addsub_0/a1" 8.408
cap "addsub_0/xor_1/Vdd!" "addsub_0/addsub_one_1/a_35_n41#" 80.98
cap "as_cout" "addsub_0/addsub_one_1/cin" 12.612
cap "addsub_0/addsub_one_1/a_11_n41#" "as_cout" 11.28
subcap "a_841_1625#" -197.328
cap "rx1" "latch_2/c" 58.7
cap "latch_2/latch_one_1/a_30_n35#" "rx1" 1.524
cap "latch_2/latch_one_1/Vdd!" "addsub_0/addsub_one_1/cin" 8.684
cap "addsub_0/addsub_one_1/GND!" "rx1" 24.915
cap "reg_0/r0" "latch_2/out1" 153.495
cap "latch_2/latch_one_1/Vdd!" "addsub_0/addsub_one_1/a" 0.312
cap "latch_2/latch_one_1/c" "rx1" 2.844
cap "latch_2/latch_one_1/Vdd!" "reg_0/r0" 56.708
cap "latch_2/c" "latch_2/out1" 482.85
cap "rx1" "latch_2/out1" 4.341
cap "latch_2/latch_one_1/Vdd!" "latch_2/GND!" 170.22
cap "latch_2/latch_one_1/Vdd!" "addsub_0/addsub_one_1/b" -2.068
cap "latch_2/latch_one_1/Vdd!" "latch_2/c" 170.22
cap "rx1" "addsub_0/s1" 3.468
cap "reg_0/r0" "rx1" 19.78
cap "latch_2/latch_one_1/Vdd!" "rx1" 116.636
cap "rx1" "latch_2/latch_one_1/a_n5_n54#" 6.195
cap "latch_2/latch_one_1/Vdd!" "addsub_0/addsub_one_1/GND!" 82.417
cap "rx1" "addsub_0/addsub_one_1/b" -2.068
cap "latch_2/GND!" "rx1" 58.7
cap "latch_2/latch_one_1/a_12_n54#" "rx1" 37.778
cap "reg_0/reg_one_6/a_33_32#" "wz1" 65.474
cap "reg_0/reg_one_6/tmp" "wz1" 8.713
cap "wz1" "reg_0/reg_one_6/Vdd!" 165.083
cap "reg_0/reg_one_6/w" "wz1" 63.082
cap "rx1" "reg_0/reg_one_6/a_21_n13#" 20.118
cap "reg_0/reg_one_6/r1" "reg_0/reg_one_6/Vdd!" 170.22
cap "reg_0/r0" "reg_0/reg_one_6/Vdd!" -7.416
cap "rx1" "reg_0/GND!" 58.7
cap "rx1" "reg_0/reg_one_6/w_n11_n27#" 8.24
cap "reg_0/reg_one_6/w" "reg_0/reg_one_6/Vdd!" 170.22
cap "wz1" "reg_0/GND!" 58.7
cap "wz1" "reg_0/reg_one_6/w_n11_n27#" 8.24
cap "reg_0/reg_one_6/r1" "rx1" 70.642
cap "wz1" "reg_0/reg_one_6/a_16_27#" 8.264
cap "reg_0/r0" "rx1" -7.416
cap "reg_1/r0" "wz1" 63.6875
cap "reg_0/reg_one_6/tmp" "rx1" 4.948
cap "reg_0/reg_one_6/Vdd!" "reg_0/GND!" 170.22
cap "reg_0/reg_one_6/w" "rx1" 219.65
cap "reg_0/reg_one_6/Vdd!" "rx1" 134.044
cap "wz1" "reg_0/in1" 14.786
cap "reg_0/reg_one_6/a_4_n13#" "rx1" 20.417
cap "reg_0/r0" "wz1" -7.416
cap "reg_0/reg_one_6/r1" "wz1" 58.7
cap "reg_0/r0" "reg_0/in1" -5.072
cap "reg_1/r0" "reg_1/reg_one_6/Vdd!" 56.708
cap "reg_1/reg_one_6/Vdd!" "reg_1/in1" 165.083
cap "reg_1/reg_one_6/a_16_27#" "reg_1/in1" 8.264
cap "reg_1/in1" "reg_1/reg_one_6/w_n11_n27#" 8.24
cap "reg_1/reg_one_6/Vdd!" "reg_1/GND!" 170.22
cap "reg_1/in1" "reg_1/reg_one_6/r1" 58.7
cap "reg_1/r0" "reg_1/in1" 89.8075
cap "reg_1/in1" "reg_1/reg_one_6/tmp" 8.713
cap "reg_1/reg_one_6/w" "reg_1/reg_one_6/Vdd!" 170.22
cap "reg_1/in1" "reg_1/GND!" 58.7
cap "reg_1/reg_one_6/w" "reg_1/in1" 63.082
cap "reg_1/in1" "reg_1/reg_one_6/a_33_32#" 65.474
cap "reg_1/reg_one_6/Vdd!" "reg_1/reg_one_6/r1" 170.22
cap "reg_2/in1" "reg_2/reg_one_6/Vdd!" 165.083
cap "reg_2/r0" "reg_2/in1" 153.495
cap "reg_2/reg_one_6/a_16_27#" "reg_2/in1" 8.264
cap "reg_2/reg_one_6/w" "reg_2/reg_one_6/Vdd!" 170.22
cap "reg_2/reg_one_6/r1" "reg_2/in1" 58.7
cap "reg_2/GND!" "reg_2/in1" 58.7
cap "reg_2/r0" "reg_2/reg_one_6/Vdd!" 56.708
cap "reg_2/reg_one_6/a_33_32#" "reg_2/in1" 65.474
cap "reg_2/GND!" "reg_2/reg_one_6/Vdd!" 170.22
cap "reg_2/reg_one_6/r1" "reg_2/reg_one_6/Vdd!" 170.22
cap "reg_2/reg_one_6/w" "reg_2/in1" 63.082
cap "reg_2/reg_one_6/tmp" "reg_2/in1" 8.713
cap "reg_2/reg_one_6/w_n11_n27#" "reg_2/in1" 8.24
cap "reg_3/in1" "reg_3/reg_one_6/w" 1.248
cap "reg_3/reg_one_6/a_33_32#" "reg_3/in1" 39.098
cap "reg_3/reg_one_6/w_n11_n27#" "reg_3/in1" 17.302
cap "reg_3/r0" "reg_3/reg_one_6/Vdd!" 56.708
cap "reg_3/reg_one_6/r1" "reg_3/reg_one_6/Vdd!" 170.22
cap "reg_3/reg_one_6/Vdd!" "reg_3/in1" 75.24
cap "reg_3/reg_one_6/Vdd!" "reg_3/GND!" 170.22
cap "reg_3/r0" "reg_3/in1" 153.495
cap "reg_3/reg_one_6/r1" "reg_3/in1" 58.7
cap "reg_3/reg_one_6/tmp" "reg_3/in1" 7.848
cap "reg_3/GND!" "reg_3/in1" 58.7
cap "reg_3/reg_one_6/a_16_27#" "reg_3/in1" 7.446
cap "mux_8bit_0/mux_one_1/2mux_nr_0/in1" "mux_8bit_0/mux_one_1/GND!" 1.42109e-14
cap "mux_8bit_0/in1_1" "mux_8bit_0/mux_one_1/sel" 63.256
cap "mux_8bit_0/mux_one_1/Vdd!" "mux_8bit_0/mux_one_1/sel" 170.22
cap "reg_3/reg_one_6/a_33_32#" "mux_8bit_0/in1_1" -4.455
cap "mux_8bit_0/in1_1" "reg_3/reg_one_6/w_n11_n27#" -2.948
cap "mux_8bit_0/mux_one_1/Vdd!" "mux_8bit_0/in1_1" 98.617
cap "reg_3/reg_one_6/w_n11_n27#" "reg_3/reg_one_6/Vdd!" -7.10543e-15
cap "mux_8bit_0/mux_one_1/2mux_nr_0/in1" "mux_8bit_0/in1_1" 18.535
cap "mux_8bit_0/in1_1" "mux_8bit_0/mux_one_1/GND!" 15.908
cap "mux_8bit_0/in1_1" "reg_3/reg_one_6/w" 58.7
cap "reg_3/reg_one_6/w" "reg_3/reg_one_6/w_n11_n27#" 1.42109e-14
cap "reg_3/reg_one_6/w_n11_n27#" "mux_8bit_0/in1_1" 8.24
cap "mux_8bit_0/in1_1" "mux_8bit_0/mux_one_1/2mux_nr_0/a_n17_n11#" 36.092
cap "reg_3/reg_one_6/Vdd!" "mux_8bit_0/in1_1" -2.948
cap "mux_8bit_0/mux_one_1/Vdd!" "reg_3/reg_one_6/w" 170.22
cap "reg_4/r0" "reg_4/reg_one_6/Vdd!" 46.94
cap "reg_4/r0" "reg_4/in1" 130.711
cap "reg_4/reg_one_6/tmp" "wz1" 6.507
cap "reg_4/reg_one_6/r1" "wz1" 58.7
cap "reg_4/reg_one_6/Vdd!" "wz1" 58.7
cap "reg_4/reg_one_6/a_33_32#" "wz1" 7.959
cap "reg_4/GND!" "reg_4/reg_one_6/Vdd!" 170.22
cap "reg_4/in1" "wz1" 2.844
cap "mux_8bit_0/mux_one_1/GND!" "reg_4/reg_one_6/Vdd!" 170.22
cap "mux_8bit_0/mux_one_1/GND!" "reg_4/in1" 135.677
cap "mux_8bit_0/mux_one_1/2mux_nr_0/a_n17_n11#" "wz1" -5.178
cap "reg_4/reg_one_6/a_16_27#" "wz1" 8.022
cap "reg_4/reg_one_6/w_n11_n27#" "wz1" 133.528
cap "mux_8bit_0/mux_one_1/2mux_nr_0/a_n17_n11#" "mux_8bit_0/mux_one_1/GND!" 3.55271e-15
cap "reg_4/r0" "wz1" 19.78
cap "reg_4/r0" "mux_8bit_0/mux_one_1/GND!" 165.587
cap "mux_8bit_0/mux_one_1/2mux_nr_0/out" "reg_4/in1" 85.4219
cap "reg_4/reg_one_6/w" "wz1" 5.064
cap "mux_8bit_0/mux_one_1/2mux_nr_0/s" "wz1" 4.948
cap "reg_4/reg_one_6/Vdd!" "reg_4/reg_one_6/r1" 170.22
cap "reg_4/GND!" "wz1" 58.7
cap "reg_4/in1" "reg_4/reg_one_6/Vdd!" 56.544
cap "mux_8bit_0/mux_one_1/GND!" "wz1" 67.786
subcap "rx_PCL1" -341.997
cap "wz1" "addsub_1/addsub_one_1/b" 97.913
cap "addsub_1/b1" "addsub_1/a1" 2.424
cap "addsub_1/xor_1/Vdd!" "addsub_1/a1" 135.212
cap "wz1" "addsub_1/xor_1/a_61_n31#" 19.78
cap "wz1" "reg_4/reg_one_6/w" 58.7
cap "addsub_1/xor_1/a_61_n1#" "addsub_1/a1" 174.249
cap "wz1" "reg_4/reg_one_6/w_n11_n27#" -2.417
cap "addsub_1/b1" "addsub_1/xor_1/a_61_n31#" -9.50351e-14
cap "wz1" "addsub_1/xor_1/a_89_n31#" 17.316
cap "reg_4/reg_one_6/w" "addsub_1/xor_1/Vdd!" 170.22
cap "reg_4/reg_one_6/w_n11_n27#" "reg_4/reg_one_6/Vdd!" -7.10543e-15
cap "addsub_1/addsub_one_1/b" "addsub_1/a1" 36.877
cap "addsub_1/xor_1/b" "wz1" 11.825
cap "addsub_1/xor_1/a_61_n31#" "addsub_1/a1" 2.424
cap "wz1" "addsub_1/b1" 26.517
cap "wz1" "addsub_1/xor_1/Vdd!" 15.72
cap "addsub_1/xor_1/b" "addsub_1/xor_1/Vdd!" 33.825
cap "addsub_1/xor_1/b" "addsub_1/b1" 11.5435
cap "addsub_1/xor_1/a_61_n1#" "wz1" 5.568
cap "addsub_1/xor_1/a_89_n31#" "addsub_1/a1" 2.424
cap "addsub_1/xor_1/Vdd!" "addsub_1/b1" 33.825
cap "wz1" "reg_4/reg_one_6/a_33_32#" -12.339
cap "wz1" "reg_4/reg_one_6/w_n11_n27#" -8.24
cap "addsub_1/xor_1/b" "addsub_1/a1" 2.424
subcap "PCLplus1_1" -99.932
subcap "a_1716_1625#" -191.416
cap "wz1" "addsub_1/addsub_one_1/GND!" 38.289
cap "addsub_1/addsub_one_1/a_11_9#" "addsub_1/addsub_one_1/Vdd!" 90.388
cap "addsub_1/addsub_one_1/b" "addsub_1/addsub_one_1/GND!" -2.27374e-13
cap "wz1" "addsub_1/addsub_one_1/a_78_n41#" 35.835
cap "addsub_1/a1" "a_2510_1893#" 8.408
cap "addsub_1/addsub_one_1/a_11_n41#" "addsub_1/addsub_one_1/Vdd!" 63.533
cap "addsub_1/addsub_one_1/b" "a_2510_1893#" 16.816
cap "addsub_1/addsub_one_1/Vdd!" "addsub_1/addsub_one_1/a_29_9#" 3.56
cap "addsub_1/addsub_one_1/a_72_n41#" "a_2510_1893#" 2.1
cap "addsub_1/addsub_one_1/Vdd!" "addsub_1/addsub_one_1/a_35_n41#" 80.98
cap "addsub_1/addsub_one_1/a_66_n41#" "a_2510_1893#" 2.1
cap "addsub_1/addsub_one_1/a_35_n41#" "wz1" 51.712
cap "addsub_1/addsub_one_1/cin" "addsub_1/addsub_one_1/Vdd!" 45.416
cap "addsub_1/addsub_one_1/a_89_n41#" "a_2510_1893#" 22.875
cap "addsub_1/addsub_one_1/cin" "wz1" 1.56
cap "addsub_1/addsub_one_1/Vdd!" "wz1" 3.171
cap "addsub_1/addsub_one_1/Vdd!" "addsub_1/a1" 27.084
cap "addsub_1/addsub_one_1/Vdd!" "addsub_1/addsub_one_1/b" 39.22
cap "addsub_1/addsub_one_1/GND!" "a_2510_1893#" 63.816
cap "wz1" "addsub_1/addsub_one_1/b" 95.736
cap "addsub_1/addsub_one_1/a_78_n41#" "a_2510_1893#" 14.192
cap "addsub_1/addsub_one_1/a_29_n41#" "a_2510_1893#" 2.1
cap "addsub_1/addsub_one_1/a_11_n41#" "a_2510_1893#" 11.28
cap "addsub_1/addsub_one_1/a_35_n41#" "a_2510_1893#" 14.854
cap "addsub_1/addsub_one_1/Vdd!" "addsub_1/addsub_one_1/GND!" 110.483
cap "addsub_1/addsub_one_1/cin" "a_2510_1893#" 12.612
subcap "a_1776_1628#" -131.059
subcap "a_1716_1625#" -182.152
cap "latch_5/c" "latch_5/out1" 1.086
cap "staticizer_2/staticizer_one_1/a_60_n45#" "latch_5/out1" 15.3913
cap "latch_5/c" "latch_5/latch_one_1/Vdd!" 1242.97
cap "latch_5/latch_one_1/Vdd!" "wz1" 117.4
cap "staticizer_2/GND!" "wz1" 58.7
cap "latch_5/latch_one_1/Vdd!" "staticizer_2/c" 170.22
cap "latch_5/GND!" "latch_5/latch_one_1/Vdd!" 170.22
cap "latch_5/latch_one_1/Vdd!" "latch_5/out1" 67.634
cap "latch_5/c" "wz1" 58.7
cap "wz1" "staticizer_2/c" 58.7
cap "latch_5/GND!" "wz1" 58.7
cap "latch_5/latch_one_1/Vdd!" "staticizer_2/GND!" 170.22
cap "staticizer_2/staticizer_one_1/out" "staticizer_2/staticizer_one_1/Vdd!" 6.811
cap "staticizer_2/staticizer_one_1/out" "staticizer_2/staticizer_one_1/a_77_n45#" 16.968
cap "staticizer_2/staticizer_one_1/out" "staticizer_2/staticizer_one_1/a_95_n27#" 5.049
cap "mux_8bit_1/mux_one_1/GND!" "mux_8bit_1/in1_1" 15.908
cap "mux_8bit_1/mux_one_1/2mux_nr_0/a_n17_n11#" "mux_8bit_1/in1_1" 36.092
cap "mux_8bit_1/mux_one_1/sel" "mux_8bit_1/in1_1" 63.256
cap "mux_8bit_1/mux_one_1/Vdd!" "mux_8bit_1/in1_1" 96.331
cap "mux_8bit_1/mux_one_1/sel" "mux_8bit_1/mux_one_1/Vdd!" 170.22
cap "mux_8bit_1/in1_1" "mux_8bit_1/mux_one_1/2mux_nr_0/in1" 18.535
cap "reg_5/in1" "reg_5/reg_one_6/Vdd!" 56.544
cap "mux_8bit_1/mux_one_1/2mux_nr_0/a_n17_n11#" "wz1" -5.178
cap "reg_5/r0" "reg_5/in1" 130.711
cap "reg_5/reg_one_6/a_33_32#" "wz1" 7.959
cap "reg_5/reg_one_6/tmp" "wz1" 6.507
cap "mux_8bit_1/mux_one_1/GND!" "reg_5/in1" 135.677
cap "reg_5/reg_one_6/w" "wz1" 5.064
cap "reg_5/reg_one_6/Vdd!" "wz1" 58.7
cap "reg_5/reg_one_6/r1" "wz1" 58.7
cap "reg_5/reg_one_6/w_n11_n27#" "wz1" 133.528
cap "reg_5/reg_one_6/r1" "reg_5/reg_one_6/Vdd!" 170.22
cap "reg_5/GND!" "wz1" 58.7
cap "reg_5/r0" "wz1" 19.78
cap "reg_5/reg_one_6/a_16_27#" "wz1" 8.022
cap "reg_5/GND!" "reg_5/reg_one_6/Vdd!" 170.22
cap "reg_5/r0" "reg_5/reg_one_6/Vdd!" 46.94
cap "mux_8bit_1/mux_one_1/GND!" "wz1" 67.786
cap "mux_8bit_1/mux_one_1/GND!" "reg_5/reg_one_6/Vdd!" 170.22
cap "reg_5/in1" "mux_8bit_1/mux_one_1/2mux_nr_0/out" 85.4219
cap "reg_5/in1" "wz1" 2.844
cap "wz1" "mux_8bit_1/mux_one_1/2mux_nr_0/s" 4.948
cap "mux_8bit_1/mux_one_1/GND!" "reg_5/r0" 165.587
cap "mux_8bit_1/mux_one_1/GND!" "mux_8bit_1/mux_one_1/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "reg_6/reg_one_6/Vdd!" "reg_6/reg_one_6/r1" 170.22
cap "reg_6/in1" "reg_6/reg_one_6/w" 5.064
cap "reg_5/reg_one_6/w" "reg_5/reg_one_6/w_n11_n27#" 2.84217e-14
cap "reg_5/reg_one_6/Vdd!" "reg_5/reg_one_6/w_n11_n27#" -7.10543e-15
cap "reg_6/reg_one_6/a_16_27#" "reg_6/in1" 8.022
cap "reg_5/reg_one_6/w" "reg_6/in1" 58.7
cap "reg_6/in1" "reg_5/reg_one_6/w_n11_n27#" -2.417
cap "reg_6/r0" "reg_6/reg_one_6/Vdd!" 56.708
cap "reg_5/reg_one_6/a_33_32#" "reg_6/in1" -12.339
cap "reg_6/in1" "reg_6/GND!" 58.7
cap "reg_6/reg_one_6/Vdd!" "reg_6/reg_one_6/r0" -7.10543e-15
cap "reg_6/in1" "reg_6/reg_one_6/r1" 58.7
cap "reg_6/in1" "reg_6/reg_one_6/w_n11_n27#" 123.733
cap "reg_5/reg_one_6/Vdd!" "reg_5/reg_one_6/w" 1.77636e-15
cap "reg_6/reg_one_6/Vdd!" "reg_5/reg_one_6/w" 170.22
cap "reg_6/in1" "reg_5/reg_one_6/w_n11_n27#" -8.24
cap "reg_6/in1" "reg_6/reg_one_6/tmp" 4.461
cap "reg_6/in1" "reg_6/reg_one_6/a_33_32#" 2.844
cap "reg_6/r0" "reg_6/in1" 128.02
cap "reg_6/reg_one_6/Vdd!" "reg_6/GND!" 170.22
cap "reg_6/reg_one_6/Vdd!" "reg_6/in1" 58.7
cap "reg_6/reg_one_6/w_n11_n27#" "mux_8bit_2/in1_1" 48.9529
cap "mux_8bit_2/mux_one_1/Vdd!" "reg_6/reg_one_6/w" 170.22
cap "reg_6/reg_one_6/tmp" "mux_8bit_2/in1_1" -4.818
cap "reg_6/reg_one_6/Vdd!" "reg_6/reg_one_6/w_n11_n27#" -7.10543e-15
cap "mux_8bit_2/mux_one_1/GND!" "mux_8bit_2/mux_one_1/2mux_nr_0/in1" 1.42109e-14
cap "mux_8bit_2/mux_one_1/Vdd!" "mux_8bit_2/in1_1" 2.035
cap "reg_6/reg_one_6/a_33_32#" "mux_8bit_2/in1_1" 5.115
cap "reg_6/reg_one_6/Vdd!" "reg_6/reg_one_6/a_4_n13#" -7.10543e-15
cap "mux_8bit_2/mux_one_1/Vdd!" "mux_8bit_2/mux_one_1/sel" 170.22
cap "mux_8bit_2/mux_one_1/GND!" "mux_8bit_2/in1_1" 2.035
cap "reg_6/reg_one_6/Vdd!" "reg_6/reg_one_6/a_33_32#" -7.10543e-15
cap "reg_6/reg_one_6/w_n11_n27#" "mux_8bit_2/in1_1" -1.886
cap "reg_6/reg_one_6/w" "mux_8bit_2/in1_1" 97.0214
cap "reg_6/reg_one_6/tmp" "reg_6/reg_one_6/w_n11_n27#" -7.10543e-15
cap "mux_8bit_2/mux_one_1/GND!" "reg_7/r0" 165.587
cap "reg_7/reg_one_6/Vdd!" "reg_7/r0" 46.94
cap "reg_7/r0" "reg_7/in1" 130.711
cap "mux_8bit_2/mux_one_1/GND!" "reg_7/reg_one_6/Vdd!" 170.22
cap "mux_8bit_2/mux_one_1/GND!" "mux_8bit_2/mux_one_1/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "mux_8bit_2/mux_one_1/2mux_nr_0/out" "reg_7/in1" 85.4219
cap "mux_8bit_2/mux_one_1/GND!" "reg_7/in1" 135.677
cap "reg_7/reg_one_6/Vdd!" "reg_7/in1" 56.544
cap "reg_7/GND!" "reg_7/reg_one_6/Vdd!" 170.22
cap "reg_7/reg_one_6/Vdd!" "reg_7/reg_one_6/r1" 170.22
subcap "rx_addrH1" -721.169
cap "addsub_2/a1" "addsub_2/xor_1/b" 2.424
cap "addsub_2/xor_1/Vdd!" "reg_7/reg_one_6/w" 170.22
cap "addsub_2/addsub_one_1/b" "addsub_2/a1" 36.877
cap "addsub_2/a1" "addsub_2/xor_1/Vdd!" 135.212
cap "addsub_2/a1" "addsub_2/b1" 2.424
cap "addsub_2/xor_1/a_61_n31#" "addsub_2/b1" -1.13687e-13
cap "addsub_2/a1" "addsub_2/xor_1/a_61_n1#" 174.249
cap "addsub_2/xor_1/Vdd!" "addsub_2/xor_1/b" 33.825
cap "reg_7/reg_one_6/Vdd!" "reg_7/reg_one_6/w_n11_n27#" -7.10543e-15
cap "addsub_2/a1" "addsub_2/xor_1/a_89_n31#" 2.424
cap "addsub_2/xor_1/Vdd!" "addsub_2/b1" 33.825
cap "addsub_2/a1" "addsub_2/xor_1/a_61_n31#" 2.424
subcap "a_2516_1625#" -191.416
cap "addsub_2/addsub_one_1/a_29_9#" "addsub_2/addsub_one_1/Vdd!" 3.56
cap "addsub_2/addsub_one_1/a_11_n41#" "addsub_2/addsub_one_1/Vdd!" 70.913
cap "addsub_2/a1" "addsub_2/addsub_one_1/Vdd!" 28.644
cap "addsub_2/addsub_one_1/a_35_n41#" "addsub_2/addsub_one_1/Vdd!" 88.745
cap "addsub_2/addsub_one_1/GND!" "addsub_2/addsub_one_1/Vdd!" 110.483
cap "addsub_2/addsub_one_1/b" "addsub_2/addsub_one_1/Vdd!" 42.92
cap "addsub_2/addsub_one_1/a_11_9#" "addsub_2/addsub_one_1/Vdd!" 90.388
cap "addsub_2/addsub_one_1/b" "addsub_2/addsub_one_1/GND!" -2.27374e-13
cap "addsub_2/addsub_one_1/a_29_n41#" "addsub_2/addsub_one_1/Vdd!" 1.78
cap "addsub_2/addsub_one_1/cin" "addsub_2/addsub_one_1/Vdd!" 49.116
subcap "a_2575_1628#" -116.962
subcap "a_2516_1625#" -182.152
cap "latch_6/latch_one_1/Vdd!" "staticizer_3/GND!" 170.22
cap "latch_6/latch_one_1/Vdd!" "staticizer_3/c" 170.22
cap "staticizer_3/staticizer_one_1/a_60_n45#" "latch_6/out1" 11.5435
cap "latch_6/latch_one_1/Vdd!" "latch_6/GND!" 170.22
cap "latch_6/out1" "latch_6/c" 2.13
cap "latch_6/latch_one_1/Vdd!" "latch_6/out1" 68.864
cap "latch_6/latch_one_1/Vdd!" "latch_6/c" 1242.9
subcap "addr_out1" -220.8
cap "staticizer_3/staticizer_one_1/Vdd!" "staticizer_3/staticizer_one_1/out" 2.84217e-14
cap "latch_7/GND!" "latch_7/latch_one_1/Vdd!" 170.22
cap "staticizer_3/staticizer_one_1/a_77_n45#" "staticizer_3/staticizer_one_1/Vdd!" 2.84217e-14
cap "latch_7/out1" "latch_7/latch_one_1/Vdd!" 68.864
cap "latch_7/latch_one_1/Vdd!" "staticizer_4/GND!" 70.212
cap "latch_7/latch_one_1/Vdd!" "latch_7/c" 1242.9
cap "latch_7/out1" "staticizer_4/staticizer_one_1/a_60_n45#" 11.5435
cap "latch_7/out1" "latch_7/c" 2.13
subcap "ry_addrH1" -1079.43
subcap "addr_out9" -259.522
cap "staticizer_5/in1" "latch_8/latch_one_1/Vdd!" -1.162
cap "latch_8/GND!" "latch_8/latch_one_1/Vdd!" 170.22
cap "staticizer_4/c" "latch_8/latch_one_1/Vdd!" 170.22
cap "staticizer_5/in1" "latch_8/c" -0.42
cap "staticizer_4/GND!" "latch_8/latch_one_1/Vdd!" 65.88
subcap "addr_out9" -50.198
cap "staticizer_5/in1" "staticizer_5/staticizer_one_1/Vdd!" 68.864
cap "staticizer_5/GND!" "staticizer_5/staticizer_one_1/Vdd!" 170.22
cap "staticizer_5/staticizer_one_1/Vdd!" "latch_8/c" 1242.9
cap "staticizer_5/staticizer_one_1/Vdd!" "staticizer_5/c" 170.22
cap "staticizer_5/in1" "latch_8/c" 2.13
cap "staticizer_5/staticizer_one_1/a_60_n45#" "staticizer_5/in1" 11.5435
cap "staticizer_1/Vdd!" "latch_4/latch_one_0/a_n5_n54#" -5.68434e-14
cap "staticizer_1/Vdd!" "staticizer_1/GND!" 169.482
cap "staticizer_1/Vdd!" "staticizer_1/staticizer_one_0/a_60_n45#" -2.27374e-13
cap "latch_4/c" "staticizer_1/in0" 0.492
cap "staticizer_1/in0" "staticizer_1/c" 1.42109e-14
cap "latch_4/c" "staticizer_1/GND!" 188.69
cap "staticizer_1/GND!" "staticizer_1/in0" 18.828
cap "staticizer_1/GND!" "staticizer_1/c" 170.22
cap "staticizer_1/staticizer_one_0/a_60_n45#" "staticizer_1/in0" 57.7175
cap "staticizer_1/Vdd!" "latch_4/c" 1061.91
cap "staticizer_1/Vdd!" "staticizer_1/in0" 73.946
subcap "a_109_1800#" -134.574
subcap "data_in0" -6.948
subcap "ld_datain" -296.37
subcap "rx0" -1774.96
cap "latch_4/Vdd!" "staticizer_0/staticizer_one_0/a_60_n45#" -4.648
cap "latch_0/out0" "latch_4/GND!" 18.828
cap "latch_4/latch_one_0/a_n5_n54#" "latch_4/in0" 69.3743
cap "latch_0/out0" "staticizer_0/staticizer_one_0/a_60_n45#" 57.7175
cap "latch_4/GND!" "latch_4/in0" 59.993
cap "latch_0/c" "latch_4/Vdd!" 1061.91
cap "latch_0/in0" "latch_0/latch_one_0/a_n5_n54#" 32.9814
cap "latch_0/c" "latch_0/out0" 0.492
cap "latch_4/GND!" "latch_0/latch_one_0/a_n5_n54#" 5.68434e-14
cap "latch_4/Vdd!" "latch_0/latch_one_0/a_12_n54#" -1.13687e-13
cap "latch_0/c" "latch_4/in0" 58.7
cap "latch_0/out0" "latch_4/Vdd!" 73.946
cap "latch_0/c" "latch_4/GND!" 188.69
cap "latch_4/Vdd!" "latch_4/in0" 565.557
cap "latch_4/Vdd!" "latch_0/in0" 67.0625
cap "latch_4/GND!" "latch_4/Vdd!" 443.576
cap "latch_4/Vdd!" "latch_0/latch_one_0/a_n5_n54#" 1.13687e-13
subcap "wz0" -2621.56
subcap "m1_136_1836#" -28.702
cap "latch_0/out0" "staticizer_0/Vdd!" 35.6
cap "shift_0/a0" "shift_0/shift_one_0/ad" 125.762
cap "shift_0/a0" "staticizer_0/c" 76.935
cap "staticizer_0/staticizer_one_0/a_60_n45#" "staticizer_0/Vdd!" -2.744
cap "shift_0/a0" "staticizer_0/Vdd!" -12.11
cap "staticizer_0/GND!" "latch_0/out0" 6.22
cap "staticizer_0/GND!" "shift_0/shift_one_0/ad" 170.22
cap "shift_0/shift_one_0/ad" "latch_0/out0" 58.7
cap "latch_0/out0" "shift_0/shift_one_0/Vdd!" 19.78
cap "staticizer_0/GND!" "staticizer_0/c" 170.22
cap "latch_0/out0" "staticizer_0/staticizer_one_0/a_60_n45#" 31.249
cap "staticizer_0/GND!" "shift_0/a0" 243.645
cap "latch_0/out0" "staticizer_0/c" 7.69567
cap "staticizer_0/staticizer_one_0/a_77_n45#" "staticizer_0/Vdd!" 1.13687e-13
cap "staticizer_0/GND!" "staticizer_0/Vdd!" 32.106
cap "rx0" "shift_0/shift_one_0/inv_2/GND!" 11.43
cap "wz0" "shift_0/shift_one_0/inv_2/GND!" 21.418
cap "Vdd!" "rx0" 58.7
cap "wz0" "Vdd!" 58.7
cap "shift_0/u" "shift_0/GND!" 170.22
cap "rx0" "shift_0/shift_one_0/inv_2/in" 14.74
cap "wz0" "shift_0/shift_one_0/inv_2/out" 25.522
cap "shift_0/shift_one_0/Vdd!" "rx0" 7.239
cap "wz0" "shift_0/shift_one_0/Vdd!" 91.858
cap "shift_0/GND!" "rx0" 58.7
cap "wz0" "shift_0/GND!" 58.7
cap "shift_0/u" "rx0" 58.7
cap "wz0" "shift_0/u" 58.7
cap "shift_0/GND!" "Vdd!" 170.22
cap "wz0" "shift_0/shift_one_0/m1_n60_n65#" 11.825
cap "shift_0/s" "rx0" 58.7
cap "latch_3/GND!" "latch_3/Vdd!" 170.22
cap "latch_3/GND!" "rx0" 107.383
cap "shift_0/shift_one_0/2mux_nr_1/out" "shift_0/shift_one_0/2mux_nr_1/GND!" 1.42109e-14
cap "latch_3/GND!" "shift_0/o0" 30.043
cap "wz0" "latch_3/latch_one_0/a_n5_n54#" 30.853
cap "wz0" "latch_3/latch_one_0/a_12_n54#" 4.95
cap "latch_3/latch_one_0/c" "wz0" 1.248
cap "latch_3/Vdd!" "latch_3/latch_one_0/a_n5_n54#" -1.13687e-13
cap "wz0" "latch_3/Vdd!" 64.715
cap "shift_0/shift_one_0/inv_3/Vdd!" "wz0" 72.651
cap "shift_0/s" "latch_3/GND!" 170.22
cap "latch_3/latch_one_0/c" "rx0" 3.12
cap "wz0" "shift_0/shift_one_0/2mux_nr_1/out" 8.599
cap "shift_0/shift_one_0/inv_3/Vdd!" "rx0" 7.239
cap "latch_3/Vdd!" "rx0" 58.7
cap "latch_3/latch_one_0/a_n5_n54#" "shift_0/o0" 57.7175
cap "wz0" "shift_0/o0" 2.184
cap "latch_3/Vdd!" "shift_0/shift_one_0/2mux_nr_1/out" 46.174
cap "wz0" "shift_0/shift_one_0/inv_3/GND!" 3.152
cap "latch_3/Vdd!" "shift_0/o0" 9.594
cap "rx0" "shift_0/o0" 20.945
cap "shift_0/shift_one_0/inv_3/Vdd!" "shift_0/o0" 1.162
cap "shift_0/shift_one_0/inv_3/GND!" "rx0" 6.096
cap "shift_0/s" "wz0" 58.7
cap "shift_0/shift_one_0/2mux_nr_1/out" "shift_0/o0" 57.7175
cap "wz0" "latch_3/GND!" 66.689
cap "latch_3/out0" "fblock_0/fblock_one_0/inv_0/GND!" 38.323
cap "fblock_0/fblock_one_0/2mux_nr_2/Vdd!" "fblock_0/a0" 82.685
cap "fblock_0/fblock_one_1/g3" "fblock_0/GND!" 207.194
cap "fblock_0/fblock_one_1/inv_2/out" "fblock_0/GND!" 25.243
cap "fblock_0/fblock_one_1/Vdd!" "fblock_0/GND!" 109.785
cap "fblock_0/a0" "latch_3/c" 78.258
cap "latch_3/out0" "fblock_0/fblock_one_0/2mux_nr_2/a_n17_n11#" 14.683
cap "fblock_0/a0" "fblock_0/fblock_one_0/inv_0/in" 9.081
cap "latch_3/latch_one_0/a_12_n54#" "latch_3/latch_one_0/Vdd!" 2.84217e-14
cap "fblock_0/a0" "fblock_0/fblock_one_0/2mux_nr_0/out" 5.115
cap "fblock_0/fblock_one_1/g3" "latch_3/out0" 58.7
cap "fblock_0/a0" "fblock_0/GND!" 58.7
cap "latch_3/out0" "fblock_0/fblock_one_0/2mux_nr_2/in0" 7.975
cap "fblock_0/fblock_one_1/inv_1/out" "fblock_0/GND!" 49.479
cap "latch_3/out0" "fblock_0/a0" 4.948
cap "fblock_0/GND!" "latch_3/c" 170.22
cap "latch_3/c" "latch_3/latch_one_0/Vdd!" -0.358
cap "latch_3/latch_one_0/GND!" "fblock_0/a0" 0.083
cap "latch_3/out0" "latch_3/c" 140.424
cap "latch_3/out0" "fblock_0/fblock_one_0/inv_0/in" 19.302
cap "fblock_0/a0" "fblock_0/fblock_one_1/g2" 58.7
cap "latch_3/out0" "fblock_0/fblock_one_0/2mux_nr_0/out" 9.35
cap "latch_3/out0" "fblock_0/GND!" 58.7
cap "latch_3/out0" "latch_3/latch_one_0/Vdd!" 0.959
cap "latch_3/latch_one_0/GND!" "latch_3/c" 2.84217e-14
cap "Vdd!" "fblock_0/fblock_one_1/inv_2/out" 2.475
cap "fblock_0/a0" "fblock_0/fblock_one_0/inv_0/GND!" 56.9869
cap "fblock_0/fblock_one_1/inv_3/GND!" "fblock_0/GND!" 15.278
cap "fblock_0/a0" "fblock_0/fblock_one_0/2mux_nr_2/a_n17_n11#" 11.004
cap "fblock_0/fblock_one_1/g3" "fblock_0/a0" 542.798
cap "fblock_0/fblock_one_1/g2" "fblock_0/GND!" 207.194
cap "Vdd!" "fblock_0/fblock_one_1/inv_1/out" 2.475
cap "latch_3/latch_one_0/GND!" "latch_3/out0" 1.209
cap "fblock_0/a0" "fblock_0/fblock_one_0/2mux_nr_2/in0" 4.389
cap "latch_3/out0" "fblock_0/fblock_one_1/g2" 58.7
cap "fblock_0/f0" "fblock_0/fblock_one_1/inv_3/Vdd!" 18.792
cap "fblock_0/fblock_one_1/inv_3/Vdd!" "wz0" 117.4
cap "latch_1/GND!" "fblock_0/fblock_one_1/inv_4/out" 17.226
cap "fblock_0/fblock_one_1/inv_3/Vdd!" "rx0" 162.528
cap "fblock_0/fblock_one_1/inv_3/Vdd!" "fblock_0/fblock_one_1/inv_4/out" 2.475
cap "fblock_0/f0" "rx0" 13.492
cap "fblock_0/f0" "wz0" 18.093
cap "fblock_0/fblock_one_0/inv_0/GND!" "wz0" 20.977
cap "latch_1/GND!" "fblock_0/fblock_one_1/g1" 207.194
cap "rx0" "fblock_0/fblock_one_0/inv_0/in" 2.844
cap "wz0" "fblock_0/fblock_one_0/inv_0/in" 4.123
cap "fblock_0/fblock_one_0/inv_0/GND!" "fblock_0/fblock_one_0/inv_0/in" 5.68434e-14
cap "latch_1/GND!" "fblock_0/fblock_one_1/inv_3/GND!" 10.044
cap "latch_1/GND!" "fblock_0/fblock_one_1/g0" 198.791
cap "fblock_0/f0" "latch_1/latch_one_0/a_n5_n54#" 57.7175
cap "rx0" "latch_1/latch_one_0/a_n5_n54#" 7.807
cap "latch_1/GND!" "fblock_0/fblock_one_1/inv_3/Vdd!" 497.855
cap "rx0" "fblock_0/fblock_one_1/g1" 58.7
cap "wz0" "latch_1/latch_one_0/a_n5_n54#" 43.4
cap "wz0" "fblock_0/fblock_one_1/g1" 58.7
cap "latch_1/latch_one_0/a_12_n54#" "wz0" 9.731
cap "wz0" "latch_1/latch_one_0/c" 4.324
cap "latch_1/GND!" "fblock_0/fblock_one_1/inv_3/out" 49.479
cap "rx0" "fblock_0/fblock_one_0/f" 85.724
cap "latch_1/GND!" "fblock_0/f0" 12.326
cap "latch_1/GND!" "rx0" 58.7
cap "rx0" "fblock_0/fblock_one_1/g0" 58.7
cap "latch_1/GND!" "wz0" 69.742
cap "wz0" "fblock_0/fblock_one_1/g0" 58.7
cap "fblock_0/fblock_one_1/inv_3/Vdd!" "fblock_0/fblock_one_1/inv_3/out" 2.475
subcap "ry0" -2468.29
cap "latch_1/latch_one_0/a_n5_n54#" "rx0" 4.948
cap "latch_1/c" "latch_1/latch_one_0/Vdd!" -0.358
cap "addsub_0/xor_0/GND!" "GND!" 33.825
cap "addsub_0/xor_0/GND!" "addsub_0/b0" 126.189
cap "latch_1/out0" "latch_1/latch_one_0/a_30_n54#" 1.524
cap "latch_1/out0" "latch_1/latch_one_0/GND!" 3.821
cap "latch_1/latch_one_0/Vdd!" "rx0" -1.405
cap "addsub_0/xor_0/GND!" "rx0" 11.825
cap "latch_1/c" "GND!" 170.22
cap "latch_1/latch_one_0/a_30_n35#" "rx0" 4.828
cap "addsub_0/xor_0/a_69_n42#" "addsub_0/b0" 2.457
cap "GND!" "addsub_0/sub" 33.825
cap "addsub_0/b0" "rx0" 2.764
cap "addsub_0/xor_0/Vdd!" "rx0" 8.496
cap "latch_1/c" "rx0" 58.7
cap "addsub_0/sub" "rx0" 11.825
cap "addsub_0/xor_0/GND!" "addsub_0/b0" 12.382
cap "latch_1/out0" "latch_1/latch_one_0/a_n5_n54#" 15.975
cap "addsub_0/xor_0/GND!" "rx0" 12.213
cap "latch_1/latch_one_0/Vdd!" "rx0" -4.367
cap "addsub_0/xor_0/GND!" "latch_1/out0" 11.825
cap "latch_1/out0" "latch_1/latch_one_0/Vdd!" 1.221
cap "latch_1/latch_one_0/a_12_n54#" "rx0" 4.948
cap "latch_1/out0" "addsub_0/sub" 11.825
cap "latch_1/out0" "latch_1/latch_one_0/GND!" 2.361
cap "latch_1/c" "latch_1/out0" 144.632
cap "latch_1/out0" "rx0" 9.182
cap "GND!" "addsub_0/addsub_one_1/Vdd!" 24.432
cap "addsub_0/addsub_one_1/GND!" "as_cout" 55.796
cap "as_cout" "addsub_0/addsub_one_0/a_89_n41#" 11.175
cap "addsub_0/addsub_one_0/Vdd!" "addsub_0/addsub_one_1/a_11_9#" 2.475
cap "addsub_0/addsub_one_1/a_11_n41#" "addsub_0/addsub_one_0/Vdd!" 2.475
cap "addsub_0/addsub_one_0/Vdd!" "addsub_0/addsub_one_1/a" 16.536
cap "rx0" "addsub_0/addsub_one_0/a_35_n41#" 19.78
cap "rx0" "addsub_0/xor_0/a_61_n1#" 56.052
cap "wz0" "addsub_0/addsub_one_0/a_35_n41#" 65.763
cap "addsub_0/addsub_one_1/a_11_n41#" "as_cout" 10.65
cap "as_cout" "addsub_0/addsub_one_1/a" 8.408
cap "addsub_0/addsub_one_0/cout" "ry0" 10.71
cap "addsub_0/addsub_one_0/a" "as_cout" 4.204
cap "addsub_0/addsub_one_0/a_35_n41#" "as_cout" 4.204
cap "wz0" "addsub_0/addsub_one_0/GND!" 0.308
cap "rx0" "addsub_0/addsub_one_0/GND!" -0.341
cap "GND!" "addsub_0/addsub_one_1/GND!" 39.821
cap "GND!" "addsub_0/addsub_one_0/Vdd!" 37.635
cap "as_cout" "addsub_0/addsub_one_0/GND!" 28.155
cap "GND!" "addsub_0/addsub_one_1/a_11_9#" 46.605
cap "GND!" "addsub_0/addsub_one_1/a" 22.336
cap "addsub_0/addsub_one_1/a_11_n41#" "GND!" 24.2
cap "addsub_0/addsub_one_0/cout" "as_cout" 14.329
cap "rx0" "addsub_0/addsub_one_0/b" 57.61
cap "addsub_0/addsub_one_0/s" "as_cout" 41.11
cap "rx0" "addsub_0/xor_0/a" 2.424
cap "ry0" "addsub_0/addsub_one_1/GND!" 24.288
cap "ry0" "addsub_0/addsub_one_0/Vdd!" 28.817
cap "addsub_0/addsub_one_0/b" "as_cout" 4.204
cap "rx0" "addsub_0/addsub_one_0/a_78_n41#" 11.825
cap "rx0" "addsub_0/addsub_one_0/a_89_9#" 4.7
cap "addsub_0/addsub_one_0/a_78_n41#" "as_cout" 4.204
cap "wz0" "addsub_0/addsub_one_1/GND!" 18.211
cap "rx0" "addsub_0/addsub_one_1/GND!" 20.114
cap "wz0" "addsub_0/addsub_one_0/Vdd!" 50.747
cap "rx0" "addsub_0/addsub_one_0/Vdd!" 89.653
cap "addsub_0/xor_0/b" "rx0" 2.424
subcap "GND!" -5613.98
subcap "a_841_1801#" -38.45
cap "addsub_0/a_127_1064#" "ry0" 1.486
cap "rx0" "latch_2/c" 61.544
cap "rx0" "latch_2/latch_one_0/a_30_n35#" 1.524
cap "latch_2/out0" "latch_2/latch_one_0/a_n5_n54#" 12.196
cap "addsub_0/addsub_one_0/GND!" "latch_2/out0" 3.399
cap "ry0" "latch_2/c" 81.378
cap "addsub_0/addsub_one_1/GND!" "latch_2/Vdd!" 451.524
cap "latch_2/c" "latch_2/out0" 499.044
cap "addsub_0/addsub_one_1/GND!" "reg_0/reg_one_7/r0" 56.708
cap "latch_2/out0" "addsub_0/addsub_one_0/a_35_n41#" -1.814
cap "addsub_0/s0" "addsub_0/addsub_one_1/GND!" 76.9567
cap "addsub_0/s0" "latch_2/Vdd!" 19.399
cap "rx0" "addsub_0/addsub_one_1/GND!" 75.673
cap "rx0" "latch_2/latch_one_0/a_12_n54#" 37.778
cap "latch_2/out0" "latch_2/latch_one_0/a_30_n54#" 2.592
cap "rx0" "latch_2/Vdd!" 116.636
cap "rx0" "reg_0/reg_one_7/r0" 19.78
cap "rx0" "addsub_0/s0" 3.468
cap "ry0" "addsub_0/addsub_one_1/GND!" 131.528
cap "ry0" "latch_2/Vdd!" 58.7
cap "addsub_0/a_127_1064#" "addsub_0/addsub_one_1/GND!" 16.962
cap "ry0" "reg_0/reg_one_7/r0" 17.308
cap "addsub_0/s0" "latch_2/latch_one_0/a_n5_n54#" 57.7175
cap "addsub_0/addsub_one_1/GND!" "latch_2/out0" 109.48
cap "latch_2/latch_one_0/a_12_n54#" "latch_2/out0" 12.473
cap "rx0" "addsub_0/addsub_one_0/b" -2.068
cap "latch_2/out0" "latch_2/Vdd!" 59.921
cap "rx0" "latch_2/latch_one_0/a_n5_n54#" 6.195
cap "reg_0/reg_one_7/r0" "latch_2/out0" 63.6875
cap "addsub_0/s0" "latch_2/out0" 4.948
cap "rx0" "addsub_0/addsub_one_0/GND!" 7.942
cap "addsub_0/addsub_one_1/GND!" "latch_2/c" 170.22
cap "addsub_0/addsub_one_1/a" "addsub_0/addsub_one_1/GND!" -1.756
cap "rx0" "latch_2/out0" 4.341
cap "addsub_0/addsub_one_1/a" "latch_2/Vdd!" 0.312
cap "latch_2/c" "latch_2/Vdd!" -0.358
cap "reg_0/reg_one_7/w_n11_n27#" "reg_0/reg_one_7/Vdd!" 170.22
cap "reg_0/reg_one_7/r1" "reg_0/reg_one_7/w_n11_n27#" 170.22
cap "reg_0/reg_one_7/r0" "reg_0/reg_one_7/w_n11_n27#" -7.416
cap "reg_0/port01" "reg_0/reg_one_7/w_n11_n27#" 121.694
cap "reg_0/port00" "reg_0/reg_one_7/a_21_n13#" 20.118
cap "reg_0/port00" "reg_0/reg_one_7/tmp" 4.948
cap "reg_0/port01" "reg_0/w" 127.744
cap "reg_0/port00" "reg_0/reg_one_7/a_4_n13#" 20.417
cap "reg_0/port01" "reg_0/reg_one_7/Vdd!" 58.7
cap "reg_0/reg_one_7/r0" "reg_0/port01" 23.94
cap "reg_0/port00" "reg_0/reg_one_7/w_n11_n27#" 194.315
cap "reg_0/reg_one_7/r1" "reg_0/port01" 64.004
cap "reg_0/port00" "reg_0/w" 434.25
cap "reg_0/port00" "reg_0/reg_one_7/Vdd!" 134.044
cap "reg_0/port00" "reg_0/reg_one_7/r0" -7.416
cap "reg_0/reg_one_7/w_n11_n27#" "reg_0/w" 170.22
cap "reg_0/port00" "reg_0/reg_one_7/r1" 70.642
cap "reg_1/port00" "reg_1/reg_one_7/a_21_n13#" 2.238
cap "reg_1/port00" "reg_1/reg_one_7/Vdd!" 75.185
cap "reg_1/port00" "reg_1/port01" 3.85
cap "reg_1/port01" "reg_1/w" 127.744
cap "reg_1/port01" "reg_1/reg_one_7/r0" 48.664
cap "reg_1/reg_one_7/a_4_n13#" "reg_1/port00" 118.494
cap "reg_1/port00" "reg_1/reg_one_7/w_n11_n27#" 198.775
cap "reg_1/w" "reg_1/reg_one_7/w_n11_n27#" 170.22
cap "reg_1/port00" "reg_1/reg_one_7/tmp" 4.694
cap "reg_1/reg_one_7/w_n11_n27#" "reg_1/reg_one_7/r0" 56.708
cap "reg_1/port01" "reg_1/reg_one_7/r1" 64.004
cap "reg_1/port00" "reg_1/w" 125.763
cap "reg_1/port01" "reg_1/reg_one_7/Vdd!" 58.7
cap "reg_1/port00" "reg_1/reg_one_7/r0" 21.144
cap "reg_1/reg_one_7/r1" "reg_1/reg_one_7/w_n11_n27#" 170.22
cap "reg_1/reg_one_7/Vdd!" "reg_1/reg_one_7/w_n11_n27#" 170.22
cap "reg_1/port01" "reg_1/reg_one_7/w_n11_n27#" 121.694
cap "reg_1/port00" "reg_1/reg_one_7/r1" 60.064
cap "reg_2/reg_one_7/w_n11_n27#" "reg_2/reg_one_7/r0" 56.708
cap "reg_2/w" "reg_2/port01" 94.2122
cap "reg_1/port00" "reg_2/reg_one_7/r0" 21.144
cap "reg_2/reg_one_7/w_n11_n27#" "reg_1/port00" 135.088
cap "reg_2/reg_one_7/Vdd!" "reg_2/port01" 58.7
cap "reg_2/reg_one_7/w_n11_n27#" "reg_2/reg_one_7/r1" 170.22
cap "reg_2/reg_one_7/r0" "reg_2/port01" 48.664
cap "reg_1/port00" "reg_2/reg_one_7/r1" 60.064
cap "reg_2/reg_one_7/w_n11_n27#" "reg_2/port01" 121.694
cap "reg_1/port00" "reg_2/port01" 3.85
cap "reg_1/port00" "reg_2/reg_one_7/a_21_n13#" 2.238
cap "reg_2/port01" "reg_2/reg_one_7/r1" 64.004
cap "reg_2/reg_one_7/w_n11_n27#" "reg_2/w" 170.22
cap "reg_2/reg_one_7/w_n11_n27#" "reg_2/reg_one_7/Vdd!" 170.22
cap "reg_2/w" "reg_1/port00" 92.2312
cap "reg_2/reg_one_7/a_4_n13#" "reg_1/port00" 118.494
cap "reg_1/port00" "reg_2/reg_one_7/Vdd!" 75.185
cap "reg_1/port00" "reg_2/reg_one_7/tmp" 4.694
cap "reg_2/port01" "reg_3/reg_one_7/r1" 64.004
cap "reg_3/port01" "reg_3/w" 5.072
cap "reg_3/reg_one_7/a_21_n13#" "reg_2/port00" 2.238
cap "reg_3/reg_one_7/w_n11_n27#" "reg_3/reg_one_7/r1" 170.22
cap "reg_3/port01" "reg_2/port00" 3.85
cap "reg_2/port00" "reg_3/reg_one_7/a_4_n13#" 118.494
cap "reg_3/reg_one_7/r0" "reg_2/port00" 21.144
cap "reg_2/w" "reg_2/port00" 33.5312
cap "reg_3/reg_one_7/w_n11_n27#" "reg_2/port00" 63.11
cap "reg_3/port01" "reg_2/port01" 73.199
cap "reg_2/port01" "reg_3/reg_one_7/r0" 48.664
cap "reg_2/port00" "reg_3/reg_one_7/Vdd!" 74.654
cap "reg_2/port01" "reg_2/w" 33.5312
cap "reg_3/reg_one_7/w_n11_n27#" "reg_2/port01" 106.567
cap "reg_3/port01" "reg_3/reg_one_7/w_n11_n27#" 1.628
cap "reg_3/reg_one_7/w_n11_n27#" "reg_3/reg_one_7/r0" 56.708
cap "reg_2/port01" "reg_3/reg_one_7/Vdd!" 58.7
cap "reg_3/reg_one_7/tmp" "reg_2/port00" 4.694
cap "reg_3/reg_one_7/w_n11_n27#" "reg_3/reg_one_7/Vdd!" 170.22
cap "reg_3/port00" "reg_2/port00" 8.58
cap "reg_2/reg_one_7/w_n11_n27#" "reg_2/port00" 63.6875
cap "reg_3/reg_one_7/r1" "reg_2/port00" 60.064
subcap "wz_addrL0" -530.966
subcap "PCL_w_muxout0" -380.236
cap "reg_3/port01" "mux_8bit_0/mux_one_0/inv2_2/GND!" 63.013
cap "mux_8bit_0/out0" "mux_8bit_0/in0_0" 30.603
cap "reg_3/port01" "reg_3/reg_one_7/w_n11_n27#" -1.039
cap "reg_3/port01" "mux_8bit_0/out0" -10.01
cap "reg_3/reg_one_7/Vdd!" "reg_3/port00" -2.898
cap "reg_3/w" "mux_8bit_0/GND!" 165.45
cap "reg_3/reg_one_7/Vdd!" "reg_3/reg_one_7/w_n11_n27#" -1.42109e-14
cap "mux_8bit_0/mux_one_0/inv2_2/GND!" "mux_8bit_0/out0" 37.928
cap "Vdd!" "mux_8bit_0/mux_one_0/inv2_2/Vdd!" 2.84217e-14
cap "mux_8bit_0/sel" "mux_8bit_0/in0_0" 58.7
cap "mux_8bit_0/mux_one_0/2mux_nr_0/in0" "mux_8bit_0/in0_0" 29.025
cap "reg_3/port01" "mux_8bit_0/sel" 58.7
cap "mux_8bit_0/mux_one_0/inv2_1/a_1_8#" "mux_8bit_0/in0_0" 19.462
cap "mux_8bit_0/sel" "mux_8bit_0/out0" 0.84
cap "mux_8bit_0/mux_one_0/inv2_2/Vdd!" "mux_8bit_0/in0_0" 20.196
cap "mux_8bit_0/sel" "mux_8bit_0/GND!" 156.28
cap "Vdd!" "mux_8bit_0/in0_0" 58.7
cap "reg_3/port01" "Vdd!" 58.7
cap "reg_3/port00" "reg_3/w" 125.763
cap "reg_3/port00" "reg_3/reg_one_7/w_n11_n27#" 135.615
cap "reg_3/port01" "reg_3/w" 127.744
cap "Vdd!" "mux_8bit_0/GND!" 156.28
cap "reg_3/port01" "reg_3/reg_one_7/w_n11_n27#" 12.7375
cap "reg_3/port00" "reg_3/reg_one_7/w_n11_n27#" -3.379
cap "mux_8bit_0/mux_one_0/inv2_2/GND!" "mux_8bit_0/in0_0" 12.279
cap "wz_addrL0" "reg_4/reg_one_7/r1" 59.948
cap "reg_4/reg_one_7/r1" "ry0" 64.004
cap "reg_4/reg_one_7/r1" "reg_4/reg_one_7/w_n11_n27#" 156.28
cap "wz_addrL0" "mux_8bit_0/mux_one_0/inv2_1/a_1_8#" -1.132
cap "mux_8bit_0/out0" "reg_4/reg_one_7/Vdd!" 31.758
cap "mux_8bit_0/out0" "mux_8bit_0/mux_one_0/2mux_nr_0/out" 50.7914
cap "mux_8bit_0/out0" "mux_8bit_0/mux_one_0/inv2_1/GND!" 400.316
cap "wz_addrL0" "reg_4/port01" 4.95
cap "ry0" "reg_4/port01" 73.199
cap "wz_addrL0" "mux_8bit_0/out0" -6.325
cap "wz_addrL0" "reg_4/reg_one_7/Vdd!" 73.616
cap "reg_4/reg_one_7/w_n11_n27#" "reg_4/port01" 1.628
cap "reg_4/port01" "reg_4/w" 5.072
cap "mux_8bit_0/out0" "ry0" -17.369
cap "wz_addrL0" "mux_8bit_0/mux_one_0/inv2_1/GND!" 6.72
cap "mux_8bit_0/out0" "reg_4/reg_one_7/w_n11_n27#" 46.74
cap "wz_addrL0" "reg_4/reg_one_7/tmp" 4.68
cap "reg_4/reg_one_7/Vdd!" "ry0" 58.7
cap "reg_4/reg_one_7/Vdd!" "reg_4/reg_one_7/w_n11_n27#" 156.28
cap "mux_8bit_0/out0" "reg_4/reg_one_7/r0" 275.521
cap "ry0" "mux_8bit_0/mux_one_0/inv2_1/GND!" -6.916
cap "reg_4/reg_one_7/w_n11_n27#" "mux_8bit_0/mux_one_0/inv2_1/GND!" -3.444
cap "reg_4/reg_one_7/Vdd!" "reg_4/reg_one_7/r0" -4.884
cap "mux_8bit_0/mux_one_0/2mux_nr_0/a_n17_n11#" "mux_8bit_0/mux_one_0/inv2_1/GND!" 3.55271e-15
cap "wz_addrL0" "reg_4/reg_one_7/a_4_n13#" 47.175
cap "wz_addrL0" "reg_4/port00" 9.229
cap "wz_addrL0" "reg_4/reg_one_7/w_n11_n27#" 135.264
cap "ry0" "reg_4/reg_one_7/w_n11_n27#" 165.267
cap "wz_addrL0" "reg_4/reg_one_7/r0" 21.028
cap "ry0" "reg_4/reg_one_7/r0" 48.664
cap "reg_4/reg_one_7/w_n11_n27#" "reg_4/reg_one_7/r0" 52.092
cap "addsub_1/b0" "reg_4/port01" 23.65
cap "reg_4/w" "reg_4/port01" 127.744
cap "reg_4/reg_one_7/w_n11_n27#" "reg_4/port01" 12.7375
cap "reg_4/w" "wz_addrL0" 58.7
cap "wz_addrL0" "addsub_1/b0" 15.95
cap "reg_4/port00" "wz_addrL0" -7.348
cap "reg_4/reg_one_7/w_n11_n27#" "wz_addrL0" 8.24
cap "addsub_1/b0" "addsub_1/addsub_one_0/Vdd!" 31.075
cap "reg_4/reg_one_7/Vdd!" "reg_4/reg_one_7/w_n11_n27#" -7.10543e-15
cap "reg_4/port00" "addsub_1/addsub_one_0/Vdd!" 22.684
cap "reg_4/w" "addsub_1/b0" 156.28
cap "addsub_1/b0" "addsub_1/xor_0/GND!" 46.222
cap "reg_4/port00" "addsub_1/b0" 154.575
cap "reg_4/reg_one_7/w_n11_n27#" "reg_4/port00" 63.6875
cap "reg_4/reg_one_7/w_n11_n27#" "reg_4/port01" -1.039
cap "addsub_1/addsub_one_0/Vdd!" "reg_4/port01" 11.825
cap "addsub_1/xor_0/a_61_n1#" "addsub_1/b0" 1.77636e-15
cap "reg_4/reg_one_7/w_n11_n27#" "wz_addrL0" -3.379
cap "reg_4/reg_one_7/Vdd!" "wz_addrL0" -2.948
cap "reg_4/port00" "addsub_1/xor_0/a_61_n1#" 50.284
cap "wz_addrL0" "addsub_1/addsub_one_0/Vdd!" 11.825
subcap "a_1716_1801#" -30.357
cap "addsub_1/addsub_one_1/GND!" "addsub_1/addsub_one_0/a_35_n41#" 5.68434e-14
cap "addsub_1/addsub_one_0/a" "a_2510_1893#" 4.204
cap "addsub_1/addsub_one_0/a_89_n41#" "a_2510_1893#" 11.175
cap "addsub_1/addsub_one_1/GND!" "addsub_1/s0" 76.9567
cap "addsub_1/addsub_one_1/a_11_9#" "addsub_1/addsub_one_0/Vdd!" 2.475
cap "addsub_1/addsub_one_1/a_11_n41#" "GND!" 24.2
cap "wz_addrL0" "addsub_1/addsub_one_0/Vdd!" 32.72
cap "addsub_1/addsub_one_1/a" "addsub_1/addsub_one_0/Vdd!" 16.848
cap "addsub_1/addsub_one_1/GND!" "ry0" 48.35
cap "addsub_1/addsub_one_1/a_11_n41#" "a_2510_1893#" 10.65
cap "addsub_1/addsub_one_1/GND!" "addsub_1/addsub_one_0/b" -5.68434e-14
cap "a_2510_1893#" "addsub_1/addsub_one_0/a_35_n41#" 4.204
cap "wz_addrL0" "addsub_1/addsub_one_0/a_35_n41#" 24.622
cap "addsub_1/s0" "a_2510_1893#" 41.11
cap "addsub_1/addsub_one_1/GND!" "GND!" 91.552
cap "a_2510_1893#" "addsub_1/addsub_one_0/GND!" 28.155
cap "GND!" "addsub_1/addsub_one_1/Vdd!" 21.003
cap "addsub_1/s0" "latch_5/latch_one_0/a_n5_n54#" 19.2392
cap "wz_addrL0" "addsub_1/addsub_one_0/GND!" 10.505
cap "addsub_1/addsub_one_1/a_11_n41#" "addsub_1/addsub_one_0/Vdd!" 2.475
cap "addsub_1/addsub_one_1/GND!" "wz_addrL0" 55.484
cap "addsub_1/addsub_one_1/GND!" "a_2510_1893#" 55.796
cap "ry0" "addsub_1/addsub_one_0/cout" 17.812
cap "a_2510_1893#" "addsub_1/addsub_one_0/b" 4.204
cap "addsub_1/s0" "addsub_1/addsub_one_0/Vdd!" -12.402
cap "addsub_1/addsub_one_0/cout" "GND!" 7.654
cap "addsub_1/addsub_one_1/a_11_9#" "GND!" 46.605
cap "addsub_1/addsub_one_1/a" "GND!" 23.7
cap "addsub_1/addsub_one_0/cout" "a_2510_1893#" 14.329
cap "ry0" "addsub_1/addsub_one_0/Vdd!" 9.108
cap "addsub_1/addsub_one_1/a" "a_2510_1893#" 8.408
cap "addsub_1/addsub_one_0/a_78_n41#" "a_2510_1893#" 4.204
cap "GND!" "addsub_1/addsub_one_0/Vdd!" -0.645
subcap "a_1776_1804#" -1.774
subcap "a_1716_1801#" -99.769
cap "latch_5/out0" "latch_5/latch_one_0/a_30_n54#" 1.524
cap "latch_5/GND!" "staticizer_2/c" 156.28
cap "latch_5/GND!" "latch_5/out0" 167.247
cap "latch_5/GND!" "latch_5/c" 170.132
cap "latch_5/Vdd!" "addsub_1/s0" 19.399
cap "latch_5/c" "latch_5/out0" 75.182
cap "staticizer_2/c" "latch_5/out0" 63.648
cap "latch_5/latch_one_0/a_n5_n54#" "latch_5/out0" 59.375
cap "latch_5/Vdd!" "ry0" 117.4
cap "latch_5/out0" "latch_5/latch_one_0/a_12_n54#" 9.731
cap "latch_5/Vdd!" "latch_5/GND!" 311.576
cap "latch_5/Vdd!" "latch_5/c" 1070.67
cap "latch_5/Vdd!" "latch_5/out0" 231.426
cap "latch_5/out0" "addsub_1/s0" 4.324
cap "latch_5/latch_one_0/a_n5_n54#" "addsub_1/s0" 57.7175
cap "latch_5/Vdd!" "latch_5/latch_one_0/a_12_n54#" 1.13687e-13
cap "latch_5/GND!" "ry0" 181.284
cap "staticizer_2/staticizer_one_0/a_77_n45#" "latch_5/out0" 9.998
cap "staticizer_2/staticizer_one_0/a_60_n45#" "latch_5/out0" 212.283
cap "staticizer_2/c" "ry0" 76.935
cap "latch_5/c" "ry0" 81.378
cap "addsub_1/GND!" "addsub_1/s0" 19.2392
subcap "wz_addrH0" -915.907
subcap "m1_1909_1774#" -380.236
cap "ry0" "Vdd!" 58.7
cap "staticizer_2/staticizer_one_0/out" "staticizer_2/staticizer_one_0/a_60_n45#" -5.616
cap "staticizer_2/staticizer_one_0/out" "staticizer_2/staticizer_one_0/c" 3.996
cap "ry0" "mux_8bit_1/out0" -10.01
cap "staticizer_2/staticizer_one_0/out" "staticizer_2/staticizer_one_0/a_95_n27#" 5.61
cap "mux_8bit_1/mux_one_0/inv2_2/Vdd!" "Vdd!" 4.26326e-14
cap "staticizer_2/staticizer_one_0/out" "staticizer_2/staticizer_one_0/a_95_n45#" 4.212
cap "ry0" "mux_8bit_1/sel" 58.7
cap "Vdd!" "mux_8bit_1/in0_0" 58.7
cap "mux_8bit_1/GND!" "Vdd!" 156.28
cap "mux_8bit_1/out0" "mux_8bit_1/sel" 0.84
cap "staticizer_2/staticizer_one_0/out" "staticizer_2/staticizer_one_0/Vdd!" 11.587
cap "ry0" "mux_8bit_1/mux_one_0/inv2_2/GND!" 63.013
cap "staticizer_2/staticizer_one_0/out" "staticizer_2/staticizer_one_0/a_77_n45#" 19.052
cap "mux_8bit_1/mux_one_0/inv2_2/Vdd!" "mux_8bit_1/in0_0" 91.282
cap "mux_8bit_1/mux_one_0/inv2_2/GND!" "mux_8bit_1/out0" 37.928
cap "staticizer_2/staticizer_one_0/out" "staticizer_2/staticizer_one_0/w_54_n57#" 2.59
cap "mux_8bit_1/sel" "mux_8bit_1/in0_0" 58.7
cap "mux_8bit_1/GND!" "mux_8bit_1/sel" 156.28
cap "ry0" "staticizer_2/staticizer_one_0/w_54_n57#" 4.329
cap "mux_8bit_1/mux_one_0/inv2_1/a_1_8#" "mux_8bit_1/in0_0" 4.95
cap "mux_8bit_1/mux_one_0/inv2_2/GND!" "mux_8bit_1/in0_0" 18.437
cap "mux_8bit_1/mux_one_0/2mux_nr_0/in0" "mux_8bit_1/in0_0" 34.083
cap "reg_5/w" "reg_5/port01" 5.072
cap "wz_addrH0" "reg_5/reg_one_7/r0" 24.728
cap "reg_5/reg_one_7/r0" "reg_5/reg_one_7/w_n11_n27#" 52.092
cap "mux_8bit_1/mux_one_0/inv2_1/GND!" "wz_addrH0" 8.954
cap "mux_8bit_1/mux_one_0/inv2_1/GND!" "reg_5/reg_one_7/w_n11_n27#" -3.444
cap "reg_5/reg_one_7/r0" "mux_8bit_1/out0" 275.521
cap "reg_5/reg_one_7/Vdd!" "ry0" 58.7
cap "mux_8bit_1/mux_one_0/inv2_1/GND!" "mux_8bit_1/out0" 400.316
cap "ry0" "reg_5/port01" 73.199
cap "wz_addrH0" "reg_5/reg_one_7/r1" 58.7
cap "reg_5/reg_one_7/r1" "reg_5/reg_one_7/w_n11_n27#" 156.28
cap "wz_addrH0" "reg_5/reg_one_7/w_n11_n27#" 117.4
cap "wz_addrH0" "mux_8bit_1/out0" -6.325
cap "mux_8bit_1/out0" "reg_5/reg_one_7/w_n11_n27#" 46.74
cap "wz_addrH0" "reg_5/reg_one_7/a_54_5#" 4.828
cap "mux_8bit_1/mux_one_0/2mux_nr_0/out" "mux_8bit_1/out0" 50.7914
cap "reg_5/reg_one_7/r0" "ry0" 48.664
cap "reg_5/reg_one_7/Vdd!" "reg_5/reg_one_7/r0" -4.884
cap "mux_8bit_1/mux_one_0/inv2_1/GND!" "ry0" -6.916
cap "ry0" "reg_5/reg_one_7/r1" 64.004
cap "ry0" "reg_5/reg_one_7/w_n11_n27#" 165.267
cap "reg_5/reg_one_7/Vdd!" "reg_5/reg_one_7/w_n11_n27#" 156.28
cap "reg_5/reg_one_7/Vdd!" "wz_addrH0" 162.612
cap "ry0" "mux_8bit_1/out0" -17.369
cap "reg_5/reg_one_7/Vdd!" "mux_8bit_1/out0" 31.758
cap "wz_addrH0" "reg_5/port00" 6.6
cap "mux_8bit_1/mux_one_0/inv2_1/GND!" "mux_8bit_1/mux_one_0/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "reg_5/port01" "reg_5/reg_one_7/w_n11_n27#" 1.628
cap "wz_addrH0" "reg_5/reg_one_7/a_4_n13#" 27.497
cap "wz_addrH0" "reg_5/reg_one_7/tmp" 4.948
cap "wz_addrH0" "reg_5/reg_one_7/Vdd!" -2.417
cap "reg_5/port01" "reg_5/reg_one_7/w_n11_n27#" 12.7375
cap "reg_6/reg_one_7/r1" "reg_6/reg_one_7/w_n11_n27#" 156.28
cap "reg_5/port00" "reg_6/reg_one_7/a_4_n13#" 87.672
cap "reg_5/port00" "reg_6/reg_one_7/r0" 26.208
cap "reg_5/reg_one_7/w_n11_n27#" "reg_5/port01" 1.628
cap "reg_5/port00" "reg_6/reg_one_7/tmp" 5.92
cap "reg_6/reg_one_7/r1" "reg_5/port01" 58.7
cap "reg_5/port01" "reg_6/reg_one_7/w_n11_n27#" 83.267
cap "reg_6/reg_one_7/w_n11_n27#" "reg_6/reg_one_7/r0" 52.092
cap "wz_addrH0" "reg_6/reg_one_7/Vdd!" 160.588
cap "wz_addrH0" "reg_5/reg_one_7/w_n11_n27#" 8.24
cap "reg_6/reg_one_7/port1" "ry0" 68.579
cap "reg_5/port00" "reg_5/w" 67.0625
cap "reg_5/port01" "reg_6/reg_one_7/r0" 19.78
cap "ry0" "reg_6/reg_one_7/Vdd!" 58.7
cap "reg_5/reg_one_7/Vdd!" "reg_5/reg_one_7/w_n11_n27#" -7.10543e-15
cap "wz_addrH0" "reg_6/reg_one_7/r1" 58.7
cap "wz_addrH0" "reg_6/reg_one_7/w_n11_n27#" 58.7
cap "reg_5/w" "reg_6/reg_one_7/w_n11_n27#" 156.28
cap "wz_addrH0" "reg_6/reg_one_7/a_54_5#" 4.828
cap "ry0" "reg_5/reg_one_7/w_n11_n27#" -2.667
cap "ry0" "reg_6/reg_one_7/r1" 64.004
cap "wz_addrH0" "reg_6/reg_one_7/a_4_n13#" 17.113
cap "wz_addrH0" "reg_6/reg_one_7/r0" 24.728
cap "reg_5/port00" "reg_6/reg_one_7/a_21_n13#" 3.96
cap "ry0" "reg_6/reg_one_7/w_n11_n27#" 101.233
cap "reg_5/w" "reg_5/port01" 69.0435
cap "wz_addrH0" "reg_6/reg_one_7/tmp" 4.948
cap "reg_6/reg_one_7/port1" "reg_5/port00" 5.5
cap "reg_5/port00" "reg_6/reg_one_7/Vdd!" 58.7
cap "ry0" "reg_6/reg_one_7/r0" 48.664
cap "reg_5/port00" "reg_5/reg_one_7/w_n11_n27#" 127.375
cap "ry0" "reg_5/port01" -17.146
cap "wz_addrH0" "reg_5/w" 58.7
cap "reg_6/reg_one_7/w_n11_n27#" "reg_6/reg_one_7/Vdd!" 156.28
cap "reg_6/reg_one_7/r1" "reg_5/port00" 64.504
cap "reg_5/port00" "reg_6/reg_one_7/w_n11_n27#" 151.215
cap "ry0" "reg_5/w" 58.7
cap "reg_5/port01" "reg_6/reg_one_7/Vdd!" 58.7
subcap "m1_2209_1774#" -380.236
cap "reg_6/w" "reg_6/port01" 127.744
cap "reg_6/port01" "reg_6/reg_one_7/w_n11_n27#" 4.295
cap "mux_8bit_2/sel" "rx_addrH0" 58.7
cap "reg_6/reg_one_7/Vdd!" "reg_6/reg_one_7/w_n11_n27#" -1.42109e-14
cap "mux_8bit_2/mux_one_0/inv2_2/Vdd!" "rx_addrH0" 17.542
cap "mux_8bit_2/mux_one_0/inv2_2/GND!" "rx_addrH0" 22.523
cap "reg_6/port01" "Vdd!" 58.7
cap "reg_6/reg_one_7/a_4_n13#" "reg_6/reg_one_7/Vdd!" -7.10543e-15
cap "reg_6/w" "ry_addrH0" 58.7
cap "reg_6/reg_one_7/w_n11_n27#" "ry_addrH0" 0.019
cap "reg_6/w" "mux_8bit_2/GND!" 156.28
cap "reg_6/port01" "reg_6/reg_one_7/w_n11_n27#" 12.7375
cap "reg_6/port01" "mux_8bit_2/out0" -10.01
cap "reg_6/reg_one_7/w_n11_n27#" "rx_addrH0" -2.286
cap "Vdd!" "ry_addrH0" 58.7
cap "reg_6/w" "rx_addrH0" 58.7
cap "mux_8bit_2/mux_one_0/inv2_2/Vdd!" "Vdd!" 2.84217e-14
cap "mux_8bit_2/GND!" "Vdd!" 156.28
cap "mux_8bit_2/mux_one_0/2mux_nr_0/in0" "rx_addrH0" 30.259
cap "reg_6/port00" "mux_8bit_2/in0_0" 3.171
cap "mux_8bit_2/mux_one_0/inv2_2/Vdd!" "mux_8bit_2/in0_0" 81.239
cap "mux_8bit_2/sel" "mux_8bit_2/in0_0" 58.7
cap "Vdd!" "rx_addrH0" 58.7
cap "mux_8bit_2/mux_one_0/inv2_1/a_1_8#" "mux_8bit_2/in0_0" 4.95
cap "mux_8bit_2/mux_one_0/inv2_2/GND!" "mux_8bit_2/in0_0" 18.437
cap "reg_6/reg_one_7/Vdd!" "reg_6/reg_one_7/tmp" -3.55271e-15
cap "mux_8bit_2/sel" "mux_8bit_2/out0" 0.84
cap "mux_8bit_2/mux_one_0/inv2_2/GND!" "mux_8bit_2/out0" 37.928
cap "reg_6/reg_one_7/Vdd!" "reg_6/port00" -7.10543e-15
cap "mux_8bit_2/in0_0" "rx_addrH0" 16.569
cap "mux_8bit_2/out0" "rx_addrH0" 19.905
cap "reg_6/reg_one_7/w_n11_n27#" "rx_addrH0" 19.776
cap "reg_6/reg_one_7/a_4_n13#" "rx_addrH0" -10.448
cap "reg_6/w" "mux_8bit_2/in0_0" 58.7
cap "mux_8bit_2/in0_0" "mux_8bit_2/mux_one_0/2mux_nr_0/in0" 34.083
cap "reg_6/port01" "mux_8bit_2/sel" 58.7
cap "Vdd!" "mux_8bit_2/in0_0" 58.7
cap "reg_6/port01" "mux_8bit_2/mux_one_0/inv2_2/GND!" 63.013
cap "reg_6/reg_one_7/w_n11_n27#" "mux_8bit_2/in0_0" 8.24
cap "reg_6/reg_one_7/Vdd!" "mux_8bit_2/in0_0" -0.393
cap "mux_8bit_2/sel" "ry_addrH0" 58.7
cap "mux_8bit_2/GND!" "mux_8bit_2/sel" 156.28
cap "reg_6/reg_one_7/a_4_n13#" "mux_8bit_2/in0_0" -1.152
cap "reg_6/port00" "rx_addrH0" 4.411
cap "mux_8bit_2/out0" "mux_8bit_2/mux_one_0/2mux_nr_0/out" 50.7914
cap "reg_7/reg_one_7/a_21_n13#" "rx_addrH0" 3.96
cap "wz_addrH0" "reg_7/reg_one_7/a_54_5#" 4.828
cap "wz_addrH0" "reg_7/port00" 6.6
cap "ry0" "reg_7/reg_one_7/Vdd!" 58.7
cap "rx_addrH0" "reg_7/reg_one_7/r0" 26.208
cap "reg_7/reg_one_7/tmp" "rx_addrH0" 5.92
cap "rx_addrH0" "reg_7/reg_one_7/w_n11_n27#" 222.213
cap "ry_addrH0" "reg_7/reg_one_7/r0" 19.78
cap "wz_addrH0" "reg_7/reg_one_7/a_4_n13#" 27.497
cap "ry_addrH0" "reg_7/reg_one_7/w_n11_n27#" 144.984
cap "mux_8bit_2/mux_one_0/inv2_1/GND!" "mux_8bit_2/mux_one_0/2mux_nr_0/a_n17_n11#" 3.55271e-15
cap "mux_8bit_2/mux_one_0/inv2_1/GND!" "rx_addrH0" 12.194
cap "reg_7/port01" "rx_addrH0" 5.5
cap "wz_addrH0" "reg_7/reg_one_7/Vdd!" 162.612
cap "reg_7/reg_one_7/Vdd!" "reg_7/reg_one_7/r0" -4.884
cap "reg_7/reg_one_7/Vdd!" "reg_7/reg_one_7/w_n11_n27#" 156.28
cap "ry0" "reg_7/reg_one_7/r0" 48.664
cap "mux_8bit_2/out0" "rx_addrH0" -6.325
cap "rx_addrH0" "reg_7/reg_one_7/r1" 64.504
cap "ry0" "reg_7/reg_one_7/w_n11_n27#" 165.267
cap "ry_addrH0" "reg_7/reg_one_7/r1" 58.7
cap "reg_7/port01" "ry0" 73.199
cap "mux_8bit_2/mux_one_0/inv2_1/GND!" "ry0" -6.916
cap "wz_addrH0" "reg_7/reg_one_7/r0" 24.728
cap "reg_7/reg_one_7/tmp" "wz_addrH0" 4.948
cap "mux_8bit_2/out0" "reg_7/reg_one_7/Vdd!" 31.758
cap "reg_7/port00" "rx_addrH0" 6.006
cap "wz_addrH0" "reg_7/reg_one_7/w_n11_n27#" 117.4
cap "reg_7/reg_one_7/w_n11_n27#" "reg_7/reg_one_7/r0" 52.092
cap "mux_8bit_2/out0" "ry0" -17.369
cap "ry0" "reg_7/reg_one_7/r1" 64.004
cap "mux_8bit_2/mux_one_0/inv2_1/GND!" "wz_addrH0" 8.954
cap "rx_addrH0" "reg_7/reg_one_7/a_4_n13#" 93.704
cap "reg_7/port01" "reg_7/reg_one_7/w_n11_n27#" 1.628
cap "mux_8bit_2/mux_one_0/inv2_1/GND!" "reg_7/reg_one_7/w_n11_n27#" -3.444
cap "reg_7/port01" "reg_7/w" 5.072
cap "rx_addrH0" "reg_7/reg_one_7/Vdd!" 58.7
cap "mux_8bit_2/out0" "wz_addrH0" -6.325
cap "mux_8bit_2/out0" "reg_7/reg_one_7/r0" 275.521
cap "wz_addrH0" "reg_7/reg_one_7/r1" 58.7
cap "reg_7/reg_one_7/Vdd!" "ry_addrH0" 58.7
cap "mux_8bit_2/out0" "reg_7/reg_one_7/w_n11_n27#" 46.74
cap "reg_7/reg_one_7/w_n11_n27#" "reg_7/reg_one_7/r1" 156.28
cap "mux_8bit_2/mux_one_0/inv2_1/GND!" "mux_8bit_2/out0" 400.316
cap "addsub_2/b0" "addsub_2/xor_0/GND!" -1.42109e-13
cap "reg_7/w" "reg_7/port01" 127.744
cap "addsub_2/b0" "addsub_2/xor_0/a_61_n31#" 4.44089e-15
cap "reg_7/w" "reg_7/port00" 125.763
cap "addsub_2/b0" "reg_7/w" 156.28
cap "wz_addrH0" "reg_7/w" 58.7
cap "addsub_2/addsub_one_0/Vdd!" "reg_7/port01" 11.825
cap "addsub_2/addsub_one_0/Vdd!" "reg_7/port00" 22.684
cap "reg_7/reg_one_7/w_n11_n27#" "reg_7/port01" -1.37
cap "reg_7/reg_one_7/w_n11_n27#" "reg_7/port00" -3.048
cap "addsub_2/addsub_one_0/Vdd!" "addsub_2/b0" 31.075
cap "wz_addrH0" "addsub_2/addsub_one_0/Vdd!" 11.825
cap "addsub_2/b0" "reg_7/port01" 23.65
cap "addsub_2/b0" "reg_7/port00" 154.575
cap "ry0" "reg_7/w" 58.7
cap "wz_addrH0" "addsub_2/b0" 17.764
cap "reg_7/reg_one_7/Vdd!" "wz_addrH0" -2.417
cap "reg_7/reg_one_7/w_n11_n27#" "reg_7/port01" 12.7375
cap "ry0" "addsub_2/addsub_one_0/Vdd!" 11.825
cap "ry0" "reg_7/port01" -17.146
cap "addsub_2/xor_0/a_61_n1#" "reg_7/port00" 50.284
cap "ry0" "reg_7/reg_one_7/w_n11_n27#" -2.667
cap "reg_7/reg_one_7/w_n11_n27#" "reg_7/port00" 135.615
cap "addsub_2/xor_0/a_61_n1#" "addsub_2/b0" 1.77636e-15
cap "wz_addrH0" "reg_7/reg_one_7/w_n11_n27#" 8.24
cap "ry0" "addsub_2/b0" 23.65
cap "reg_7/reg_one_7/Vdd!" "reg_7/reg_one_7/w_n11_n27#" -7.10543e-15
subcap "a_2516_1801#" -30.357
cap "addsub_2/addsub_one_1/a_11_9#" "addsub_2/addsub_one_0/Vdd!" 2.475
cap "addsub_2/addsub_one_0/GND!" "wz_addrH0" 4.95
cap "addsub_2/addsub_one_1/GND!" "wz_addrH0" 39.409
cap "addsub_2/addsub_one_1/a_11_n41#" "addsub_2/addsub_one_0/Vdd!" 2.475
cap "addsub_2/addsub_one_1/a_11_9#" "GND!" 46.605
cap "addsub_2/addsub_one_0/Vdd!" "addsub_2/s0" -12.402
cap "addsub_2/addsub_one_0/Vdd!" "ry0" 9.108
cap "latch_6/latch_one_0/a_n5_n54#" "addsub_2/s0" 19.2392
cap "addsub_2/addsub_one_1/a_11_n41#" "GND!" 31.965
cap "addsub_2/addsub_one_0/a_35_n41#" "addsub_2/addsub_one_1/GND!" 5.68434e-14
cap "addsub_2/addsub_one_0/a_35_n41#" "wz_addrH0" 19.78
cap "ry_addrH0" "addsub_2/addsub_one_1/GND!" 45.221
cap "GND!" "addsub_2/addsub_one_1/GND!" 97.862
cap "addsub_2/addsub_one_1/GND!" "addsub_2/addsub_one_0/b" -5.68434e-14
cap "addsub_2/addsub_one_0/cout" "ry_addrH0" 2.474
cap "addsub_2/addsub_one_0/cout" "GND!" 7.654
cap "addsub_2/addsub_one_0/Vdd!" "wz_addrH0" 22.705
cap "addsub_2/addsub_one_1/Vdd!" "GND!" 21.003
cap "addsub_2/addsub_one_0/Vdd!" "addsub_2/addsub_one_1/a" 18.408
cap "GND!" "addsub_2/addsub_one_1/a" 25.84
cap "addsub_2/addsub_one_0/Vdd!" "GND!" -0.645
cap "addsub_2/addsub_one_1/GND!" "addsub_2/s0" 76.9567
cap "addsub_2/addsub_one_0/Vdd!" "ry_addrH0" -4.455
cap "ry0" "addsub_2/addsub_one_1/GND!" 52.91
cap "addsub_2/addsub_one_0/cout" "ry0" 19.952
cap "addsub_2/s0" "wz_addrH0" 50.259
subcap "a_2516_1801#" -99.769
cap "staticizer_3/staticizer_one_0/out" "latch_6/c" 61.66
cap "staticizer_3/c" "ry0" 76.935
cap "latch_6/latch_one_0/a_12_n54#" "latch_6/Vdd!" 1.13687e-13
cap "ry0" "latch_6/Vdd!" 117.4
cap "staticizer_3/staticizer_one_0/out" "staticizer_3/staticizer_one_0/a_77_n45#" 5.115
cap "latch_6/out0" "latch_6/c" 9.252
cap "ry0" "latch_6/GND!" 181.284
cap "latch_6/c" "latch_6/Vdd!" 1070.07
cap "latch_6/GND!" "latch_6/c" 170.132
cap "latch_6/c" "ry_addrH0" 58.7
cap "latch_6/latch_one_0/a_n5_n54#" "addsub_2/s0" 57.7175
cap "staticizer_3/staticizer_one_0/out" "latch_6/latch_one_0/a_n5_n54#" 59.464
cap "staticizer_3/staticizer_one_0/out" "addsub_2/s0" 6.404
cap "ry0" "latch_6/c" 81.378
cap "latch_6/out0" "staticizer_3/staticizer_one_0/out" 7.047
cap "staticizer_3/staticizer_one_0/out" "staticizer_3/c" 61.544
cap "staticizer_3/staticizer_one_0/out" "latch_6/Vdd!" 169.606
cap "latch_6/Vdd!" "addsub_2/s0" 19.399
cap "staticizer_3/staticizer_one_0/out" "latch_6/latch_one_0/a_30_n35#" 1.88
cap "staticizer_3/staticizer_one_0/out" "latch_6/GND!" 117.4
cap "latch_6/out0" "latch_6/Vdd!" 107.428
cap "staticizer_3/staticizer_one_0/out" "staticizer_3/staticizer_one_0/a_60_n45#" 75.3524
cap "latch_6/out0" "latch_6/GND!" 10.156
cap "staticizer_3/c" "ry_addrH0" 58.7
cap "staticizer_3/c" "latch_6/GND!" 156.28
cap "latch_6/Vdd!" "ry_addrH0" 117.4
cap "addsub_2/GND!" "addsub_2/s0" 19.2392
cap "latch_6/GND!" "latch_6/Vdd!" 312.56
cap "staticizer_3/staticizer_one_0/out" "latch_6/latch_one_0/a_12_n54#" 9.708
cap "latch_6/out0" "staticizer_3/staticizer_one_0/a_60_n45#" 150.065
cap "latch_6/GND!" "ry_addrH0" 117.4
subcap "addr_out0" -56.838
cap "staticizer_3/staticizer_one_0/a_77_n45#" "staticizer_3/staticizer_one_0/out" 2.728
cap "staticizer_3/staticizer_one_0/w_54_n57#" "staticizer_3/staticizer_one_0/c" -1.42109e-14
cap "latch_7/GND!" "ry_addrH0" 77.41
cap "ry_addrH0" "latch_7/Vdd!" 117.4
cap "latch_7/latch_one_0/a_12_n54#" "latch_7/Vdd!" 1.13687e-13
cap "latch_7/c" "latch_7/Vdd!" 1070.07
cap "staticizer_3/staticizer_one_0/Vdd!" "latch_7/in0" 11.463
cap "latch_7/GND!" "latch_7/c" 170.132
cap "latch_7/out0" "latch_7/c" 9.252
cap "staticizer_3/staticizer_one_0/Vdd!" "staticizer_3/staticizer_one_0/out" 6.001
cap "latch_7/c" "ry_addrH0" 58.7
cap "latch_7/in0" "latch_7/latch_one_0/a_n5_n54#" 57.7175
cap "staticizer_3/staticizer_one_0/Vdd!" "staticizer_3/staticizer_one_0/a_77_n45#" 2.84217e-14
cap "latch_7/GND!" "staticizer_4/staticizer_one_0/a_60_n45#" 5.68434e-14
cap "latch_7/in0" "latch_7/Vdd!" 286.786
cap "latch_7/GND!" "latch_7/in0" 6.956
cap "latch_7/in0" "staticizer_3/staticizer_one_0/out" 23.087
cap "staticizer_3/staticizer_one_0/a_60_n45#" "staticizer_3/staticizer_one_0/out" 0.709429
cap "latch_7/latch_one_0/a_n5_n54#" "latch_7/Vdd!" -1.13687e-13
cap "staticizer_3/staticizer_one_0/w_54_n57#" "latch_7/in0" 17.972
cap "latch_7/out0" "staticizer_4/staticizer_one_0/a_60_n45#" 150.065
cap "latch_7/GND!" "latch_7/Vdd!" 311.822
cap "staticizer_3/staticizer_one_0/w_54_n57#" "staticizer_3/staticizer_one_0/out" 8.272
cap "latch_7/out0" "latch_7/Vdd!" 107.428
cap "latch_7/GND!" "latch_7/out0" 10.156
subcap "ry_addrH0" -836.866
subcap "addr_out8" -305.874
cap "latch_8/in0" "staticizer_4/c" 58.7
cap "latch_8/in0" "staticizer_4/staticizer_one_0/Vdd!" 11.463
cap "latch_8/in0" "staticizer_4/staticizer_one_0/out" 57.7175
cap "latch_8/Vdd!" "latch_8/latch_one_0/a_12_n54#" 1.13687e-13
cap "latch_8/c" "staticizer_5/in0" -0.42
cap "latch_8/in0" "latch_8/latch_one_0/a_n5_n54#" 57.7175
cap "latch_8/in0" "staticizer_4/GND!" 28.061
cap "staticizer_4/staticizer_one_0/Vdd!" "staticizer_4/staticizer_one_0/a_77_n45#" 1.13687e-13
cap "latch_8/latch_one_0/a_n5_n54#" "latch_8/Vdd!" -1.13687e-13
cap "latch_8/Vdd!" "staticizer_4/GND!" 156.28
cap "latch_8/in0" "latch_8/Vdd!" 367.261
cap "staticizer_4/staticizer_one_0/Vdd!" "staticizer_4/staticizer_one_0/out" -5.68434e-14
cap "latch_8/Vdd!" "staticizer_5/in0" -1.162
cap "staticizer_4/staticizer_one_0/a_60_n45#" "staticizer_4/GND!" 2.84217e-14
cap "staticizer_4/GND!" "staticizer_4/c" 156.28
cap "staticizer_5/Vdd!" "staticizer_5/in0" 107.428
cap "latch_8/c" "staticizer_5/in0" 9.252
cap "staticizer_5/Vdd!" "staticizer_5/GND!" 156.28
cap "latch_8/c" "staticizer_5/GND!" 170.132
cap "staticizer_5/staticizer_one_0/a_60_n45#" "staticizer_5/in0" 150.065
cap "staticizer_5/in0" "staticizer_5/GND!" 10.156
cap "staticizer_5/GND!" "staticizer_5/c" 156.28
cap "latch_8/c" "staticizer_5/Vdd!" 1070.07
subcap "data_out0" -209.716
subcap "m1_n42_1842#" -39.925
subcap "rd_dataout" -45.482
subcap "m1_n56_1860#" -41.198
cap "staticizer_1/GND!" "staticizer_1/Vdd!" 22.779
cap "staticizer_1/Vdd!" "latch_4/c" 33.991
cap "staticizer_1/GND!" "latch_4/c" 33.171
cap "staticizer_1/Vdd!" "staticizer_1/c" 6.84
subcap "m1_65_1845#" -32.826
subcap "ld_datain" -117.642
cap "latch_0/c" "4nor2_0/GND!" 39.372
cap "latch_0/GND!" "4nor2_0/GND!" 9.808
cap "latch_0/c" "4nor2_0/out" 90.1832
cap "latch_0/c" "4nor2_0/Vdd!" 66.904
cap "4nor2_0/out" "4nor2_0/Vdd!" -13.532
cap "4nor2_0/Vdd!" "staticizer_0/Vdd!" 3.734
subcap "wz0" -2839.21
subcap "m1_136_1836#" -34.45
subcap "ros" -394.529
subcap "ras" -1107.34
subcap "rfb" -1238.24
cap "staticizer_0/c" "4nor2_0/Vdd!" 20.074
cap "4nor2_0/c" "shift_0/shift_one_0/inv_0/out" 5.94
cap "4nor2_0/c" "4nor2_0/Vdd!" 181.828
cap "staticizer_0/staticizer_one_0/out" "staticizer_0/c" 7.69567
cap "4nor2_0/b" "4nor2_0/Vdd!" 181.828
cap "4nor2_0/c" "shift_0/shift_one_0/inv_0/Vdd!" 35.586
cap "4nor2_0/Vdd!" "4nor2_0/a" 181.828
cap "rfb" "shift_0/u" 28.824
cap "shift_0/u" "ros" 59.69
cap "ros" "shift_0/shift_one_0/2mux_nr_1/Vdd!" 1.724
cap "ros" "shift_0/shift_one_0/inv_0/Vdd!" -0.274
cap "shift_0/shift_one_0/GND!" "ros" 189.796
cap "shift_0/shift_one_0/inv_0/out" "ros" 46.885
cap "ros" "shift_0/shift_one_0/2mux_nr_0/Vdd!" 22.973
cap "ros" "shift_0/s" 59.69
cap "ros" "shift_0/shift_one_0/2mux_nr_1/GND!" 126.614
cap "shift_0/s" "rfb" 28.824
cap "ros" "shift_0/shift_one_0/2mux_nr_1/Vdd!" 17.82
subcap "fb_g1" -71.727
subcap "fb_g2" -9.681
subcap "fb_g3" -6.2
cap "fblock_0/g2" "rfb" 58.7
cap "fblock_0/g2" "fblock_0/b0" 58.7
cap "ras" "fblock_0/g3" 58.7
cap "fblock_0/fblock_one_0/inv_1/out" "ras" 31.68
cap "fblock_0/fblock_one_0/2mux_nr_1/Vdd!" "rfb" 62.239
cap "fblock_0/fblock_one_0/inv_2/out" "ras" 23.34
cap "fblock_0/fblock_one_0/2mux_nr_1/Vdd!" "fblock_0/b0" 13.163
cap "fblock_0/fblock_one_0/2mux_nr_0/a_n17_n11#" "fblock_0/b0" 34.591
cap "fblock_0/fblock_one_0/Vdd!" "fblock_0/g3" 11.054
cap "rfb" "fblock_0/g3" 58.7
cap "fblock_0/fblock_one_0/2mux_nr_0/out" "fblock_0/b0" 11.825
cap "fblock_0/b0" "fblock_0/GND!" 11.577
cap "fblock_0/fblock_one_0/inv_1/out" "rfb" 16.49
cap "fblock_0/fblock_one_0/GND!" "ras" 51.025
cap "fblock_0/b0" "fblock_0/g3" 140.424
cap "fblock_0/fblock_one_0/inv_1/out" "fblock_0/b0" 4.95
cap "fblock_0/fblock_one_0/inv_2/out" "rfb" 23.085
cap "fblock_0/b0" "rfb" 10.608
cap "fblock_0/g2" "ras" 58.7
cap "fblock_0/b0" "fblock_0/fblock_one_0/inv_2/out" 11.825
cap "fblock_0/g2" "fblock_0/fblock_one_0/Vdd!" 7.49
subcap "fb_g0" -9.435
subcap "fb_g1" -10.955
cap "rfb" "fblock_0/fblock_one_0/inv_3/out" 23.085
cap "rfb" "fblock_0/fblock_one_0/2mux_nr_1/s" 7.488
cap "fblock_0/fblock_one_0/inv_4/out" "ras" 11.044
cap "ras" "fblock_0/Vdd!" 88.368
cap "ras" "fblock_0/fblock_one_0/inv_3/out" 32.24
cap "ry0" "fblock_0/fblock_one_0/2mux_nr_1/out" 11.825
cap "rfb" "fblock_0/g0" 58.7
cap "fblock_0/g1" "rfb" 58.7
cap "ry0" "fblock_0/fblock_one_0/inv_3/GND!" 24.128
cap "ras" "fblock_0/g0" 58.7
cap "ras" "fblock_0/g1" 58.7
cap "fblock_0/Vdd!" "ry0" 83.852
cap "fblock_0/fblock_one_0/inv_4/out" "ry0" 2.75
cap "fblock_0/Vdd!" "fblock_0/g0" 7.49
cap "fblock_0/Vdd!" "fblock_0/g1" 7.49
cap "fblock_0/fblock_one_0/inv_3/out" "ry0" 4.95
cap "ry0" "fblock_0/fblock_one_0/2mux_nr_1/s" 16.386
cap "rfb" "fblock_0/fblock_one_0/inv_3/GND!" 19.78
cap "fblock_0/g0" "ry0" 58.7
cap "fblock_0/g1" "ry0" 58.7
cap "fblock_0/fblock_one_0/inv_4/out" "rfb" 18.632
cap "fblock_0/Vdd!" "rfb" 128.172
cap "ras" "fblock_0/fblock_one_0/inv_3/GND!" 44.047
cap "ry0" "fblock_0/fblock_one_0/2mux_nr_1/a_n17_n11#" 31.949
subcap "as_sub" -30.66
cap "ras" "addsub_0/xor_0/GND!" 11.825
cap "addsub_0/xor_0/out" "ry0" 31.486
cap "ry0" "addsub_0/xor_0/a_89_n31#" 3.068
cap "ry0" "addsub_0/xor_0/GND!" 39.103
cap "addsub_0/xor_0/a_61_n31#" "ry0" 7.218
cap "ry0" "addsub_0/sub" 4.168
cap "ry0" "addsub_0/xor_0/a_100_n42#" 0.707
cap "addsub_0/addsub_one_0/a_11_n41#" "ras" 19.78
cap "addsub_0/addsub_one_0/a_66_n41#" "as_cout" 2.1
cap "addsub_0/addsub_one_0/a_35_n41#" "as_cout" 14.854
cap "addsub_0/addsub_one_0/b" "as_cout" 12.612
cap "addsub_0/xor_0/a_89_n31#" "addsub_0/a0" 2.424
cap "addsub_0/addsub_one_0/a_72_n41#" "as_cout" 2.1
cap "addsub_0/addsub_one_0/a_11_9#" "ras" 23.59
cap "addsub_0/addsub_one_0/b" "addsub_0/a0" 36.877
cap "addsub_0/addsub_one_0/a_35_n41#" "addsub_0/addsub_one_0/GND!" 2.27374e-13
cap "as_cout" "addsub_0/addsub_one_0/cin" 12.612
cap "as_cout" "addsub_0/a0" 12.612
cap "addsub_0/addsub_one_0/a_89_n41#" "as_cout" 11.7
cap "addsub_0/addsub_one_0/GND!" "as_cout" 64.179
cap "addsub_0/addsub_one_0/a_11_n41#" "as_cout" 21.93
cap "addsub_0/Vdd!" "addsub_0/a0" 100.243
cap "addsub_0/addsub_one_0/a_35_n41#" "ras" 58.475
cap "addsub_0/xor_0/a_61_n31#" "addsub_0/a0" 2.424
cap "addsub_0/xor_0/a_61_n1#" "addsub_0/a0" 85.487
cap "as_cout" "addsub_0/addsub_one_0/a_78_n41#" 10.86
cap "ras" "addsub_0/addsub_one_0/cin" 19.884
cap "as_cout" "addsub_0/addsub_one_0/a_29_n41#" 2.1
cap "addsub_0/Vdd!" "ras" 33.301
cap "ras" "addsub_0/a0" 3.388
cap "addsub_0/addsub_one_0/GND!" "ras" 10.875
subcap "A_r1" -27.836
subcap "as_cin" -17.42
subcap "as_cout" -1614.1
cap "reg_0/in0" "reg_0/r0" 153.495
cap "latch_2/GND!" "latch_2/Vdd!" 21.252
cap "latch_2/c" "addsub_0/addsub_one_0/GND!" 28.429
cap "latch_2/GND!" "latch_2/c" 19.274
cap "latch_2/Vdd!" "latch_one_0/a_n5_n54#" 12.624
cap "addsub_0/addsub_one_0/GND!" "addsub_0/cin" 101.744
cap "latch_2/c" "addsub_0/cin" -0.864
cap "latch_2/c" "latch_one_0/out" 8.196
subcap "A_w" -210.148
subcap "A_r1" -1.23
subcap "DB_r0" -22.058
subcap "m1_985_1902#" -0.389
subcap "m1_952_1914#" -180.741
subcap "m1_940_1901#" -58.018
cap "reg_0/w" "wz0" 63.082
cap "reg_0/reg_one_7/w_n11_n27#" "wz0" 8.24
cap "reg_one_0/a_4_n13#" "latch_one_0/Vdd!" -5.81
cap "reg_one_0/r0" "reg_one_0/a_4_n13#" 145.492
cap "reg_one_0/r0" "staticizer_one_0/c" 50.0725
cap "latch_one_0/Vdd!" "reg_one_0/Vdd!" -6.105
cap "reg_one_0/r0" "reg_one_0/r1" -5.68434e-14
cap "reg_0/in0" "reg_0/r0" -5.072
cap "reg_0/reg_one_7/a_33_32#" "wz0" 65.474
cap "reg_one_0/r0" "staticizer_one_0/a_60_n45#" 17.421
cap "wz0" "reg_1/r0" 63.6875
cap "reg_0/reg_one_7/a_16_27#" "wz0" 8.264
cap "reg_one_0/r0" "wz0" 58.7
cap "reg_0/r1" "wz0" 58.7
cap "latch_one_0/c" "reg_one_0/r0" 23.087
cap "staticizer_one_0/a_77_n45#" "staticizer_one_0/c" 8.085
cap "wz0" "reg_0/reg_one_7/tmp" 8.713
cap "reg_0/in0" "wz0" 14.786
cap "wz0" "reg_0/r0" -7.416
cap "reg_0/Vdd!" "wz0" 58.7
cap "wz0" "reg_0/reg_one_7/Vdd!" 106.383
cap "staticizer_one_0/a_60_n45#" "staticizer_one_0/c" 17.421
subcap "DB_w" -210.148
subcap "DB_r1" -1.23
cap "reg_1/in0" "reg_1/reg_one_7/a_33_32#" 65.474
cap "reg_1/in0" "reg_1/GND!" 58.7
cap "reg_1/w" "reg_1/in0" 63.082
cap "reg_1/reg_one_7/tmp" "reg_1/in0" 8.713
cap "reg_1/reg_one_7/a_16_27#" "reg_1/in0" 8.264
cap "reg_1/r1" "reg_1/in0" 58.7
cap "reg_1/reg_one_7/Vdd!" "reg_1/r1" 1.77636e-15
cap "reg_1/in0" "reg_1/Vdd!" 58.7
cap "reg_1/in0" "reg_1/r0" 89.8075
cap "reg_1/reg_one_7/w_n11_n27#" "reg_1/in0" 8.24
cap "reg_1/reg_one_7/Vdd!" "reg_1/in0" 106.383
subcap "X_r1" -1.23
cap "reg_2/r1" "reg_2/reg_one_7/Vdd!" 1.77636e-15
cap "reg_2/w" "reg_2/reg_one_7/Vdd!" -7.10543e-15
cap "reg_2/reg_one_7/a_16_27#" "reg_2/in0" 2.764
cap "reg_2/reg_one_7/w_n11_n27#" "reg_2/in0" 8.24
cap "reg_2/in0" "reg_2/GND!" 58.7
cap "reg_2/in0" "reg_2/reg_one_7/tmp" 8.713
cap "reg_2/r0" "reg_2/in0" 153.495
cap "reg_2/reg_one_7/a_33_32#" "reg_2/in0" 65.474
cap "reg_2/Vdd!" "reg_2/in0" 58.7
cap "reg_2/reg_one_7/Vdd!" "reg_2/in0" 88.158
cap "reg_2/in0" "reg_2/reg_one_7/Vdd!" 18.225
cap "reg_2/r1" "reg_2/in0" 58.7
cap "reg_2/in0" "reg_2/reg_one_7/w" 1.422
cap "reg_2/w" "reg_2/in0" 61.66
cap "reg_2/reg_one_7/a_16_27#" "reg_2/in0" 5.5
subcap "Y_r1" -1.23
subcap "X_w" -104.776
cap "reg_3/reg_one_7/w_n11_n27#" "reg_3/in0" 17.302
cap "reg_3/reg_one_7/tmp" "reg_3/in0" 7.848
cap "reg_3/Vdd!" "reg_3/in0" 58.7
cap "reg_3/reg_one_7/Vdd!" "reg_3/r1" 1.77636e-15
cap "reg_3/reg_one_7/a_16_27#" "reg_3/in0" 2.496
cap "reg_3/reg_one_7/a_16_27#" "reg_3/in0" 4.95
cap "reg_3/r1" "reg_3/in0" 58.7
cap "reg_3/reg_one_7/Vdd!" "reg_3/in0" 16.54
cap "reg_3/GND!" "reg_3/in0" 58.7
cap "reg_3/reg_one_7/a_33_32#" "reg_3/in0" 39.098
cap "reg_3/w" "reg_3/in0" 1.248
cap "reg_3/r0" "reg_3/in0" 153.495
subcap "m1_1422_1870#" -271.496
subcap "m1_1422_1899#" -534.65
cap "reg_3/reg_one_7/a_33_32#" "mux_8bit_0/in1_0" -4.455
cap "mux_8bit_0/in1_0" "reg_3/reg_one_7/w_n11_n27#" 8.24
cap "mux_8bit_0/in1_0" "mux_8bit_0/mux_one_0/2mux_nr_0/a_n17_n11#" 36.092
cap "mux_8bit_0/in1_0" "mux_8bit_0/mux_one_0/2mux_nr_0/in1" 18.535
cap "mux_8bit_0/in1_0" "mux_8bit_0/sel" 63.256
cap "mux_8bit_0/in1_0" "mux_8bit_0/Vdd!" 98.617
cap "mux_8bit_0/in1_0" "reg_3/reg_one_7/Vdd!" -2.948
cap "mux_8bit_0/GND!" "mux_8bit_0/mux_one_0/2mux_nr_0/in1" 1.42109e-14
cap "mux_8bit_0/GND!" "mux_8bit_0/sel" 3.511
cap "reg_3/w" "mux_8bit_0/in1_0" 58.7
cap "inv2_6/a_6_n1#" "mux_8bit_0/Vdd!" 2.84217e-14
cap "mux_8bit_0/in1_0" "reg_3/reg_one_7/w_n11_n27#" -2.948
cap "mux_8bit_0/in1_0" "mux_8bit_0/GND!" 15.908
cap "mux_8bit_0/Vdd!" "mux_8bit_0/sel" 3.511
cap "reg_3/w" "reg_3/reg_one_7/w_n11_n27#" 1.42109e-14
subcap "PCL_w" -189.023
subcap "PCL_r1" -1.23
subcap "m1_1422_1870#" -36.18
subcap "m1_1422_1899#" -299.334
cap "reg_4/r0" "mux_8bit_0/GND!" 165.587
cap "reg_4/in0" "wz0" 2.844
cap "reg_4/in0" "reg_4/reg_one_7/Vdd!" 24.786
cap "wz0" "reg_4/r1" 58.7
cap "wz0" "reg_4/w" 5.064
cap "reg_4/in0" "mux_8bit_0/mux_one_0/2mux_nr_0/out" 44.5249
cap "reg_4/in0" "reg_4/r0" 38.48
cap "reg_4/in0" "mux_8bit_0/GND!" 61.8402
cap "wz0" "mux_8bit_0/mux_one_0/2mux_nr_0/s" 4.948
cap "wz0" "reg_4/reg_one_7/tmp" 6.507
cap "reg_4/reg_one_7/a_33_32#" "wz0" 7.959
cap "wz0" "reg_4/reg_one_7/a_16_27#" 8.022
cap "wz0" "reg_4/r0" 19.78
cap "reg_4/r0" "reg_4/reg_one_7/Vdd!" -4.884
cap "wz0" "mux_8bit_0/GND!" 67.786
cap "wz0" "reg_4/reg_one_7/w_n11_n27#" 133.528
cap "wz0" "reg_4/GND!" 58.7
cap "wz0" "reg_4/Vdd!" 58.7
cap "wz0" "mux_8bit_0/mux_one_0/2mux_nr_0/a_n17_n11#" -5.178
subcap "rx_PCL0" -299.525
cap "addsub_1/xor_0/a_61_n31#" "addsub_1/a0" 2.424
cap "reg_4/reg_one_7/a_33_32#" "wz0" -12.339
cap "wz0" "addsub_1/Vdd!" 15.72
cap "wz0" "addsub_1/xor_0/a_61_n1#" 5.568
cap "addsub_1/addsub_one_0/b" "addsub_1/a0" 36.877
cap "addsub_1/Vdd!" "addsub_1/a0" 104.832
cap "addsub_1/xor_0/a_61_n1#" "addsub_1/a0" 123.965
cap "wz0" "reg_4/reg_one_7/w_n11_n27#" -8.24
cap "wz0" "addsub_1/sub" 26.517
cap "reg_4/reg_one_7/w_n11_n27#" "wz0" -2.417
cap "wz0" "reg_4/w" 58.7
cap "addsub_1/xor_0/a_89_n31#" "wz0" 17.316
cap "addsub_1/xor_0/a_89_n31#" "addsub_1/sub" 2.4869e-14
cap "addsub_1/xor_0/a_61_n31#" "wz0" 19.78
cap "addsub_1/xor_0/a_61_n31#" "addsub_1/sub" -9.76996e-15
cap "wz0" "addsub_1/addsub_one_0/b" 97.913
cap "addsub_1/xor_0/a_89_n31#" "addsub_1/a0" 2.424
subcap "addsub1_a0" -267.132
cap "addsub_1/addsub_one_0/a_78_n41#" "wz0" 35.835
cap "addsub_1/addsub_one_0/a_72_n41#" "a_2510_1893#" 2.1
cap "addsub_1/addsub_one_0/a_78_n41#" "a_2510_1893#" 10.86
cap "a_2510_1893#" "addsub_1/a0" 4.204
cap "wz0" "addsub_1/addsub_one_0/a_35_n41#" 51.712
cap "a_2510_1893#" "addsub_1/addsub_one_0/a_35_n41#" 15.544
cap "wz0" "addsub_1/addsub_one_0/GND!" 38.289
cap "a_2510_1893#" "addsub_1/addsub_one_0/GND!" 74.734
cap "wz0" "addsub_1/addsub_one_0/b" 95.736
cap "addsub_1/addsub_one_0/a_11_n41#" "addsub_1/Vdd!" 114.315
cap "a_2510_1893#" "addsub_1/addsub_one_0/b" 8.408
cap "addsub_1/Vdd!" "addsub_1/addsub_one_0/a_89_9#" -4.61853e-14
cap "addsub_1/Vdd!" "addsub_1/addsub_one_0/a_78_n41#" -1.42109e-14
cap "a_2510_1893#" "addsub_1/addsub_one_0/a_89_n41#" 11.7
cap "addsub_1/Vdd!" "addsub_1/a0" 62.736
cap "addsub_1/Vdd!" "addsub_1/addsub_one_0/a_35_n41#" -4.26326e-14
cap "a_2510_1893#" "addsub_1/addsub_one_0/a_66_n41#" 2.1
cap "addsub_1/addsub_one_0/a_11_n41#" "addsub_1/addsub_one_0/GND!" -5.68434e-14
cap "addsub_1/Vdd!" "addsub_1/addsub_one_0/GND!" 203.242
cap "addsub_1/Vdd!" "wz0" 4.731
cap "addsub_1/Vdd!" "a_2510_1893#" 16.036
cap "addsub_1/Vdd!" "addsub_1/addsub_one_0/a_11_9#" 141.295
cap "addsub_1/Vdd!" "addsub_1/addsub_one_0/b" 1.98952e-13
cap "addsub_1/addsub_one_0/a_11_n41#" "a_2510_1893#" 11.28
subcap "m1_1796_1867#" -0.154
subcap "rPCplus1L" -54.962
subcap "m1_1793_1885#" -46.013
subcap "a_1710_1893#" -275.575
cap "wz0" "latch_5/c" 4.948
cap "latch_5/Vdd!" "inv2_4/GND!" 15.768
cap "latch_5/Vdd!" "latch_5/c" 65.831
cap "latch_5/Vdd!" "wz0" 19.181
cap "inv2_4/a_6_n1#" "inv2_4/GND!" 4.5
cap "wz0" "inv2_4/a_6_n1#" 11.019
cap "addsub_1/GND!" "a_1710_1893#" 19.2392
cap "a_2510_1893#" "inv2_4/GND!" 11.43
cap "latch_5/c" "inv2_4/GND!" 3.265
subcap "m1_1922_1870#" -271.496
subcap "m1_1922_1899#" -534.65
cap "mux_8bit_1/sel" "mux_8bit_1/GND!" 3.511
cap "a_2510_1893#" "mux_8bit_1/GND!" 16.135
cap "mux_8bit_1/in1_0" "mux_8bit_1/GND!" 15.908
cap "mux_8bit_1/Vdd!" "mux_8bit_1/sel" 3.511
cap "mux_8bit_1/Vdd!" "inv2_12/a_6_n1#" 2.84217e-14
cap "mux_8bit_1/Vdd!" "a_2510_1893#" 44.529
cap "inv2_12/a_6_n1#" "a_2510_1893#" 13.073
cap "mux_8bit_1/sel" "mux_8bit_1/in1_0" 63.256
cap "mux_8bit_1/mux_one_0/2mux_nr_0/a_n17_n11#" "mux_8bit_1/in1_0" 36.092
cap "mux_8bit_1/Vdd!" "mux_8bit_1/in1_0" 96.331
cap "mux_8bit_1/mux_one_0/2mux_nr_0/in1" "mux_8bit_1/in1_0" 18.535
subcap "PCH_w" -189.023
subcap "PCH_r1" -1.23
subcap "m1_1922_1870#" -36.18
subcap "m1_1922_1899#" -299.334
cap "reg_5/r0" "reg_5/in0" 38.48
cap "a_2510_1893#" "mux_8bit_1/GND!" 10.598
cap "reg_5/in0" "mux_8bit_1/mux_one_0/2mux_nr_0/out" 44.5249
cap "reg_5/reg_one_7/a_16_27#" "wz0" 8.022
cap "reg_5/r0" "reg_5/reg_one_7/Vdd!" -4.884
cap "reg_5/w" "wz0" 5.064
cap "mux_8bit_1/GND!" "wz0" 67.786
cap "reg_5/r0" "wz0" 19.78
cap "reg_5/r0" "mux_8bit_1/GND!" 165.587
cap "reg_5/reg_one_7/w_n11_n27#" "wz0" 133.528
cap "reg_5/reg_one_7/Vdd!" "reg_5/in0" 24.786
cap "reg_5/GND!" "wz0" 58.7
cap "reg_5/Vdd!" "wz0" 58.7
cap "reg_5/reg_one_7/tmp" "wz0" 6.507
cap "reg_5/reg_one_7/a_33_32#" "wz0" 7.959
cap "reg_5/in0" "wz0" 2.844
cap "reg_5/in0" "mux_8bit_1/GND!" 61.8402
cap "reg_5/r1" "wz0" 58.7
cap "mux_8bit_1/mux_one_0/2mux_nr_0/a_n17_n11#" "wz0" -5.178
cap "mux_8bit_1/mux_one_0/2mux_nr_0/s" "wz0" 4.948
subcap "ABL_w" -116.733
subcap "ABL_r1" -1.23
cap "reg_6/in0" "reg_5/reg_one_7/w_n11_n27#" -2.417
cap "reg_5/w" "reg_5/reg_one_7/w_n11_n27#" 2.84217e-14
cap "reg_5/reg_one_7/a_33_32#" "reg_6/in0" -12.339
cap "reg_6/GND!" "reg_6/in0" 58.7
cap "reg_6/in0" "reg_6/Vdd!" 58.7
cap "reg_6/in0" "reg_6/reg_one_7/a_16_27#" 6.6
cap "reg_6/r0" "reg_6/in0" 128.02
cap "reg_6/in0" "reg_6/reg_one_7/w_n11_n27#" 123.733
cap "reg_6/w" "reg_6/in0" 5.064
cap "reg_6/reg_one_7/a_33_32#" "reg_6/in0" 2.844
cap "reg_6/r1" "reg_6/reg_one_7/Vdd!" 1.77636e-15
cap "reg_6/reg_one_7/tmp" "reg_6/in0" 4.461
cap "reg_6/reg_one_7/a_16_27#" "reg_6/in0" 1.422
cap "reg_6/r1" "reg_6/in0" 58.7
cap "reg_5/w" "reg_6/in0" 58.7
cap "reg_5/reg_one_7/w_n11_n27#" "reg_6/in0" -8.24
subcap "ABL_w" -154.204
subcap "m1_2222_1870#" -271.496
subcap "m1_2222_1899#" -534.65
cap "mux_8bit_2/GND!" "a_2510_1893#" 16.135
cap "mux_8bit_2/in1_0" "reg_6/w" 97.0214
cap "mux_8bit_2/Vdd!" "a_2510_1893#" 44.529
cap "inv2_16/a_6_n1#" "a_2510_1893#" 13.073
cap "reg_6/reg_one_7/w_n11_n27#" "mux_8bit_2/in1_0" -1.886
cap "mux_8bit_2/GND!" "mux_8bit_2/in1_0" 2.035
cap "mux_8bit_2/sel" "mux_8bit_2/GND!" 3.511
cap "mux_8bit_2/in1_0" "mux_8bit_2/Vdd!" 2.035
cap "mux_8bit_2/sel" "mux_8bit_2/Vdd!" 3.511
cap "mux_8bit_2/mux_one_0/2mux_nr_0/in1" "mux_8bit_2/GND!" 1.42109e-14
cap "mux_8bit_2/in1_0" "reg_6/reg_one_7/w_n11_n27#" 48.9529
cap "mux_8bit_2/in1_0" "reg_6/reg_one_7/tmp" -4.818
cap "mux_8bit_2/in1_0" "reg_6/reg_one_7/a_33_32#" 5.115
cap "inv2_16/a_6_n1#" "mux_8bit_2/Vdd!" 2.84217e-14
cap "reg_6/reg_one_7/w_n11_n27#" "reg_6/reg_one_7/tmp" -7.10543e-15
subcap "ABH_w" -189.649
subcap "ABH_r1" -1.23
subcap "m1_2222_1870#" -36.18
subcap "m1_2222_1899#" -299.334
cap "reg_7/r0" "reg_7/reg_one_7/Vdd!" -4.884
cap "mux_8bit_2/mux_one_0/2mux_nr_0/out" "reg_7/in0" 44.5249
cap "reg_7/in0" "reg_7/reg_one_7/Vdd!" 24.786
cap "reg_7/in0" "reg_7/r0" 38.48
cap "a_2510_1893#" "mux_8bit_2/GND!" 10.598
cap "mux_8bit_2/GND!" "reg_7/r0" 165.587
cap "reg_7/in0" "mux_8bit_2/GND!" 61.8402
subcap "rx_addrH0" -685.645
cap "addsub_2/sub" "addsub_2/xor_0/a_89_n31#" 2.84217e-14
cap "addsub_2/a0" "addsub_2/xor_0/a_89_n31#" 2.424
cap "addsub_2/a0" "addsub_2/xor_0/Vdd!" 104.832
cap "addsub_2/addsub_one_0/b" "addsub_2/a0" 36.877
cap "addsub_2/xor_0/a_61_n1#" "addsub_2/a0" 123.965
cap "addsub_2/a0" "addsub_2/xor_0/a_61_n31#" 2.424
cap "a_2510_1893#" "addsub_2/xor_0/Vdd!" 11.825
cap "addsub_2/sub" "a_2510_1893#" 11.825
subcap "a_2510_1893#" -2109.14
cap "addsub_2/cin" "addsub_2/addsub_one_0/a_35_n41#" 64.64
cap "addsub_2/addsub_one_0/GND!" "addsub_2/cin" 129.086
cap "addsub_2/cin" "addsub_2/addsub_one_0/Vdd!" 1.767
cap "addsub_2/addsub_one_0/GND!" "addsub_2/addsub_one_0/a_11_n41#" 2.84217e-14
cap "addsub_2/addsub_one_0/a_11_9#" "addsub_2/cin" 23.59
cap "addsub_2/addsub_one_0/Vdd!" "addsub_2/cin" 11.825
cap "addsub_2/cin" "addsub_2/addsub_one_0/a_11_n41#" 21.685
cap "addsub_2/cin" "addsub_2/a0" 3.388
subcap "m1_2596_1867#" -0.154
subcap "rPCplus1H" -54.962
subcap "m1_2593_1885#" -46.013
subcap "a_2510_1893#" -2146.7
cap "addsub_2/GND!" "a_2510_1893#" 19.2392
cap "latch_6/c" "latch_6/Vdd!" 65.831
cap "staticizer_3/c" "staticizer_3/GND!" 4.5
cap "latch_6/Vdd!" "staticizer_3/GND!" 15.768
cap "latch_6/c" "staticizer_3/GND!" 3.265
subcap "m1_2720_1867#" -114.073
subcap "rd_addrL" -54.962
subcap "m1_2717_1885#" -84.81
cap "latch_7/c" "inv2_1/GND!" 3.265
cap "latch_7/c" "latch_7/Vdd!" 65.831
cap "latch_7/Vdd!" "inv2_1/GND!" 13.716
cap "inv2_1/a_6_n1#" "inv2_1/GND!" 5.1
subcap "rd_addrH" -111.725
subcap "m1_2720_1867#" -32.14
subcap "m1_2717_1885#" -58.547
cap "inv2_1/GND!" "inv2_1/a_6_n1#" -5.22
cap "inv2_1/GND!" "inv2_1/Vdd!" 1.56
subcap "m1_2844_1867#" -0.154
subcap "rd_addrH" -62.762
subcap "m1_2841_1885#" -43.689
cap "staticizer_5/GND!" "staticizer_5/Vdd!" 15.768
cap "latch_8/c" "staticizer_5/Vdd!" 71.641
cap "staticizer_5/GND!" "staticizer_5/c" 4.5
cap "latch_8/c" "staticizer_5/GND!" 9.075
cap "fblock_0/fblock_one_0/Vdd!" "fb_g3" 22.102
cap "fb_g2" "fblock_0/fblock_one_0/Vdd!" 19.548
cap "fblock_0/fblock_one_0/inv_3/Vdd!" "fb_g1" 19.548
cap "fblock_0/fblock_one_0/inv_3/Vdd!" "fb_g0" 19.548
cap "as_cout" "addsub_0/GND!" 11.7
subcap "m1_877_1966#" -96.856
subcap "as_cout" -1306.66
subcap "wzCflag" -597.158
subcap "a_860_1991#" -106.18
cap "latch_one_0/GND!" "latch_one_1/in" 1.744
cap "ras" "latch_one_1/out" 24.732
cap "2nor_0/Vdd!" "latch_one_0/GND!" 1.61
cap "latch_one_1/c" "latch_one_1/a_n5_n54#" 1.988
cap "latch_one_0/GND!" "latch_one_1/out" -3.55271e-15
cap "latch_one_0/a_n5_n54#" "latch_one_0/GND!" 1.42109e-14
cap "ras" "latch_one_0/GND!" 1.1
cap "latch_one_1/c" "latch_one_1/a_12_n54#" 15.3433
cap "latch_one_1/a_n5_n54#" "latch_one_1/in" 261.653
cap "latch_one_1/c" "latch_one_1/in" 70.609
cap "2nor_0/Vdd!" "latch_one_1/a_n5_n54#" 52.438
cap "2nor_0/Vdd!" "latch_one_1/c" 59.522
cap "latch_one_1/c" "latch_one_1/out" 60.2664
cap "ras" "latch_one_1/c" 44.7083
cap "latch_one_0/c" "latch_one_0/GND!" 7.10543e-15
cap "2nor_0/Vdd!" "latch_one_1/a_12_n54#" 111.206
cap "2nor_0/Vdd!" "latch_one_0/in" 11.57
cap "2nor_0/Vdd!" "latch_one_1/in" 162.512
cap "latch_one_1/in" "latch_one_1/out" 10.908
cap "latch_one_0/a_n5_n54#" "latch_one_1/in" 36.385
cap "latch_one_0/a_n5_n54#" "latch_one_0/in" 38.4783
cap "2nor_0/Vdd!" "latch_one_1/out" 8.044
cap "2nor_0/Vdd!" "latch_one_0/a_12_n54#" 125.616
cap "2nor_0/Vdd!" "latch_one_0/a_n5_n54#" 57.312
cap "2nor_0/Vdd!" "ras" 11.569
subcap "wzCflag" -175.864
cap "reg_one_0/Vdd!" "2nor_0/a" 7.09
cap "2nor_0/a" "staticizer_one_0/a_77_n45#" 13.434
cap "latch_one_0/GND!" "reg_one_0/in" 25.326
cap "2nor_0/a" "2nor_0/GND!" 121.638
cap "reg_one_0/Vdd!" "reg_one_0/in" 249.376
cap "2nor_0/out" "staticizer_one_0/a_60_n45#" 31.644
cap "2nor_0/GND!" "reg_one_0/in" 148.04
cap "2nor_0/b" "latch_one_1/Vdd!" 53.893
cap "2nor_0/a" "2nor_0/out" 57.7175
cap "reg_one_0/Vdd!" "staticizer_one_0/a_77_n45#" 82.386
cap "latch_one_1/Vdd!" "2nor_0/Vdd!" -1.833
cap "2nor_0/b" "2nor_0/out" 8.124
cap "reg_one_0/Vdd!" "2nor_0/GND!" 68.714
cap "latch_one_1/Vdd!" "reg_one_0/in" 14.966
cap "staticizer_one_0/a_77_n45#" "2nor_0/GND!" 8.1
cap "2nor_0/out" "2nor_0/Vdd!" 2.612
cap "2nor_0/out" "staticizer_one_0/c" 5
cap "2nor_0/out" "reg_one_0/in" 60.6915
cap "staticizer_one_0/a_60_n45#" "reg_one_0/in" 76.9567
cap "latch_one_1/GND!" "reg_one_0/in" 69.33
cap "2nor_0/b" "latch_one_1/a_12_n54#" 15.3433
cap "reg_one_0/Vdd!" "reg_one_0/a_16_27#" -3.19744e-14
cap "2nor_0/a" "2nor_0/Vdd!" 80.4742
cap "reg_one_0/Vdd!" "2nor_0/out" 71.414
cap "2nor_0/a" "reg_one_0/in" 4.77
cap "staticizer_one_0/a_77_n45#" "2nor_0/out" 9.24
cap "2nor_0/b" "2nor_0/Vdd!" 157.164
cap "2nor_0/out" "2nor_0/GND!" 23.996
cap "2nor_0/b" "reg_one_0/in" 32.5884
cap "reg_one_0/Vdd!" "reg_one_0/a_4_n13#" 3.55271e-15
cap "staticizer_one_0/a_60_n45#" "2nor_0/GND!" 31.644
cap "reg_one_0/w_n11_n27#" "reg_one_0/w" 2.884
subcap "PCL_w_sel" -12.16
cap "inv2_6/GND!" "inv2_6/a_1_8#" 8.88178e-16
cap "inv2_6/Vdd!" "inv2_6/a_1_8#" -6.21725e-15
cap "inv2_6/Vdd!" "inv2_8/a_6_n1#" 2.84217e-14
subcap "PCH_w_sel" -12.16
cap "inv2_12/GND!" "inv2_12/a_1_8#" 8.88178e-16
cap "inv2_12/Vdd!" "inv2_10/a_1_8#" 2.84217e-14
cap "inv2_12/a_1_8#" "inv2_12/Vdd!" -6.21725e-15
subcap "ABH_w_sel" -7.846
cap "inv2_16/a_1_8#" "inv2_16/GND!" 8.88178e-16
cap "inv2_16/Vdd!" "inv2_14/a_6_n1#" 2.84217e-14
cap "inv2_16/a_1_8#" "inv2_16/Vdd!" -6.21725e-15
merge "inv2_14/Vdd!" "inv2_9/Vdd!" -1462.35 0 0 0 0 -236 -574 0 0 0 0 0 0 0 0 -630 -472 -70 -68 -50 -70 0 0 0 0 0 0
merge "inv2_9/Vdd!" "inv2_8/Vdd!"
merge "inv2_8/Vdd!" "reg_one_0/r1"
merge "reg_one_0/r1" "latch_one_1/Vdd!"
merge "latch_one_1/Vdd!" "2nor_0/Vdd!"
merge "2nor_0/Vdd!" "latch_one_0/Vdd!"
merge "latch_one_0/Vdd!" "staticizer_one_0/Vdd!"
merge "staticizer_one_0/Vdd!" "reg_one_0/Vdd!"
merge "reg_one_0/Vdd!" "inv2_2/Vdd!"
merge "inv2_2/Vdd!" "inv2_1/Vdd!"
merge "inv2_1/Vdd!" "inv2_5/Vdd!"
merge "inv2_5/Vdd!" "inv2_13/Vdd!"
merge "inv2_13/Vdd!" "inv2_15/Vdd!"
merge "inv2_15/Vdd!" "inv2_16/Vdd!"
merge "inv2_16/Vdd!" "m1_2180_1902#"
merge "m1_2180_1902#" "inv2_10/Vdd!"
merge "inv2_10/Vdd!" "inv2_11/Vdd!"
merge "inv2_11/Vdd!" "inv2_12/Vdd!"
merge "inv2_12/Vdd!" "m1_1880_1902#"
merge "m1_1880_1902#" "inv2_4/Vdd!"
merge "inv2_4/Vdd!" "addsub_1/cin"
merge "addsub_1/cin" "inv2_7/Vdd!"
merge "inv2_7/Vdd!" "inv2_3/Vdd!"
merge "inv2_3/Vdd!" "inv2_6/Vdd!"
merge "inv2_6/Vdd!" "m1_1380_1902#"
merge "m1_1380_1902#" "4nor2_0/Vdd!"
merge "4nor2_0/Vdd!" "staticizer_0/staticizer_one_0/Vdd!"
merge "staticizer_0/staticizer_one_0/Vdd!" "inv2_0/Vdd!"
merge "inv2_0/Vdd!" "latch_8/latch_one_0/Vdd!"
merge "latch_8/latch_one_0/Vdd!" "staticizer_5/Vdd!"
merge "staticizer_5/Vdd!" "m1_2828_1843#"
merge "m1_2828_1843#" "latch_8/Vdd!"
merge "latch_8/Vdd!" "staticizer_5/staticizer_one_0/Vdd!"
merge "staticizer_5/staticizer_one_0/Vdd!" "staticizer_4/Vdd!"
merge "staticizer_4/Vdd!" "latch_7/Vdd!"
merge "latch_7/Vdd!" "staticizer_3/Vdd!"
merge "staticizer_3/Vdd!" "addsub_2/addsub_one_0/Vdd!"
merge "addsub_2/addsub_one_0/Vdd!" "reg_7/reg_one_7/Vdd!"
merge "reg_7/reg_one_7/Vdd!" "mux_8bit_2/Vdd!"
merge "mux_8bit_2/Vdd!" "reg_6/reg_one_7/Vdd!"
merge "reg_6/reg_one_7/Vdd!" "reg_5/reg_one_7/Vdd!"
merge "reg_5/reg_one_7/Vdd!" "mux_8bit_1/Vdd!"
merge "mux_8bit_1/Vdd!" "staticizer_2/Vdd!"
merge "staticizer_2/Vdd!" "addsub_1/addsub_one_0/Vdd!"
merge "addsub_1/addsub_one_0/Vdd!" "reg_4/reg_one_7/Vdd!"
merge "reg_4/reg_one_7/Vdd!" "mux_8bit_0/Vdd!"
merge "mux_8bit_0/Vdd!" "reg_3/reg_one_7/Vdd!"
merge "reg_3/reg_one_7/Vdd!" "reg_2/reg_one_7/Vdd!"
merge "reg_2/reg_one_7/Vdd!" "reg_1/reg_one_7/Vdd!"
merge "reg_1/reg_one_7/Vdd!" "reg_0/reg_one_7/Vdd!"
merge "reg_0/reg_one_7/Vdd!" "latch_2/Vdd!"
merge "latch_2/Vdd!" "m1_865_1958#"
merge "m1_865_1958#" "addsub_0/addsub_one_0/Vdd!"
merge "addsub_0/addsub_one_0/Vdd!" "latch_1/Vdd!"
merge "latch_1/Vdd!" "fblock_0/fblock_one_1/inv_3/Vdd!"
merge "fblock_0/fblock_one_1/inv_3/Vdd!" "latch_3/Vdd!"
merge "latch_3/Vdd!" "shift_0/Vdd!"
merge "shift_0/Vdd!" "staticizer_0/Vdd!"
merge "staticizer_0/Vdd!" "latch_0/Vdd!"
merge "latch_0/Vdd!" "latch_4/Vdd!"
merge "latch_4/Vdd!" "latch_4/latch_one_0/Vdd!"
merge "latch_4/latch_one_0/Vdd!" "staticizer_1/Vdd!"
merge "staticizer_1/Vdd!" "m1_n30_1884#"
merge "m1_n30_1884#" "latch_8/latch_one_1/Vdd!"
merge "latch_8/latch_one_1/Vdd!" "staticizer_5/staticizer_one_1/Vdd!"
merge "staticizer_5/staticizer_one_1/Vdd!" "staticizer_4/staticizer_one_1/Vdd!"
merge "staticizer_4/staticizer_one_1/Vdd!" "latch_7/latch_one_1/Vdd!"
merge "latch_7/latch_one_1/Vdd!" "staticizer_3/staticizer_one_1/Vdd!"
merge "staticizer_3/staticizer_one_1/Vdd!" "latch_6/latch_one_1/Vdd!"
merge "latch_6/latch_one_1/Vdd!" "latch_6/Vdd!"
merge "latch_6/Vdd!" "addsub_2/Vdd!"
merge "addsub_2/Vdd!" "addsub_2/xor_1/Vdd!"
merge "addsub_2/xor_1/Vdd!" "reg_7/reg_one_6/Vdd!"
merge "reg_7/reg_one_6/Vdd!" "mux_8bit_2/mux_one_1/Vdd!"
merge "mux_8bit_2/mux_one_1/Vdd!" "reg_6/reg_one_6/Vdd!"
merge "reg_6/reg_one_6/Vdd!" "reg_5/reg_one_6/Vdd!"
merge "reg_5/reg_one_6/Vdd!" "mux_8bit_1/mux_one_1/Vdd!"
merge "mux_8bit_1/mux_one_1/Vdd!" "staticizer_2/staticizer_one_1/Vdd!"
merge "staticizer_2/staticizer_one_1/Vdd!" "latch_5/latch_one_1/Vdd!"
merge "latch_5/latch_one_1/Vdd!" "latch_5/Vdd!"
merge "latch_5/Vdd!" "addsub_1/Vdd!"
merge "addsub_1/Vdd!" "addsub_1/xor_1/Vdd!"
merge "addsub_1/xor_1/Vdd!" "reg_4/reg_one_6/Vdd!"
merge "reg_4/reg_one_6/Vdd!" "mux_8bit_0/mux_one_1/Vdd!"
merge "mux_8bit_0/mux_one_1/Vdd!" "reg_3/reg_one_6/Vdd!"
merge "reg_3/reg_one_6/Vdd!" "reg_2/reg_one_6/Vdd!"
merge "reg_2/reg_one_6/Vdd!" "reg_1/reg_one_6/Vdd!"
merge "reg_1/reg_one_6/Vdd!" "reg_0/reg_one_6/Vdd!"
merge "reg_0/reg_one_6/Vdd!" "latch_2/latch_one_1/Vdd!"
merge "latch_2/latch_one_1/Vdd!" "addsub_0/xor_1/Vdd!"
merge "addsub_0/xor_1/Vdd!" "latch_1/latch_one_1/Vdd!"
merge "latch_1/latch_one_1/Vdd!" "fblock_0/Vdd!"
merge "fblock_0/Vdd!" "latch_3/latch_one_1/Vdd!"
merge "latch_3/latch_one_1/Vdd!" "shift_0/shift_one_1/2mux_nr_1/Vdd!"
merge "shift_0/shift_one_1/2mux_nr_1/Vdd!" "staticizer_0/staticizer_one_1/Vdd!"
merge "staticizer_0/staticizer_one_1/Vdd!" "latch_0/latch_one_1/Vdd!"
merge "latch_0/latch_one_1/Vdd!" "latch_4/latch_one_1/Vdd!"
merge "latch_4/latch_one_1/Vdd!" "staticizer_1/staticizer_one_1/Vdd!"
merge "staticizer_1/staticizer_one_1/Vdd!" "Vdd!"
merge "Vdd!" "m1_150_1845#"
merge "m1_150_1845#" "latch_0/latch_one_0/Vdd!"
merge "latch_0/latch_one_0/Vdd!" "m1_1780_1843#"
merge "m1_1780_1843#" "m1_2580_1843#"
merge "m1_2580_1843#" "m1_2704_1843#"
merge "m1_2704_1843#" "staticizer_1/staticizer_one_0/Vdd!"
merge "staticizer_1/staticizer_one_0/Vdd!" "m1_1380_1876#"
merge "m1_1380_1876#" "a_1710_1893#"
merge "a_1710_1893#" "m1_1880_1876#"
merge "m1_1880_1876#" "m1_2180_1876#"
merge "reg_6/r1" "ABL_r1" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "latch_8/out0" "staticizer_5/in0" -147.242 0 0 0 0 0 0 0 0 0 0 25 -14 0 0 5 -16 0 0 0 0 0 0 0 0 0 0
merge "staticizer_5/in0" "addr_out8"
merge "staticizer_3/in6" "latch_6/out6" -179.922 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 9 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_6/out6" "a_2575_748#"
merge "staticizer_2/staticizer_one_3/out" "staticizer_2/in3" -738.27 0 0 0 0 0 0 0 0 0 0 -11 -16 0 0 -90 -54 0 0 0 0 -1500 -600 0 0 0 0
merge "staticizer_2/in3" "latch_5/out3"
merge "latch_5/out3" "a_1776_1276#"
merge "a_1776_1276#" "mux_8bit_0/in0_3"
merge "mux_8bit_0/in0_3" "wz_addrL3"
merge "reg_7/in0" "mux_8bit_2/out0" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_2/out0" "m1_2209_1774#"
merge "latch_7/in7" "reg_6/port71" -1961.17 0 0 0 0 0 0 0 0 0 0 -6 -14 0 0 -4 -14 0 -60 55 0 -5990 -2600 0 0 0 0
merge "reg_6/port71" "reg_4/port71"
merge "reg_4/port71" "reg_3/port71"
merge "reg_3/port71" "reg_2/port71"
merge "reg_2/port71" "reg_1/port71"
merge "reg_1/port71" "reg_0/port71"
merge "reg_0/port71" "addsub_0/b7"
merge "addsub_0/b7" "fblock_0/b7"
merge "fblock_0/b7" "ry7"
merge "addsub_0/a6" "latch_4/in6" -1177.34 0 0 0 0 0 0 0 0 0 0 -6 -16 0 0 87 -54 35 0 468 -51 -2520 -1071 0 0 0 0
merge "latch_4/in6" "reg_3/port60"
merge "reg_3/port60" "reg_2/port60"
merge "reg_2/port60" "reg_1/port60"
merge "reg_1/port60" "reg_0/port60"
merge "reg_0/port60" "fblock_0/a6"
merge "fblock_0/a6" "shift_0/a6"
merge "shift_0/a6" "rx6"
merge "mux_8bit_2/in1_2" "reg_6/in2" -2039.37 0 0 0 0 0 0 0 0 0 0 15 0 0 0 -135 -205 -50 -30 -25 -20 -5000 -2000 0 0 0 0
merge "reg_6/in2" "mux_8bit_1/in1_2"
merge "mux_8bit_1/in1_2" "mux_8bit_0/in1_2"
merge "mux_8bit_0/in1_2" "reg_3/in2"
merge "reg_3/in2" "reg_2/in2"
merge "reg_2/in2" "reg_1/in2"
merge "reg_1/in2" "reg_0/in2"
merge "reg_0/in2" "latch_2/out2"
merge "latch_2/out2" "latch_1/out2"
merge "latch_1/out2" "latch_3/out2"
merge "latch_3/out2" "staticizer_0/in2"
merge "staticizer_0/in2" "latch_0/out2"
merge "latch_0/out2" "a_109_1448#"
merge "a_109_1448#" "wz2"
merge "latch_7/in3" "reg_6/port31" -2103.91 0 0 0 0 0 0 0 0 0 0 -6 -14 0 0 -10 -14 0 -60 15 -7 -6570 -2671 0 0 0 0
merge "reg_6/port31" "reg_4/port31"
merge "reg_4/port31" "reg_3/port31"
merge "reg_3/port31" "reg_2/port31"
merge "reg_2/port31" "reg_1/port31"
merge "reg_1/port31" "reg_0/port31"
merge "reg_0/port31" "addsub_0/b3"
merge "addsub_0/b3" "fblock_0/b3"
merge "fblock_0/b3" "ry3"
merge "reg_4/reg_one_4/a_33_32#" "PCL3" -9.866 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -20 -18 0 0 0 0 0 0 0 0
merge "addsub_2/a2" "reg_7/port20" -394.642 0 0 0 0 0 0 0 0 0 0 -24 -10 0 0 24 -20 0 0 0 0 -400 -400 0 0 0 0
merge "reg_7/port20" "reg_5/port20"
merge "reg_5/port20" "rx_addrH2"
merge "latch_8/in3" "reg_7/port31" -662.772 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 0 0 -20 0 0 -2500 -1000 0 0 0 0
merge "reg_7/port31" "reg_5/port31"
merge "reg_5/port31" "ry_addrH3"
merge "addsub_2/a3" "reg_7/port30" -370.582 0 0 0 0 0 0 0 0 0 0 18 -10 0 0 60 -20 0 0 0 0 -1000 -400 0 0 0 0
merge "reg_7/port30" "reg_5/port30"
merge "reg_5/port30" "rx_addrH3"
merge "reg_6/port30" "m1_2132_1259#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "addsub_2/xor_4/GND!" "addsub_2/b4" -33.932 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "addsub_2/b4" "a_2351_1097#"
merge "latch_4/latch_one_6/GND!" "staticizer_1/staticizer_one_6/w_54_n57#" 0 0 0 0 0 0 0 0 0 0 -22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_8/latch_one_6/Vdd!" "staticizer_5/staticizer_one_6/Vdd!" 110.187 0 0 0 0 189 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_2/staticizer_one_5/w_54_n57#" "latch_5/latch_one_5/GND!" -9.45022e-13 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "reg_4/in0" "mux_8bit_0/out0" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_0/out0" "PCL_w_muxout0"
merge "reg_1/r0" "DB_r0" -6.105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "mux_8bit_2/in1_1" "reg_6/in1" -1827.29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -170 -205 -50 -30 -25 -20 -4000 -1600 0 0 0 0
merge "reg_6/in1" "mux_8bit_1/in1_1"
merge "mux_8bit_1/in1_1" "mux_8bit_0/in1_1"
merge "mux_8bit_0/in1_1" "reg_3/in1"
merge "reg_3/in1" "reg_2/in1"
merge "reg_2/in1" "reg_1/in1"
merge "reg_1/in1" "reg_0/in1"
merge "reg_0/in1" "staticizer_0/in1"
merge "staticizer_0/in1" "latch_0/out1"
merge "latch_0/out1" "a_109_1624#"
merge "a_109_1624#" "latch_2/out1"
merge "latch_2/out1" "latch_1/out1"
merge "latch_1/out1" "latch_3/out1"
merge "latch_3/out1" "wz1"
merge "staticizer_3/staticizer_one_4/Vdd!" "latch_6/latch_one_4/Vdd!" 1.13687e-12 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "addsub_2/xor_5/GND!" "addsub_2/m1_n4_99#" -33.932 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "addsub_2/m1_n4_99#" "addsub_2/b5"
merge "addsub_2/b5" "a_2351_921#"
merge "latch_4/latch_one_2/Vdd!" "staticizer_1/staticizer_one_2/Vdd!" -4.54747e-13 0 0 0 0 0 -48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "addsub_0/a2" "fblock_0/a2" -1187.34 0 0 0 0 0 0 0 0 0 0 8 -16 0 0 44 -54 0 0 433 -43 -2540 -1071 0 0 0 0
merge "fblock_0/a2" "latch_4/in2"
merge "latch_4/in2" "reg_3/port20"
merge "reg_3/port20" "reg_2/port20"
merge "reg_2/port20" "reg_1/port20"
merge "reg_1/port20" "reg_0/port20"
merge "reg_0/port20" "shift_0/a2"
merge "shift_0/a2" "rx2"
merge "mux_8bit_2/in1_3" "reg_6/in3" -1859.52 0 0 0 0 0 0 0 0 0 0 15 0 0 0 -60 -205 -50 -30 -25 -20 -2000 -2000 0 0 0 0
merge "reg_6/in3" "mux_8bit_1/in1_3"
merge "mux_8bit_1/in1_3" "mux_8bit_0/in1_3"
merge "mux_8bit_0/in1_3" "reg_3/in3"
merge "reg_3/in3" "reg_2/in3"
merge "reg_2/in3" "reg_1/in3"
merge "reg_1/in3" "reg_0/in3"
merge "reg_0/in3" "latch_2/out3"
merge "latch_2/out3" "latch_1/out3"
merge "latch_1/out3" "latch_3/out3"
merge "latch_3/out3" "staticizer_0/in3"
merge "staticizer_0/in3" "latch_0/out3"
merge "latch_0/out3" "a_109_1272#"
merge "a_109_1272#" "wz3"
merge "staticizer_0/staticizer_one_4/w_54_n57#" "latch_0/latch_one_4/GND!" -5.68434e-14 0 0 0 0 0 0 0 0 140 -40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "fblock_0/b0" "latch_7/in0" -2049.22 0 0 0 0 0 0 0 0 0 0 -6 -14 0 0 -10 -14 0 -60 -145 -63 -6815 -2736 0 0 0 0
merge "latch_7/in0" "reg_6/port01"
merge "reg_6/port01" "reg_4/port01"
merge "reg_4/port01" "reg_3/port01"
merge "reg_3/port01" "reg_2/port01"
merge "reg_2/port01" "reg_1/port01"
merge "reg_1/port01" "reg_0/port01"
merge "reg_0/port01" "addsub_0/b0"
merge "addsub_0/b0" "ry0"
merge "mux_8bit_2/in1_0" "reg_6/in0" -1887.05 0 0 0 0 0 0 0 0 0 0 15 0 0 0 -90 -205 27 -30 52 -20 -2928 -2000 0 0 0 0
merge "reg_6/in0" "mux_8bit_1/in1_0"
merge "mux_8bit_1/in1_0" "mux_8bit_0/in1_0"
merge "mux_8bit_0/in1_0" "reg_3/in0"
merge "reg_3/in0" "reg_2/in0"
merge "reg_2/in0" "reg_1/in0"
merge "reg_1/in0" "reg_0/in0"
merge "reg_0/in0" "staticizer_0/staticizer_one_0/out"
merge "staticizer_0/staticizer_one_0/out" "latch_2/out0"
merge "latch_2/out0" "latch_1/out0"
merge "latch_1/out0" "latch_3/out0"
merge "latch_3/out0" "staticizer_0/in0"
merge "staticizer_0/in0" "latch_0/out0"
merge "latch_0/out0" "a_109_1800#"
merge "a_109_1800#" "wz0"
merge "4nor2_0/c" "latch_3/c" -333.741 0 0 0 0 0 0 0 0 0 0 0 -4 0 0 0 0 0 0 40 -10 -1000 -400 0 0 0 0
merge "latch_3/c" "ros"
merge "latch_8/out1" "staticizer_5/in1" -188.602 0 0 0 0 0 0 0 0 0 0 8 -14 0 0 -9 -16 0 0 0 0 0 0 0 0 0 0
merge "staticizer_5/in1" "addr_out9"
merge "mux_8bit_2/in1_4" "mux_8bit_1/in1_4" -1978.78 0 0 0 0 0 0 0 0 0 0 15 0 0 0 -65 -205 5 -30 -10 -20 -4508 -2000 0 0 0 0
merge "mux_8bit_1/in1_4" "mux_8bit_0/in1_4"
merge "mux_8bit_0/in1_4" "staticizer_0/staticizer_one_4/out"
merge "staticizer_0/staticizer_one_4/out" "reg_6/in4"
merge "reg_6/in4" "reg_3/in4"
merge "reg_3/in4" "reg_2/in4"
merge "reg_2/in4" "reg_1/in4"
merge "reg_1/in4" "reg_0/in4"
merge "reg_0/in4" "latch_2/out4"
merge "latch_2/out4" "latch_1/out4"
merge "latch_1/out4" "latch_3/out4"
merge "latch_3/out4" "staticizer_0/in4"
merge "staticizer_0/in4" "latch_0/out4"
merge "latch_0/out4" "a_109_1096#"
merge "a_109_1096#" "wz4"
merge "reg_4/reg_one_2/a_33_32#" "PCL5" -9.866 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -20 -18 0 0 0 0 0 0 0 0
merge "staticizer_2/staticizer_one_4/out" "staticizer_2/in4" -734.711 0 0 0 0 0 0 0 0 0 0 -11 -16 0 0 -78 -54 -3 0 -11 0 -1500 -600 0 0 0 0
merge "staticizer_2/in4" "latch_5/out4"
merge "latch_5/out4" "a_1776_1100#"
merge "a_1776_1100#" "mux_8bit_0/in0_4"
merge "mux_8bit_0/in0_4" "wz_addrL4"
merge "reg_7/in1" "mux_8bit_2/out1" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_2/out1" "m1_2209_1598#"
merge "addsub_2/xor_6/GND!" "addsub_2/b6" -33.932 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "addsub_2/b6" "a_2351_745#"
merge "reg_4/r0" "PCL_r0" -7.118 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "staticizer_2/staticizer_one_4/w_54_n57#" "latch_5/latch_one_4/GND!" -1.27898e-12 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "fblock_0/b4" "latch_7/in4" -2059.46 0 0 0 0 0 0 0 0 0 0 -6 -14 0 0 -10 -14 0 -60 -125 -55 -6850 -2745 0 0 0 0
merge "latch_7/in4" "reg_6/port41"
merge "reg_6/port41" "reg_4/port41"
merge "reg_4/port41" "reg_3/port41"
merge "reg_3/port41" "reg_2/port41"
merge "reg_2/port41" "reg_1/port41"
merge "reg_1/port41" "reg_0/port41"
merge "reg_0/port41" "addsub_0/b4"
merge "addsub_0/b4" "ry4"
merge "reg_4/reg_one_3/a_33_32#" "PCL4" -5.802 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 -18 0 0 0 0 0 0 0 0
merge "latch_7/in6" "addsub_0/b6" -1850.13 0 0 0 0 0 0 0 0 0 0 -6 -14 0 0 -10 -14 0 -60 -75 -35 -5605 -2247 0 0 0 0
merge "addsub_0/b6" "fblock_0/b6"
merge "fblock_0/b6" "reg_6/port61"
merge "reg_6/port61" "reg_4/port61"
merge "reg_4/port61" "reg_3/port61"
merge "reg_3/port61" "reg_2/port61"
merge "reg_2/port61" "reg_1/port61"
merge "reg_1/port61" "reg_0/port61"
merge "reg_0/port61" "ry6"
merge "addsub_0/a5" "reg_3/port50" -1136.76 0 0 0 0 0 0 0 0 0 0 -11 -16 0 0 65 -54 70 0 518 -50 -1752 -1219 0 0 0 0
merge "reg_3/port50" "reg_2/port50"
merge "reg_2/port50" "reg_1/port50"
merge "reg_1/port50" "reg_0/port50"
merge "reg_0/port50" "fblock_0/a5"
merge "fblock_0/a5" "shift_0/a5"
merge "shift_0/a5" "latch_4/in5"
merge "latch_4/in5" "rx5"
merge "reg_6/w" "ABL_w" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "inv2_14/GND!" "inv2_9/GND!" -1028.84 0 0 0 0 0 0 0 0 92 -368 -6 -10 0 0 -271 -436 -25 -20 -25 -50 0 0 0 0 0 0
merge "inv2_9/GND!" "inv2_8/GND!"
merge "inv2_8/GND!" "2nor_0/GND!"
merge "2nor_0/GND!" "latch_one_1/GND!"
merge "latch_one_1/GND!" "latch_one_1/in"
merge "latch_one_1/in" "a_860_1991#"
merge "a_860_1991#" "inv2_2/GND!"
merge "inv2_2/GND!" "inv2_1/GND!"
merge "inv2_1/GND!" "inv2_5/GND!"
merge "inv2_5/GND!" "inv2_13/GND!"
merge "inv2_13/GND!" "inv2_15/GND!"
merge "inv2_15/GND!" "inv2_16/GND!"
merge "inv2_16/GND!" "m1_2222_1899#"
merge "m1_2222_1899#" "inv2_10/GND!"
merge "inv2_10/GND!" "inv2_11/GND!"
merge "inv2_11/GND!" "inv2_12/GND!"
merge "inv2_12/GND!" "m1_1922_1899#"
merge "m1_1922_1899#" "inv2_4/GND!"
merge "inv2_4/GND!" "inv2_7/GND!"
merge "inv2_7/GND!" "inv2_3/GND!"
merge "inv2_3/GND!" "inv2_6/GND!"
merge "inv2_6/GND!" "m1_1422_1899#"
merge "m1_1422_1899#" "latch_one_0/GND!"
merge "latch_one_0/GND!" "staticizer_one_0/w_54_n57#"
merge "staticizer_one_0/w_54_n57#" "4nor2_0/GND!"
merge "4nor2_0/GND!" "inv2_0/GND!"
merge "inv2_0/GND!" "latch_8/latch_one_0/GND!"
merge "latch_8/latch_one_0/GND!" "staticizer_5/GND!"
merge "staticizer_5/GND!" "m1_2841_1885#"
merge "m1_2841_1885#" "latch_8/GND!"
merge "latch_8/GND!" "staticizer_5/staticizer_one_0/w_54_n57#"
merge "staticizer_5/staticizer_one_0/w_54_n57#" "staticizer_4/GND!"
merge "staticizer_4/GND!" "latch_7/GND!"
merge "latch_7/GND!" "staticizer_3/GND!"
merge "staticizer_3/GND!" "latch_6/GND!"
merge "latch_6/GND!" "addsub_2/xor_0/GND!"
merge "addsub_2/xor_0/GND!" "addsub_2/sub"
merge "addsub_2/sub" "m1_2336_1834#"
merge "m1_2336_1834#" "addsub_2/b0"
merge "addsub_2/b0" "a_2351_1801#"
merge "a_2351_1801#" "reg_7/GND!"
merge "reg_7/GND!" "mux_8bit_2/GND!"
merge "mux_8bit_2/GND!" "reg_6/GND!"
merge "reg_6/GND!" "reg_5/GND!"
merge "reg_5/GND!" "mux_8bit_1/GND!"
merge "mux_8bit_1/GND!" "staticizer_2/GND!"
merge "staticizer_2/GND!" "latch_5/GND!"
merge "latch_5/GND!" "addsub_1/xor_0/GND!"
merge "addsub_1/xor_0/GND!" "addsub_1/sub"
merge "addsub_1/sub" "m1_1536_1834#"
merge "m1_1536_1834#" "addsub_1/b0"
merge "addsub_1/b0" "a_1545_1808#"
merge "a_1545_1808#" "reg_4/GND!"
merge "reg_4/GND!" "mux_8bit_0/GND!"
merge "mux_8bit_0/GND!" "reg_3/GND!"
merge "reg_3/GND!" "reg_2/GND!"
merge "reg_2/GND!" "reg_1/GND!"
merge "reg_1/GND!" "reg_0/GND!"
merge "reg_0/GND!" "latch_2/GND!"
merge "latch_2/GND!" "m1_877_1966#"
merge "m1_877_1966#" "addsub_0/addsub_one_1/GND!"
merge "addsub_0/addsub_one_1/GND!" "latch_1/GND!"
merge "latch_1/GND!" "fblock_0/GND!"
merge "fblock_0/GND!" "latch_3/GND!"
merge "latch_3/GND!" "shift_0/GND!"
merge "shift_0/GND!" "staticizer_0/GND!"
merge "staticizer_0/GND!" "latch_0/latch_one_0/GND!"
merge "latch_0/latch_one_0/GND!" "staticizer_0/staticizer_one_0/w_54_n57#"
merge "staticizer_0/staticizer_one_0/w_54_n57#" "latch_0/GND!"
merge "latch_0/GND!" "m1_65_1845#"
merge "m1_65_1845#" "latch_4/GND!"
merge "latch_4/GND!" "staticizer_1/GND!"
merge "staticizer_1/GND!" "m1_n42_1842#"
merge "m1_n42_1842#" "GND!"
merge "GND!" "m1_1793_1885#"
merge "m1_1793_1885#" "m1_2593_1885#"
merge "m1_2593_1885#" "m1_2717_1885#"
merge "m1_2717_1885#" "reg_one_0/w_n11_n27#"
merge "reg_one_0/w_n11_n27#" "m1_952_1914#"
merge "m1_952_1914#" "reg_one_0/r0"
merge "reg_one_0/r0" "m1_985_1902#"
merge "m1_985_1902#" "m2_980_1900#"
merge "m2_980_1900#" "m1_1422_1870#"
merge "m1_1422_1870#" "m1_1922_1870#"
merge "m1_1922_1870#" "m1_2222_1870#"
merge "addsub_2/a1" "reg_7/port10" -370.582 0 0 0 0 0 0 0 0 0 0 18 -10 0 0 60 -20 0 0 0 0 -1000 -400 0 0 0 0
merge "reg_7/port10" "reg_5/port10"
merge "reg_5/port10" "rx_addrH1"
merge "latch_8/in2" "reg_7/port21" -718.279 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 0 0 -20 -100 -45 -2725 -1095 0 0 0 0
merge "reg_7/port21" "reg_5/port21"
merge "reg_5/port21" "ry_addrH2"
merge "addsub_2/a4" "reg_7/port40" -370.582 0 0 0 0 0 0 0 0 0 0 18 -10 0 0 60 -20 0 0 0 0 -1000 -400 0 0 0 0
merge "reg_7/port40" "reg_5/port40"
merge "reg_5/port40" "rx_addrH4"
merge "addsub_0/a7" "reg_3/port70" -1155.82 0 0 0 0 0 0 0 0 0 0 -6 -16 0 0 65 -54 35 0 223 -133 -2945 -1220 0 0 0 0
merge "reg_3/port70" "reg_2/port70"
merge "reg_2/port70" "reg_1/port70"
merge "reg_1/port70" "reg_0/port70"
merge "reg_0/port70" "fblock_0/a7"
merge "fblock_0/a7" "shift_0/a7"
merge "shift_0/a7" "latch_4/in7"
merge "latch_4/in7" "rx7"
merge "reg_1/r1" "DB_r1" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "reg_4/in1" "mux_8bit_0/out1" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_0/out1" "PCL_w_muxout1"
merge "inv2_1/a_1_8#" "latch_7/c" -70.286 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -25 -20 0 0 25 -10 0 0 0 0 0 0
merge "latch_7/c" "rd_addrL"
merge "addsub_2/xor_3/GND!" "addsub_2/b3" -33.932 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "addsub_2/b3" "a_2351_1273#"
merge "addsub_0/a3" "reg_3/port30" -1184.34 0 0 0 0 0 0 0 0 0 0 -6 -16 0 0 65 -54 35 0 243 -125 -2945 -1220 0 0 0 0
merge "reg_3/port30" "reg_2/port30"
merge "reg_2/port30" "reg_1/port30"
merge "reg_1/port30" "reg_0/port30"
merge "reg_0/port30" "fblock_0/a3"
merge "fblock_0/a3" "shift_0/a3"
merge "shift_0/a3" "latch_4/in3"
merge "latch_4/in3" "rx3"
merge "staticizer_3/staticizer_one_2/w_54_n57#" "latch_6/latch_one_2/GND!" -1.98952e-13 0 0 0 0 0 0 0 0 -413 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/xor_3/GND!" "addsub_1/b3" -115.486 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -20 -20 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/b3" "a_1545_1280#"
merge "latch_8/out2" "staticizer_5/in2" -147.242 0 0 0 0 0 0 0 0 0 0 25 -14 0 0 5 -16 0 0 0 0 0 0 0 0 0 0
merge "staticizer_5/in2" "addr_out10"
merge "staticizer_3/staticizer_one_6/Vdd!" "latch_6/latch_one_6/Vdd!" -4.54747e-13 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "reg_7/in2" "mux_8bit_2/out2" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_2/out2" "m1_2209_1422#"
merge "staticizer_2/staticizer_one_5/out" "staticizer_2/in5" -681.649 0 0 0 0 0 0 0 0 0 0 -91 0 0 0 -80 -40 0 0 -84 -47 -2025 -817 0 0 0 0
merge "staticizer_2/in5" "latch_5/out5"
merge "latch_5/out5" "a_1776_924#"
merge "a_1776_924#" "mux_8bit_0/in0_5"
merge "mux_8bit_0/in0_5" "wz_addrL5"
merge "reg_4/r1" "PCL_r1" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "inv2_0/a_6_n1#" "staticizer_1/c" -52.526 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -45 -28 0 0 5 -10 0 0 0 0 0 0
merge "staticizer_1/c" "m1_n56_1860#"
merge "addsub_0/a4" "reg_3/port40" -1183.34 0 0 0 0 0 0 0 0 0 0 -6 -16 0 0 65 -54 35 0 363 -77 -2945 -1220 0 0 0 0
merge "reg_3/port40" "reg_2/port40"
merge "reg_2/port40" "reg_1/port40"
merge "reg_1/port40" "reg_0/port40"
merge "reg_0/port40" "fblock_0/a4"
merge "fblock_0/a4" "shift_0/a4"
merge "shift_0/a4" "latch_4/in4"
merge "latch_4/in4" "rx4"
merge "latch_3/in7" "shift_0/o7" -62.527 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "shift_0/o7" "a_373_564#"
merge "fblock_0/b5" "latch_7/in5" -2017.22 0 0 0 0 0 0 0 0 0 0 -2 -14 0 0 -10 -14 0 -60 0 0 -6500 -2600 0 0 0 0
merge "latch_7/in5" "reg_6/port51"
merge "reg_6/port51" "reg_4/port51"
merge "reg_4/port51" "reg_3/port51"
merge "reg_3/port51" "reg_2/port51"
merge "reg_2/port51" "reg_1/port51"
merge "reg_1/port51" "reg_0/port51"
merge "reg_0/port51" "addsub_0/b5"
merge "addsub_0/b5" "ry5"
merge "inv2_9/a_6_n1#" "inv2_10/a_1_8#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "addsub_2/a0" "reg_7/port00" -370.582 0 0 0 0 0 0 0 0 0 0 18 -10 0 0 60 -20 0 0 0 0 -1000 -400 0 0 0 0
merge "reg_7/port00" "reg_5/port00"
merge "reg_5/port00" "rx_addrH0"
merge "latch_8/in1" "reg_7/port11" -645.744 0 0 0 0 0 0 0 0 0 0 12 -10 0 0 0 0 0 -20 0 0 -2500 -1000 0 0 0 0
merge "reg_7/port11" "reg_5/port11"
merge "reg_5/port11" "ry_addrH1"
merge "addsub_2/a5" "reg_7/port50" -370.582 0 0 0 0 0 0 0 0 0 0 18 -10 0 0 60 -20 0 0 0 0 -1000 -400 0 0 0 0
merge "reg_7/port50" "reg_5/port50"
merge "reg_5/port50" "rx_addrH5"
merge "staticizer_3/staticizer_one_4/w_54_n57#" "latch_6/latch_one_4/GND!" -1.27898e-12 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/xor_5/GND!" "addsub_1/b5" -161.86 0 0 0 0 0 0 0 0 0 0 -20 -14 0 0 -40 -20 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/b5" "a_1545_928#"
merge "addsub_2/xor_1/GND!" "addsub_2/m1_n4_803#" -33.932 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "addsub_2/m1_n4_803#" "addsub_2/b1"
merge "addsub_2/b1" "a_2351_1625#"
merge "reg_4/in2" "mux_8bit_0/out2" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_0/out2" "PCL_w_muxout2"
merge "inv2_2/a_1_8#" "latch_8/c" -97.666 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -50 -25 0 0 25 -10 0 0 0 0 0 0
merge "latch_8/c" "rd_addrH"
merge "latch_0/in0" "data_in0" -13.896 0 0 0 0 0 0 0 0 0 0 0 -6 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_4/staticizer_one_4/Vdd!" "latch_7/latch_one_4/Vdd!" -6.82121e-13 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_2/in1_5" "reg_6/in5" -1843.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -219 -205 -50 -30 -25 -20 -4000 -1600 0 0 0 0
merge "reg_6/in5" "mux_8bit_1/in1_5"
merge "mux_8bit_1/in1_5" "mux_8bit_0/in1_5"
merge "mux_8bit_0/in1_5" "reg_3/in5"
merge "reg_3/in5" "reg_2/in5"
merge "reg_2/in5" "reg_1/in5"
merge "reg_1/in5" "reg_0/in5"
merge "reg_0/in5" "staticizer_0/staticizer_one_5/out"
merge "staticizer_0/staticizer_one_5/out" "staticizer_0/in5"
merge "staticizer_0/in5" "latch_0/out5"
merge "latch_0/out5" "a_109_920#"
merge "a_109_920#" "latch_2/out5"
merge "latch_2/out5" "latch_1/out5"
merge "latch_1/out5" "latch_3/out5"
merge "latch_3/out5" "wz5"
merge "addsub_1/xor_1/GND!" "addsub_1/b1" -134.226 0 0 0 0 0 0 0 0 0 0 -20 -16 0 0 -20 -24 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/b1" "a_1545_1632#"
merge "reg_7/r0" "ABH_r0" -7.118 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "latch_8/out3" "staticizer_5/in3" -147.242 0 0 0 0 0 0 0 0 0 0 25 -14 0 0 5 -16 0 0 0 0 0 0 0 0 0 0
merge "staticizer_5/in3" "addr_out11"
merge "latch_one_1/out" "staticizer_one_0/in" -514.822 0 0 0 0 0 0 0 0 0 0 -58 -62 0 0 -45 -51 0 0 0 0 0 0 0 0 0 0
merge "staticizer_one_0/in" "latch_one_0/out"
merge "latch_one_0/out" "staticizer_one_0/out"
merge "staticizer_one_0/out" "wzCflag"
merge "wzCflag" "reg_one_0/in"
merge "reg_one_0/in" "m1_979_1961#"
merge "reg_7/in3" "mux_8bit_2/out3" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_2/out3" "m1_2209_1246#"
merge "staticizer_2/staticizer_one_6/out" "staticizer_2/in6" -668.206 0 0 0 0 0 0 0 0 0 0 -11 -16 0 0 -75 -54 0 0 44 0 -285 -600 0 0 0 0
merge "staticizer_2/in6" "latch_5/out6"
merge "latch_5/out6" "a_1776_748#"
merge "a_1776_748#" "mux_8bit_0/in0_6"
merge "mux_8bit_0/in0_6" "wz_addrL6"
merge "latch_3/in5" "shift_0/o5" -62.527 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "shift_0/o5" "a_373_916#"
merge "inv2_5/a_6_n1#" "staticizer_3/c" -14.384 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 -4 -10 0 0 0 0 0 0
merge "staticizer_3/c" "m1_2596_1867#"
merge "latch_5/in0" "addsub_1/s0" -62.943 0 0 0 0 0 0 0 0 0 0 -10 -13 0 0 0 0 -20 -28 0 0 0 0 0 0 0 0
merge "addsub_1/s0" "a_1716_1801#"
merge "a_1716_1801#" "PCLplus1_0"
merge "reg_4/reg_one_1/a_33_32#" "PCL6" -9.866 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -20 -18 0 0 0 0 0 0 0 0
merge "latch_8/in0" "reg_7/port01" -662.772 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 0 0 -20 0 0 -2500 -1000 0 0 0 0
merge "reg_7/port01" "reg_5/port01"
merge "reg_5/port01" "ry_addrH0"
merge "staticizer_3/staticizer_one_7/Vdd!" "latch_6/latch_one_7/Vdd!" 1.02318e-12 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "4nor2_0/out" "staticizer_0/c" -55.344 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -25 -20 0 0 5 -10 0 0 0 0 0 0
merge "staticizer_0/c" "m1_136_1836#"
merge "latch_8/latch_one_2/Vdd!" "staticizer_5/staticizer_one_2/Vdd!" 110.187 0 0 0 0 189 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_one_0/in" "addsub_0/cout" -1090.56 0 0 0 0 0 0 0 0 0 0 0 -4 0 0 -15 -20 0 0 -4121 -2628 0 0 0 0 0 0
merge "addsub_0/cout" "as_cout"
merge "staticizer_0/w_90_n1211#" "staticizer_0/staticizer_one_7/w_54_n57#" -1.20792e-13 0 0 0 0 0 0 0 0 140 -40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_0/staticizer_one_7/w_54_n57#" "latch_0/latch_one_7/GND!"
merge "addsub_2/xor_7/GND!" "addsub_2/b7" -61.042 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -12 0 0 0 0 0 0 0 0 0 0
merge "addsub_2/b7" "a_2351_569#"
merge "addsub_2/a6" "reg_7/port60" -432.685 0 0 0 0 0 0 0 0 0 0 18 -10 0 0 60 -20 0 0 0 0 -1000 -400 0 0 0 0
merge "reg_7/port60" "reg_5/port60"
merge "reg_5/port60" "rx_addrH6"
merge "latch_4/latch_one_5/Vdd!" "staticizer_1/staticizer_one_5/Vdd!" 2.27374e-13 0 0 0 0 0 -48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "reg_4/in3" "mux_8bit_0/out3" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_0/out3" "PCL_w_muxout3"
merge "addsub_0/cin" "as_cin" -9.264 0 0 0 0 0 0 0 0 0 0 0 -4 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_2/staticizer_one_0/out" "staticizer_2/in0" -735.585 0 0 0 0 0 0 0 0 0 0 -11 -16 0 0 -83 -54 1 0 -3 0 -1500 -600 0 0 0 0
merge "staticizer_2/in0" "latch_5/out0"
merge "latch_5/out0" "a_1776_1804#"
merge "a_1776_1804#" "mux_8bit_0/in0_0"
merge "mux_8bit_0/in0_0" "wz_addrL0"
merge "latch_0/in1" "data_in1" -14.842 0 0 0 0 0 0 0 0 0 0 -1 -6 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_2/in1_6" "reg_6/in6" -2094.08 0 0 0 0 0 0 0 0 0 0 15 0 0 0 -81 -205 -50 -30 -25 -20 -5000 -2200 0 0 0 0
merge "reg_6/in6" "mux_8bit_1/in1_6"
merge "mux_8bit_1/in1_6" "mux_8bit_0/in1_6"
merge "mux_8bit_0/in1_6" "reg_3/in6"
merge "reg_3/in6" "reg_2/in6"
merge "reg_2/in6" "reg_1/in6"
merge "reg_1/in6" "reg_0/in6"
merge "reg_0/in6" "staticizer_0/in6"
merge "staticizer_0/in6" "latch_0/out6"
merge "latch_0/out6" "a_109_744#"
merge "a_109_744#" "latch_2/out6"
merge "latch_2/out6" "latch_1/out6"
merge "latch_1/out6" "latch_3/out6"
merge "latch_3/out6" "wz6"
merge "staticizer_1/staticizer_one_5/out" "latch_4/out5" -61.888 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4 -20 0 0 0 0 0 0 0 0 0 0
merge "latch_4/out5" "staticizer_1/in5"
merge "staticizer_1/in5" "a_n24_920#"
merge "a_n24_920#" "data_out5"
merge "reg_7/r1" "ABH_r1" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "reg_5/in3" "mux_8bit_1/out3" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_1/out3" "m1_1909_1246#"
merge "addsub_1/xor_7/GND!" "addsub_1/b7" -115.486 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/b7" "a_1545_576#"
merge "staticizer_2/w_90_n1211#" "latch_5/latch_one_7/GND!" -1.13687e-12 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_8/out4" "staticizer_5/in4" -147.242 0 0 0 0 0 0 0 0 0 0 25 -14 0 0 5 -16 0 0 0 0 0 0 0 0 0 0
merge "staticizer_5/in4" "addr_out12"
merge "staticizer_2/staticizer_one_7/out" "staticizer_2/in7" -738.12 0 0 0 0 0 0 0 0 0 0 -11 -16 0 0 -90 -54 0 0 0 0 -1500 -600 0 0 0 0
merge "staticizer_2/in7" "latch_5/out7"
merge "latch_5/out7" "a_1776_572#"
merge "a_1776_572#" "mux_8bit_0/in0_7"
merge "mux_8bit_0/in0_7" "wz_addrL7"
merge "latch_6/in7" "addsub_2/s7" -45.555 0 0 0 0 0 0 0 0 0 0 -10 -13 0 0 0 0 40 -10 0 0 0 0 0 0 0 0
merge "addsub_2/s7" "a_2516_569#"
merge "inv2_1/a_6_n1#" "staticizer_4/c" -11.33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 -10 0 0 10 -10 0 0 0 0 0 0
merge "staticizer_4/c" "m1_2720_1867#"
merge "staticizer_1/staticizer_one_0/out" "latch_4/out0" -193.078 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -30 -36 0 0 0 0 0 0 0 0 0 0
merge "latch_4/out0" "staticizer_1/in0"
merge "staticizer_1/in0" "a_n24_1800#"
merge "a_n24_1800#" "data_out0"
merge "reg_7/in4" "mux_8bit_2/out4" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_2/out4" "m1_2209_1070#"
merge "inv2_7/a_1_8#" "inv2_8/a_6_n1#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "inv2_15/a_1_8#" "inv2_16/a_6_n1#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "2nor_0/b" "latch_one_1/c" -777.911 0 0 0 0 0 0 0 0 0 0 0 -8 0 0 0 0 0 0 40 -20 -2000 -805 0 0 0 0
merge "latch_one_1/c" "4nor2_0/b"
merge "4nor2_0/b" "latch_1/c"
merge "latch_1/c" "rfb"
merge "latch_3/in0" "shift_0/o0" -62.527 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "shift_0/o0" "a_373_1796#"
merge "latch_5/in1" "addsub_1/s1" -35.439 0 0 0 0 0 0 0 0 0 0 18 -13 0 0 0 0 -12 -28 0 0 0 0 0 0 0 0
merge "addsub_1/s1" "a_1716_1625#"
merge "a_1716_1625#" "PCLplus1_1"
merge "reg_4/reg_one_0/a_33_32#" "PCL7" -9.866 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -20 -18 0 0 0 0 0 0 0 0
merge "staticizer_0/staticizer_one_2/w_54_n57#" "latch_0/latch_one_2/GND!" 1.42109e-13 0 0 0 0 0 0 0 0 -273 -40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_4/staticizer_one_3/w_54_n57#" "latch_7/latch_one_3/GND!" 1.476 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "addsub_2/a7" "reg_7/port70" -356.092 0 0 0 0 0 0 0 0 0 0 18 -10 0 0 60 -20 0 0 0 0 -1000 -400 0 0 0 0
merge "reg_7/port70" "reg_5/port70"
merge "reg_5/port70" "rx_addrH7"
merge "2nor_0/out" "staticizer_one_0/c" -173.633 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -75 -50 -25 -20 -155 -67 0 0 0 0 0 0
merge "staticizer_one_0/c" "m1_940_1901#"
merge "reg_4/w" "PCL_w" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "staticizer_2/staticizer_one_1/out" "staticizer_2/in1" -691.659 0 0 0 0 0 0 0 0 0 0 -49 -4 0 0 -101 -40 0 0 -68 -39 -2025 -817 0 0 0 0
merge "staticizer_2/in1" "latch_5/out1"
merge "latch_5/out1" "a_1776_1628#"
merge "a_1776_1628#" "mux_8bit_0/in0_1"
merge "mux_8bit_0/in0_1" "wz_addrL1"
merge "reg_4/in4" "mux_8bit_0/out4" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_0/out4" "PCL_w_muxout4"
merge "staticizer_3/staticizer_one_5/w_54_n57#" "latch_6/latch_one_5/GND!" -9.45022e-13 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_0/in2" "data_in2" -13.896 0 0 0 0 0 0 0 0 0 0 0 -6 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_2/in1_7" "reg_6/in7" -2024.19 0 0 0 0 0 0 0 0 0 0 15 0 0 0 -135 -205 -50 -30 -25 -20 -5000 -2000 0 0 0 0
merge "reg_6/in7" "mux_8bit_1/in1_7"
merge "mux_8bit_1/in1_7" "mux_8bit_0/in1_7"
merge "mux_8bit_0/in1_7" "reg_3/in7"
merge "reg_3/in7" "reg_2/in7"
merge "reg_2/in7" "reg_1/in7"
merge "reg_1/in7" "reg_0/in7"
merge "reg_0/in7" "latch_2/out7"
merge "latch_2/out7" "latch_1/out7"
merge "latch_1/out7" "latch_3/out7"
merge "latch_3/out7" "staticizer_0/in7"
merge "staticizer_0/in7" "latch_0/out7"
merge "latch_0/out7" "a_109_568#"
merge "a_109_568#" "wz7"
merge "reg_6/port00" "m1_2132_1787#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "reg_4/reg_one_5/a_33_32#" "PCL2" -9.866 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -20 -18 0 0 0 0 0 0 0 0
merge "staticizer_4/staticizer_one_3/Vdd!" "latch_7/latch_one_3/Vdd!" -2.27374e-13 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_8/out5" "staticizer_5/in5" -164.27 0 0 0 0 0 0 0 0 0 0 7 -14 0 0 5 -16 0 0 0 0 0 0 0 0 0 0
merge "staticizer_5/in5" "addr_out13"
merge "inv2_15/a_6_n1#" "mux_8bit_2/sel" -47.791 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -30 -22 0 0 0 0 0 0 0 0 0 0
merge "reg_7/in5" "mux_8bit_2/out5" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_2/out5" "m1_2209_894#"
merge "inv2_2/a_6_n1#" "staticizer_5/c" -13.32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 10 -10 0 0 0 0 0 0
merge "staticizer_5/c" "m1_2844_1867#"
merge "addsub_0/a1" "reg_3/port10" -1220.83 0 0 0 0 0 0 0 0 0 0 -7 -16 0 0 81 -54 35 0 527 -50 -1545 -1206 0 0 0 0
merge "reg_3/port10" "reg_2/port10"
merge "reg_2/port10" "reg_1/port10"
merge "reg_1/port10" "reg_0/port10"
merge "reg_0/port10" "fblock_0/a1"
merge "fblock_0/a1" "shift_0/a1"
merge "shift_0/a1" "latch_4/in1"
merge "latch_4/in1" "rx1"
merge "latch_3/in1" "shift_0/o1" -34.147 0 0 0 0 0 0 0 0 0 0 24 -10 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "shift_0/o1" "a_373_1620#"
merge "latch_7/in2" "addsub_0/b2" -1488.24 0 0 0 0 0 0 0 0 0 0 -6 -14 0 0 -10 -14 0 -60 -55 -27 1595 -2247 0 0 0 0
merge "addsub_0/b2" "fblock_0/b2"
merge "fblock_0/b2" "reg_6/port21"
merge "reg_6/port21" "reg_4/port21"
merge "reg_4/port21" "reg_3/port21"
merge "reg_3/port21" "reg_2/port21"
merge "reg_2/port21" "reg_1/port21"
merge "reg_1/port21" "reg_0/port21"
merge "reg_0/port21" "ry2"
merge "staticizer_3/staticizer_one_2/out" "mux_8bit_2/in0_2" -842.312 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 -60 70 0 35 0 -2965 -1200 0 0 0 0
merge "mux_8bit_2/in0_2" "mux_8bit_1/in0_2"
merge "mux_8bit_1/in0_2" "wz_addrH2"
merge "latch_5/in2" "addsub_1/s2" -62.943 0 0 0 0 0 0 0 0 0 0 -10 -13 0 0 0 0 -20 -28 0 0 0 0 0 0 0 0
merge "addsub_1/s2" "a_1716_1449#"
merge "a_1716_1449#" "PCLplus1_2"
merge "staticizer_0/staticizer_one_6/w_54_n57#" "latch_0/latch_one_6/GND!" -7.10543e-15 0 0 0 0 0 0 0 0 77 -40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_4/staticizer_one_7/Vdd!" "latch_7/latch_one_7/Vdd!" -7.95808e-13 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_4/staticizer_one_7/w_54_n57#" "latch_7/latch_one_7/GND!" 1.476 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_2/staticizer_one_2/out" "staticizer_2/in2" -580.462 0 0 0 0 0 0 0 0 0 0 -11 -16 0 0 -55 -54 0 0 28 0 1335 -600 0 0 0 0
merge "staticizer_2/in2" "latch_5/out2"
merge "latch_5/out2" "a_1776_1452#"
merge "a_1776_1452#" "mux_8bit_0/in0_2"
merge "mux_8bit_0/in0_2" "wz_addrL2"
merge "reg_4/in5" "mux_8bit_0/out5" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_0/out5" "PCL_w_muxout5"
merge "latch_0/in3" "data_in3" -13.896 0 0 0 0 0 0 0 0 0 0 0 -6 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "inv2_11/a_6_n1#" "mux_8bit_1/sel" -47.791 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -30 -22 0 0 0 0 0 0 0 0 0 0
merge "staticizer_5/in6" "latch_8/out6" -150.426 0 0 0 0 0 0 0 0 0 0 25 -14 0 0 -3 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_8/out6" "addr_out14"
merge "latch_8/latch_one_1/GND!" "staticizer_5/staticizer_one_1/w_54_n57#" 1.95399e-14 0 0 0 0 0 0 0 0 154 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_8/latch_one_5/Vdd!" "staticizer_5/staticizer_one_5/Vdd!" 65.296 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "reg_7/in6" "mux_8bit_2/out6" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_2/out6" "m1_2209_718#"
merge "addsub_0/a0" "reg_3/port00" -1181.43 0 0 0 0 0 0 0 0 0 0 -6 -16 0 0 65 -54 35 0 383 -69 -2945 -1220 0 0 0 0
merge "reg_3/port00" "reg_2/port00"
merge "reg_2/port00" "reg_1/port00"
merge "reg_1/port00" "reg_0/port00"
merge "reg_0/port00" "fblock_0/a0"
merge "fblock_0/a0" "shift_0/a0"
merge "shift_0/a0" "latch_4/in0"
merge "latch_4/in0" "rx0"
merge "fblock_0/b1" "latch_7/in1" -2007.76 0 0 0 0 0 0 0 0 0 0 8 -14 0 0 -10 -14 0 -60 0 0 -6500 -2600 0 0 0 0
merge "latch_7/in1" "reg_6/port11"
merge "reg_6/port11" "reg_4/port11"
merge "reg_4/port11" "reg_3/port11"
merge "reg_3/port11" "reg_2/port11"
merge "reg_2/port11" "reg_1/port11"
merge "reg_1/port11" "reg_0/port11"
merge "reg_0/port11" "addsub_0/b1"
merge "addsub_0/b1" "ry1"
merge "latch_3/in2" "shift_0/o2" -62.527 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "shift_0/o2" "a_373_1444#"
merge "latch_4/latch_one_1/GND!" "staticizer_1/staticizer_one_1/w_54_n57#" -7.10543e-14 0 0 0 0 0 0 0 0 0 -40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_5/in3" "addsub_1/s3" -62.943 0 0 0 0 0 0 0 0 0 0 -10 -13 0 0 0 0 -20 -28 0 0 0 0 0 0 0 0
merge "addsub_1/s3" "a_1716_1273#"
merge "a_1716_1273#" "PCLplus1_3"
merge "latch_4/latch_one_3/Vdd!" "staticizer_1/staticizer_one_3/Vdd!" -9.09495e-13 0 0 0 0 0 -48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_8/latch_one_2/GND!" "staticizer_5/staticizer_one_2/w_54_n57#" -7.10543e-14 0 0 0 0 0 0 0 0 -259 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "reg_4/in6" "mux_8bit_0/out6" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_0/out6" "PCL_w_muxout6"
merge "latch_0/in4" "data_in4" -13.896 0 0 0 0 0 0 0 0 0 0 0 -6 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "addsub_2/xor_2/GND!" "addsub_2/b2" -33.932 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "addsub_2/b2" "a_2351_1449#"
merge "latch_8/out7" "staticizer_5/in7" -147.242 0 0 0 0 0 0 0 0 0 0 25 -14 0 0 5 -16 0 0 0 0 0 0 0 0 0 0
merge "staticizer_5/in7" "addr_out15"
merge "addsub_1/xor_2/GND!" "addsub_1/b2" -115.486 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -20 -20 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/b2" "a_1545_1456#"
merge "reg_7/in7" "mux_8bit_2/out7" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_2/out7" "m1_2209_542#"
merge "latch_3/in3" "shift_0/o3" -62.527 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "shift_0/o3" "a_373_1268#"
merge "latch_5/in4" "addsub_1/s4" -62.943 0 0 0 0 0 0 0 0 0 0 -10 -13 0 0 0 0 -20 -28 0 0 0 0 0 0 0 0
merge "addsub_1/s4" "a_1716_1097#"
merge "a_1716_1097#" "PCLplus1_4"
merge "latch_4/latch_one_5/GND!" "staticizer_1/staticizer_one_5/w_54_n57#" -6.39488e-14 0 0 0 0 0 0 0 0 0 -40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_8/latch_one_6/GND!" "staticizer_5/staticizer_one_6/w_54_n57#" -1.42109e-14 0 0 0 0 0 0 0 0 154 -22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_4/staticizer_one_6/Vdd!" "latch_7/latch_one_6/Vdd!" -9.09495e-13 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_2/staticizer_one_4/Vdd!" "latch_5/latch_one_4/Vdd!" -0.246 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "reg_4/in7" "mux_8bit_0/out7" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_0/out7" "PCL_w_muxout7"
merge "staticizer_0/staticizer_one_2/Vdd!" "latch_0/latch_one_2/Vdd!" 99.174 0 0 0 0 168 -48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_4/out3" "staticizer_1/in3" -197.058 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -40 -36 0 0 0 0 0 0 0 0 0 0
merge "staticizer_1/in3" "a_n24_1272#"
merge "a_n24_1272#" "data_out3"
merge "latch_0/in5" "data_in5" -18.626 0 0 0 0 0 0 0 0 0 0 -5 -6 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "reg_2/w" "X_w" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "reg_5/in7" "mux_8bit_1/out7" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_1/out7" "m1_1909_542#"
merge "staticizer_3/w_90_n1211#" "latch_6/latch_one_7/GND!" -1.13687e-12 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_4/staticizer_one_6/w_54_n57#" "latch_7/latch_one_6/GND!" -1.42109e-14 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_4/out6" "staticizer_1/in6" -197.058 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -40 -36 0 0 0 0 0 0 0 0 0 0
merge "staticizer_1/in6" "a_n24_744#"
merge "a_n24_744#" "data_out6"
merge "staticizer_3/staticizer_one_5/out" "mux_8bit_2/in0_5" -657.622 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -82 -60 28 0 35 0 1727 -1200 0 0 0 0
merge "mux_8bit_2/in0_5" "mux_8bit_1/in0_5"
merge "mux_8bit_1/in0_5" "wz_addrH5"
merge "reg_5/in0" "mux_8bit_1/out0" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_1/out0" "m1_1909_1774#"
merge "latch_3/in4" "shift_0/o4" -62.527 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "shift_0/o4" "a_373_1092#"
merge "latch_5/in5" "addsub_1/s5" -44.759 0 0 0 0 0 0 0 0 0 0 6 -13 0 0 0 0 4 -28 0 0 0 0 0 0 0 0
merge "addsub_1/s5" "a_1716_921#"
merge "a_1716_921#" "PCLplus1_5"
merge "reg_3/w" "Y_w" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "latch_6/in0" "addsub_2/s0" -53.077 0 0 0 0 0 0 0 0 0 0 -10 -13 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_2/s0" "a_2516_1801#"
merge "latch_4/out1" "staticizer_1/in1" -64.576 0 0 0 0 0 0 0 0 0 0 12 0 0 0 -16 -20 0 0 0 0 0 0 0 0 0 0
merge "staticizer_1/in1" "a_n24_1624#"
merge "a_n24_1624#" "data_out1"
merge "latch_0/in6" "data_in6" -13.896 0 0 0 0 0 0 0 0 0 0 0 -6 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_8/latch_one_4/GND!" "staticizer_5/staticizer_one_4/w_54_n57#" -3.73035e-14 0 0 0 0 0 0 0 0 154 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_4/latch_one_2/GND!" "staticizer_1/staticizer_one_2/w_54_n57#" 0 0 0 0 0 0 0 0 0 -413 -40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_4/latch_one_6/Vdd!" "staticizer_1/staticizer_one_6/Vdd!" -4.54747e-13 0 0 0 0 0 -48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "inv2_4/a_6_n1#" "staticizer_2/c" -14.384 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 -4 -10 0 0 0 0 0 0
merge "staticizer_2/c" "m1_1796_1867#"
merge "staticizer_0/staticizer_one_4/Vdd!" "latch_0/latch_one_4/Vdd!" 100.404 0 0 0 0 168 -48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_5/in6" "addsub_1/s6" -62.943 0 0 0 0 0 0 0 0 0 0 -10 -13 0 0 0 0 -20 -28 0 0 0 0 0 0 0 0
merge "addsub_1/s6" "a_1716_745#"
merge "a_1716_745#" "PCLplus1_6"
merge "latch_6/in1" "addsub_2/s1" -26.589 0 0 0 0 0 0 0 0 0 0 18 -13 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_2/s1" "a_2516_1625#"
merge "latch_4/latch_one_7/GND!" "staticizer_1/w_90_n1211#" -4.26326e-14 0 0 0 0 0 0 0 0 0 -40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_1/in4" "fblock_0/f4" -57.014 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "fblock_0/f4" "a_580_1091#"
merge "latch_0/in7" "data_in7" -13.896 0 0 0 0 0 0 0 0 0 0 0 -6 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_4/in0" "latch_7/out0" -189.474 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -15 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_7/out0" "addr_out0"
merge "latch_4/out2" "staticizer_1/in2" -197.058 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -40 -36 0 0 0 0 0 0 0 0 0 0
merge "staticizer_1/in2" "a_n24_1448#"
merge "a_n24_1448#" "data_out2"
merge "staticizer_2/staticizer_one_7/Vdd!" "latch_5/latch_one_7/Vdd!" -0.246 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_3/in6" "shift_0/o6" -62.527 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "shift_0/o6" "a_373_740#"
merge "latch_5/in7" "addsub_1/s7" -55.421 0 0 0 0 0 0 0 0 0 0 -10 -13 0 0 0 0 20 -28 0 0 0 0 0 0 0 0
merge "addsub_1/s7" "PCLplus1_7"
merge "PCLplus1_7" "a_1716_569#"
merge "staticizer_0/staticizer_one_5/Vdd!" "latch_0/latch_one_5/Vdd!" 100.404 0 0 0 0 168 -48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_6/in2" "addsub_2/s2" -53.077 0 0 0 0 0 0 0 0 0 0 -10 -13 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_2/s2" "a_2516_1449#"
merge "staticizer_3/staticizer_one_2/Vdd!" "latch_6/latch_one_2/Vdd!" 1.36424e-12 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "reg_0/w" "A_w" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "latch_1/in2" "fblock_0/f2" -57.014 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "fblock_0/f2" "a_580_1443#"
merge "inv2_8/a_1_8#" "PCL_w_sel" -37.504 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -30 -22 0 0 0 0 0 0 0 0 0 0
merge "2nor_0/a" "latch_one_0/c" -934.555 0 0 0 0 0 0 0 0 0 0 0 -14 0 0 -25 -25 -25 -25 -120 -113 -2190 -1211 0 0 0 0
merge "latch_one_0/c" "4nor2_0/a"
merge "4nor2_0/a" "latch_2/c"
merge "latch_2/c" "ras"
merge "inv2_13/a_6_n1#" "inv2_16/a_1_8#" -3.66 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 -10 0 0 0 0 0 0 0 0 0 0
merge "latch_2/in5" "addsub_0/s5" -40.307 0 0 0 0 0 0 0 0 0 0 10 -10 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_0/s5" "a_841_921#"
merge "staticizer_4/in1" "latch_7/out1" -263.944 0 0 0 0 0 0 0 0 0 0 -62 -14 0 0 -29 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_7/out1" "addr_out1"
merge "staticizer_3/in4" "latch_6/out4" -189.474 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -15 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_6/out4" "a_2575_1100#"
merge "staticizer_3/staticizer_one_3/w_54_n57#" "latch_6/latch_one_3/GND!" -1.22213e-12 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_6/in3" "addsub_2/s3" -53.077 0 0 0 0 0 0 0 0 0 0 -10 -13 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_2/s3" "a_2516_1273#"
merge "latch_8/latch_one_7/GND!" "staticizer_5/staticizer_one_7/w_54_n57#" -8.88178e-15 0 0 0 0 0 0 0 0 154 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_3/staticizer_one_3/Vdd!" "latch_6/latch_one_3/Vdd!" 2.27374e-12 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_4/in2" "latch_7/out2" -189.474 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -15 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_7/out2" "addr_out2"
merge "staticizer_0/staticizer_one_3/w_54_n57#" "latch_0/latch_one_3/GND!" -5.68434e-14 0 0 0 0 0 0 0 0 140 -40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_0/staticizer_one_7/Vdd!" "latch_0/latch_one_7/Vdd!" 100.404 0 0 0 0 168 -48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_1/staticizer_one_4/out" "latch_4/out4" -185.118 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -10 -36 0 0 0 0 0 0 0 0 0 0
merge "latch_4/out4" "staticizer_1/in4"
merge "staticizer_1/in4" "a_n24_1096#"
merge "a_n24_1096#" "data_out4"
merge "addsub_1/a7" "reg_4/port70" -84.839 0 0 0 0 0 0 0 0 0 0 18 -10 0 0 30 -10 0 0 0 0 0 0 0 0 0 0
merge "reg_4/port70" "rx_PCL7"
merge "latch_1/in7" "fblock_0/f7" -57.014 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "fblock_0/f7" "a_580_563#"
merge "reg_5/in1" "mux_8bit_1/out1" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_1/out1" "m1_1909_1598#"
merge "staticizer_2/staticizer_one_3/w_54_n57#" "latch_5/latch_one_3/GND!" -1.22213e-12 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_6/in4" "addsub_2/s4" -53.077 0 0 0 0 0 0 0 0 0 0 -10 -13 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_2/s4" "a_2516_1097#"
merge "shift_0/s" "os_s" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "latch_4/out7" "staticizer_1/in7" -197.058 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -40 -36 0 0 0 0 0 0 0 0 0 0
merge "staticizer_1/in7" "a_n24_568#"
merge "a_n24_568#" "data_out7"
merge "reg_2/r0" "X_r0" -6.105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "staticizer_4/in3" "latch_7/out3" -189.474 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -15 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_7/out3" "addr_out3"
merge "latch_1/in5" "fblock_0/f5" -57.014 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "fblock_0/f5" "a_580_915#"
merge "staticizer_3/staticizer_one_1/w_54_n57#" "latch_6/latch_one_1/GND!" -1.12266e-12 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_0/staticizer_one_1/w_54_n57#" "latch_0/latch_one_1/GND!" -2.84217e-14 0 0 0 0 0 0 0 0 140 -40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/a6" "reg_4/port60" -99.329 0 0 0 0 0 0 0 0 0 0 18 -10 0 0 30 -10 0 0 0 0 0 0 0 0 0 0
merge "reg_4/port60" "rx_PCL6"
merge "staticizer_3/staticizer_one_5/Vdd!" "latch_6/latch_one_5/Vdd!" -6.82121e-13 0 0 0 0 0 -32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_2/in0" "addsub_0/s0" -55.443 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_0/s0" "a_841_1801#"
merge "staticizer_4/staticizer_one_2/w_54_n57#" "latch_7/latch_one_2/GND!" 1.476 0 0 0 0 0 0 0 0 -413 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "reg_5/in6" "mux_8bit_1/out6" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_1/out6" "m1_1909_718#"
merge "reg_5/in2" "mux_8bit_1/out2" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_1/out2" "m1_1909_1422#"
merge "latch_6/in5" "addsub_2/s5" -37.941 0 0 0 0 0 0 0 0 0 0 6 -13 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_2/s5" "a_2516_921#"
merge "addsub_1/xor_4/GND!" "addsub_1/b4" -115.486 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -20 -20 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/b4" "a_1545_1104#"
merge "reg_2/r1" "X_r1" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "staticizer_4/in4" "latch_7/out4" -189.474 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -15 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_7/out4" "addr_out4"
merge "staticizer_0/staticizer_one_5/w_54_n57#" "latch_0/latch_one_5/GND!" 1.42109e-14 0 0 0 0 0 0 0 0 140 -40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/a5" "reg_4/port50" -99.329 0 0 0 0 0 0 0 0 0 0 18 -10 0 0 30 -10 0 0 0 0 0 0 0 0 0 0
merge "reg_4/port50" "rx_PCL5"
merge "inv2_5/a_1_8#" "latch_6/c" -70.286 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -25 -20 0 0 25 -10 0 0 0 0 0 0
merge "latch_6/c" "rPCplus1H"
merge "inv2_13/a_1_8#" "inv2_14/a_6_n1#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "reg_5/r0" "PCH_r0" -7.118 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "latch_6/in6" "addsub_2/s6" -53.077 0 0 0 0 0 0 0 0 0 0 -10 -13 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_2/s6" "a_2516_745#"
merge "inv2_11/a_1_8#" "inv2_12/a_6_n1#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "inv2_3/a_1_8#" "inv2_6/a_6_n1#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "shift_0/u" "os_u" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "latch_4/latch_one_4/Vdd!" "staticizer_1/staticizer_one_4/Vdd!" -9.09495e-13 0 0 0 0 0 -48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_4/in5" "latch_7/out5" -259.478 0 0 0 0 0 0 0 0 0 0 -84 -14 0 0 -15 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_7/out5" "addr_out5"
merge "latch_1/in3" "fblock_0/f3" -57.014 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "fblock_0/f3" "a_580_1267#"
merge "staticizer_2/staticizer_one_6/w_54_n57#" "latch_5/latch_one_6/GND!" -4.83169e-13 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/a4" "reg_4/port40" -99.329 0 0 0 0 0 0 0 0 0 0 18 -10 0 0 30 -10 0 0 0 0 0 0 0 0 0 0
merge "reg_4/port40" "rx_PCL4"
merge "latch_2/in6" "addsub_0/s6" -55.443 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_0/s6" "a_841_745#"
merge "inv2_10/a_6_n1#" "inv2_12/a_1_8#" -3.66 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 -10 0 0 0 0 0 0 0 0 0 0
merge "reg_5/in4" "mux_8bit_1/out4" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_1/out4" "m1_1909_1070#"
merge "reg_5/r1" "PCH_r1" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "latch_1/in1" "fblock_0/f1" -41.878 0 0 0 0 0 0 0 0 0 0 12 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "fblock_0/f1" "a_580_1619#"
merge "staticizer_4/in6" "latch_7/out6" -179.922 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 9 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_7/out6" "addr_out6"
merge "staticizer_4/staticizer_one_2/Vdd!" "latch_7/latch_one_2/Vdd!" -2.27374e-13 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_4/latch_one_4/GND!" "staticizer_1/staticizer_one_4/w_54_n57#" -7.10543e-14 0 0 0 0 0 0 0 0 0 -40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/a3" "reg_4/port30" -99.329 0 0 0 0 0 0 0 0 0 0 18 -10 0 0 30 -10 0 0 0 0 0 0 0 0 0 0
merge "reg_4/port30" "rx_PCL3"
merge "reg_5/in5" "mux_8bit_1/out5" -124.882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -24 0 0 0 0 0 0 0 0 0 0
merge "mux_8bit_1/out5" "m1_1909_894#"
merge "latch_8/latch_one_5/GND!" "staticizer_5/staticizer_one_5/w_54_n57#" 1.95399e-14 0 0 0 0 0 0 0 0 154 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "4nor2_0/d" "latch_0/c" -117.262 0 0 0 0 0 0 0 0 0 0 0 -4 0 0 0 0 0 0 5 -10 0 0 0 0 0 0
merge "latch_0/c" "ld_datain"
merge "staticizer_3/staticizer_one_1/out" "mux_8bit_2/in0_1" -809.139 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -89 -60 77 0 56 0 -1404 -1200 0 0 0 0
merge "mux_8bit_2/in0_1" "mux_8bit_1/in0_1"
merge "mux_8bit_1/in0_1" "wz_addrH1"
merge "latch_2/in3" "addsub_0/s3" -55.443 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_0/s3" "a_841_1273#"
merge "staticizer_4/in7" "latch_7/out7" -189.474 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -15 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_7/out7" "addr_out7"
merge "reg_one_0/port1" "Cflag" -11.315 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -25 -20 0 0 0 0 0 0 0 0
merge "inv2_9/a_1_8#" "PCH_w_sel" -37.504 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -30 -22 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/a2" "reg_4/port20" -146.225 0 0 0 0 0 0 0 0 0 0 -24 -10 0 0 12 -10 0 0 0 0 0 0 0 0 0 0
merge "reg_4/port20" "rx_PCL2"
merge "latch_8/latch_one_4/Vdd!" "staticizer_5/staticizer_one_4/Vdd!" 110.187 0 0 0 0 189 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_4/latch_one_7/Vdd!" "staticizer_1/staticizer_one_7/Vdd!" -9.09495e-13 0 0 0 0 0 -48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "inv2_0/a_1_8#" "latch_4/c" -65.814 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -25 -20 0 0 5 -10 0 0 0 0 0 0
merge "latch_4/c" "rd_dataout"
merge "latch_1/in6" "fblock_0/f6" -57.014 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "fblock_0/f6" "a_580_739#"
merge "addsub_2/cin" "addsub_1/cout" -1956.18 0 0 0 0 0 0 0 0 0 0 0 -4 0 0 -20 -18 0 0 -6330 -2537 -3160 -1269 0 0 0 0
merge "addsub_1/cout" "a_2510_1893#"
merge "latch_2/in1" "addsub_0/s1" -38.415 0 0 0 0 0 0 0 0 0 0 12 -10 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_0/s1" "a_841_1625#"
merge "reg_7/w" "ABH_w" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "staticizer_3/staticizer_one_0/out" "mux_8bit_2/in0_0" -870.172 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -40 -60 70 0 35 0 -2965 -1200 0 0 0 0
merge "mux_8bit_2/in0_0" "mux_8bit_1/in0_0"
merge "mux_8bit_1/in0_0" "wz_addrH0"
merge "addsub_1/a1" "reg_4/port10" -99.329 0 0 0 0 0 0 0 0 0 0 18 -10 0 0 30 -10 0 0 0 0 0 0 0 0 0 0
merge "reg_4/port10" "rx_PCL1"
merge "latch_2/in2" "addsub_0/s2" -55.443 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_0/s2" "a_841_1449#"
merge "staticizer_4/staticizer_one_5/Vdd!" "latch_7/latch_one_5/Vdd!" 0 0 0 0 0 0 -32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_2/staticizer_one_3/Vdd!" "latch_5/latch_one_3/Vdd!" -0.246 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/a0" "reg_4/port00" -90.303 0 0 0 0 0 0 0 0 0 0 14 -20 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "reg_4/port00" "rx_PCL0"
merge "rx_PCL0" "addsub1_a0"
merge "reg_4/reg_one_7/a_33_32#" "PCL0" -9.866 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -20 -18 0 0 0 0 0 0 0 0
merge "staticizer_3/staticizer_one_4/out" "mux_8bit_2/in0_4" -870.172 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -40 -60 70 0 35 0 -2965 -1200 0 0 0 0
merge "mux_8bit_2/in0_4" "mux_8bit_1/in0_4"
merge "mux_8bit_1/in0_4" "wz_addrH4"
merge "staticizer_4/staticizer_one_5/w_54_n57#" "latch_7/latch_one_5/GND!" 0.738 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_1/in0" "fblock_0/f0" -57.014 0 0 0 0 0 0 0 0 0 0 -4 -8 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "fblock_0/f0" "a_580_1795#"
merge "latch_2/in7" "addsub_0/s7" -55.443 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_0/s7" "a_841_569#"
merge "reg_0/r0" "A_r0" -6.105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "latch_8/in7" "reg_7/port71" -626.245 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 0 0 -20 0 0 -2500 -1000 0 0 0 0
merge "reg_7/port71" "reg_5/port71"
merge "reg_5/port71" "ry_addrH7"
merge "staticizer_3/in2" "latch_6/out2" -189.474 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -15 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_6/out2" "a_2575_1452#"
merge "reg_one_0/w" "Cflag_w" -6.82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -25 -20 0 0 0 0 0 0
merge "latch_8/latch_one_3/GND!" "staticizer_5/staticizer_one_3/w_54_n57#" 1.95399e-14 0 0 0 0 0 0 0 0 154 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "latch_8/latch_one_7/Vdd!" "staticizer_5/staticizer_one_7/Vdd!" 110.187 0 0 0 0 189 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_0/staticizer_one_3/Vdd!" "latch_0/latch_one_3/Vdd!" 100.404 0 0 0 0 168 -48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "reg_0/r1" "A_r1" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "staticizer_3/in0" "latch_6/out0" -189.474 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -15 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_6/out0" "a_2575_1804#"
merge "fblock_0/g0" "fb_g0" -25.132 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -80 -47 0 0 0 0 0 0
merge "latch_2/in4" "addsub_0/s4" -55.443 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "addsub_0/s4" "a_841_1097#"
merge "latch_8/in6" "reg_7/port61" -720.175 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 0 0 -20 -120 -53 -2725 -1095 0 0 0 0
merge "reg_7/port61" "reg_5/port61"
merge "reg_5/port61" "ry_addrH6"
merge "inv2_7/a_6_n1#" "inv2_6/a_1_8#" -3.66 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 -10 0 0 0 0 0 0 0 0 0 0
merge "inv2_4/a_1_8#" "latch_5/c" -70.286 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -25 -20 0 0 25 -10 0 0 0 0 0 0
merge "latch_5/c" "rPCplus1L"
merge "staticizer_3/staticizer_one_3/out" "mux_8bit_2/in0_3" -870.172 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -40 -60 70 0 35 0 -2965 -1200 0 0 0 0
merge "mux_8bit_2/in0_3" "mux_8bit_1/in0_3"
merge "mux_8bit_1/in0_3" "wz_addrH3"
merge "reg_5/w" "PCH_w" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "staticizer_3/staticizer_one_6/w_54_n57#" "latch_6/latch_one_6/GND!" -4.83169e-13 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_2/staticizer_one_6/Vdd!" "latch_5/latch_one_6/Vdd!" -0.246 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "fblock_0/g1" "fb_g1" -21.484 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -32 -47 0 0 0 0 0 0
merge "latch_8/in5" "reg_7/port51" -647.636 0 0 0 0 0 0 0 0 0 0 10 -10 0 0 0 0 0 -20 0 0 -2500 -1000 0 0 0 0
merge "reg_7/port51" "reg_5/port51"
merge "reg_5/port51" "ry_addrH5"
merge "inv2_3/a_6_n1#" "mux_8bit_0/sel" -47.791 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -30 -22 0 0 0 0 0 0 0 0 0 0
merge "staticizer_4/staticizer_one_1/w_54_n57#" "latch_7/latch_one_1/GND!" 0.738 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_3/staticizer_one_7/out" "mux_8bit_2/in0_7" -865.136 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -40 -60 70 0 35 0 -2965 -1200 0 0 0 0
merge "mux_8bit_2/in0_7" "mux_8bit_1/in0_7"
merge "mux_8bit_1/in0_7" "wz_addrH7"
merge "inv2_14/a_1_8#" "ABH_w_sel" -33.19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -25 -20 0 0 0 0 0 0 0 0 0 0
merge "fblock_0/g2" "fb_g2" -25.132 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -80 -47 0 0 0 0 0 0
merge "latch_8/in4" "reg_7/port41" -662.772 0 0 0 0 0 0 0 0 0 0 -6 -10 0 0 0 0 0 -20 0 0 -2500 -1000 0 0 0 0
merge "reg_7/port41" "reg_5/port41"
merge "reg_5/port41" "ry_addrH4"
merge "staticizer_0/staticizer_one_6/Vdd!" "latch_0/latch_one_6/Vdd!" 99.174 0 0 0 0 168 -48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_3/in1" "latch_6/out1" -263.944 0 0 0 0 0 0 0 0 0 0 -62 -14 0 0 -29 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_6/out1" "a_2575_1628#"
merge "staticizer_2/staticizer_one_2/w_54_n57#" "latch_5/latch_one_2/GND!" -1.98952e-13 0 0 0 0 0 0 0 0 -413 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "fblock_0/g3" "fb_g3" -25.132 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -80 -47 0 0 0 0 0 0
merge "staticizer_3/staticizer_one_6/out" "mux_8bit_2/in0_6" -862.28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 -60 54 0 19 0 -2981 -1200 0 0 0 0
merge "mux_8bit_2/in0_6" "mux_8bit_1/in0_6"
merge "mux_8bit_1/in0_6" "wz_addrH6"
merge "staticizer_3/in3" "latch_6/out3" -189.474 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -15 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_6/out3" "a_2575_1276#"
merge "latch_4/latch_one_3/GND!" "staticizer_1/staticizer_one_3/w_54_n57#" -7.10543e-14 0 0 0 0 0 0 0 0 0 -40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "reg_3/r0" "Y_r0" -6.105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "reg_6/port70" "m1_2132_555#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "reg_3/r1" "Y_r1" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "reg_6/port60" "m1_2132_731#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "addsub_0/sub" "as_sub" -33.19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -25 -20 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/xor_6/GND!" "addsub_1/b6" -115.486 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -20 -20 0 0 0 0 0 0 0 0 0 0
merge "addsub_1/b6" "a_1545_752#"
merge "reg_6/r0" "ABL_r0" -6.105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0
merge "reg_6/port50" "m1_2132_907#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "staticizer_3/in5" "latch_6/out5" -282.182 0 0 0 0 0 0 0 0 0 0 -108 -14 0 0 -15 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_6/out5" "a_2575_924#"
merge "reg_1/w" "DB_w" -2.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0
merge "reg_6/port10" "m1_2132_1611#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "reg_6/port40" "m1_2132_1083#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "latch_8/latch_one_3/Vdd!" "staticizer_5/staticizer_one_3/Vdd!" 110.187 0 0 0 0 189 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_3/in7" "latch_6/out7" -189.474 0 0 0 0 0 0 0 0 0 0 -10 -14 0 0 -15 -16 0 0 0 0 0 0 0 0 0 0
merge "latch_6/out7" "a_2575_572#"
merge "staticizer_2/staticizer_one_2/Vdd!" "latch_5/latch_one_2/Vdd!" -0.246 0 0 0 0 0 -54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "reg_6/port20" "m1_2132_1435#" -11.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10 0 0 0 0 0 0 0 0 0 0
merge "reg_4/reg_one_6/a_33_32#" "PCL1" -9.866 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -20 -18 0 0 0 0 0 0 0 0
merge "staticizer_4/staticizer_one_4/w_54_n57#" "latch_7/latch_one_4/GND!" 1.476 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_2/staticizer_one_5/Vdd!" "latch_5/latch_one_5/Vdd!" -6.82121e-13 0 0 0 0 0 -32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "staticizer_2/staticizer_one_1/w_54_n57#" "latch_5/latch_one_1/GND!" -1.12266e-12 0 0 0 0 0 0 0 0 0 -44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0