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Initial public release
Signed-off-by: Michael Neuling <[email protected]> Signed-off-by: Anton Blanchard <[email protected]>
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‎.gitignore

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# Python
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__pycache__/
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/*.egg-info
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/.eggs
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/dist
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# tests
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*.v
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*.vcd
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*.gtkw

‎LICENSE

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© IBM Corp. 2021
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Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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the terms below; you may not use the files in this repository except in
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compliance with the License as modified. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Modified Terms:
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1) For the purpose of the patent license granted to you in Section 3 of
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the License, the "Work" hereby includes implementations of the work of
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authorship in physical form.
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Unless required by applicable law or agreed to in writing, the reference design
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distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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License for the specific language governing permissions and limitations under
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the License.
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Brief explanation of modifications:
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Modification 1: This modification extends the patent license to an
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implementation of the Work in physical form – i.e.,it unambiguously permits a
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user to make and use the physical chip.

‎README.md

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# LPC Peripheral Overview
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This is an LPC peripheral that implements LPC IO and FW cycles so that
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it can boot a host like a POWER9. This peripheral would typically sit
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inside a BMC SoC.
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# System diagram
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```
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.
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.
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LPC LPC Clock . System Clock
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pins . LPC FW DMA
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+---------+ +------------+ +--------+ Wishbone +--------+ Wishbone
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| | | ASYNC | | | | LPC | Master
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LCLK | +---->| FIFO WR +---->| +--------->| CTRL +-------->
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------->| LPC | | | | | | |
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| Front | +------------+ | LOGIC | +--------+
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LFRAME | | . | |
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------->| | +------------+ | | +--------+
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| | | ASYNC | | | | IPMI BT|
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LAD | |<----+ FIFO RD |<----+ +--------->| FIFO |<--------
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<------>| | | | | | | | IO
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+---------+ +------------+ +--------+ LPC IO +--------+ Wishbone
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. Wishbone | UART | Slave
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. | |
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. +--------+
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. | CTRL |
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| |
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+--------+
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```
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The design translates the LPC IO accesses into a wishbone master. The
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same is done for FW accesses.
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The LPC IO wishbone master bus has devices attached to it. These
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include a an IPMI BT FIFO and standard 16550 UART. The back end of
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these can then be access by an external IO wishbone slave (which would
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typically come from the BMC CPU).
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The LPC FW wishbone master gets translated into an external wishbone
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master. This translation provides an offset and mask so the external
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wishbone master accesses occur can be controlled. Typically this
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external wishbone will be hooked into a DMA path the system bus of the
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BMC, so where this can access needs to be controlled.
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The LPC front end runs using the LPC clock. The rest of the design
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works on the normal system clock. Async FIFOs provide a safe boundary
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between the two.
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HDL is written in nmigen because that's what all the cool kids are
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doing. This is our first nmigen project, and we are software
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developers, so be kind!
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# Building
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This is designed to be integrated into some other project (like
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microwatt for libreBMC) not build as a standalone project.
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If you want the verilog, do this to produce a lpcperipheral.v
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```
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python -m lpcperipheral.lpcperipheral
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```
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# Testing
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There are an extensive set of tests in tests/. To run these do:
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```
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python -m unittest
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```

‎lpcperipheral/__init__.py

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‎lpcperipheral/io_space.py

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from nmigen import Elaboratable, Module, Signal
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from nmigen.back import verilog
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from nmigen_soc.wishbone import Decoder as WishboneDecoder
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from nmigen_soc.wishbone import Interface as WishboneInterface
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from nmigen_soc.memory import MemoryMap
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from .ipmi_bt import IPMI_BT
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from .vuart_joined import VUartJoined
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class IOSpace(Elaboratable):
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def __init__(self, vuart_depth=2048, bmc_vuart_addr=0x0, bmc_ipmi_addr=0x1000,
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bmc_lpc_ctrl_addr=0x2000,
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target_vuart_addr=0x3f8, target_ipmi_addr=0xe4):
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self.vuart_depth = vuart_depth
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# BMC wishbone is 32 bit wide, so divide addresses by 4
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self.bmc_vuart_addr = bmc_vuart_addr // 4
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self.bmc_ipmi_addr = bmc_ipmi_addr // 4
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self.bmc_lpc_ctrl_addr = bmc_lpc_ctrl_addr // 4
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self.target_vuart_addr = target_vuart_addr
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self.target_ipmi_addr = target_ipmi_addr
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self.bmc_vuart_irq = Signal()
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self.bmc_ipmi_irq = Signal()
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self.bmc_wb = WishboneInterface(addr_width=14, data_width=8)
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self.target_vuart_irq = Signal()
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self.target_ipmi_irq = Signal()
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self.target_wb = WishboneInterface(addr_width=16, data_width=8, features=["err"])
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self.lpc_ctrl_wb = WishboneInterface(addr_width=3, data_width=8)
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self.error_wb = WishboneInterface(addr_width=2, data_width=8,
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features=["err"])
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def elaborate(self, platform):
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m = Module()
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m.submodules.vuart_joined = vuart_joined = VUartJoined(depth=self.vuart_depth)
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m.submodules.ipmi_bt = ipmi_bt = IPMI_BT()
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# BMC address decode
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m.submodules.bmc_decode = bmc_decode = WishboneDecoder(addr_width=14, data_width=8, granularity=8)
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bmc_ipmi_bus = ipmi_bt.bmc_wb
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bmc_ipmi_bus.memory_map = MemoryMap(addr_width=3, data_width=8)
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bmc_decode.add(bmc_ipmi_bus, addr=self.bmc_ipmi_addr)
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bmc_vuart_bus = vuart_joined.wb_a
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bmc_vuart_bus.memory_map = MemoryMap(addr_width=3, data_width=8)
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bmc_decode.add(bmc_vuart_bus, addr=self.bmc_vuart_addr)
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lpc_ctrl_bus = self.lpc_ctrl_wb
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lpc_ctrl_bus.memory_map = MemoryMap(addr_width=3, data_width=8)
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bmc_decode.add(lpc_ctrl_bus, addr=self.bmc_lpc_ctrl_addr)
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m.d.comb += [
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self.bmc_ipmi_irq.eq(ipmi_bt.bmc_irq),
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self.bmc_vuart_irq.eq(vuart_joined.irq_a),
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self.bmc_wb.connect(bmc_decode.bus)
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]
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# Target address decode
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m.submodules.target_decode = target_decode = WishboneDecoder(addr_width=16, data_width=8, granularity=8, features=["err"])
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target_ipmi_bus = ipmi_bt.target_wb
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target_ipmi_bus.memory_map = MemoryMap(addr_width=2, data_width=8)
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target_decode.add(target_ipmi_bus, addr=self.target_ipmi_addr)
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target_vuart_bus = vuart_joined.wb_b
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target_vuart_bus.memory_map = MemoryMap(addr_width=3, data_width=8)
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target_decode.add(target_vuart_bus, addr=self.target_vuart_addr)
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target_error_bus = self.error_wb
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target_error_bus.memory_map = MemoryMap(addr_width=2, data_width=8)
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# Generate a signal when we'd expect an ACK on the target bus
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ack_expected = Signal()
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m.d.sync += ack_expected.eq(self.target_wb.sel & self.target_wb.cyc &
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~ack_expected)
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# Generate an error if no ack from ipmi_bt or vuart
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m.d.comb += self.error_wb.err.eq(0)
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with m.If (ack_expected):
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m.d.comb += self.error_wb.err.eq(~ipmi_bt.target_wb.ack &
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~vuart_joined.wb_b.ack)
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target_decode.add(target_error_bus, addr=0x0)
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m.d.comb += [
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self.target_ipmi_irq.eq(ipmi_bt.target_irq),
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self.target_vuart_irq.eq(vuart_joined.irq_b),
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self.target_wb.connect(target_decode.bus)
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]
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return m
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if __name__ == "__main__":
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top = IOSpace()
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with open("io_map.v", "w") as f:
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f.write(verilog.convert(top))

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