PyHDI
diff --git a/‎examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/ultra96v2_pynq/blinkled_v1_0/component.xml
+1-1 b/‎examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/ultra96v2_pynq/blinkled_v1_0/component.xml
+1-1
diff --git a/‎examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/ultra96v2_pynq/blinkled_v1_0/hdl/blinkled.v
+448-430 b/‎examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/ultra96v2_pynq/blinkled_v1_0/hdl/blinkled.v
+448-430
diff --git a/‎examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/ultra96v2_pynq/stream_axi_stream_fifo_ipxact.bit
0 Bytes b/‎examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/ultra96v2_pynq/stream_axi_stream_fifo_ipxact.bit
0 Bytes
diff --git a/‎examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/ultra96v2_pynq/stream_axi_stream_fifo_ipxact.hwh
+295-295 b/‎examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/ultra96v2_pynq/stream_axi_stream_fifo_ipxact.hwh
+295-295
diff --git a/‎examples/stream_axi_stream_fifo_ultra96v2_pynq/ultra96v2_pynq/stream_axi_stream_fifo.bit
0 Bytes b/‎examples/stream_axi_stream_fifo_ultra96v2_pynq/ultra96v2_pynq/stream_axi_stream_fifo.bit
0 Bytes
diff --git a/‎examples/stream_axi_stream_fifo_ultra96v2_pynq/ultra96v2_pynq/stream_axi_stream_fifo.hwh
+538-1,043 b/‎examples/stream_axi_stream_fifo_ultra96v2_pynq/ultra96v2_pynq/stream_axi_stream_fifo.hwh
+538-1,043
diff --git a/‎examples/stream_axi_stream_fifo_ultra96v2_pynq/ultra96v2_pynq/stream_axi_stream_fifo.v
+448-430 b/‎examples/stream_axi_stream_fifo_ultra96v2_pynq/ultra96v2_pynq/stream_axi_stream_fifo.v
+448-430
diff --git a/‎examples/stream_matmul_ultra96v2_pynq/ultra96v2_pynq/stream_matmul.bit
0 Bytes b/‎examples/stream_matmul_ultra96v2_pynq/ultra96v2_pynq/stream_matmul.bit
0 Bytes
diff --git a/‎examples/stream_matmul_ultra96v2_pynq/ultra96v2_pynq/stream_matmul.hwh
+1-1 b/‎examples/stream_matmul_ultra96v2_pynq/ultra96v2_pynq/stream_matmul.hwh
+1-1
@@ -1699,7 +1699,7 @@
       </xilinx:taxonomies>
       <xilinx:displayName>blinkled_v1_0</xilinx:displayName>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2022-03-06T10:09:37Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2022-04-03T13:52:11Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
       <xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
 
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Mar  6 12:04:25 2022" VIVADOVERSION="2021.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Apr  3 16:34:06 2022" VIVADOVERSION="2021.2">
 
   <SYSTEMINFO ARCH="zynquplus" BOARD="em.avnet.com:ultra96v2:part0:1.0" DEVICE="xczu3eg" NAME="design_1" PACKAGE="sbva484" SPEEDGRADE="-1"/>