README

Author: shtaxxx

README.md

@@ -31,7 +31,7 @@ Requirements
 * Python (2.7 or later, 3.3 or later)
 * Pyverilog (Python-based Verilog HDL Design Processing Toolkit)
     - Install from pip: 'pip install pyverilog' for Python2.7 or 'pip3 install pyverilog' for Python3
-    - Otherwise, install from github into this package: 'cd Pycoram; git clone https://github.com/shtaxxx/Pyverilog.git; cd pycoram; ln -s ../Pyverilog/pyverilog'
+    - Otherwise, install from github into this package: 'cd Pycoram; git clone https://github.com/PyHDI/Pyverilog.git; cd pycoram; ln -s ../Pyverilog/pyverilog'
 * Jinja2 (2.7 or later)
    - The code generator (in Pyverilog) uses Jinja2 template engine.
    - 'pip install jinja2' (for Python 2.x) or 'pip3 install jinja2' (for Python 3.x)
@@ -179,5 +179,5 @@ Not yet.
 Related Project
 ==============================
 
-[Pyverilog](https://github.com/Pyverilog/Pyverilog)
+[Pyverilog](https://github.com/PyHDI/Pyverilog)
 - Python-based Hardware Design Processing Toolkit for Verilog HDL

README.rst

@@ -36,7 +36,7 @@ Requirements
    -  Install from pip: 'pip install pyverilog' for Python2.7 or 'pip3
       install pyverilog' for Python3
    -  Otherwise, install from github into this package: 'cd Pycoram; git
-      clone https://github.com/shtaxxx/Pyverilog.git; cd pycoram; ln -s
+      clone https://github.com/PyHDI/Pyverilog.git; cd pycoram; ln -s
       ../Pyverilog/pyverilog'
 
 -  Jinja2 (2.7 or later)
@@ -195,5 +195,5 @@ Not yet.
 Related Project
 ===============
 
-`Pyverilog <https://github.com/shtaxxx/Pyverilog>`__ - Python-based
+`Pyverilog <https://github.com/PyHDI/Pyverilog>`__ - Python-based
 Hardware Design Processing Toolkit for Verilog HDL