Merge branch '2.1.0-rc'

Author: shtaxxx

README.md

@@ -82,15 +82,18 @@ Installation
 Requirements
 --------------------
 
-- Python3: 3.7 or later
+- Python: 3.7.7 or later
+    - Python 3.9.5 (via pyenv) is recommended for macOS with Apple Silicon.
 - Icarus Verilog: 10.1 or later
 
 ```
 sudo apt install iverilog
 ```
 
-- Pyverilog: 1.3.0 or later
-- NumPy: 1.17 or later
+- pyverilog: 1.3.0 or later
+    - pyverilog requires Jinja2. Jinja2 3.0.3 is recommended for macOS with Apple Silicon.
+- numpy: 1.17 or later
+    - numpy 1.22.1 is recommended for macOS with Apple Silicon.
 
 ```
 pip3 install pyverilog numpy
@@ -111,7 +114,7 @@ pip3 install pytest pytest-pythonpath
 
 For fast RTL simulation, we recommend to install Verilator.
 
-- Verilator: 3.916 or later
+- Verilator: 4.028 or later
 
 ```
 sudo apt install verilator
@@ -122,8 +125,8 @@ Optional installation for visualization
 
 To visualize the generated hardware by veriloggen.stream, these libraries are required.
 
-- Graphviz: 2.38.0 or later
-- Pygraphviz: 1.3.1 or later
+- graphviz: 2.38.0 or later
+- pygraphviz: 1.3.1 or later
 
 ```
 sudo apt install graphviz

examples/thread_nexys4/Makefile renamed to examples/axi_stream_ultra96v2_pynq/Makefile

@@ -0,0 +1,60 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.abspath(__file__)))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+
+    axi_a = vthread.AXIStreamIn(m, 'axi_a', clk, rst, datawidth, with_last=True)
+    axi_b = vthread.AXIStreamOut(m, 'axi_b', clk, rst, datawidth, with_last=True)
+
+    saxi = vthread.AXISLiteRegister(m, 'saxi', clk, rst, datawidth)
+
+    def comp():
+
+        while True:
+            saxi.wait_flag(0, value=1, resetvalue=0)
+            saxi.write(1, 1)  # set busy
+            size = saxi.read(2)
+
+            for i in range(size):
+                a, a_last = axi_a.read()
+                b = a + 1
+                b_last = a_last
+                axi_b.write(b, b_last)
+
+            saxi.write(1, 0)  # unset busy
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start()
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    test = mkLed()
+
+    code = test.to_verilog(filename)
+    return code
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)