Merge branch 'fix_reset_visitor'

Author: shtaxxx

tests/extension/seq_/countup_cat/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/extension/seq_/countup_cat/seq_countup_cat.py

@@ -0,0 +1,76 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+
+
+def mkLed():
+    m = Module('blinkled')
+    interval = m.Parameter('INTERVAL', 16)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', 8, initval=0)
+
+    count0 = m.Reg('count0', 4, initval=0)
+    count1 = m.Reg('count1', 4, initval=0)
+
+    seq = Seq(m, 'seq', clk, rst)
+
+    seq(
+        Systask('display', 'LED:%d count0:%d count1:%d', led, count0, count1)
+    )
+
+    seq.If(Cat(count0, count1) < interval-1)(
+        Cat(count0, count1[0:4])(Cat(count0, count1) + 1)
+    )
+    seq.If(Cat(count0, count1) == interval-1)(
+        Cat(count0, count1[0:4])(0)
+    )
+    seq.If(Cat(count0, count1) == interval-1)(
+        led(led + 1)
+    )
+
+    seq.make_always()
+
+    return m
+
+
+def mkTest():
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    #simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog()
+    print(verilog)

tests/extension/seq_/countup_cat/test_seq_countup_cat.py

@@ -0,0 +1,103 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import veriloggen
+import seq_countup_cat
+
+expected_verilog = """
+module test #
+(
+  parameter INTERVAL = 16
+)
+(
+
+);
+
+  reg CLK;
+  reg RST;
+  wire [8-1:0] LED;
+
+  blinkled
+  #(
+    .INTERVAL(INTERVAL)
+  )
+  uut
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .LED(LED)
+  );
+
+
+  initial begin
+    CLK = 0;
+    forever begin
+      #5 CLK = !CLK;
+    end
+  end
+
+
+  initial begin
+    RST = 0;
+    #100;
+    RST = 1;
+    #100;
+    RST = 0;
+    #1000;
+    $finish;
+  end
+
+
+endmodule
+
+
+
+module blinkled #
+(
+  parameter INTERVAL = 16
+)
+(
+  input CLK,
+  input RST,
+  output reg [8-1:0] LED
+);
+
+  reg [4-1:0] count0;
+  reg [4-1:0] count1;
+  localparam [4-1:0] _tmp_0 = (0 >> 0) & { 4{ 1'd1 } };
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      { count0, count1[3:0] } <= { 4'd0, _tmp_0 };
+      LED <= 0;
+    end else begin
+      $display("LED:%d count0:%d count1:%d", LED, count0, count1);
+      if({ count0, count1 } < INTERVAL - 1) begin
+        { count0, count1[3:0] } <= { count0, count1 } + 1;
+      end 
+      if({ count0, count1 } == INTERVAL - 1) begin
+        { count0, count1[3:0] } <= 0;
+      end 
+      if({ count0, count1 } == INTERVAL - 1) begin
+        LED <= LED + 1;
+      end 
+    end
+  end
+
+
+endmodule
+"""
+
+
+def test():
+    veriloggen.reset()
+    test_module = seq_countup_cat.mkTest()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)

veriloggen/seq/reset_visitor.py

@@ -3,6 +3,7 @@
 
 import os
 import sys
+import copy
 
 import veriloggen.core.vtypes as vtypes
 
@@ -57,9 +58,21 @@ def visit_Slice(self, node):
     def visit_Cat(self, node):
         left_values = []
         right_values = []
+
         for v in node.vars:
             val = self.visit(v)
-            right = vtypes.IntX() if val is None else val.right
+            width = v.bit_length()
+            if val is None:
+                right = vtypes.IntX(width)
+            elif isinstance(val.right, int):
+                right = vtypes.Int(val.right, width)
+            elif isinstance(val.right, vtypes._Constant):
+                right = copy.deepcopy(val.right)
+                right.width = width
+            else:
+                right = v._get_module().TmpLocalparam(val.right, width)
+
             left_values.append(v)
             right_values.append(right)
-        return vtypes.Subst(vtypes.Cat(tuple(left_values)), vtypes.Cat(tuple(right_values)))
+
+        return vtypes.Subst(vtypes.Cat(*left_values), vtypes.Cat(*right_values))