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1.8.9-rc
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-5126
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39 files changed

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‎examples/simulation_verilator/test_simulation_verilator.py

+10-10
Original file line numberDiff line numberDiff line change
@@ -640,7 +640,7 @@
640640
assign myaxi_arprot = 0;
641641
assign myaxi_arqos = 0;
642642
assign myaxi_aruser = 0;
643-
reg [32-1:0] outstanding_wreq_count_0;
643+
reg [3-1:0] outstanding_wcount_0;
644644
reg _myaxi_read_start;
645645
reg [8-1:0] _myaxi_read_op_sel;
646646
reg [32-1:0] _myaxi_read_local_addr;
@@ -771,7 +771,7 @@
771771
wire [32-1:0] _dataflow__variable_odata_2;
772772
wire _dataflow__variable_ovalid_2;
773773
wire _dataflow__variable_oready_2;
774-
assign _dataflow__variable_oready_2 = (_myaxi_write_fsm == 3) && (_myaxi_write_op_sel == 1) && ((counter_30 > 0) && (myaxi_wready || !myaxi_wvalid));
774+
assign _dataflow__variable_oready_2 = (_myaxi_write_fsm == 3) && (_myaxi_write_op_sel == 1) && ((counter_30 > 0) && (outstanding_wcount_0 < 6) && (myaxi_wready || !myaxi_wvalid));
775775
reg _myaxi_cond_2_1;
776776
assign _myaxi_write_data_done = (last_31 && myaxi_wvalid && myaxi_wready)? 1 : 0;
777777
reg axim_flag_32;
@@ -1017,7 +1017,7 @@
10171017
10181018
always @(posedge CLK) begin
10191019
if(RST) begin
1020-
outstanding_wreq_count_0 <= 0;
1020+
outstanding_wcount_0 <= 0;
10211021
_myaxi_read_start <= 0;
10221022
_myaxi_write_start <= 0;
10231023
_myaxi_ram_a_0_read_start <= 0;
@@ -1084,11 +1084,11 @@
10841084
myaxi_wlast <= 0;
10851085
last_31 <= 0;
10861086
end
1087-
if(myaxi_wlast && myaxi_wvalid && myaxi_wready && !(myaxi_bvalid && myaxi_bready)) begin
1088-
outstanding_wreq_count_0 <= outstanding_wreq_count_0 + 1;
1087+
if(myaxi_wlast && myaxi_wvalid && myaxi_wready && !(myaxi_bvalid && myaxi_bready) && (outstanding_wcount_0 < 7)) begin
1088+
outstanding_wcount_0 <= outstanding_wcount_0 + 1;
10891089
end
1090-
if(!(myaxi_wlast && myaxi_wvalid && myaxi_wready) && (myaxi_bvalid && myaxi_bready) && (outstanding_wreq_count_0 > 0)) begin
1091-
outstanding_wreq_count_0 <= outstanding_wreq_count_0 - 1;
1090+
if(!(myaxi_wlast && myaxi_wvalid && myaxi_wready) && (myaxi_bvalid && myaxi_bready) && (outstanding_wcount_0 > 0)) begin
1091+
outstanding_wcount_0 <= outstanding_wcount_0 - 1;
10921092
end
10931093
_myaxi_read_start <= 0;
10941094
_myaxi_write_start <= 0;
@@ -1181,14 +1181,14 @@
11811181
if(myaxi_awvalid && !myaxi_awready) begin
11821182
myaxi_awvalid <= myaxi_awvalid;
11831183
end
1184-
if(_dataflow__variable_ovalid_2 && ((_myaxi_write_fsm == 3) && (_myaxi_write_op_sel == 1) && ((counter_30 > 0) && (myaxi_wready || !myaxi_wvalid))) && ((counter_30 > 0) && (myaxi_wready || !myaxi_wvalid) && (counter_30 > 0))) begin
1184+
if(_dataflow__variable_ovalid_2 && ((_myaxi_write_fsm == 3) && (_myaxi_write_op_sel == 1) && ((counter_30 > 0) && (outstanding_wcount_0 < 6) && (myaxi_wready || !myaxi_wvalid))) && ((counter_30 > 0) && (outstanding_wcount_0 < 6) && (myaxi_wready || !myaxi_wvalid) && (counter_30 > 0))) begin
11851185
myaxi_wdata <= _dataflow__variable_odata_2;
11861186
myaxi_wvalid <= 1;
11871187
myaxi_wlast <= 0;
11881188
myaxi_wstrb <= { 4{ 1'd1 } };
11891189
counter_30 <= counter_30 - 1;
11901190
end
1191-
if(_dataflow__variable_ovalid_2 && ((_myaxi_write_fsm == 3) && (_myaxi_write_op_sel == 1) && ((counter_30 > 0) && (myaxi_wready || !myaxi_wvalid))) && ((counter_30 > 0) && (myaxi_wready || !myaxi_wvalid) && (counter_30 > 0)) && (counter_30 == 1)) begin
1191+
if(_dataflow__variable_ovalid_2 && ((_myaxi_write_fsm == 3) && (_myaxi_write_op_sel == 1) && ((counter_30 > 0) && (outstanding_wcount_0 < 6) && (myaxi_wready || !myaxi_wvalid))) && ((counter_30 > 0) && (outstanding_wcount_0 < 6) && (myaxi_wready || !myaxi_wvalid) && (counter_30 > 0)) && (counter_30 == 1)) begin
11921192
myaxi_wlast <= 1;
11931193
last_31 <= 1;
11941194
end
@@ -1517,7 +1517,7 @@
15171517
th_matmul <= th_matmul_32;
15181518
end
15191519
th_matmul_32: begin
1520-
if(_myaxi_write_idle && (outstanding_wreq_count_0 == 0)) begin
1520+
if(_myaxi_write_idle && (outstanding_wcount_0 == 0)) begin
15211521
th_matmul <= th_matmul_33;
15221522
end
15231523
end

‎examples/thread_add_ipxact/test_thread_add_ipxact.py

+13-13
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@
5555
assign _saxi_bready = 1;
5656
assign _saxi_arcache = 3;
5757
assign _saxi_arprot = 0;
58-
reg [32-1:0] outstanding_wreq_count_0;
58+
reg [3-1:0] outstanding_wcount_0;
5959
wire [32-1:0] _tmp_1;
6060
assign _tmp_1 = _saxi_awaddr;
6161
@@ -234,7 +234,7 @@
234234
_saxi_wvalid = 0;
235235
_saxi_araddr = 0;
236236
_saxi_arvalid = 0;
237-
outstanding_wreq_count_0 = 0;
237+
outstanding_wcount_0 = 0;
238238
counter = 0;
239239
th_ctrl = th_ctrl_init;
240240
_th_ctrl_i_3 = 0;
@@ -270,7 +270,7 @@
270270
271271
always @(posedge CLK) begin
272272
if(RST) begin
273-
outstanding_wreq_count_0 <= 0;
273+
outstanding_wcount_0 <= 0;
274274
_saxi_awaddr <= 0;
275275
_saxi_awvalid <= 0;
276276
__saxi_cond_0_1 <= 0;
@@ -315,11 +315,11 @@
315315
if(__saxi_cond_8_1) begin
316316
_saxi_arvalid <= 0;
317317
end
318-
if(_saxi_wvalid && _saxi_wready && !(_saxi_bvalid && _saxi_bready)) begin
319-
outstanding_wreq_count_0 <= outstanding_wreq_count_0 + 1;
318+
if(_saxi_wvalid && _saxi_wready && !(_saxi_bvalid && _saxi_bready) && (outstanding_wcount_0 < 7)) begin
319+
outstanding_wcount_0 <= outstanding_wcount_0 + 1;
320320
end
321-
if(!(_saxi_wvalid && _saxi_wready) && (_saxi_bvalid && _saxi_bready) && (outstanding_wreq_count_0 > 0)) begin
322-
outstanding_wreq_count_0 <= outstanding_wreq_count_0 - 1;
321+
if(!(_saxi_wvalid && _saxi_wready) && (_saxi_bvalid && _saxi_bready) && (outstanding_wcount_0 > 0)) begin
322+
outstanding_wcount_0 <= outstanding_wcount_0 - 1;
323323
end
324324
if((th_ctrl == 7) && (_saxi_awready || !_saxi_awvalid)) begin
325325
_saxi_awaddr <= _th_ctrl_awaddr_4;
@@ -329,7 +329,7 @@
329329
if(_saxi_awvalid && !_saxi_awready) begin
330330
_saxi_awvalid <= _saxi_awvalid;
331331
end
332-
if((th_ctrl == 8) && (_saxi_wready || !_saxi_wvalid)) begin
332+
if((th_ctrl == 8) && ((outstanding_wcount_0 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
333333
_saxi_wdata <= _th_ctrl_a_5;
334334
_saxi_wvalid <= 1;
335335
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -346,7 +346,7 @@
346346
if(_saxi_awvalid && !_saxi_awready) begin
347347
_saxi_awvalid <= _saxi_awvalid;
348348
end
349-
if((th_ctrl == 13) && (_saxi_wready || !_saxi_wvalid)) begin
349+
if((th_ctrl == 13) && ((outstanding_wcount_0 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
350350
_saxi_wdata <= _th_ctrl_b_6;
351351
_saxi_wvalid <= 1;
352352
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -363,7 +363,7 @@
363363
if(_saxi_awvalid && !_saxi_awready) begin
364364
_saxi_awvalid <= _saxi_awvalid;
365365
end
366-
if((th_ctrl == 18) && (_saxi_wready || !_saxi_wvalid)) begin
366+
if((th_ctrl == 18) && ((outstanding_wcount_0 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
367367
_saxi_wdata <= 1;
368368
_saxi_wvalid <= 1;
369369
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -500,7 +500,7 @@
500500
end
501501
end
502502
th_ctrl_8: begin
503-
if(_saxi_wready || !_saxi_wvalid) begin
503+
if((outstanding_wcount_0 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
504504
th_ctrl <= th_ctrl_9;
505505
end
506506
end
@@ -522,7 +522,7 @@
522522
end
523523
end
524524
th_ctrl_13: begin
525-
if(_saxi_wready || !_saxi_wvalid) begin
525+
if((outstanding_wcount_0 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
526526
th_ctrl <= th_ctrl_14;
527527
end
528528
end
@@ -544,7 +544,7 @@
544544
end
545545
end
546546
th_ctrl_18: begin
547-
if(_saxi_wready || !_saxi_wvalid) begin
547+
if((outstanding_wcount_0 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
548548
th_ctrl <= th_ctrl_19;
549549
end
550550
end

‎examples/thread_embedded_verilog_ipcore/Makefile renamed to ‎examples/thread_embedded_verilog_ipxact/Makefile

File renamed without changes.

‎examples/thread_embedded_verilog_ipcore/test_thread_embedded_verilog_ipxact.py renamed to ‎examples/thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py

+25-25
Original file line numberDiff line numberDiff line change
@@ -299,7 +299,7 @@
299299
assign _saxi_bready = 1;
300300
assign _saxi_arcache = 3;
301301
assign _saxi_arprot = 0;
302-
reg [32-1:0] outstanding_wreq_count_9;
302+
reg [3-1:0] outstanding_wcount_9;
303303
wire [32-1:0] _tmp_10;
304304
assign _tmp_10 = _saxi_awaddr;
305305
@@ -465,7 +465,7 @@
465465
_saxi_wvalid = 0;
466466
_saxi_araddr = 0;
467467
_saxi_arvalid = 0;
468-
outstanding_wreq_count_9 = 0;
468+
outstanding_wcount_9 = 0;
469469
counter = 0;
470470
th_ctrl = th_ctrl_init;
471471
_th_ctrl_i_11 = 0;
@@ -744,7 +744,7 @@
744744
745745
always @(posedge uut_CLK) begin
746746
if(uut_RST) begin
747-
outstanding_wreq_count_9 <= 0;
747+
outstanding_wcount_9 <= 0;
748748
_saxi_awaddr <= 0;
749749
_saxi_awvalid <= 0;
750750
__saxi_cond_0_1 <= 0;
@@ -793,11 +793,11 @@
793793
if(__saxi_cond_9_1) begin
794794
_saxi_arvalid <= 0;
795795
end
796-
if(_saxi_wvalid && _saxi_wready && !(_saxi_bvalid && _saxi_bready)) begin
797-
outstanding_wreq_count_9 <= outstanding_wreq_count_9 + 1;
796+
if(_saxi_wvalid && _saxi_wready && !(_saxi_bvalid && _saxi_bready) && (outstanding_wcount_9 < 7)) begin
797+
outstanding_wcount_9 <= outstanding_wcount_9 + 1;
798798
end
799-
if(!(_saxi_wvalid && _saxi_wready) && (_saxi_bvalid && _saxi_bready) && (outstanding_wreq_count_9 > 0)) begin
800-
outstanding_wreq_count_9 <= outstanding_wreq_count_9 - 1;
799+
if(!(_saxi_wvalid && _saxi_wready) && (_saxi_bvalid && _saxi_bready) && (outstanding_wcount_9 > 0)) begin
800+
outstanding_wcount_9 <= outstanding_wcount_9 - 1;
801801
end
802802
if((th_ctrl == 6) && (_saxi_awready || !_saxi_awvalid)) begin
803803
_saxi_awaddr <= _th_ctrl_awaddr_12;
@@ -807,7 +807,7 @@
807807
if(_saxi_awvalid && !_saxi_awready) begin
808808
_saxi_awvalid <= _saxi_awvalid;
809809
end
810-
if((th_ctrl == 7) && (_saxi_wready || !_saxi_wvalid)) begin
810+
if((th_ctrl == 7) && ((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
811811
_saxi_wdata <= 4096;
812812
_saxi_wvalid <= 1;
813813
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -824,7 +824,7 @@
824824
if(_saxi_awvalid && !_saxi_awready) begin
825825
_saxi_awvalid <= _saxi_awvalid;
826826
end
827-
if((th_ctrl == 12) && (_saxi_wready || !_saxi_wvalid)) begin
827+
if((th_ctrl == 12) && ((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
828828
_saxi_wdata <= _th_ctrl_src_offset_13;
829829
_saxi_wvalid <= 1;
830830
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -841,7 +841,7 @@
841841
if(_saxi_awvalid && !_saxi_awready) begin
842842
_saxi_awvalid <= _saxi_awvalid;
843843
end
844-
if((th_ctrl == 17) && (_saxi_wready || !_saxi_wvalid)) begin
844+
if((th_ctrl == 17) && ((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
845845
_saxi_wdata <= _th_ctrl_dst_offset_14;
846846
_saxi_wvalid <= 1;
847847
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -858,7 +858,7 @@
858858
if(_saxi_awvalid && !_saxi_awready) begin
859859
_saxi_awvalid <= _saxi_awvalid;
860860
end
861-
if((th_ctrl == 22) && (_saxi_wready || !_saxi_wvalid)) begin
861+
if((th_ctrl == 22) && ((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid))) begin
862862
_saxi_wdata <= 1;
863863
_saxi_wvalid <= 1;
864864
_saxi_wstrb <= { 4{ 1'd1 } };
@@ -980,7 +980,7 @@
980980
end
981981
end
982982
th_ctrl_7: begin
983-
if(_saxi_wready || !_saxi_wvalid) begin
983+
if((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
984984
th_ctrl <= th_ctrl_8;
985985
end
986986
end
@@ -1002,7 +1002,7 @@
10021002
end
10031003
end
10041004
th_ctrl_12: begin
1005-
if(_saxi_wready || !_saxi_wvalid) begin
1005+
if((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
10061006
th_ctrl <= th_ctrl_13;
10071007
end
10081008
end
@@ -1024,7 +1024,7 @@
10241024
end
10251025
end
10261026
th_ctrl_17: begin
1027-
if(_saxi_wready || !_saxi_wvalid) begin
1027+
if((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
10281028
th_ctrl <= th_ctrl_18;
10291029
end
10301030
end
@@ -1046,7 +1046,7 @@
10461046
end
10471047
end
10481048
th_ctrl_22: begin
1049-
if(_saxi_wready || !_saxi_wvalid) begin
1049+
if((outstanding_wcount_9 < 6) && (_saxi_wready || !_saxi_wvalid)) begin
10501050
th_ctrl <= th_ctrl_23;
10511051
end
10521052
end
@@ -1216,7 +1216,7 @@
12161216
assign maxi_arprot = 0;
12171217
assign maxi_arqos = 0;
12181218
assign maxi_aruser = 0;
1219-
reg [32-1:0] outstanding_wreq_count_0;
1219+
reg [3-1:0] outstanding_wcount_0;
12201220
reg _maxi_read_start;
12211221
reg [8-1:0] _maxi_read_op_sel;
12221222
reg [32-1:0] _maxi_read_local_addr;
@@ -1393,7 +1393,7 @@
13931393
wire [32-1:0] _dataflow__variable_odata_1;
13941394
wire _dataflow__variable_ovalid_1;
13951395
wire _dataflow__variable_oready_1;
1396-
assign _dataflow__variable_oready_1 = (_maxi_write_fsm == 3) && (_maxi_write_op_sel == 1) && ((counter_30 > 0) && (maxi_wready || !maxi_wvalid));
1396+
assign _dataflow__variable_oready_1 = (_maxi_write_fsm == 3) && (_maxi_write_op_sel == 1) && ((counter_30 > 0) && (outstanding_wcount_0 < 6) && (maxi_wready || !maxi_wvalid));
13971397
reg _maxi_cond_2_1;
13981398
assign _maxi_write_data_done = (last_31 && maxi_wvalid && maxi_wready)? 1 : 0;
13991399
reg axim_flag_32;
@@ -1476,7 +1476,7 @@
14761476
14771477
always @(posedge CLK) begin
14781478
if(RST) begin
1479-
outstanding_wreq_count_0 <= 0;
1479+
outstanding_wcount_0 <= 0;
14801480
_maxi_read_start <= 0;
14811481
_maxi_write_start <= 0;
14821482
_maxi_ram_a_0_read_start <= 0;
@@ -1531,11 +1531,11 @@
15311531
maxi_wlast <= 0;
15321532
last_31 <= 0;
15331533
end
1534-
if(maxi_wlast && maxi_wvalid && maxi_wready && !(maxi_bvalid && maxi_bready)) begin
1535-
outstanding_wreq_count_0 <= outstanding_wreq_count_0 + 1;
1534+
if(maxi_wlast && maxi_wvalid && maxi_wready && !(maxi_bvalid && maxi_bready) && (outstanding_wcount_0 < 7)) begin
1535+
outstanding_wcount_0 <= outstanding_wcount_0 + 1;
15361536
end
1537-
if(!(maxi_wlast && maxi_wvalid && maxi_wready) && (maxi_bvalid && maxi_bready) && (outstanding_wreq_count_0 > 0)) begin
1538-
outstanding_wreq_count_0 <= outstanding_wreq_count_0 - 1;
1537+
if(!(maxi_wlast && maxi_wvalid && maxi_wready) && (maxi_bvalid && maxi_bready) && (outstanding_wcount_0 > 0)) begin
1538+
outstanding_wcount_0 <= outstanding_wcount_0 - 1;
15391539
end
15401540
_maxi_read_start <= 0;
15411541
_maxi_write_start <= 0;
@@ -1608,14 +1608,14 @@
16081608
if(maxi_awvalid && !maxi_awready) begin
16091609
maxi_awvalid <= maxi_awvalid;
16101610
end
1611-
if(_dataflow__variable_ovalid_1 && ((_maxi_write_fsm == 3) && (_maxi_write_op_sel == 1) && ((counter_30 > 0) && (maxi_wready || !maxi_wvalid))) && ((counter_30 > 0) && (maxi_wready || !maxi_wvalid) && (counter_30 > 0))) begin
1611+
if(_dataflow__variable_ovalid_1 && ((_maxi_write_fsm == 3) && (_maxi_write_op_sel == 1) && ((counter_30 > 0) && (outstanding_wcount_0 < 6) && (maxi_wready || !maxi_wvalid))) && ((counter_30 > 0) && (outstanding_wcount_0 < 6) && (maxi_wready || !maxi_wvalid) && (counter_30 > 0))) begin
16121612
maxi_wdata <= _dataflow__variable_odata_1;
16131613
maxi_wvalid <= 1;
16141614
maxi_wlast <= 0;
16151615
maxi_wstrb <= { 4{ 1'd1 } };
16161616
counter_30 <= counter_30 - 1;
16171617
end
1618-
if(_dataflow__variable_ovalid_1 && ((_maxi_write_fsm == 3) && (_maxi_write_op_sel == 1) && ((counter_30 > 0) && (maxi_wready || !maxi_wvalid))) && ((counter_30 > 0) && (maxi_wready || !maxi_wvalid) && (counter_30 > 0)) && (counter_30 == 1)) begin
1618+
if(_dataflow__variable_ovalid_1 && ((_maxi_write_fsm == 3) && (_maxi_write_op_sel == 1) && ((counter_30 > 0) && (outstanding_wcount_0 < 6) && (maxi_wready || !maxi_wvalid))) && ((counter_30 > 0) && (outstanding_wcount_0 < 6) && (maxi_wready || !maxi_wvalid) && (counter_30 > 0)) && (counter_30 == 1)) begin
16191619
maxi_wlast <= 1;
16201620
last_31 <= 1;
16211621
end
@@ -2030,7 +2030,7 @@
20302030
th_memcpy <= th_memcpy_23;
20312031
end
20322032
th_memcpy_23: begin
2033-
if(_maxi_write_idle && (outstanding_wreq_count_0 == 0)) begin
2033+
if(_maxi_write_idle && (outstanding_wcount_0 == 0)) begin
20342034
th_memcpy <= th_memcpy_24;
20352035
end
20362036
end

‎examples/thread_embedded_verilog_ipcore/thread_embedded_verilog_ipxact.py renamed to ‎examples/thread_embedded_verilog_ipxact/thread_embedded_verilog_ipxact.py

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