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Updated test codes
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7 files changed

+769
-752
lines changed

7 files changed

+769
-752
lines changed

‎examples/thread_stream_axi_stream_fifo/test_thread_stream_axi_stream_fifo.py

+336-328
Large diffs are not rendered by default.

‎examples/thread_stream_axi_stream_fifo_ipxact/Makefile

+1
Original file line numberDiff line numberDiff line change
@@ -27,3 +27,4 @@ check:
2727
.PHONY: clean
2828
clean:
2929
rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
30+
rm -rf *_v1_0

‎examples/thread_stream_axi_stream_fifo_ipxact/test_thread_stream_axi_stream_fifo_ipxact.py

+336-328
Large diffs are not rendered by default.

‎tests/extension/thread_/axi_stream/test_thread_axi_stream.py

+24-24
Original file line numberDiff line numberDiff line change
@@ -72,13 +72,13 @@
7272
localparam _saxi_shift = 2;
7373
reg [32-1:0] _saxi_register_fsm;
7474
localparam _saxi_register_fsm_init = 0;
75-
reg [32-1:0] _tmp_0;
76-
reg _tmp_1;
77-
reg _tmp_2;
78-
reg _tmp_3;
79-
reg _tmp_4;
80-
assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
81-
assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
75+
reg [32-1:0] addr_0;
76+
reg writevalid_1;
77+
reg readvalid_2;
78+
reg prev_awvalid_3;
79+
reg prev_arvalid_4;
80+
assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_1 && !readvalid_2 && !saxi_bvalid && prev_awvalid_3);
81+
assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_2 && !writevalid_1 && prev_arvalid_4 && !prev_awvalid_3);
8282
reg [_saxi_maskwidth-1:0] _tmp_5;
8383
wire signed [32-1:0] _tmp_6;
8484
assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 :
@@ -149,11 +149,11 @@
149149
always @(posedge CLK) begin
150150
if(RST) begin
151151
saxi_bvalid <= 0;
152-
_tmp_3 <= 0;
153-
_tmp_4 <= 0;
154-
_tmp_1 <= 0;
155-
_tmp_2 <= 0;
156-
_tmp_0 <= 0;
152+
prev_awvalid_3 <= 0;
153+
prev_arvalid_4 <= 0;
154+
writevalid_1 <= 0;
155+
readvalid_2 <= 0;
156+
addr_0 <= 0;
157157
saxi_rdata <= 0;
158158
saxi_rvalid <= 0;
159159
_saxi_cond_0_1 <= 0;
@@ -175,16 +175,16 @@
175175
if(saxi_wvalid && saxi_wready) begin
176176
saxi_bvalid <= 1;
177177
end
178-
_tmp_3 <= saxi_awvalid;
179-
_tmp_4 <= saxi_arvalid;
180-
_tmp_1 <= 0;
181-
_tmp_2 <= 0;
178+
prev_awvalid_3 <= saxi_awvalid;
179+
prev_arvalid_4 <= saxi_arvalid;
180+
writevalid_1 <= 0;
181+
readvalid_2 <= 0;
182182
if(saxi_awready && saxi_awvalid && !saxi_bvalid) begin
183-
_tmp_0 <= saxi_awaddr;
184-
_tmp_1 <= 1;
183+
addr_0 <= saxi_awaddr;
184+
writevalid_1 <= 1;
185185
end else if(saxi_arready && saxi_arvalid) begin
186-
_tmp_0 <= saxi_araddr;
187-
_tmp_2 <= 1;
186+
addr_0 <= saxi_araddr;
187+
readvalid_2 <= 1;
188188
end
189189
if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin
190190
saxi_rdata <= _tmp_6;
@@ -279,13 +279,13 @@
279279
end else begin
280280
case(_saxi_register_fsm)
281281
_saxi_register_fsm_init: begin
282-
if(_tmp_2 || _tmp_1) begin
283-
_tmp_5 <= (_tmp_0 >> _saxi_shift) & _saxi_mask;
282+
if(readvalid_2 || writevalid_1) begin
283+
_tmp_5 <= (addr_0 >> _saxi_shift) & _saxi_mask;
284284
end
285-
if(_tmp_2) begin
285+
if(readvalid_2) begin
286286
_saxi_register_fsm <= _saxi_register_fsm_1;
287287
end
288-
if(_tmp_1) begin
288+
if(writevalid_1) begin
289289
_saxi_register_fsm <= _saxi_register_fsm_3;
290290
end
291291
end

‎tests/extension/thread_/stream_axi_stream/test_thread_stream_axi_stream.py

+24-24
Original file line numberDiff line numberDiff line change
@@ -83,13 +83,13 @@
8383
localparam _saxi_shift = 2;
8484
reg [32-1:0] _saxi_register_fsm;
8585
localparam _saxi_register_fsm_init = 0;
86-
reg [32-1:0] _tmp_0;
87-
reg _tmp_1;
88-
reg _tmp_2;
89-
reg _tmp_3;
90-
reg _tmp_4;
91-
assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
92-
assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
86+
reg [32-1:0] addr_0;
87+
reg writevalid_1;
88+
reg readvalid_2;
89+
reg prev_awvalid_3;
90+
reg prev_arvalid_4;
91+
assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_1 && !readvalid_2 && !saxi_bvalid && prev_awvalid_3);
92+
assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_2 && !writevalid_1 && prev_arvalid_4 && !prev_awvalid_3);
9393
reg [_saxi_maskwidth-1:0] _tmp_5;
9494
wire signed [32-1:0] _tmp_6;
9595
assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 :
@@ -582,11 +582,11 @@
582582
always @(posedge CLK) begin
583583
if(RST) begin
584584
saxi_bvalid <= 0;
585-
_tmp_3 <= 0;
586-
_tmp_4 <= 0;
587-
_tmp_1 <= 0;
588-
_tmp_2 <= 0;
589-
_tmp_0 <= 0;
585+
prev_awvalid_3 <= 0;
586+
prev_arvalid_4 <= 0;
587+
writevalid_1 <= 0;
588+
readvalid_2 <= 0;
589+
addr_0 <= 0;
590590
saxi_rdata <= 0;
591591
saxi_rvalid <= 0;
592592
_saxi_cond_0_1 <= 0;
@@ -608,16 +608,16 @@
608608
if(saxi_wvalid && saxi_wready) begin
609609
saxi_bvalid <= 1;
610610
end
611-
_tmp_3 <= saxi_awvalid;
612-
_tmp_4 <= saxi_arvalid;
613-
_tmp_1 <= 0;
614-
_tmp_2 <= 0;
611+
prev_awvalid_3 <= saxi_awvalid;
612+
prev_arvalid_4 <= saxi_arvalid;
613+
writevalid_1 <= 0;
614+
readvalid_2 <= 0;
615615
if(saxi_awready && saxi_awvalid && !saxi_bvalid) begin
616-
_tmp_0 <= saxi_awaddr;
617-
_tmp_1 <= 1;
616+
addr_0 <= saxi_awaddr;
617+
writevalid_1 <= 1;
618618
end else if(saxi_arready && saxi_arvalid) begin
619-
_tmp_0 <= saxi_araddr;
620-
_tmp_2 <= 1;
619+
addr_0 <= saxi_araddr;
620+
readvalid_2 <= 1;
621621
end
622622
if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin
623623
saxi_rdata <= _tmp_6;
@@ -712,13 +712,13 @@
712712
end else begin
713713
case(_saxi_register_fsm)
714714
_saxi_register_fsm_init: begin
715-
if(_tmp_2 || _tmp_1) begin
716-
_tmp_5 <= (_tmp_0 >> _saxi_shift) & _saxi_mask;
715+
if(readvalid_2 || writevalid_1) begin
716+
_tmp_5 <= (addr_0 >> _saxi_shift) & _saxi_mask;
717717
end
718-
if(_tmp_2) begin
718+
if(readvalid_2) begin
719719
_saxi_register_fsm <= _saxi_register_fsm_1;
720720
end
721-
if(_tmp_1) begin
721+
if(writevalid_1) begin
722722
_saxi_register_fsm <= _saxi_register_fsm_3;
723723
end
724724
end

‎tests/extension/thread_/stream_axi_stream_async/test_thread_stream_axi_stream_async.py

+24-24
Original file line numberDiff line numberDiff line change
@@ -83,13 +83,13 @@
8383
localparam _saxi_shift = 2;
8484
reg [32-1:0] _saxi_register_fsm;
8585
localparam _saxi_register_fsm_init = 0;
86-
reg [32-1:0] _tmp_0;
87-
reg _tmp_1;
88-
reg _tmp_2;
89-
reg _tmp_3;
90-
reg _tmp_4;
91-
assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
92-
assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
86+
reg [32-1:0] addr_0;
87+
reg writevalid_1;
88+
reg readvalid_2;
89+
reg prev_awvalid_3;
90+
reg prev_arvalid_4;
91+
assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_1 && !readvalid_2 && !saxi_bvalid && prev_awvalid_3);
92+
assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_2 && !writevalid_1 && prev_arvalid_4 && !prev_awvalid_3);
9393
reg [_saxi_maskwidth-1:0] _tmp_5;
9494
wire signed [32-1:0] _tmp_6;
9595
assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 :
@@ -582,11 +582,11 @@
582582
always @(posedge CLK) begin
583583
if(RST) begin
584584
saxi_bvalid <= 0;
585-
_tmp_3 <= 0;
586-
_tmp_4 <= 0;
587-
_tmp_1 <= 0;
588-
_tmp_2 <= 0;
589-
_tmp_0 <= 0;
585+
prev_awvalid_3 <= 0;
586+
prev_arvalid_4 <= 0;
587+
writevalid_1 <= 0;
588+
readvalid_2 <= 0;
589+
addr_0 <= 0;
590590
saxi_rdata <= 0;
591591
saxi_rvalid <= 0;
592592
_saxi_cond_0_1 <= 0;
@@ -608,16 +608,16 @@
608608
if(saxi_wvalid && saxi_wready) begin
609609
saxi_bvalid <= 1;
610610
end
611-
_tmp_3 <= saxi_awvalid;
612-
_tmp_4 <= saxi_arvalid;
613-
_tmp_1 <= 0;
614-
_tmp_2 <= 0;
611+
prev_awvalid_3 <= saxi_awvalid;
612+
prev_arvalid_4 <= saxi_arvalid;
613+
writevalid_1 <= 0;
614+
readvalid_2 <= 0;
615615
if(saxi_awready && saxi_awvalid && !saxi_bvalid) begin
616-
_tmp_0 <= saxi_awaddr;
617-
_tmp_1 <= 1;
616+
addr_0 <= saxi_awaddr;
617+
writevalid_1 <= 1;
618618
end else if(saxi_arready && saxi_arvalid) begin
619-
_tmp_0 <= saxi_araddr;
620-
_tmp_2 <= 1;
619+
addr_0 <= saxi_araddr;
620+
readvalid_2 <= 1;
621621
end
622622
if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin
623623
saxi_rdata <= _tmp_6;
@@ -712,13 +712,13 @@
712712
end else begin
713713
case(_saxi_register_fsm)
714714
_saxi_register_fsm_init: begin
715-
if(_tmp_2 || _tmp_1) begin
716-
_tmp_5 <= (_tmp_0 >> _saxi_shift) & _saxi_mask;
715+
if(readvalid_2 || writevalid_1) begin
716+
_tmp_5 <= (addr_0 >> _saxi_shift) & _saxi_mask;
717717
end
718-
if(_tmp_2) begin
718+
if(readvalid_2) begin
719719
_saxi_register_fsm <= _saxi_register_fsm_1;
720720
end
721-
if(_tmp_1) begin
721+
if(writevalid_1) begin
722722
_saxi_register_fsm <= _saxi_register_fsm_3;
723723
end
724724
end

‎tests/extension/thread_/stream_ram_external_ports/test_thread_stream_ram_external_ports.py

+24-24
Original file line numberDiff line numberDiff line change
@@ -134,13 +134,13 @@
134134
localparam _saxi_shift = 2;
135135
reg [32-1:0] _saxi_register_fsm;
136136
localparam _saxi_register_fsm_init = 0;
137-
reg [32-1:0] _tmp_0;
138-
reg _tmp_1;
139-
reg _tmp_2;
140-
reg _tmp_3;
141-
reg _tmp_4;
142-
assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
143-
assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
137+
reg [32-1:0] addr_0;
138+
reg writevalid_1;
139+
reg readvalid_2;
140+
reg prev_awvalid_3;
141+
reg prev_arvalid_4;
142+
assign saxi_awready = (_saxi_register_fsm == 0) && (!writevalid_1 && !readvalid_2 && !saxi_bvalid && prev_awvalid_3);
143+
assign saxi_arready = (_saxi_register_fsm == 0) && (!readvalid_2 && !writevalid_1 && prev_arvalid_4 && !prev_awvalid_3);
144144
reg [_saxi_maskwidth-1:0] _tmp_5;
145145
wire signed [32-1:0] _tmp_6;
146146
assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 :
@@ -329,11 +329,11 @@
329329
always @(posedge CLK) begin
330330
if(RST) begin
331331
saxi_bvalid <= 0;
332-
_tmp_3 <= 0;
333-
_tmp_4 <= 0;
334-
_tmp_1 <= 0;
335-
_tmp_2 <= 0;
336-
_tmp_0 <= 0;
332+
prev_awvalid_3 <= 0;
333+
prev_arvalid_4 <= 0;
334+
writevalid_1 <= 0;
335+
readvalid_2 <= 0;
336+
addr_0 <= 0;
337337
saxi_rdata <= 0;
338338
saxi_rvalid <= 0;
339339
_saxi_cond_0_1 <= 0;
@@ -355,16 +355,16 @@
355355
if(saxi_wvalid && saxi_wready) begin
356356
saxi_bvalid <= 1;
357357
end
358-
_tmp_3 <= saxi_awvalid;
359-
_tmp_4 <= saxi_arvalid;
360-
_tmp_1 <= 0;
361-
_tmp_2 <= 0;
358+
prev_awvalid_3 <= saxi_awvalid;
359+
prev_arvalid_4 <= saxi_arvalid;
360+
writevalid_1 <= 0;
361+
readvalid_2 <= 0;
362362
if(saxi_awready && saxi_awvalid && !saxi_bvalid) begin
363-
_tmp_0 <= saxi_awaddr;
364-
_tmp_1 <= 1;
363+
addr_0 <= saxi_awaddr;
364+
writevalid_1 <= 1;
365365
end else if(saxi_arready && saxi_arvalid) begin
366-
_tmp_0 <= saxi_araddr;
367-
_tmp_2 <= 1;
366+
addr_0 <= saxi_araddr;
367+
readvalid_2 <= 1;
368368
end
369369
if((_saxi_register_fsm == 1) && (saxi_rready || !saxi_rvalid)) begin
370370
saxi_rdata <= _tmp_6;
@@ -459,13 +459,13 @@
459459
end else begin
460460
case(_saxi_register_fsm)
461461
_saxi_register_fsm_init: begin
462-
if(_tmp_2 || _tmp_1) begin
463-
_tmp_5 <= (_tmp_0 >> _saxi_shift) & _saxi_mask;
462+
if(readvalid_2 || writevalid_1) begin
463+
_tmp_5 <= (addr_0 >> _saxi_shift) & _saxi_mask;
464464
end
465-
if(_tmp_2) begin
465+
if(readvalid_2) begin
466466
_saxi_register_fsm <= _saxi_register_fsm_1;
467467
end
468-
if(_tmp_1) begin
468+
if(writevalid_1) begin
469469
_saxi_register_fsm <= _saxi_register_fsm_3;
470470
end
471471
end

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