1.4.1

Update

• In Stream, the dump condition of source RAM is updated.

Test environment

Mac OSX 10.14

• Python 3.7.1
• Icarus Verilog 10.2
• Pyverilog 1.1.2
• IPgen 1.0.0

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.2
• IPgen 1.0.0

1.4.0

Update

• Some bugs of Fixed Point operations in Stream are fixed.
• Dump mode of Stream is enhanced for RAM read/write.

Test environment

Mac OSX 10.14

• Python 3.7.1
• Icarus Verilog 10.2
• Pyverilog 1.1.2
• IPgen 1.0.0

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.2
• IPgen 1.0.0

1.3.1

Update

• A bug fix of veriloggen.core.seq.reset_visitor for None width variables.

Test environment

Mac OSX 10.14

• Python 3.7.1
• Icarus Verilog 10.2
• Pyverilog 1.1.2
• IPgen 1.0.0

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.2
• IPgen 1.0.0

1.3.0

Update

• Int (veriloggen.core.vtypes) supports a raw value in str for very wide integer values.
• RAM (veriloggen.types.ram and veriloggen.thread.ram) supports initial values.
• Stream (veriloggen.stream and veriloggen.thread) supports a dump mode for debug.

Test environment

Mac OSX 10.14

• Python 3.7.1
• Icarus Verilog 10.2
• Pyverilog 1.1.2
• IPgen 1.0.0

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.2
• IPgen 1.0.0

1.2.3

Update

• veriloggen/thread/axi.py: A bug fix of the hung up bug of DMA read/write with a wider AXI data width and odd DMA size.
• README.rst: A bug fix of syntax error.

Test environment

Mac OSX 10.14

• Python 3.7.0
• Icarus Verilog 10.2
• Pyverilog 1.1.2
• IPgen 1.0.0

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.2
• IPgen 1.0.0

1.2.2

Update

• veriloggen/seq/reset_visitor.py: Additional bug fix of the visitor pattern for Cat operator.

Test environment

Mac OSX 10.14

• Python 3.7.0
• Icarus Verilog 10.2
• Pyverilog 1.1.2
• IPgen 1.0.0

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.2
• IPgen 1.0.0

1.2.1

Update

• veriloggen/seq/reset_visitor.py: Bug fix of the visitor pattern for Cat operator.
• setup.py is updated for successfully install by pip.

Test environment

Mac OSX 10.14

• Python 3.7.0
• Icarus Verilog 10.2
• Pyverilog 1.1.2
• IPgen 1.0.0

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.2
• IPgen 1.0.0

1.2.0

Update

(Breaking change)

• Method rename: types.axi.AxiMemoryModel.memory_word_length() -> types.axi.AxiMemoryModel.shape_to_memory_size()
• Some memory access methods of AxiMemoryModel, such as "set_memory()", uses the bit-level alignment instead of the word-level alignment in the previous version.

Test environment

Mac OSX 10.14

• Python 3.7.0
• Icarus Verilog 10.2
• Pyverilog 1.1.2
• IPgen 1.0.0

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.2
• IPgen 1.0.0

1.1.0

Update

• Big update of Veriloggen.Thread and Stream
• (Breaking change) No python 2.x support

Test environment

Mac OSX 10.14

• Python 3.7.0
• Icarus Verilog 10.2
• Pyverilog 1.1.2
• IPgen 1.0.0

Ubuntu 18.04.1

• Python 3.6.6
• Icarus Verilog 10.1
• Pyverilog 1.1.2
• IPgen 1.0.0

1.0.5

Update

• More general operator name aliases, such as Add, Sub, Mul, and Div, are added.

Test environment

Mac OSX 10.12.6

• Python 3.6.2
• Python 2.7.10
• Icarus Verilog 0.9.7
• Pyverilog 1.1.1
• IPgen 0.3.1

Ubuntu 16.04

• Python 3.5.2
• Python 2.7.12
• Icarus Verilog 0.9.7
• Pyverilog 1.1.1
• IPgen 0.3.1