Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Equivilance checking for gate scheduler. #83

Open
weinbe58 opened this issue Feb 12, 2025 · 1 comment
Open

Equivilance checking for gate scheduler. #83

weinbe58 opened this issue Feb 12, 2025 · 1 comment
Labels
enhancement New feature or request qasm2 issues or PR related to QASM2 support rewrite rewrite rules

Comments

@weinbe58
Copy link
Member

Currently in order to check of gates can be merged in the scheduler we need to check the equivalence of the gate parameters not including the input qubit:

def same_id_checker(ssa1: ir.SSAValue, ssa2: ir.SSAValue):
    return ssa1 is ssa2

def check_equiv_args(
    args1: Iterable[ir.SSAValue],
    args2: Iterable[ir.SSAValue],
    checker: Callable[[ir.SSAValue, ir.SSAValue], bool] = same_id_checker,
):
    try:
        return all(checker(ssa1, ssa2) for ssa1, ssa2 in zip(args1, args2, strict=True))
    except ValueError:
        return False


def can_merge(stmt1: ir.Statement, stmt2: ir.Statement):
    from bloqade.qasm2.dialects import uop, parallel

    match stmt1, stmt2:
        case (
            (parallel.UGate(), parallel.UGate())
            | (parallel.UGate(), uop.UGate())
            | (uop.UGate(), parallel.UGate())
            | (uop.UGate(), parallel.UGate())
            | (uop.UGate(), parallel.UGate())
            | (parallel.RZ(), parallel.RZ())
        ):
            return check_equiv_args(stmt1.args[1:], stmt2.args[1:])
        case (
            (parallel.CZ(), parallel.CZ())
            | (parallel.CZ, uop.CZ)
            | (uop.CZ, parallel.CZ)
        ):
            return True

Note that the current implementation misses cases where the parameters could point to constant statements that have equivilant values so this code would not be able to merge something like:

qasm2.u(q[0], 0.1, 0.2, 0.3)
qasm2.u(q[1], 0.1, 0.2, 0.3)

Because the constant values have separate SSA values.

@weinbe58 weinbe58 changed the title Equivilance checking for Gate Scheduler. Equivilance checking for gate scheduler. Feb 12, 2025
@weinbe58 weinbe58 added enhancement New feature or request qasm2 issues or PR related to QASM2 support optimization labels Feb 12, 2025
@Roger-luo
Copy link
Member

this needs GVN (global value numbering) crossref QuEraComputing/kirin#239

@Roger-luo Roger-luo added rewrite rewrite rules and removed optimization labels Feb 14, 2025
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
enhancement New feature or request qasm2 issues or PR related to QASM2 support rewrite rewrite rules
Projects
None yet
Development

No branches or pull requests

2 participants