Shortened shift_reg_4608 to 4607 to leave one CLB for constant generator.

Signed-off-by: Maciej Kurc <[email protected]>

Author: mkurc-ant

quicklogic/qlf_k4n8/tests/features/CMakeLists.txt

@@ -7,7 +7,8 @@ add_subdirectory(pcf_option)
 add_subdirectory(pcf_and_sdc_option)
 add_subdirectory(adder_columns)
 add_subdirectory(adder_max)
-add_subdirectory(shift_reg_4608)
+#add_subdirectory(shift_reg_4608) # Disabled as it doesn't fit k4n8. Need one free LUT for const0 generator
+add_subdirectory(shift_reg_4607)
 add_subdirectory(install_test)
 add_subdirectory(io_max)
 add_subdirectory(io_reg_max)

quicklogic/qlf_k4n8/tests/features/shift_reg_4607/CMakeLists.txt

@@ -0,0 +1,11 @@
+add_file_target(FILE shift_reg_4607.v SCANNER_TYPE verilog)
+
+add_fpga_target(
+  NAME shift_reg_4607_test-umc22-adder
+  TOP shift_reg_4607
+  BOARD qlf_k4n8-qlf_k4n8_umc22_slow_board
+  SOURCES shift_reg_4607.v
+  EXPLICIT_ADD_FILE_TARGET
+  )
+
+add_dependencies(all_qlf_k4n8_tests_adder    shift_reg_4607_test-umc22-adder_bit)

quicklogic/qlf_k4n8/tests/features/shift_reg_4607/shift_reg_4607.v

@@ -0,0 +1,27 @@
+//-----------------------------------------------------//
+// Design Name : Shift_reg
+// File Name   : Shift_reg_4608.v
+// Function    : Shift register
+//------------------------------------------------------//
+
+
+module shift_reg_4607 #( parameter size = 4606 ) (shift_in, clk, clr, shift_out);
+
+    // Port Declaration
+    input   shift_in;
+    input   clk;
+    input   clr;
+    output  shift_out;
+
+    reg [ size:0 ] shift; // shift register
+
+    always @ (posedge clk) begin
+        if (clr)
+            shift <= 0;
+        else
+            shift <= { shift[size-1:0] , shift_in } ;
+    end
+
+    assign shift_out = shift[size];
+
+endmodule