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Specified top-level module names for test designs
Signed-off-by: Maciej Kurc <[email protected]>
1 parent 42a5b05 commit 3ceaf4c

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14 files changed

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14 files changed

+30
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lines changed

‎quicklogic/qlf_k6n10/tests/design_flow/adder_128/CMakeLists.txt‎

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Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ set(ADDER_128 ${QL_DESIGNS_DIR}/adder_128/adder_128.v)
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add_fpga_target(
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NAME adder_128-gf12-no-adder
5+
TOP adder_128
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
67
SOURCES ${ADDER_128}
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EXPLICIT_ADD_FILE_TARGET
@@ -10,6 +11,7 @@ add_fpga_target(
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add_fpga_target(
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NAME adder_128-gf12-adder
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TOP adder_128
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${ADDER_128}
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EXPLICIT_ADD_FILE_TARGET

‎quicklogic/qlf_k6n10/tests/design_flow/adder_64/CMakeLists.txt‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ set(ADDER_64 ${QL_DESIGNS_DIR}/adder_64/adder_64.v)
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add_fpga_target(
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NAME adder_64-gf12-no-adder
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TOP adder_64
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${ADDER_64}
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EXPLICIT_ADD_FILE_TARGET
@@ -10,6 +11,7 @@ add_fpga_target(
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add_fpga_target(
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NAME adder_64-gf12-adder
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TOP adder_64
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${ADDER_64}
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EXPLICIT_ADD_FILE_TARGET

‎quicklogic/qlf_k6n10/tests/design_flow/adder_8/CMakeLists.txt‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ set(ADDER_8 ${QL_DESIGNS_DIR}/adder_8/adder_8.v)
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add_fpga_target(
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NAME adder_8-gf12-no-adder
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TOP adder_8
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${ADDER_8}
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EXPLICIT_ADD_FILE_TARGET
@@ -10,6 +11,7 @@ add_fpga_target(
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add_fpga_target(
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NAME adder_8-gf12-adder
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TOP adder_8
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${ADDER_8}
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EXPLICIT_ADD_FILE_TARGET

‎quicklogic/qlf_k6n10/tests/design_flow/and2/CMakeLists.txt‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ set(AND2 ${QL_DESIGNS_DIR}/and2/and2.v)
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add_fpga_target(
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NAME and2-gf12-no-adder
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TOP and2
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${AND2}
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EXPLICIT_ADD_FILE_TARGET
@@ -10,6 +11,7 @@ add_fpga_target(
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add_fpga_target(
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NAME and2-gf12-adder
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TOP and2
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${AND2}
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EXPLICIT_ADD_FILE_TARGET

‎quicklogic/qlf_k6n10/tests/design_flow/and2_latch/CMakeLists.txt‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ set(AND2_LATCH ${QL_DESIGNS_DIR}/and2_latch/and2_latch.v)
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add_fpga_target(
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NAME and2_latch-gf12-no-adder
5+
TOP and2_latch
56
BOARD qlf_k6n10-qlf_k6n10_gf12_board
67
SOURCES ${AND2_LATCH}
78
EXPLICIT_ADD_FILE_TARGET
@@ -10,6 +11,7 @@ add_fpga_target(
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add_fpga_target(
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NAME and2_latch-gf12-adder
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TOP and2_latch
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${AND2_LATCH}
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EXPLICIT_ADD_FILE_TARGET

‎quicklogic/qlf_k6n10/tests/design_flow/bin2bcd/CMakeLists.txt‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ set(BIN2BCD ${QL_DESIGNS_DIR}/bin2bcd/bin2bcd.v)
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add_fpga_target(
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NAME bin2bcd-gf12-no-adder
5+
TOP bin2bcd
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${BIN2BCD}
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EXPLICIT_ADD_FILE_TARGET
@@ -10,6 +11,7 @@ add_fpga_target(
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add_fpga_target(
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NAME bin2bcd-gf12-adder
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TOP bin2bcd
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${BIN2BCD}
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EXPLICIT_ADD_FILE_TARGET

‎quicklogic/qlf_k6n10/tests/design_flow/bram/CMakeLists.txt‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@ add_file_target(FILE ${BRAM} SCANNER_TYPE verilog)
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add_fpga_target(
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NAME bram-gf12-mode0
9+
TOP BRAM_32x512
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${BRAM}
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EXPLICIT_ADD_FILE_TARGET
@@ -14,6 +15,7 @@ add_fpga_target(
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add_fpga_target(
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NAME bram-gf12-mode1
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TOP BRAM_16x1024
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${BRAM}
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EXPLICIT_ADD_FILE_TARGET
@@ -24,6 +26,7 @@ add_fpga_target(
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add_fpga_target(
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NAME bram-gf12-mode2
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TOP BRAM_8x2048
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${BRAM}
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EXPLICIT_ADD_FILE_TARGET
@@ -32,6 +35,7 @@ add_fpga_target(
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add_fpga_target(
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NAME bram-gf12-mode3
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TOP BRAM_4x4096
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${BRAM}
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EXPLICIT_ADD_FILE_TARGET

‎quicklogic/qlf_k6n10/tests/design_flow/counter/CMakeLists.txt‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@ add_file_target(FILE ${COUNTER} SCANNER_TYPE verilog)
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add_fpga_target(
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NAME counter-gf12-no-adder
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TOP top
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
78
SOURCES ${COUNTER}
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EXPLICIT_ADD_FILE_TARGET
@@ -11,6 +12,7 @@ add_fpga_target(
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add_fpga_target(
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NAME counter-gf12-adder
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TOP top
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${COUNTER}
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EXPLICIT_ADD_FILE_TARGET

‎quicklogic/qlf_k6n10/tests/design_flow/mac_16/CMakeLists.txt‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,13 +4,15 @@ add_file_target(FILE ${MAC_16} SCANNER_TYPE verilog)
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add_fpga_target(
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NAME mac_16-gf12-dsp
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TOP mac_16
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${MAC_16}
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EXPLICIT_ADD_FILE_TARGET
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)
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add_fpga_target(
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NAME mac_16-gf12-adder
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TOP mac_16
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${MAC_16}
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EXPLICIT_ADD_FILE_TARGET

‎quicklogic/qlf_k6n10/tests/design_flow/multiplier_8bit/CMakeLists.txt‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ set(MULTIPLIER_8BIT ${QL_DESIGNS_DIR}/multiplier_8bit/multiplier_8bit.v)
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add_fpga_target(
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NAME multiplier_8bit-gf12-no-adder
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TOP multiplier_8bit
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${MULTIPLIER_8BIT}
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EXPLICIT_ADD_FILE_TARGET
@@ -10,6 +11,7 @@ add_fpga_target(
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add_fpga_target(
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NAME multiplier_8bit-gf12-adder
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TOP multiplier_8bit
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BOARD qlf_k6n10-qlf_k6n10_gf12_board
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SOURCES ${MULTIPLIER_8BIT}
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EXPLICIT_ADD_FILE_TARGET

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