Add crc16 module

Author: RDSik

modules/crc/Manifest.py

@@ -1,3 +1,3 @@
 files = [
-    "crc12.v",
+    "crc16.v",
 ]

modules/crc/crc12.v

@@ -0,0 +1,48 @@
+// Description : x^16 + x^12 + x^5 + 1
+// Algorithm   : CRC-16-CCIT
+// Polynomial  : 0x1021
+// Init value  : 0xFFFF
+
+module crc16 #(
+    parameter DATA_WIDHT = 8,
+    parameter CRC_WIDTH  = 16
+) (
+    input  wire                  clk,
+    input  wire                  arstn,
+    input  wire                  en,
+    input  wire [DATA_WIDHT-1:0] data,
+    output reg  [CRC_WIDTH-1:0 ] crc16
+);
+  
+    always @(posedge clk or negedge arstn) begin
+        if (~arstn) begin
+            crc16 <= 16'hffff;
+        end else begin
+            crc16 <= en ? crc16_byte(crc16, data) : crc16;
+        end
+    end
+
+    function [CRC_WIDTH-1:0] crc16_bit;
+        input [CRC_WIDTH-1:0] crc;
+        input                 data;
+        begin
+            crc16_bit     = crc << 1;
+            crc16_bit[0]  = crc[15] ^ data;
+            crc16_bit[5]  = crc[15] ^ data ^ crc[4];
+            crc16_bit[12] = crc[15] ^ data ^ crc[11];
+        end
+    endfunction
+
+    function [CRC_WIDTH-1:0] crc16_byte;
+        input [CRC_WIDTH-1:0 ] crc;
+        input [DATA_WIDHT-1:0] data;
+        integer                i;
+        begin
+            crc16_byte = crc;
+            for (i = DATA_WIDHT - 1; i >= 0; i = i - 1) begin
+                crc16_byte = crc16_bit(crc16_byte, data[i]);
+            end
+        end
+    endfunction
+
+endmodule

modules/crc/crc16.v

@@ -1,6 +1,6 @@
 `timescale 1ps / 1ps
 
-module crc12_tb();
+module crc16_tb();
 
 localparam CLK_PERIOD = 2;
 localparam SIM_TIME   = 100;
@@ -10,14 +10,14 @@ reg       arstn;
 reg       en;
 reg [7:0] data;
 
-wire [11:0] crc12;
+wire [15:0] crc16;
 
-crc12 dut(
+crc16 dut(
     .clk    (clk  ),
     .arstn  (arstn),
     .en     (en   ),
     .data   (data ),
-    .crc12  (crc12)
+    .crc16  (crc16)
 );
 
 task rst();
@@ -34,7 +34,6 @@ endtask
 
 task data_gen();
     begin
-        rst();
         repeat (5) begin
             en = 1;
             data = $urandom_range(0, 256);
@@ -53,13 +52,14 @@ initial begin
 end
 
 initial begin
+    rst();
     data_gen();
 end
 
 initial begin
-    $dumpfile("crc12_tb.vcd");
-    $dumpvars(0, crc12_tb);
-    $monitor("time=%g, crc=0x%h", $time, crc12);
+    $dumpfile("crc16_tb.vcd");
+    $dumpvars(0, crc16_tb);
+    $monitor("time=%g, crc=0x%h", $time, crc16);
 end
 
 initial begin