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RobbbertRobbbert
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Merge remote-tracking branch 'upstream/master'
# Conflicts: # src/mame/netronics/elf.cpp
2 parents e38f3cd + 8cfc62f commit 78d24b4

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‎.github/workflows/ci-linux.yml

+1-1
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ jobs:
4848
- name: Install dependencies
4949
run: |
5050
sudo apt-get update
51-
sudo apt-get install -y libsdl2-dev libsdl2-ttf-dev libasound2-dev libxinerama-dev libxi-dev qtbase5-dev qtbase5-dev-tools
51+
sudo apt-get install -y libsdl2-dev libsdl2-ttf-dev libfontconfig-dev libasound2-dev libxinerama-dev libxi-dev qtbase5-dev qtbase5-dev-tools
5252
- name: Install clang
5353
if: matrix.compiler == 'clang'
5454
run: sudo apt-get install -y clang

‎3rdparty/asmjit/CMakeLists.txt

+13-43
Original file line numberDiff line numberDiff line change
@@ -1,38 +1,16 @@
1-
cmake_minimum_required(VERSION 3.8 FATAL_ERROR)
1+
cmake_minimum_required(VERSION 3.19 FATAL_ERROR)
22

3-
cmake_policy(PUSH)
4-
5-
if (POLICY CMP0063)
6-
cmake_policy(SET CMP0063 NEW) # Honor visibility properties.
7-
endif()
8-
9-
if (POLICY CMP0092)
10-
cmake_policy(SET CMP0092 NEW) # Don't add -W3 warning level by default.
11-
endif()
12-
13-
# Don't create a project if it was already created by another CMakeLists.txt.
14-
# This allows one library to embed another library without making a collision.
3+
# Don't create a project if it was already created by another CMakeLists.txt. This makes
4+
# it possible to support both add_subdirectory() and include() ways of using AsmJit as a
5+
# dependency.
156
if (NOT CMAKE_PROJECT_NAME OR "${CMAKE_PROJECT_NAME}" STREQUAL "asmjit")
167
project(asmjit CXX)
178
endif()
189

1910
include(CheckCXXCompilerFlag)
20-
INCLUDE(CheckCXXSourceCompiles)
11+
include(CheckCXXSourceCompiles)
2112
include(GNUInstallDirs)
2213

23-
# AsmJit - Deprecated
24-
# ===================
25-
26-
if (DEFINED ASMJIT_BUILD_EMBED)
27-
message(DEPRECATION "ASMJIT_BUILD_EMBED is deprecated, use ASMJIT_EMBED")
28-
set(ASMJIT_EMBED "${ASMJIT_BUILD_EMBED}")
29-
endif()
30-
31-
if (DEFINED ASMJIT_BUILD_STATIC)
32-
message(DEPRECATION "ASMJIT_BUILD_STATIC is deprecated, use ASMJIT_STATIC")
33-
set(ASMJIT_STATIC "${ASMJIT_BUILD_STATIC}")
34-
endif()
35-
3614
# AsmJit - Configuration - Build
3715
# ==============================
3816

@@ -212,18 +190,14 @@ function(asmjit_add_target target target_type)
212190
add_library(${target} ${target_type} ${X_SOURCES})
213191
endif()
214192

215-
set_target_properties(${target} PROPERTIES DEFINE_SYMBOL "")
216-
target_link_libraries(${target} PRIVATE ${X_LIBRARIES})
217-
218-
# target_link_options was added in cmake v3.13, don't use it for now...
219-
foreach(link_flag ${ASMJIT_PRIVATE_LFLAGS})
220-
set_property(TARGET ${target} APPEND_STRING PROPERTY LINK_FLAGS " ${link_flag}")
221-
endforeach()
222-
223-
target_compile_features(${target} PUBLIC cxx_std_11)
224-
set_property(TARGET ${target} PROPERTY CXX_EXTENSIONS NO)
225-
set_property(TARGET ${target} PROPERTY CXX_VISIBILITY_PRESET hidden)
193+
set_target_properties(${target}
194+
PROPERTIES
195+
DEFINE_SYMBOL ""
196+
CXX_VISIBILITY_PRESET hidden)
226197
target_compile_options(${target} PRIVATE ${X_CFLAGS} ${ASMJIT_SANITIZE_CFLAGS} $<$<CONFIG:Debug>:${X_CFLAGS_DBG}> $<$<NOT:$<CONFIG:Debug>>:${X_CFLAGS_REL}>)
198+
target_compile_features(${target} PUBLIC cxx_std_11)
199+
target_link_options(${target} PRIVATE ${ASMJIT_PRIVATE_LFLAGS})
200+
target_link_libraries(${target} PRIVATE ${X_LIBRARIES})
227201

228202
if ("${target_type}" STREQUAL "TEST")
229203
add_test(NAME ${target} COMMAND ${target})
@@ -590,10 +564,8 @@ if (NOT ASMJIT_EMBED)
590564
$<BUILD_INTERFACE:${ASMJIT_INCLUDE_DIRS}>
591565
$<INSTALL_INTERFACE:${CMAKE_INSTALL_INCLUDEDIR}>)
592566

593-
# Add blend2d::blend2d alias.
567+
# Create an asmjit::asmjit alias.
594568
add_library(asmjit::asmjit ALIAS asmjit)
595-
# TODO: [CMAKE] Deprecated alias - we use projectname::libraryname convention now.
596-
add_library(AsmJit::AsmJit ALIAS asmjit)
597569

598570
# Add AsmJit install instructions (library and public headers).
599571
if (NOT ASMJIT_NO_INSTALL)
@@ -713,5 +685,3 @@ if (NOT ASMJIT_EMBED)
713685

714686
endif()
715687
endif()
716-
717-
cmake_policy(POP)

‎3rdparty/asmjit/src/asmjit/arm/a64assembler.cpp

+46-12
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,21 @@ static constexpr uint32_t kWX = InstDB::kWX;
5353
static const uint8_t armShiftOpToLdStOptMap[] = { ASMJIT_LOOKUP_TABLE_16(VALUE, 0) };
5454
#undef VALUE
5555

56+
// a64::Assembler - ExtendOpToRegType
57+
// ==================================
58+
59+
static inline RegType extendOptionToRegType(uint32_t option) noexcept {
60+
uint32_t pred = (uint32_t(RegType::kARM_GpW) << (0x0 * 4)) | // 0b000 - UXTB.
61+
(uint32_t(RegType::kARM_GpW) << (0x1 * 4)) | // 0b001 - UXTH.
62+
(uint32_t(RegType::kARM_GpW) << (0x2 * 4)) | // 0b010 - UXTW.
63+
(uint32_t(RegType::kARM_GpX) << (0x3 * 4)) | // 0b011 - UXTX|LSL.
64+
(uint32_t(RegType::kARM_GpW) << (0x4 * 4)) | // 0b100 - SXTB.
65+
(uint32_t(RegType::kARM_GpW) << (0x5 * 4)) | // 0b101 - SXTH.
66+
(uint32_t(RegType::kARM_GpW) << (0x6 * 4)) | // 0b110 - SXTW.
67+
(uint32_t(RegType::kARM_GpX) << (0x7 * 4)) ; // 0b111 - SXTX.
68+
return RegType((pred >> (option * 4u)) & 0xFu);
69+
}
70+
5671
// asmjit::a64::Assembler - SizeOp
5772
// ===============================
5873

@@ -1228,9 +1243,6 @@ Error Assembler::_emit(InstId instId, const Operand_& o0, const Operand_& o1, co
12281243
}
12291244

12301245
if (isign4 == ENC_OPS3(Reg, Reg, Reg) || isign4 == ENC_OPS4(Reg, Reg, Reg, Imm)) {
1231-
if (!checkSignature(o1, o2))
1232-
goto InvalidInstruction;
1233-
12341246
uint32_t opSize = x ? 64 : 32;
12351247
uint64_t shift = 0;
12361248
uint32_t sType = uint32_t(ShiftOp::kLSL);
@@ -1247,11 +1259,17 @@ Error Assembler::_emit(InstId instId, const Operand_& o0, const Operand_& o1, co
12471259
if (sType <= uint32_t(ShiftOp::kASR)) {
12481260
bool hasSP = o0.as<Gp>().isSP() || o1.as<Gp>().isSP();
12491261
if (!hasSP) {
1250-
if (!checkGpId(o0, o1, kZR))
1262+
if (!checkSignature(o1, o2)) {
1263+
goto InvalidInstruction;
1264+
}
1265+
1266+
if (!checkGpId(o0, o1, kZR)) {
12511267
goto InvalidPhysId;
1268+
}
12521269

1253-
if (shift >= opSize)
1270+
if (shift >= opSize) {
12541271
goto InvalidImmediate;
1272+
}
12551273

12561274
opcode.reset(uint32_t(opData.shiftedOp) << 21);
12571275
opcode.addImm(x, 31);
@@ -1264,17 +1282,20 @@ Error Assembler::_emit(InstId instId, const Operand_& o0, const Operand_& o1, co
12641282
}
12651283

12661284
// SP register can only be used with LSL or Extend.
1267-
if (sType != uint32_t(ShiftOp::kLSL))
1285+
if (sType != uint32_t(ShiftOp::kLSL)) {
12681286
goto InvalidImmediate;
1287+
}
1288+
12691289
sType = x ? uint32_t(ShiftOp::kUXTX) : uint32_t(ShiftOp::kUXTW);
12701290
}
12711291

12721292
// Extend operation - UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX.
12731293
opcode.reset(uint32_t(opData.extendedOp) << 21);
12741294
sType -= uint32_t(ShiftOp::kUXTB);
12751295

1276-
if (sType > 7 || shift > 4)
1296+
if (sType > 7 || shift > 4) {
12771297
goto InvalidImmediate;
1298+
}
12781299

12791300
if (!(opcode.get() & B(29))) {
12801301
// ADD|SUB (extend) - ZR is not allowed.
@@ -1287,6 +1308,11 @@ Error Assembler::_emit(InstId instId, const Operand_& o0, const Operand_& o1, co
12871308
goto InvalidPhysId;
12881309
}
12891310

1311+
// Validate whether the register operands match extend option.
1312+
if (o2.as<Reg>().type() != extendOptionToRegType(sType) || o1.as<Reg>().type() < o2.as<Reg>().type()) {
1313+
goto InvalidInstruction;
1314+
}
1315+
12901316
opcode.addImm(x, 31);
12911317
opcode.addReg(o2, 16);
12921318
opcode.addImm(sType, 13);
@@ -1412,9 +1438,6 @@ Error Assembler::_emit(InstId instId, const Operand_& o0, const Operand_& o1, co
14121438
}
14131439

14141440
if (isign4 == ENC_OPS2(Reg, Reg) || isign4 == ENC_OPS3(Reg, Reg, Imm)) {
1415-
if (!checkSignature(o0, o1))
1416-
goto InvalidInstruction;
1417-
14181441
uint32_t opSize = x ? 64 : 32;
14191442
uint32_t sType = 0;
14201443
uint64_t shift = 0;
@@ -1429,8 +1452,13 @@ Error Assembler::_emit(InstId instId, const Operand_& o0, const Operand_& o1, co
14291452
// Shift operation - LSL, LSR, ASR.
14301453
if (sType <= uint32_t(ShiftOp::kASR)) {
14311454
if (!hasSP) {
1432-
if (shift >= opSize)
1455+
if (!checkSignature(o0, o1)) {
1456+
goto InvalidInstruction;
1457+
}
1458+
1459+
if (shift >= opSize) {
14331460
goto InvalidImmediate;
1461+
}
14341462

14351463
opcode.reset(uint32_t(opData.shiftedOp) << 21);
14361464
opcode.addImm(x, 31);
@@ -1451,8 +1479,14 @@ Error Assembler::_emit(InstId instId, const Operand_& o0, const Operand_& o1, co
14511479

14521480
// Extend operation - UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX.
14531481
sType -= uint32_t(ShiftOp::kUXTB);
1454-
if (sType > 7 || shift > 4)
1482+
if (sType > 7 || shift > 4) {
14551483
goto InvalidImmediate;
1484+
}
1485+
1486+
// Validate whether the register operands match extend option.
1487+
if (o1.as<Reg>().type() != extendOptionToRegType(sType) || o0.as<Reg>().type() < o1.as<Reg>().type()) {
1488+
goto InvalidInstruction;
1489+
}
14561490

14571491
opcode.reset(uint32_t(opData.extendedOp) << 21);
14581492
opcode.addImm(x, 31);

‎3rdparty/asmjit/src/asmjit/arm/a64emitter.h

+11
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,17 @@ struct EmitterExplicitT {
8484

8585
//! \endcond
8686

87+
88+
//! \name Native Registers
89+
//! \{
90+
91+
//! Returns either 32-bit or 64-bit GP register of the given `id` depending on the emitter's architecture.
92+
inline Gp gpz(uint32_t id) const noexcept { return Gp(_emitter()->_gpSignature, id); }
93+
//! Clones the given `reg` to either 32-bit or 64-bit GP register depending on the emitter's architecture.
94+
inline Gp gpz(const Gp& reg) const noexcept { return Gp(_emitter()->_gpSignature, reg.id()); }
95+
96+
//! \}
97+
8798
//! \name General Purpose Instructions
8899
//! \{
89100

‎3rdparty/asmjit/src/asmjit/arm/a64func.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ ASMJIT_BEGIN_SUB_NAMESPACE(a64)
1313

1414
namespace FuncInternal {
1515

16-
static inline bool shouldThreatAsCDecl(CallConvId ccId) noexcept {
16+
static inline bool shouldTreatAsCDecl(CallConvId ccId) noexcept {
1717
return ccId == CallConvId::kCDecl ||
1818
ccId == CallConvId::kStdCall ||
1919
ccId == CallConvId::kFastCall ||
@@ -53,7 +53,7 @@ ASMJIT_FAVOR_SIZE Error initCallConv(CallConv& cc, CallConvId ccId, const Enviro
5353
cc.setPassedOrder(RegGroup::kVec, 0, 1, 2, 3, 4, 5, 6, 7);
5454
cc.setNaturalStackAlignment(16);
5555

56-
if (shouldThreatAsCDecl(ccId)) {
56+
if (shouldTreatAsCDecl(ccId)) {
5757
// ARM doesn't have that many calling conventions as we can find in X86 world, treat most conventions as __cdecl.
5858
cc.setId(CallConvId::kCDecl);
5959
cc.setPreservedRegs(RegGroup::kGp, Support::bitMask(Gp::kIdOs, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30));

‎3rdparty/asmjit/src/asmjit/arm/a64globals.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ ASMJIT_BEGIN_SUB_NAMESPACE(a64)
2121
//! AArch64 instruction.
2222
//!
2323
//! \note Only used to hold ARM-specific enumerations and static functions.
24-
struct Inst {
24+
namespace Inst {
2525
//! Instruction id.
2626
enum Id : uint32_t {
2727
// ${InstId:Begin}

‎3rdparty/asmjit/src/asmjit/arm/a64instapi.cpp

+7-2
Original file line numberDiff line numberDiff line change
@@ -137,11 +137,13 @@ Error queryRWInfo(const BaseInst& inst, const Operand_* operands, size_t opCount
137137

138138
if (memOp.hasBase()) {
139139
op.addOpFlags(OpRWFlags::kMemBaseRead);
140+
if ((memOp.hasIndex() || memOp.hasOffset()) && memOp.isPreOrPost()) {
141+
op.addOpFlags(OpRWFlags::kMemBaseWrite);
142+
}
140143
}
141144

142145
if (memOp.hasIndex()) {
143146
op.addOpFlags(OpRWFlags::kMemIndexRead);
144-
op.addOpFlags(memOp.isPreOrPost() ? OpRWFlags::kMemIndexWrite : OpRWFlags::kNone);
145147
}
146148
}
147149
}
@@ -191,10 +193,13 @@ Error queryRWInfo(const BaseInst& inst, const Operand_* operands, size_t opCount
191193

192194
if (memOp.hasBase()) {
193195
op.addOpFlags(OpRWFlags::kMemBaseRead);
196+
if ((memOp.hasIndex() || memOp.hasOffset()) && memOp.isPreOrPost()) {
197+
op.addOpFlags(OpRWFlags::kMemBaseWrite);
198+
}
194199
}
195200

196201
if (memOp.hasIndex()) {
197-
op.addOpFlags(memOp.isPreOrPost() ? OpRWFlags::kMemIndexRW : OpRWFlags::kMemIndexRead);
202+
op.addOpFlags(OpRWFlags::kMemIndexRead);
198203
}
199204
}
200205
}

‎3rdparty/asmjit/src/asmjit/arm/a64instdb.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -210,7 +210,7 @@ const InstInfo _instInfoTable[] = {
210210
INST(Ldlarb , BaseRM_NoImm , (0b0000100011011111011111, kW , kZR, 0 ) , kRWI_W , 0 , 8 ), // #149
211211
INST(Ldlarh , BaseRM_NoImm , (0b0100100011011111011111, kW , kZR, 0 ) , kRWI_W , 0 , 9 ), // #150
212212
INST(Ldnp , BaseLdpStp , (0b0010100001, 0 , kWX, 31, 2) , kRWI_WW , 0 , 0 ), // #151
213-
INST(Ldp , BaseLdpStp , (0b0010100101, 0b0010100011, kWX, 31, 2) , kRWI_W , 0 , 1 ), // #152
213+
INST(Ldp , BaseLdpStp , (0b0010100101, 0b0010100011, kWX, 31, 2) , kRWI_WW , 0 , 1 ), // #152
214214
INST(Ldpsw , BaseLdpStp , (0b0110100101, 0b0110100011, kX , 0 , 2) , kRWI_WW , 0 , 2 ), // #153
215215
INST(Ldr , BaseLdSt , (0b1011100101, 0b10111000010, 0b10111000011, 0b00011000, kWX, 30, 2, Inst::kIdLdur) , kRWI_W , 0 , 0 ), // #154
216216
INST(Ldraa , BaseRM_SImm10 , (0b1111100000100000000001, kX , kZR, 0, 3) , kRWI_W , 0 , 0 ), // #155

‎3rdparty/asmjit/src/asmjit/arm/a64operand.h

+39-11
Original file line numberDiff line numberDiff line change
@@ -129,17 +129,45 @@ class Vec : public BaseVec {
129129
//! Resets vector element type to none.
130130
ASMJIT_INLINE_NODEBUG void resetElementType() noexcept { _signature.setField<kSignatureRegElementTypeMask>(0); }
131131

132-
ASMJIT_INLINE_NODEBUG constexpr bool isVecB8() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementB); }
133-
ASMJIT_INLINE_NODEBUG constexpr bool isVecH4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementH); }
134-
ASMJIT_INLINE_NODEBUG constexpr bool isVecS2() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementS); }
135-
ASMJIT_INLINE_NODEBUG constexpr bool isVecD1() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecD>::kSignature); }
136-
137-
ASMJIT_INLINE_NODEBUG constexpr bool isVecB16() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementB); }
138-
ASMJIT_INLINE_NODEBUG constexpr bool isVecH8() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementH); }
139-
ASMJIT_INLINE_NODEBUG constexpr bool isVecS4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementS); }
140-
ASMJIT_INLINE_NODEBUG constexpr bool isVecD2() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementD); }
141-
ASMJIT_INLINE_NODEBUG constexpr bool isVecB4x4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementB4); }
142-
ASMJIT_INLINE_NODEBUG constexpr bool isVecH2x4() const noexcept { return _signature.subset(kBaseSignatureMask | kSignatureRegElementTypeMask) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementH2); }
132+
ASMJIT_INLINE_NODEBUG constexpr bool isVecB8() const noexcept {
133+
return _signature.subset(uint32_t(kBaseSignatureMask) | uint32_t(kSignatureRegElementTypeMask)) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementB);
134+
}
135+
136+
ASMJIT_INLINE_NODEBUG constexpr bool isVecH4() const noexcept {
137+
return _signature.subset(uint32_t(kBaseSignatureMask) | uint32_t(kSignatureRegElementTypeMask)) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementH);
138+
}
139+
140+
ASMJIT_INLINE_NODEBUG constexpr bool isVecS2() const noexcept {
141+
return _signature.subset(uint32_t(kBaseSignatureMask) | uint32_t(kSignatureRegElementTypeMask)) == (RegTraits<RegType::kARM_VecD>::kSignature | kSignatureElementS);
142+
}
143+
144+
ASMJIT_INLINE_NODEBUG constexpr bool isVecD1() const noexcept {
145+
return _signature.subset(uint32_t(kBaseSignatureMask) | uint32_t(kSignatureRegElementTypeMask)) == (RegTraits<RegType::kARM_VecD>::kSignature);
146+
}
147+
148+
ASMJIT_INLINE_NODEBUG constexpr bool isVecB16() const noexcept {
149+
return _signature.subset(uint32_t(kBaseSignatureMask) | uint32_t(kSignatureRegElementTypeMask)) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementB);
150+
}
151+
152+
ASMJIT_INLINE_NODEBUG constexpr bool isVecH8() const noexcept {
153+
return _signature.subset(uint32_t(kBaseSignatureMask) | uint32_t(kSignatureRegElementTypeMask)) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementH);
154+
}
155+
156+
ASMJIT_INLINE_NODEBUG constexpr bool isVecS4() const noexcept {
157+
return _signature.subset(uint32_t(kBaseSignatureMask) | uint32_t(kSignatureRegElementTypeMask)) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementS);
158+
}
159+
160+
ASMJIT_INLINE_NODEBUG constexpr bool isVecD2() const noexcept {
161+
return _signature.subset(uint32_t(kBaseSignatureMask) | uint32_t(kSignatureRegElementTypeMask)) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementD);
162+
}
163+
164+
ASMJIT_INLINE_NODEBUG constexpr bool isVecB4x4() const noexcept {
165+
return _signature.subset(uint32_t(kBaseSignatureMask) | uint32_t(kSignatureRegElementTypeMask)) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementB4);
166+
}
167+
168+
ASMJIT_INLINE_NODEBUG constexpr bool isVecH2x4() const noexcept {
169+
return _signature.subset(uint32_t(kBaseSignatureMask) | uint32_t(kSignatureRegElementTypeMask)) == (RegTraits<RegType::kARM_VecV>::kSignature | kSignatureElementH2);
170+
}
143171

144172
//! Creates a cloned register with element access.
145173
ASMJIT_INLINE_NODEBUG Vec at(uint32_t elementIndex) const noexcept {

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