Set port_id for Verific bus ports

Author: rocallahan

frontends/verific/verific.cc

@@ -1570,6 +1570,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		RTLIL::Wire *wire = module->addWire(RTLIL::escape_id(portbus->Name()), portbus->Size());
 		wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
 		wire->upto = portbus->IsUp();
+		wire->port_id = nl->IndexOf(portbus) + 1;
 		import_attributes(wire->attributes, portbus, nl, portbus->Size());
 		if (portbus->Size() == 1)
 			wire->set_bool_attribute(ID::single_bit_vector);