diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index a40e1f5a9..0180dfc5e 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -148,7 +148,8 @@ jobs: [ espressif/esp, gigadevice/gd32, - #microchip/avr, + hdsc/hc32l110, + #microchip/avr, microchip/atsam, nordic/nrf5x, nxp/lpc, diff --git a/build.zig b/build.zig index 32a3197c3..211d31060 100644 --- a/build.zig +++ b/build.zig @@ -21,6 +21,7 @@ const port_list: []const struct { } = &.{ .{ .name = "esp", .dep_name = "port/espressif/esp" }, .{ .name = "gd32", .dep_name = "port/gigadevice/gd32" }, + .{ .name = "hc32l110", .dep_name = "port/hdsc/hc32l110" }, .{ .name = "atsam", .dep_name = "port/microchip/atsam" }, .{ .name = "avr", .dep_name = "port/microchip/avr" }, .{ .name = "nrf5x", .dep_name = "port/nordic/nrf5x" }, diff --git a/build.zig.zon b/build.zig.zon index 6b92289c9..1ff89481a 100644 --- a/build.zig.zon +++ b/build.zig.zon @@ -24,6 +24,7 @@ // ports .@"port/espressif/esp" = .{ .path = "port/espressif/esp", .lazy = true }, .@"port/gigadevice/gd32" = .{ .path = "port/gigadevice/gd32", .lazy = true }, + .@"port/hdsc/hc32l110" = .{ .path = "port/hdsc/hc32l110", .lazy = true }, .@"port/microchip/atsam" = .{ .path = "port/microchip/atsam", .lazy = true }, .@"port/microchip/avr" = .{ .path = "port/microchip/avr", .lazy = true }, .@"port/nordic/nrf5x" = .{ .path = "port/nordic/nrf5x", .lazy = true }, diff --git a/core/src/mmio.zig b/core/src/mmio.zig index c17c9f9cb..1c7aede72 100644 --- a/core/src/mmio.zig +++ b/core/src/mmio.zig @@ -93,5 +93,21 @@ pub fn Mmio(comptime PackedT: type) type { } write(addr, val); } + + pub inline fn write_bit(addr: *volatile Self, offset: u5, value: u1) void { + if (value == 1) { + addr.raw |= 1 << offset; + } else { + addr.raw &= ~@as(IntT, 1 << offset); + } + } + + pub inline fn read_bit(addr: *volatile Self, offset: u5) u1 { + return @truncate(addr.raw >> offset); + } + + pub inline fn toggle_bit(addr: *volatile Self, offset: u5) void { + addr.raw ^= 1 << offset; + } }; } diff --git a/examples/hdsc/hc32l110/README.md b/examples/hdsc/hc32l110/README.md new file mode 100644 index 000000000..5164edfce --- /dev/null +++ b/examples/hdsc/hc32l110/README.md @@ -0,0 +1 @@ +# Examples for the BSP `hdsc-hc32l110` diff --git a/examples/hdsc/hc32l110/build.zig b/examples/hdsc/hc32l110/build.zig new file mode 100644 index 000000000..5ce4abdd5 --- /dev/null +++ b/examples/hdsc/hc32l110/build.zig @@ -0,0 +1,44 @@ +const std = @import("std"); +const microzig = @import("microzig"); + +const MicroBuild = microzig.MicroBuild(.{ + .hc32l110 = true, +}); + +pub fn build(b: *std.Build) void { + const optimize = b.standardOptimizeOption(.{}); + const maybe_example = b.option([]const u8, "example", "only build matching examples"); + + const mz_dep = b.dependency("microzig", .{}); + const mb = MicroBuild.init(b, mz_dep) orelse return; + + const rtt = b.dependency("rtt", .{}); + + const examples: []const Example = &.{ + .{ .name = "blinky", .file = "src/blinky.zig" }, + .{ .name = "crc16", .file = "src/crc16.zig" }, + .{ .name = "i2c_ssd1306", .file = "src/i2c_ssd1306.zig" }, + }; + + for (examples) |example| { + if (maybe_example) |selected_example| + if (!std.mem.containsAtLeast(u8, example.name, 1, selected_example)) + continue; + + const firmware = mb.add_firmware(.{ + .name = example.name, + .target = mb.ports.hc32l110.chips.hc32l110x6, + .optimize = optimize, + .root_source_file = b.path(example.file), + }); + firmware.add_app_import("rtt", rtt.module("rtt"), .{}); + + mb.install_firmware(firmware, .{}); + mb.install_firmware(firmware, .{ .format = .elf }); + } +} + +const Example = struct { + name: []const u8, + file: []const u8, +}; diff --git a/examples/hdsc/hc32l110/build.zig.zon b/examples/hdsc/hc32l110/build.zig.zon new file mode 100644 index 000000000..0b31377bc --- /dev/null +++ b/examples/hdsc/hc32l110/build.zig.zon @@ -0,0 +1,18 @@ +.{ + .name = .examples_hdsc_hc32l110, + .fingerprint = 0x6b64a904e57948a3, + .version = "0.0.0", + .dependencies = .{ + .microzig = .{ .path = "../../.." }, + .rtt = .{ + .url = "git+https://github.com/haydenridd/zig-rtt#b21fa1b54176e9aa5d17aefe4a7c4e0d9a89a09e", + .hash = "rtt-0.0.0-s7auv1V5AAAtPzKYj-8Kbj7dD1JPkDJBsVxrKGfnIwqj", + }, + }, + .paths = .{ + "README.md", + "build.zig", + "build.zig.zon", + "src", + }, +} diff --git a/examples/hdsc/hc32l110/src/blinky.zig b/examples/hdsc/hc32l110/src/blinky.zig new file mode 100644 index 000000000..315538c3c --- /dev/null +++ b/examples/hdsc/hc32l110/src/blinky.zig @@ -0,0 +1,20 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const hal = microzig.hal; +const time = hal.time; +const clocks = hal.clocks; +const gpio = hal.gpio; + +const led = gpio.num(3, 6); + +pub fn main() !void { + clocks.gate.enable(.Gpio); + + led.init(.out); + led.put(0); + + while (true) { + time.sleep_ms(250); + led.toggle(); + } +} diff --git a/examples/hdsc/hc32l110/src/crc16.zig b/examples/hdsc/hc32l110/src/crc16.zig new file mode 100644 index 000000000..680d79af6 --- /dev/null +++ b/examples/hdsc/hc32l110/src/crc16.zig @@ -0,0 +1,17 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const hal = microzig.hal; +const clocks = hal.clocks; +const crc16 = hal.crc16; + +pub fn main() !void { + clocks.gate.enable(.Crc); + + const value = crc16.calculate(u8, &.{ 0xDE, 0xAD, 0xBE, 0xEF }); + if (value != 0xE5CB) @panic("invalid value"); + + if (!crc16.check(u8, &.{ 0xDE, 0xAD, 0xBE, 0xEF }, 0xE5CB)) + @panic("invalid value"); + + while (true) {} +} diff --git a/examples/hdsc/hc32l110/src/i2c_ssd1306.zig b/examples/hdsc/hc32l110/src/i2c_ssd1306.zig new file mode 100644 index 000000000..e8644158f --- /dev/null +++ b/examples/hdsc/hc32l110/src/i2c_ssd1306.zig @@ -0,0 +1,56 @@ +const std = @import("std"); +const microzig = @import("microzig"); + +const hal = microzig.hal; +const time = microzig.time; +const i2c = hal.i2c; +const gpio = hal.gpio; +const clocks = hal.clocks; +const peripherals = microzig.chip.peripherals; + +const drivers = microzig.drivers; +const display = drivers.display; +const ssd1306 = display.ssd1306; + +const i2c0 = i2c.instance.num(0); + +const sda_pin = gpio.num(0, 1); +const scl_pin = gpio.num(0, 2); + +var framebuffer: drivers.display.ssd1306.Framebuffer = .init(.black); + +pub fn main() !void { + clocks.gate.enable(.Gpio); + clocks.gate.enable(.I2c); + + inline for (&.{ scl_pin, sda_pin }) |pin| { + pin.set_direction(.out); + pin.set_pull(.disabled); + pin.set_open_drain(.enabled); + pin.set_drive_strength(.normal); + pin.set_analog(.disabled); + } + // TODO: + sda_pin.set_function(2); + scl_pin.set_function(2); + + try i2c0.apply(.{ .baud = 32 }); + i2c0.enable(); + + const i2c_device = i2c0.device(.new(0x3c)); + const disp = ssd1306.init(.i2c, i2c_device, null) catch |err| + switch (err) { + error.Timeout => while (true) {}, + else => return err, + }; + + var color: display.colors.BlackWhite = .white; + + while (true) { + framebuffer.clear(color); + color = if (color == .black) .white else .black; + + try disp.write_full_display(framebuffer.bit_stream()); + hal.time.sleep_ms(100); + } +} diff --git a/port/hdsc/hc32l110/README.md b/port/hdsc/hc32l110/README.md new file mode 100644 index 000000000..fe6192aef --- /dev/null +++ b/port/hdsc/hc32l110/README.md @@ -0,0 +1,34 @@ +# hdsc-hc32l110 + +HAL and register definitions for the HC32L110 family of microcontrollers + +## Status +- [ ] adc +- [ ] adt +- [-] clocks +- [x] crc +- [ ] flash +- [x] gpio +- [-] i2c + - [x] master + - [ ] slave +- [ ] irq +- [ ] lpm - Low Power Management +- [ ] lpt - Low Power Timer +- [ ] lpuart - Low Power UART +- [ ] lvd - Lov Voltage Detector +- [ ] pca - Programmable Counter Array +- [ ] rtc +- [ ] spi + - [ ] master + - [ ] slave +- [ ] trim - Clock Trimming +- [ ] timers +- [ ] uart +- [ ] vc - Voltage Comparator +- [ ] wdt + +Legend: + - [ ] nothing implemented + - [-] partially implemented and working ish + - [x] implemented and tested on real hardware diff --git a/port/hdsc/hc32l110/build.zig b/port/hdsc/hc32l110/build.zig new file mode 100644 index 000000000..bfd03b95f --- /dev/null +++ b/port/hdsc/hc32l110/build.zig @@ -0,0 +1,86 @@ +const std = @import("std"); +const microzig = @import("microzig/build-internals"); + +const Self = @This(); + +chips: struct { + hc32l110x4: *const microzig.Target, + hc32l110x6: *const microzig.Target, +}, + +boards: struct { + // lilygo: struct { + // t_hc32: *const microzig.Target, + // }, +}, + +pub fn init(dep: *std.Build.Dependency) Self { + const b = dep.builder; + + const hal: microzig.HardwareAbstractionLayer = .{ + .root_source_file = b.path("src/hal.zig"), + }; + + const chip_hc32l110x4: microzig.Target = .{ + .dep = dep, + .preferred_binary_format = .{ .bin = {} }, + .zig_target = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .chip = .{ + .name = "HDSC_HC32L110", + .register_definition = .{ .svd = b.path("src/chips/HC32L110.svd") }, + .memory_regions = &.{ + .{ .kind = .flash, .offset = 0x00000000, .length = 16 * 1024 }, + .{ .kind = .ram, .offset = 0x20000000, .length = 2 * 1024 }, + }, + .patches = @import("patches/hc32l110.zig").patches, + }, + .hal = hal, + }; + + const chip_hc32l110x6: microzig.Target = .{ + .dep = dep, + .preferred_binary_format = .{ .bin = {} }, + .zig_target = .{ + .cpu_arch = .thumb, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus }, + .os_tag = .freestanding, + .abi = .eabi, + }, + .chip = .{ + .name = "HDSC_HC32L110", + .register_definition = .{ .svd = b.path("src/chips/HC32L110.svd") }, + .memory_regions = &.{ + .{ .kind = .flash, .offset = 0x00000000, .length = 32 * 1024 }, + .{ .kind = .ram, .offset = 0x20000000, .length = 4 * 1024 }, + }, + .patches = @import("patches/hc32l110.zig").patches, + }, + .hal = hal, + }; + + return .{ + .chips = .{ + .hc32l110x4 = chip_hc32l110x4.derive(.{}), + .hc32l110x6 = chip_hc32l110x6.derive(.{}), + }, + .boards = .{}, + }; +} + +pub fn build(b: *std.Build) !void { + const optimize = b.standardOptimizeOption(.{}); + + const unit_tests = b.addTest(.{ + .root_source_file = b.path("src/hal.zig"), + .optimize = optimize, + }); + + const unit_tests_run = b.addRunArtifact(unit_tests); + const test_step = b.step("test", "Run platform agnostic unit tests"); + test_step.dependOn(&unit_tests_run.step); +} diff --git a/port/hdsc/hc32l110/build.zig.zon b/port/hdsc/hc32l110/build.zig.zon new file mode 100644 index 000000000..7e164351f --- /dev/null +++ b/port/hdsc/hc32l110/build.zig.zon @@ -0,0 +1,14 @@ +.{ + .name = .microzig_port_hdsc_hc32l110, + .fingerprint = 0x75d5d0484fa537e9, + .version = "0.0.0", + .dependencies = .{ + .@"microzig/build-internals" = .{ .path = "../../../build-internals" }, + }, + .paths = .{ + "README.md", + "build.zig.zon", + "build.zig", + "src", + }, +} diff --git a/port/hdsc/hc32l110/patches/hc32l110.zig b/port/hdsc/hc32l110/patches/hc32l110.zig new file mode 100644 index 000000000..20c8169ca --- /dev/null +++ b/port/hdsc/hc32l110/patches/hc32l110.zig @@ -0,0 +1,17 @@ +const Patch = @import("microzig/build-internals").Patch; + +pub const patches: []const Patch = &.{ + .{ .add_interrupt = .{ .device_name = "HDSC_HC32L110", .idx = 0, .name = "PORT0" } }, + .{ .add_interrupt = .{ .device_name = "HDSC_HC32L110", .idx = 1, .name = "PORT1" } }, + .{ .add_interrupt = .{ .device_name = "HDSC_HC32L110", .idx = 2, .name = "PORT2" } }, + .{ .add_interrupt = .{ .device_name = "HDSC_HC32L110", .idx = 3, .name = "PORT3" } }, + .{ .add_interrupt = .{ .device_name = "HDSC_HC32L110", .idx = 6, .name = "UART0" } }, + .{ .add_interrupt = .{ .device_name = "HDSC_HC32L110", .idx = 7, .name = "UART1" } }, + .{ .add_interrupt = .{ .device_name = "HDSC_HC32L110", .idx = 8, .name = "LPUART" } }, + .{ .add_interrupt = .{ .device_name = "HDSC_HC32L110", .idx = 10, .name = "SPI" } }, + .{ .add_interrupt = .{ .device_name = "HDSC_HC32L110", .idx = 12, .name = "I2C" } }, + .{ .add_interrupt = .{ .device_name = "HDSC_HC32L110", .idx = 14, .name = "TIM0" } }, + .{ .add_interrupt = .{ .device_name = "HDSC_HC32L110", .idx = 15, .name = "TIM1" } }, + .{ .add_interrupt = .{ .device_name = "HDSC_HC32L110", .idx = 16, .name = "TIM2" } }, + .{ .add_interrupt = .{ .device_name = "HDSC_HC32L110", .idx = 17, .name = "LPTIM" } }, +}; diff --git a/port/hdsc/hc32l110/src/chips/HC32L110.svd b/port/hdsc/hc32l110/src/chips/HC32L110.svd new file mode 100644 index 000000000..9d585381a --- /dev/null +++ b/port/hdsc/hc32l110/src/chips/HC32L110.svd @@ -0,0 +1,10109 @@ + + + HDSC Co.Ltd + HDSC + HDSC_HC32L110 + ARMCM0P + 1.2 + + CM0 + r0p0 + little + false + false + 3 + false + + 8 + 32 + 32 + read-write + 0x0 + 0x0 + + + ADC + desc ADC + 0x40002400 + + 0x0 + 0x74 + + + + CR0 + desc CR0 + 0x4 + 32 + read-write + 0x13F0 + 0x5FFF + + + ADCEN + desc ADCEN + 0 + 0 + read-write + + + START + desc START + 1 + 1 + read-write + + + CLKSEL + desc CLKSEL + 3 + 2 + read-write + + + SEL + desc SEL + 7 + 4 + read-write + + + SREF + desc SREF + 9 + 8 + read-write + + + BUFEN + desc BUFEN + 10 + 10 + read-write + + + SAM + desc SAM + 12 + 11 + read-write + + + IE + desc IE + 14 + 14 + read-write + + + STATERST + desc STATERST + 15 + 15 + read-write + + + + + CR1 + desc CR1 + 0x8 + 32 + read-write + 0x7000 + 0xFFFF + + + TRIGS0 + desc TRIGS0 + 4 + 0 + read-write + + + TRIGS1 + desc TRIGS1 + 9 + 5 + read-write + + + CT + desc CT + 10 + 10 + read-write + + + RACC_EN + desc RACC_EN + 11 + 11 + read-write + + + LTCMP + desc LTCMP + 12 + 12 + read-write + + + HTCMP + desc HTCMP + 13 + 13 + read-write + + + REGCMP + desc REGCMP + 14 + 14 + read-write + + + RACC_CLR + desc RACC_CLR + 15 + 15 + read-write + + + + + CR2 + desc CR2 + 0xC + 32 + read-write + 0x0 + 0xFFFF + + + CH0EN + desc CH0EN + 0 + 0 + read-write + + + CH1EN + desc CH1EN + 1 + 1 + read-write + + + CH2EN + desc CH2EN + 2 + 2 + read-write + + + CH3EN + desc CH3EN + 3 + 3 + read-write + + + CH4EN + desc CH4EN + 4 + 4 + read-write + + + CH5EN + desc CH5EN + 5 + 5 + read-write + + + CH6EN + desc CH6EN + 6 + 6 + read-write + + + CH7EN + desc CH7EN + 7 + 7 + read-write + + + ADCCNT + desc ADCCNT + 15 + 8 + read-write + + + + + RESULT0 + desc RESULT0 + 0x30 + 32 + read-only + 0x0 + 0xFFF + + + RESULT0 + desc RESULT0 + 11 + 0 + read-only + + + + + RESULT1 + desc RESULT1 + 0x34 + 32 + read-only + 0x0 + 0xFFF + + + RESULT1 + desc RESULT1 + 11 + 0 + read-only + + + + + RESULT2 + desc RESULT2 + 0x38 + 32 + read-only + 0x0 + 0xFFF + + + RESULT2 + desc RESULT2 + 11 + 0 + read-only + + + + + RESULT3 + desc RESULT3 + 0x3C + 32 + read-only + 0x0 + 0xFFF + + + RESULT3 + desc RESULT3 + 11 + 0 + read-only + + + + + RESULT4 + desc RESULT4 + 0x40 + 32 + read-only + 0x0 + 0xFFF + + + RESULT4 + desc RESULT4 + 11 + 0 + read-only + + + + + RESULT5 + desc RESULT5 + 0x44 + 32 + read-only + 0x0 + 0xFFF + + + RESULT5 + desc RESULT5 + 11 + 0 + read-only + + + + + RESULT6 + desc RESULT6 + 0x48 + 32 + read-only + 0x0 + 0xFFF + + + RESULT6 + desc RESULT6 + 11 + 0 + read-only + + + + + RESULT7 + desc RESULT7 + 0x4C + 32 + read-only + 0x0 + 0xFFF + + + RESULT7 + desc RESULT7 + 11 + 0 + read-only + + + + + RESULT8 + desc RESULT8 + 0x50 + 32 + read-only + 0x0 + 0xFFF + + + RESULT8 + desc RESULT8 + 11 + 0 + read-only + + + + + RESULT_ACC + desc RESULT_ACC + 0x54 + 32 + read-only + 0x0 + 0xFFFFF + + + RESULT_ACC + desc RESULT_ACC + 19 + 0 + read-only + + + + + HT + desc HT + 0x58 + 32 + read-only + 0xFFF + 0xFFF + + + HT + desc HT + 11 + 0 + read-only + + + + + LT + desc LT + 0x5C + 32 + read-only + 0x0 + 0xFFF + + + LT + desc LT + 11 + 0 + read-only + + + + + IFR + desc IFR + 0x60 + 32 + read-only + 0x0 + 0xF + + + LLT_INTF + desc LLT_INTF + 0 + 0 + read-only + + + HHT_INTF + desc HHT_INTF + 1 + 1 + read-only + + + REG_INTF + desc REG_INTF + 2 + 2 + read-only + + + CONT_INTF + desc CONT_INTF + 3 + 3 + read-only + + + + + ICLR + desc ICLR + 0x64 + 32 + write-only + 0x4 + 0xF + + + LLT_INTC + desc LLT_INTC + 0 + 0 + write-only + + + HHT_INTC + desc HHT_INTC + 1 + 1 + write-only + + + REG_INTC + desc REG_INTC + 2 + 2 + write-only + + + CONT_INTC + desc CONT_INTC + 3 + 3 + write-only + + + + + RESULT + desc RESULT + 0x68 + 32 + read-only + 0x0 + 0xFFF + + + RESULT + desc RESULT + 11 + 0 + read-only + + + + + + + ADT0 + desc ADT + 0x40003000 + + 0x0 + 0x400 + + + + CNTER + desc CNTER + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + CNT + desc CNT + 15 + 0 + read-write + + + + + PERAR + desc PERAR + 0x4 + 32 + read-write + 0xFFFF + 0xFFFF + + + PERA + desc PERA + 15 + 0 + read-write + + + + + PERBR + desc PERBR + 0x8 + 32 + read-write + 0xFFFF + 0xFFFF + + + PERB + desc PERB + 15 + 0 + read-write + + + + + GCMAR + desc GCMAR + 0x10 + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMA + desc GCMA + 15 + 0 + read-write + + + + + GCMBR + desc GCMBR + 0x14 + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMB + desc GCMB + 15 + 0 + read-write + + + + + GCMCR + desc GCMCR + 0x18 + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMC + desc GCMC + 15 + 0 + read-write + + + + + GCMDR + desc GCMDR + 0x1C + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMD + desc GCMD + 15 + 0 + read-write + + + + + DTUAR + desc DTUAR + 0x40 + 32 + read-write + 0xFFFF + 0xFFFF + + + DTUA + desc DTUA + 15 + 0 + read-write + + + + + DTDAR + desc DTDAR + 0x44 + 32 + read-write + 0xFFFF + 0xFFFF + + + DTDA + desc DTDA + 15 + 0 + read-write + + + + + GCONR + desc GCONR + 0x50 + 32 + read-write + 0x100 + 0xF017F + + + START + desc START + 0 + 0 + read-write + + + MODE + desc MODE + 3 + 1 + read-write + + + CKDIV + desc CKDIV + 6 + 4 + read-write + + + DIR + desc DIR + 8 + 8 + read-write + + + ZMSKREV + desc ZMSKREV + 16 + 16 + read-write + + + ZMSKPOS + desc ZMSKPOS + 17 + 17 + read-write + + + ZMSK + desc ZMSK + 19 + 18 + read-write + + + + + ICONR + desc ICONR + 0x54 + 32 + read-write + 0x0 + 0xC1CF + + + INTENA + desc INTENA + 0 + 0 + read-write + + + INTENB + desc INTENB + 1 + 1 + read-write + + + INTENC + desc INTENC + 2 + 2 + read-write + + + INTEND + desc INTEND + 3 + 3 + read-write + + + INTENOVF + desc INTENOVF + 6 + 6 + read-write + + + INTENUDF + desc INTENUDF + 7 + 7 + read-write + + + INTENDE + desc INTENDE + 8 + 8 + read-write + + + + + PCONR + desc PCONR + 0x58 + 32 + read-write + 0x0 + 0x1FFF1FFF + + + CAPCA + desc CAPCA + 0 + 0 + read-write + + + STACA + desc STACA + 1 + 1 + read-write + + + STPCA + desc STPCA + 2 + 2 + read-write + + + STASTPSA + desc STASTPSA + 3 + 3 + read-write + + + CMPCA + desc CMPCA + 5 + 4 + read-write + + + PERCA + desc PERCA + 7 + 6 + read-write + + + OUTENA + desc OUTENA + 8 + 8 + read-write + + + DISSELA + desc DISSELA + 10 + 9 + read-write + + + DISVALA + desc DISVALA + 12 + 11 + read-write + + + CAPCB + desc CAPCB + 16 + 16 + read-write + + + STACB + desc STACB + 17 + 17 + read-write + + + STPCB + desc STPCB + 18 + 18 + read-write + + + STASTPSB + desc STASTPSB + 19 + 19 + read-write + + + CMPCB + desc CMPCB + 21 + 20 + read-write + + + PERCB + desc PERCB + 23 + 22 + read-write + + + OUTENB + desc OUTENB + 24 + 24 + read-write + + + DISSELB + desc DISSELB + 26 + 25 + read-write + + + DISVALB + desc DISVALB + 28 + 27 + read-write + + + + + BCONR + desc BCONR + 0x5C + 32 + read-write + 0x0 + 0x185 + + + BENA + desc BENA + 0 + 0 + read-write + + + BENB + desc BENB + 2 + 2 + read-write + + + BENP + desc BENP + 8 + 8 + read-write + + + + + DCONR + desc DCONR + 0x60 + 32 + read-write + 0x0 + 0x101 + + + DTCEN + desc DTCEN + 0 + 0 + read-write + + + SEPA + desc SEPA + 8 + 8 + read-write + + + + + FCONR + desc FCONR + 0x68 + 32 + read-write + 0x0 + 0x77770077 + + + NOFIENGA + desc NOFIENGA + 0 + 0 + read-write + + + NOFICKGA + desc NOFICKGA + 2 + 1 + read-write + + + NOFIENGB + desc NOFIENGB + 4 + 4 + read-write + + + NOFICKGB + desc NOFICKGB + 6 + 5 + read-write + + + NOFIENTA + desc NOFIENTA + 16 + 16 + read-write + + + NOFICKTA + desc NOFICKTA + 18 + 17 + read-write + + + NOFIENTB + desc NOFIENTB + 20 + 20 + read-write + + + NOFICKTB + desc NOFICKTB + 22 + 21 + read-write + + + NOFIENTC + desc NOFIENTC + 24 + 24 + read-write + + + NOFICKTC + desc NOFICKTC + 26 + 25 + read-write + + + NOFIENTD + desc NOFIENTD + 28 + 28 + read-write + + + NOFICKTD + desc NOFICKTD + 30 + 29 + read-write + + + + + VPERR + desc VPERR + 0x6C + 32 + read-write + 0x0 + 0x1F000F + + + GEPERIA + desc GEPERIA + 0 + 0 + read-write + + + GEPERIB + desc GEPERIB + 1 + 1 + read-write + + + GEPERIC + desc GEPERIC + 2 + 2 + read-write + + + GEPERID + desc GEPERID + 3 + 3 + read-write + + + PCNTE + desc PCNTE + 17 + 16 + read-write + + + PCNTS + desc PCNTS + 20 + 18 + read-write + + + + + STFLR + desc STFLR + 0x70 + 32 + read-write + 0x0 + 0x80CE001CF + + + CMAF + desc CMAF + 0 + 0 + read-write + + + CMBF + desc CMBF + 1 + 1 + read-write + + + CMCF + desc CMCF + 2 + 2 + read-write + + + CMDF + desc CMDF + 3 + 3 + read-write + + + OVFF + desc OVFF + 6 + 6 + read-write + + + UDFF + desc UDFF + 7 + 7 + read-write + + + DTEF + desc DTEF + 8 + 8 + read-write + + + VPERNUM + desc VPERNUM + 23 + 21 + read-only + + + DIRF + desc DIRF + 31 + 31 + read-only + + + + + HSTAR + desc HSTAR + 0x74 + 32 + read-write + 0x0 + 0x8000FFFF + + + HSTA0 + desc HSTA0 + 0 + 0 + read-write + + + HSTA1 + desc HSTA1 + 1 + 1 + read-write + + + HSTA2 + desc HSTA2 + 2 + 2 + read-write + + + HSTA3 + desc HSTA3 + 3 + 3 + read-write + + + HSTA4 + desc HSTA4 + 4 + 4 + read-write + + + HSTA5 + desc HSTA5 + 5 + 5 + read-write + + + HSTA6 + desc HSTA6 + 6 + 6 + read-write + + + HSTA7 + desc HSTA7 + 7 + 7 + read-write + + + HSTA8 + desc HSTA8 + 8 + 8 + read-write + + + HSTA9 + desc HSTA9 + 9 + 9 + read-write + + + HSTA10 + desc HSTA10 + 10 + 10 + read-write + + + HSTA11 + desc HSTA11 + 11 + 11 + read-write + + + HSTA12 + desc HSTA12 + 12 + 12 + read-write + + + HSTA13 + desc HSTA13 + 13 + 13 + read-write + + + HSTA14 + desc HSTA14 + 14 + 14 + read-write + + + HSTA15 + desc HSTA15 + 15 + 15 + read-write + + + STARTS + desc STARTS + 31 + 31 + read-write + + + + + HSTPR + desc HSTPR + 0x78 + 32 + read-write + 0x0 + 0x8000FFFF + + + HSTP0 + desc HSTP0 + 0 + 0 + read-write + + + HSTP1 + desc HSTP1 + 1 + 1 + read-write + + + HSTP2 + desc HSTP2 + 2 + 2 + read-write + + + HSTP3 + desc HSTP3 + 3 + 3 + read-write + + + HSTP4 + desc HSTP4 + 4 + 4 + read-write + + + HSTP5 + desc HSTP5 + 5 + 5 + read-write + + + HSTP6 + desc HSTP6 + 6 + 6 + read-write + + + HSTP7 + desc HSTP7 + 7 + 7 + read-write + + + HSTP8 + desc HSTP8 + 8 + 8 + read-write + + + HSTP9 + desc HSTP9 + 9 + 9 + read-write + + + HSTP10 + desc HSTP10 + 10 + 10 + read-write + + + HSTP11 + desc HSTP11 + 11 + 11 + read-write + + + HSTP12 + desc HSTP12 + 12 + 12 + read-write + + + HSTP13 + desc HSTP13 + 13 + 13 + read-write + + + HSTP14 + desc HSTP14 + 14 + 14 + read-write + + + HSTP15 + desc HSTP15 + 15 + 15 + read-write + + + STOPS + desc STOPS + 31 + 31 + read-write + + + + + HCELR + desc HCELR + 0x7C + 32 + read-write + 0x0 + 0x8000FFFF + + + HCEL0 + desc HCEL0 + 0 + 0 + read-write + + + HCEL1 + desc HCEL1 + 1 + 1 + read-write + + + HCEL2 + desc HCEL2 + 2 + 2 + read-write + + + HCEL3 + desc HCEL3 + 3 + 3 + read-write + + + HCEL4 + desc HCEL4 + 4 + 4 + read-write + + + HCEL5 + desc HCEL5 + 5 + 5 + read-write + + + HCEL6 + desc HCEL6 + 6 + 6 + read-write + + + HCEL7 + desc HCEL7 + 7 + 7 + read-write + + + HCEL8 + desc HCEL8 + 8 + 8 + read-write + + + HCEL9 + desc HCEL9 + 9 + 9 + read-write + + + HCEL10 + desc HCEL10 + 10 + 10 + read-write + + + HCEL11 + desc HCEL11 + 11 + 11 + read-write + + + HCEL12 + desc HCEL12 + 12 + 12 + read-write + + + HCEL13 + desc HCEL13 + 13 + 13 + read-write + + + HCEL14 + desc HCEL14 + 14 + 14 + read-write + + + HCEL15 + desc HCEL15 + 15 + 15 + read-write + + + CLEARS + desc CLEARS + 31 + 31 + read-write + + + + + HCPAR + desc HCPAR + 0x80 + 32 + read-write + 0x0 + 0xFFFF + + + HCPA0 + desc HCPA0 + 0 + 0 + read-write + + + HCPA1 + desc HCPA1 + 1 + 1 + read-write + + + HCPA2 + desc HCPA2 + 2 + 2 + read-write + + + HCPA3 + desc HCPA3 + 3 + 3 + read-write + + + HCPA4 + desc HCPA4 + 4 + 4 + read-write + + + HCPA5 + desc HCPA5 + 5 + 5 + read-write + + + HCPA6 + desc HCPA6 + 6 + 6 + read-write + + + HCPA7 + desc HCPA7 + 7 + 7 + read-write + + + HCPA8 + desc HCPA8 + 8 + 8 + read-write + + + HCPA9 + desc HCPA9 + 9 + 9 + read-write + + + HCPA10 + desc HCPA10 + 10 + 10 + read-write + + + HCPA11 + desc HCPA11 + 11 + 11 + read-write + + + HCPA12 + desc HCPA12 + 12 + 12 + read-write + + + HCPA13 + desc HCPA13 + 13 + 13 + read-write + + + HCPA14 + desc HCPA14 + 14 + 14 + read-write + + + HCPA15 + desc HCPA15 + 15 + 15 + read-write + + + + + HCPBR + desc HCPBR + 0x84 + 32 + read-write + 0x0 + 0xFFFF + + + HCPB0 + desc HCPB0 + 0 + 0 + read-write + + + HCPB1 + desc HCPB1 + 1 + 1 + read-write + + + HCPB2 + desc HCPB2 + 2 + 2 + read-write + + + HCPB3 + desc HCPB3 + 3 + 3 + read-write + + + HCPB4 + desc HCPB4 + 4 + 4 + read-write + + + HCPB5 + desc HCPB5 + 5 + 5 + read-write + + + HCPB6 + desc HCPB6 + 6 + 6 + read-write + + + HCPB7 + desc HCPB7 + 7 + 7 + read-write + + + HCPB8 + desc HCPB8 + 8 + 8 + read-write + + + HCPB9 + desc HCPB9 + 9 + 9 + read-write + + + HCPB10 + desc HCPB10 + 10 + 10 + read-write + + + HCPB11 + desc HCPB11 + 11 + 11 + read-write + + + HCPB12 + desc HCPB12 + 12 + 12 + read-write + + + HCPB13 + desc HCPB13 + 13 + 13 + read-write + + + HCPB14 + desc HCPB14 + 14 + 14 + read-write + + + HCPB15 + desc HCPB15 + 15 + 15 + read-write + + + + + HCUPR + desc HCUPR + 0x88 + 32 + read-write + 0x0 + 0xFFFFF + + + HCUP0 + desc HCUP0 + 0 + 0 + read-write + + + HCUP1 + desc HCUP1 + 1 + 1 + read-write + + + HCUP2 + desc HCUP2 + 2 + 2 + read-write + + + HCUP3 + desc HCUP3 + 3 + 3 + read-write + + + HCUP4 + desc HCUP4 + 4 + 4 + read-write + + + HCUP5 + desc HCUP5 + 5 + 5 + read-write + + + HCUP6 + desc HCUP6 + 6 + 6 + read-write + + + HCUP7 + desc HCUP7 + 7 + 7 + read-write + + + HCUP8 + desc HCUP8 + 8 + 8 + read-write + + + HCUP9 + desc HCUP9 + 9 + 9 + read-write + + + HCUP10 + desc HCUP10 + 10 + 10 + read-write + + + HCUP11 + desc HCUP11 + 11 + 11 + read-write + + + HCUP12 + desc HCUP12 + 12 + 12 + read-write + + + HCUP13 + desc HCUP13 + 13 + 13 + read-write + + + HCUP14 + desc HCUP14 + 14 + 14 + read-write + + + HCUP15 + desc HCUP15 + 15 + 15 + read-write + + + HCUP16 + desc HCUP16 + 16 + 16 + read-write + + + HCUP17 + desc HCUP17 + 17 + 17 + read-write + + + HCUP18 + desc HCUP18 + 18 + 18 + read-write + + + HCUP19 + desc HCUP19 + 19 + 19 + read-write + + + + + HCDOR + desc HCDOR + 0x8C + 32 + read-write + 0x0 + 0xFFFFF + + + HCDO0 + desc HCDO0 + 0 + 0 + read-write + + + HCDO1 + desc HCDO1 + 1 + 1 + read-write + + + HCDO2 + desc HCDO2 + 2 + 2 + read-write + + + HCDO3 + desc HCDO3 + 3 + 3 + read-write + + + HCDO4 + desc HCDO4 + 4 + 4 + read-write + + + HCDO5 + desc HCDO5 + 5 + 5 + read-write + + + HCDO6 + desc HCDO6 + 6 + 6 + read-write + + + HCDO7 + desc HCDO7 + 7 + 7 + read-write + + + HCDO8 + desc HCDO8 + 8 + 8 + read-write + + + HCDO9 + desc HCDO9 + 9 + 9 + read-write + + + HCDO10 + desc HCDO10 + 10 + 10 + read-write + + + HCDO11 + desc HCDO11 + 11 + 11 + read-write + + + HCDO12 + desc HCDO12 + 12 + 12 + read-write + + + HCDO13 + desc HCDO13 + 13 + 13 + read-write + + + HCDO14 + desc HCDO14 + 14 + 14 + read-write + + + HCDO15 + desc HCDO15 + 15 + 15 + read-write + + + HCDO16 + desc HCDO16 + 16 + 16 + read-write + + + HCDO17 + desc HCDO17 + 17 + 17 + read-write + + + HCDO18 + desc HCDO18 + 18 + 18 + read-write + + + HCDO19 + desc HCDO19 + 19 + 19 + read-write + + + + + IFR + desc IFR + 0x100 + 32 + read-only + 0x0 + 0xC1CF + + + CMAF + desc CMAF + 0 + 0 + read-only + + + CMBF + desc CMBF + 1 + 1 + read-only + + + CMCF + desc CMCF + 2 + 2 + read-only + + + CMDF + desc CMDF + 3 + 3 + read-only + + + OVFF + desc OVFF + 6 + 6 + read-only + + + UDFF + desc UDFF + 7 + 7 + read-only + + + DTEF + desc DTEF + 8 + 8 + read-only + + + SAMLF + desc SAMLF + 14 + 14 + read-only + + + SAMHF + desc SAMHF + 15 + 15 + read-only + + + + + ICLR + desc ICLR + 0x104 + 32 + write-only + 0x0 + 0xC1CF + + + CMAC + desc CMAC + 0 + 0 + write-only + + + CMBC + desc CMBC + 1 + 1 + write-only + + + CMCC + desc CMCC + 2 + 2 + write-only + + + CMDC + desc CMDC + 3 + 3 + write-only + + + OVFC + desc OVFC + 6 + 6 + write-only + + + UDFC + desc UDFC + 7 + 7 + write-only + + + DTEC + desc DTEC + 8 + 8 + write-only + + + SAMLC + desc SAMLC + 14 + 14 + write-only + + + SAMHC + desc SAMHC + 15 + 15 + write-only + + + + + CR + desc CR + 0x108 + 32 + read-write + 0x0 + 0x7CF + + + CMAE + desc CMAE + 0 + 0 + read-write + + + CMBE + desc CMBE + 1 + 1 + read-write + + + CMCE + desc CMCE + 2 + 2 + read-write + + + CMDE + desc CMDE + 3 + 3 + read-write + + + OVFE + desc OVFE + 6 + 6 + read-write + + + UDFE + desc UDFE + 7 + 7 + read-write + + + DITENA + desc DITENA + 8 + 8 + read-write + + + DITENB + desc DITENB + 9 + 9 + read-write + + + DITENS + desc DITENS + 10 + 10 + read-write + + + + + AOSSR + desc AOSSR + 0x110 + 32 + read-write + 0x0 + 0x3F9F + + + FBRAKE + desc FBRAKE + 0 + 0 + read-write + + + FSAME + desc FSAME + 1 + 1 + read-write + + + BFILTS + desc BFILTS + 3 + 2 + read-write + + + BFILTEN + desc BFILTEN + 4 + 4 + read-write + + + SOFTBK + desc SOFTBK + 7 + 7 + read-write + + + SML0 + desc SML0 + 8 + 8 + read-write + + + SML1 + desc SML1 + 9 + 9 + read-write + + + SML2 + desc SML2 + 10 + 10 + read-write + + + SMH0 + desc SMH0 + 11 + 11 + read-write + + + SMH1 + desc SMH1 + 12 + 12 + read-write + + + SMH2 + desc SMH2 + 13 + 13 + read-write + + + + + AOSCL + desc AOSCL + 0x114 + 32 + read-only + 0x0 + 0x3 + + + FBRAKE + desc FBRAKE + 0 + 0 + read-only + + + FSAME + desc FSAME + 1 + 1 + read-only + + + + + PTBKS + desc PTBKS + 0x118 + 32 + read-write + 0x0 + 0xFFFF + + + EN0 + desc EN0 + 0 + 0 + read-write + + + EN1 + desc EN1 + 1 + 1 + read-write + + + EN2 + desc EN2 + 2 + 2 + read-write + + + EN3 + desc EN3 + 3 + 3 + read-write + + + EN4 + desc EN4 + 4 + 4 + read-write + + + EN5 + desc EN5 + 5 + 5 + read-write + + + EN6 + desc EN6 + 6 + 6 + read-write + + + EN7 + desc EN7 + 7 + 7 + read-write + + + EN8 + desc EN8 + 8 + 8 + read-write + + + EN9 + desc EN9 + 9 + 9 + read-write + + + EN10 + desc EN10 + 10 + 10 + read-write + + + EN11 + desc EN11 + 11 + 11 + read-write + + + EN12 + desc EN12 + 12 + 12 + read-write + + + EN13 + desc EN13 + 13 + 13 + read-write + + + EN14 + desc EN14 + 14 + 14 + read-write + + + EN15 + desc EN15 + 15 + 15 + read-write + + + + + TTRIG + desc TTRIG + 0x11C + 32 + read-write + 0x0 + 0xFFFF + + + TRIGAS + desc TRIGAS + 3 + 0 + read-write + + + TRIGBS + desc TRIGBS + 7 + 4 + read-write + + + TRIGCS + desc TRIGCS + 11 + 8 + read-write + + + TRIGDS + desc TRIGDS + 15 + 12 + read-write + + + + + ITRIG + desc ITRIG + 0x120 + 32 + read-write + 0x0 + 0xFFFF + + + IAOS0S + desc IAOS0S + 3 + 0 + read-write + + + IAOS1S + desc IAOS1S + 7 + 4 + read-write + + + IAOS2S + desc IAOS2S + 11 + 8 + read-write + + + IAOS3S + desc IAOS3S + 15 + 12 + read-write + + + + + PTBKP + desc PTBKP + 0x124 + 32 + read-write + 0x0 + 0xFFFF + + + POL0 + desc POL0 + 0 + 0 + read-write + + + POL1 + desc POL1 + 1 + 1 + read-write + + + POL2 + desc POL2 + 2 + 2 + read-write + + + POL3 + desc POL3 + 3 + 3 + read-write + + + POL4 + desc POL4 + 4 + 4 + read-write + + + POL5 + desc POL5 + 5 + 5 + read-write + + + POL6 + desc POL6 + 6 + 6 + read-write + + + POL7 + desc POL7 + 7 + 7 + read-write + + + POL8 + desc POL8 + 8 + 8 + read-write + + + POL9 + desc POL9 + 9 + 9 + read-write + + + POL10 + desc POL10 + 10 + 10 + read-write + + + POL11 + desc POL11 + 11 + 11 + read-write + + + POL12 + desc POL12 + 12 + 12 + read-write + + + POL13 + desc POL13 + 13 + 13 + read-write + + + POL14 + desc POL14 + 14 + 14 + read-write + + + POL15 + desc POL15 + 15 + 15 + read-write + + + + + SSTAR + desc SSTAR + 0x3F4 + 32 + read-write + 0x0 + 0x7 + + + SSTA0 + desc SSTA0 + 0 + 0 + read-write + + + SSTA1 + desc SSTA1 + 1 + 1 + read-write + + + SSTA2 + desc SSTA2 + 2 + 2 + read-write + + + + + SSTPR + desc SSTPR + 0x3F8 + 32 + read-write + 0x0 + 0x7 + + + SSTP0 + desc SSTP0 + 0 + 0 + read-write + + + SSTP1 + desc SSTP1 + 1 + 1 + read-write + + + SSTP2 + desc SSTP2 + 2 + 2 + read-write + + + + + SCLRR + desc SCLRR + 0x3FC + 32 + read-write + 0x0 + 0x7 + + + SCLR0 + desc SCLR0 + 0 + 0 + read-write + + + SCLR1 + desc SCLR1 + 1 + 1 + read-write + + + SCLR2 + desc SCLR2 + 2 + 2 + read-write + + + + + + + ADT1 + desc ADT + 0x40003400 + + 0x0 + 0x400 + + + + ADT2 + desc ADT + 0x40003800 + + 0x0 + 0x400 + + + + BGR + desc BGR + 0x40002400 + ADC + + 0x0 + 0x40002400 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x3 + + + BGR_EN + desc BGR_EN + 0 + 0 + read-write + + + TS_EN + desc TS_EN + 1 + 1 + read-write + + + + + + + BT0 + desc BT + 0x40000C00 + + 0x0 + 0x18 + + + + ARR + desc ARR + 0x0 + 32 + read-write + 0x0 + 0xFF + + + ARR + desc ARR + 15 + 0 + read-write + + + + + CNT + desc CNT + 0x4 + 32 + read-write + 0x0 + 0xFF + + + CNT + desc CNT + 15 + 0 + read-write + + + + + CNT32 + desc CNT32 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CNT32 + desc CNT32 + 31 + 0 + read-write + + + + + CR + desc CR + 0xC + 32 + read-write + 0x8 + 0x77F + + + TR + desc TR + 0 + 0 + read-write + + + MD + desc MD + 1 + 1 + read-write + + + CT + desc CT + 2 + 2 + read-write + + + TOG_EN + desc TOG_EN + 3 + 3 + read-write + + + PRS + desc PRS + 6 + 4 + read-write + + + GATE + desc GATE + 8 + 8 + read-write + + + GATE_P + desc GATE_P + 9 + 9 + read-write + + + IE + desc IE + 10 + 10 + read-write + + + + + IFR + desc IFR + 0x10 + 32 + read-only + 0x0 + 0x1 + + + TF + desc TF + 0 + 0 + read-only + + + + + ICLR + desc ICLR + 0x14 + 32 + write-only + 0x1 + 0x1 + + + TFC + desc TFC + 0 + 0 + write-only + + + + + + + BT1 + desc BT + 0x40000C20 + + 0x0 + 0x18 + + + + BT2 + desc BT + 0x40000C40 + + 0x0 + 0x18 + + + + CLK_TRIM + desc CLK_TRIM + 0x40001800 + + 0x0 + 0x1C + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0xFF + + + TRIM_START + desc TRIM_START + 0 + 0 + read-write + + + REFCLK_SEL + desc REFCLK_SEL + 3 + 1 + read-write + + + CALCLK_SEL + desc CALCLK_SEL + 5 + 4 + read-write + + + MON_EN + desc MON_EN + 6 + 6 + read-write + + + IE + desc IE + 7 + 7 + read-write + + + + + REFCON + desc REFCON + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RCNTVAL + desc RCNTVAL + 31 + 0 + read-write + + + + + REFCNT + desc REFCNT + 0x8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + REFCNT + desc REFCNT + 31 + 0 + read-only + + + + + CALCNT + desc CALCNT + 0xC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + CALCNT + desc CALCNT + 31 + 0 + read-only + + + + + IFR + desc IFR + 0x10 + 32 + read-only + 0x0 + 0xF + + + STOP + desc STOP + 0 + 0 + read-only + + + CALCNT_OF + desc CALCNT_OF + 1 + 1 + read-only + + + XTL_FAULT + desc XTL_FAULT + 2 + 2 + read-only + + + XTH_FAULT + desc XTH_FAULT + 3 + 3 + read-only + + + + + ICLR + desc ICLR + 0x14 + 32 + read-write + 0x11111111 + 0xC + + + XTL_FAULT_CLR + desc XTL_FAULT_CLR + 2 + 2 + read-write + + + XTH_FAULT_CLR + desc XTH_FAULT_CLR + 3 + 3 + read-write + + + + + CALCON + desc CALCON + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CCNTVAL + desc CCNTVAL + 31 + 0 + read-write + + + + + + + CLOCK + desc CLOCK + 0x40002000 + + 0x0 + 0x54 + + + + SYSCTRL0 + desc SYSCTRL0 + 0x0 + 32 + read-write + 0x1 + 0x87FF + + + RCH_EN + desc RCH_EN + 0 + 0 + read-write + + + XTH_EN + desc XTH_EN + 1 + 1 + read-write + + + RCL_EN + desc RCL_EN + 2 + 2 + read-write + + + XTL_EN + desc XTL_EN + 3 + 3 + read-write + + + CLK_SW4_SEL + desc CLK_SW4_SEL + 5 + 4 + read-write + + + HCLK_PRS + desc HCLK_PRS + 8 + 6 + read-write + + + PCLK_PRS + desc PCLK_PRS + 10 + 9 + read-write + + + WAKEUP_BYRCH + desc WAKEUP_BYRCH + 15 + 15 + read-write + + + + + SYSCTRL1 + desc SYSCTRL1 + 0x4 + 32 + read-write + 0x8 + 0xFFE + + + EXTH_EN + desc EXTH_EN + 1 + 1 + read-write + + + EXTL_EN + desc EXTL_EN + 2 + 2 + read-write + + + XTL_ALWAYSON + desc XTL_ALWAYSON + 3 + 3 + read-write + + + CLOCK_FT_EN + desc CLOCK_FT_EN + 4 + 4 + read-write + + + RTC_LPW + desc RTC_LPW + 5 + 5 + read-write + + + LOCK_EN + desc LOCK_EN + 6 + 6 + read-write + + + RES_UIO + desc RES_UIO + 7 + 7 + read-write + + + SWD_UIO + desc SWD_UIO + 8 + 8 + read-write + + + RTC_FREQ_ADJUST + desc RTC_FREQ_ADJUST + 11 + 9 + read-write + + + + + SYSCTRL2 + desc SYSCTRL2 + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + SYSCTRL2 + desc SYSCTRL2 + 15 + 0 + read-write + + + + + RCH_CR + desc RCH_CR + 0xC + 32 + read-write + 0x126 + 0xFFF + + + TRIM + desc TRIM + 10 + 0 + read-write + + + STABLE + desc STABLE + 11 + 11 + read-only + + + + + XTH_CR + desc XTH_CR + 0x10 + 32 + read-write + 0x22 + 0x7F + + + DRIVER + desc DRIVER + 3 + 0 + read-write + + + STARTUP + desc STARTUP + 5 + 4 + read-write + + + STABLE + desc STABLE + 6 + 6 + read-only + + + + + RCL_CR + desc RCL_CR + 0x14 + 32 + read-write + 0x33F + 0x1FFF + + + TRIM + desc TRIM + 9 + 0 + read-write + + + STARTUP + desc STARTUP + 11 + 10 + read-write + + + STABLE + desc STABLE + 12 + 12 + read-only + + + + + XTL_CR + desc XTL_CR + 0x18 + 32 + read-write + 0x21 + 0x7F + + + DRIVER + desc DRIVER + 3 + 0 + read-write + + + STARTUP + desc STARTUP + 5 + 4 + read-write + + + STABLE + desc STABLE + 6 + 6 + read-only + + + + + PERI_CLKEN + desc PERI_CLKEN + 0x20 + 32 + read-write + 0x0 + 0x9733C777 + + + UART0 + desc UART0 + 0 + 0 + read-write + + + UART1 + desc UART1 + 1 + 1 + read-write + + + LPUART + desc LPUART + 2 + 2 + read-write + + + I2C + desc I2C + 4 + 4 + read-write + + + SPI + desc SPI + 6 + 6 + read-write + + + BASETIM + desc BASETIM + 8 + 8 + read-write + + + LPTIM + desc LPTIM + 9 + 9 + read-write + + + ADVTIM + desc ADVTIM + 10 + 10 + read-write + + + PCA + desc PCA + 14 + 14 + read-write + + + WDT + desc WDT + 15 + 15 + read-write + + + ADC + desc ADC + 16 + 16 + read-write + + + VC + desc VC + 17 + 17 + read-write + + + RTC + desc RTC + 20 + 20 + read-write + + + TRIM + desc TRIM + 21 + 21 + read-write + + + TICK + desc TICK + 24 + 24 + read-write + + + CRC + desc CRC + 26 + 26 + read-write + + + GPIO + desc GPIO + 28 + 28 + read-write + + + FLASH + desc FLASH + 31 + 31 + read-write + + + + + SYSTICK_CR + desc SYSTICK_CR + 0x34 + 32 + read-write + 0x1000147 + 0xFFFFFFF + + + STCALIB + desc STCALIB + 23 + 0 + read-write + + + SKEW + desc SKEW + 24 + 24 + read-write + + + NOREF + desc NOREF + 25 + 25 + read-write + + + CLK_SEL + desc CLK_SEL + 27 + 26 + read-write + + + + + DEBUG_ACTIVE + desc DEBUG_ACTIVE + 0x38 + 32 + read-write + 0x7FF + 0x7FF + + + TIM0 + desc TIM0 + 0 + 0 + read-write + + + TIM1 + desc TIM1 + 1 + 1 + read-write + + + TIM2 + desc TIM2 + 2 + 2 + read-write + + + LPTIM + desc LPTIM + 3 + 3 + read-write + + + TIM4 + desc TIM4 + 4 + 4 + read-write + + + TIM5 + desc TIM5 + 5 + 5 + read-write + + + TIM6 + desc TIM6 + 6 + 6 + read-write + + + PCA + desc PCA + 7 + 7 + read-write + + + WDT + desc WDT + 8 + 8 + read-write + + + RTC + desc RTC + 9 + 9 + read-write + + + TICK + desc TICK + 10 + 10 + read-write + + + + + + + CRC + desc CRC + 0x40020900 + + 0x0 + 0x100 + + + + RESULT + desc RESULT + 0x4 + 32 + read-write + 0xFFFF + 0x1FFFF + + + RESULT + desc RESULT + 15 + 0 + read-write + + + FLAG + desc FLAG + 16 + 16 + read-only + + + + + DATA + desc DATA + 0x80 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + DATA + desc DATA + 31 + 0 + write-only + + + + + + + FLASH + desc FLASH + 0x40020000 + + 0x0 + 0x34 + + + + TNVS + desc TNVS + 0x0 + 32 + read-write + 0x32 + 0x1FF + + + TNVS + desc TNVS + 8 + 0 + read-write + + + + + TPGS + desc TPGS + 0x4 + 32 + read-write + 0x23 + 0xFF + + + TPGS + desc TPGS + 7 + 0 + read-write + + + + + TPROG + desc TPROG + 0x8 + 32 + read-write + 0x27 + 0xFF + + + TPROG + desc TPROG + 7 + 0 + read-write + + + + + TSERASE + desc TSERASE + 0xC + 32 + read-write + 0x18000 + 0x3FFFF + + + TSERASE + desc TSERASE + 17 + 0 + read-write + + + + + TMERASE + desc TMERASE + 0x10 + 32 + read-write + 0x140000 + 0x1FFFFF + + + TMERASE + desc TMERASE + 20 + 0 + read-write + + + + + TPRCV + desc TPRCV + 0x14 + 32 + read-write + 0x24 + 0xFFF + + + TPRCV + desc TPRCV + 11 + 0 + read-write + + + + + TSRCV + desc TSRCV + 0x18 + 32 + read-write + 0x240 + 0xFFF + + + TSRCV + desc TSRCV + 11 + 0 + read-write + + + + + TMRCV + desc TMRCV + 0x1C + 32 + read-write + 0x1000 + 0x1FFF + + + TMRCV + desc TMRCV + 12 + 0 + read-write + + + + + CR + desc CR + 0x20 + 32 + read-write + 0x0 + 0x7F + + + OP + desc OP + 1 + 0 + read-write + + + WAIT + desc WAIT + 2 + 2 + read-write + + + BUSY + desc BUSY + 4 + 4 + read-only + + + IE + desc IE + 6 + 5 + read-write + + + + + IFR + desc IFR + 0x24 + 32 + read-only + 0x0 + 0x3 + + + IF0 + desc IF0 + 0 + 0 + read-only + + + IF1 + desc IF1 + 1 + 1 + read-only + + + + + ICLR + desc ICLR + 0x28 + 32 + write-only + 0x3 + 0x3 + + + ICLR0 + desc ICLR0 + 0 + 0 + write-only + + + ICLR1 + desc ICLR1 + 1 + 1 + write-only + + + + + BYPASS + desc BYPASS + 0x2C + 32 + write-only + 0x0 + 0xFFFF + + + BYSEQ + desc BYSEQ + 15 + 0 + write-only + + + + + SLOCK + desc SLOCK + 0x30 + 32 + read-write + 0x0 + 0xFFFF + + + SLOCK + desc SLOCK + 15 + 0 + read-write + + + + + + + GPIO + desc GPIO + 0x40020C00 + + 0x0 + 0x400 + + + + P01_SEL + desc P01_SEL + 0x4 + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P02_SEL + desc P02_SEL + 0x8 + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P03_SEL + desc P03_SEL + 0xC + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P14_SEL + desc P14_SEL + 0x50 + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P15_SEL + desc P15_SEL + 0x54 + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P23_SEL + desc P23_SEL + 0x8C + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P24_SEL + desc P24_SEL + 0x90 + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P25_SEL + desc P25_SEL + 0x94 + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P26_SEL + desc P26_SEL + 0x98 + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P27_SEL + desc P27_SEL + 0x9C + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P31_SEL + desc P31_SEL + 0xC4 + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P32_SEL + desc P32_SEL + 0xC8 + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P33_SEL + desc P33_SEL + 0xCC + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P34_SEL + desc P34_SEL + 0xD0 + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P35_SEL + desc P35_SEL + 0xD4 + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P36_SEL + desc P36_SEL + 0xD8 + 32 + read-write + 0x0 + 0x7 + + + SEL + desc SEL + 2 + 0 + read-write + + + + + P0DIR + desc P0DIR + 0x100 + 32 + read-write + 0xFFFFFFFF + 0xE + + + P01 + desc P01 + 1 + 1 + read-write + + + P02 + desc P02 + 2 + 2 + read-write + + + P03 + desc P03 + 3 + 3 + read-write + + + + + P0IN + desc P0IN + 0x104 + 32 + read-only + 0x0 + 0xF + + + P00 + desc P00 + 0 + 0 + read-only + + + P01 + desc P01 + 1 + 1 + read-only + + + P02 + desc P02 + 2 + 2 + read-only + + + P03 + desc P03 + 3 + 3 + read-only + + + + + P0OUT + desc P0OUT + 0x108 + 32 + read-write + 0x0 + 0xE + + + P01 + desc P01 + 1 + 1 + read-write + + + P02 + desc P02 + 2 + 2 + read-write + + + P03 + desc P03 + 3 + 3 + read-write + + + + + P0ADS + desc P0ADS + 0x10C + 32 + read-write + 0x0 + 0xE + + + P01 + desc P01 + 1 + 1 + read-write + + + P02 + desc P02 + 2 + 2 + read-write + + + P03 + desc P03 + 3 + 3 + read-write + + + + + P0DR + desc P0DR + 0x11C + 32 + read-write + 0x0 + 0xE + + + P01 + desc P01 + 1 + 1 + read-write + + + P02 + desc P02 + 2 + 2 + read-write + + + P03 + desc P03 + 3 + 3 + read-write + + + + + P0PU + desc P0PU + 0x120 + 32 + read-write + 0x0 + 0xE + + + P01 + desc P01 + 1 + 1 + read-write + + + P02 + desc P02 + 2 + 2 + read-write + + + P03 + desc P03 + 3 + 3 + read-write + + + + + P0PD + desc P0PD + 0x124 + 32 + read-write + 0x0 + 0xE + + + P01 + desc P01 + 1 + 1 + read-write + + + P02 + desc P02 + 2 + 2 + read-write + + + P03 + desc P03 + 3 + 3 + read-write + + + + + P0OD + desc P0OD + 0x12C + 32 + read-write + 0x0 + 0xE + + + P01 + desc P01 + 1 + 1 + read-write + + + P02 + desc P02 + 2 + 2 + read-write + + + P03 + desc P03 + 3 + 3 + read-write + + + + + P0HIE + desc P0HIE + 0x130 + 32 + read-only + 0x0 + 0xF + + + P00 + desc P00 + 0 + 0 + read-only + + + P01 + desc P01 + 1 + 1 + read-only + + + P02 + desc P02 + 2 + 2 + read-only + + + P03 + desc P03 + 3 + 3 + read-only + + + + + P0LIE + desc P0LIE + 0x134 + 32 + read-only + 0x0 + 0xF + + + P00 + desc P00 + 0 + 0 + read-only + + + P01 + desc P01 + 1 + 1 + read-only + + + P02 + desc P02 + 2 + 2 + read-only + + + P03 + desc P03 + 3 + 3 + read-only + + + + + P0RIE + desc P0RIE + 0x138 + 32 + read-only + 0x0 + 0xF + + + P00 + desc P00 + 0 + 0 + read-only + + + P01 + desc P01 + 1 + 1 + read-only + + + P02 + desc P02 + 2 + 2 + read-only + + + P03 + desc P03 + 3 + 3 + read-only + + + + + P0FIE + desc P0FIE + 0x13C + 32 + read-only + 0x0 + 0xF + + + P00 + desc P00 + 0 + 0 + read-only + + + P01 + desc P01 + 1 + 1 + read-only + + + P02 + desc P02 + 2 + 2 + read-only + + + P03 + desc P03 + 3 + 3 + read-only + + + + + P1DIR + desc P1DIR + 0x140 + 32 + read-write + 0xFFFFFFFF + 0x30 + + + P14 + desc P14 + 4 + 4 + read-write + + + P15 + desc P15 + 5 + 5 + read-write + + + + + P1IN + desc P1IN + 0x144 + 32 + read-only + 0x0 + 0x3 + + + P14 + desc P14 + 4 + 4 + read-only + + + P15 + desc P15 + 5 + 5 + read-only + + + + + P1OUT + desc P1OUT + 0x148 + 32 + read-write + 0x0 + 0x30 + + + P14 + desc P14 + 4 + 4 + read-write + + + P15 + desc P15 + 5 + 5 + read-write + + + + + P1ADS + desc P1ADS + 0x14C + 32 + read-write + 0x0 + 0x30 + + + P14 + desc P14 + 4 + 4 + read-write + + + P15 + desc P15 + 5 + 5 + read-write + + + + + P1DR + desc P1DR + 0x15C + 32 + read-write + 0x0 + 0x30 + + + P14 + desc P14 + 4 + 4 + read-write + + + P15 + desc P15 + 5 + 5 + read-write + + + + + P1PU + desc P1PU + 0x160 + 32 + read-write + 0x0 + 0x30 + + + P14 + desc P14 + 4 + 4 + read-write + + + P15 + desc P15 + 5 + 5 + read-write + + + + + P1PD + desc P1PD + 0x164 + 32 + read-write + 0x0 + 0x30 + + + P14 + desc P14 + 4 + 4 + read-write + + + P15 + desc P15 + 5 + 5 + read-write + + + + + P1OD + desc P1OD + 0x16C + 32 + read-write + 0x0 + 0x30 + + + P14 + desc P14 + 4 + 4 + read-write + + + P15 + desc P15 + 5 + 5 + read-write + + + + + P1HIE + desc P1HIE + 0x170 + 32 + read-only + 0x0 + 0x3 + + + P14 + desc P14 + 4 + 4 + read-only + + + P15 + desc P15 + 5 + 5 + read-only + + + + + P1LIE + desc P1LIE + 0x174 + 32 + read-only + 0x0 + 0x3 + + + P14 + desc P14 + 4 + 4 + read-only + + + P15 + desc P15 + 5 + 5 + read-only + + + + + P1RIE + desc P1RIE + 0x178 + 32 + read-only + 0x0 + 0x3 + + + P14 + desc P14 + 4 + 4 + read-only + + + P15 + desc P15 + 5 + 5 + read-only + + + + + P1FIE + desc P1FIE + 0x17C + 32 + read-only + 0x0 + 0x3 + + + P14 + desc P14 + 4 + 4 + read-only + + + P15 + desc P15 + 5 + 5 + read-only + + + + + P2DIR + desc P2DIR + 0x180 + 32 + read-write + 0xFFFFFFFF + 0xF8 + + + P23 + desc P23 + 3 + 3 + read-write + + + P24 + desc P24 + 4 + 4 + read-write + + + P25 + desc P25 + 5 + 5 + read-write + + + P26 + desc P26 + 6 + 6 + read-write + + + P27 + desc P27 + 7 + 7 + read-write + + + + + P2IN + desc P2IN + 0x184 + 32 + read-only + 0x0 + 0x3 + + + P23 + desc P23 + 3 + 3 + read-only + + + P24 + desc P24 + 4 + 4 + read-only + + + P25 + desc P25 + 5 + 5 + read-only + + + P26 + desc P26 + 6 + 6 + read-only + + + P27 + desc P27 + 7 + 7 + read-only + + + + + P2OUT + desc P2OUT + 0x188 + 32 + read-write + 0x0 + 0xF8 + + + P23 + desc P23 + 3 + 3 + read-write + + + P24 + desc P24 + 4 + 4 + read-write + + + P25 + desc P25 + 5 + 5 + read-write + + + P26 + desc P26 + 6 + 6 + read-write + + + P27 + desc P27 + 7 + 7 + read-write + + + + + P2ADS + desc P2ADS + 0x18C + 32 + read-write + 0x0 + 0xF8 + + + P23 + desc P23 + 3 + 3 + read-write + + + P24 + desc P24 + 4 + 4 + read-write + + + P25 + desc P25 + 5 + 5 + read-write + + + P26 + desc P26 + 6 + 6 + read-write + + + P27 + desc P27 + 7 + 7 + read-write + + + + + P2DR + desc P2DR + 0x19C + 32 + read-write + 0x0 + 0xF8 + + + P23 + desc P23 + 3 + 3 + read-write + + + P24 + desc P24 + 4 + 4 + read-write + + + P25 + desc P25 + 5 + 5 + read-write + + + P26 + desc P26 + 6 + 6 + read-write + + + P27 + desc P27 + 7 + 7 + read-write + + + + + P2PU + desc P2PU + 0x1A0 + 32 + read-write + 0x0 + 0xF8 + + + P23 + desc P23 + 3 + 3 + read-write + + + P24 + desc P24 + 4 + 4 + read-write + + + P25 + desc P25 + 5 + 5 + read-write + + + P26 + desc P26 + 6 + 6 + read-write + + + P27 + desc P27 + 7 + 7 + read-write + + + + + P2PD + desc P2PD + 0x1A4 + 32 + read-write + 0x0 + 0xF8 + + + P23 + desc P23 + 3 + 3 + read-write + + + P24 + desc P24 + 4 + 4 + read-write + + + P25 + desc P25 + 5 + 5 + read-write + + + P26 + desc P26 + 6 + 6 + read-write + + + P27 + desc P27 + 7 + 7 + read-write + + + + + P2OD + desc P2OD + 0x1AC + 32 + read-write + 0x0 + 0xF8 + + + P23 + desc P23 + 3 + 3 + read-write + + + P24 + desc P24 + 4 + 4 + read-write + + + P25 + desc P25 + 5 + 5 + read-write + + + P26 + desc P26 + 6 + 6 + read-write + + + P27 + desc P27 + 7 + 7 + read-write + + + + + P2HIE + desc P2HIE + 0x1B0 + 32 + read-only + 0x0 + 0x3 + + + P23 + desc P23 + 3 + 3 + read-only + + + P24 + desc P24 + 4 + 4 + read-only + + + P25 + desc P25 + 5 + 5 + read-only + + + P26 + desc P26 + 6 + 6 + read-only + + + P27 + desc P27 + 7 + 7 + read-only + + + + + P2LIE + desc P2LIE + 0x1B4 + 32 + read-only + 0x0 + 0x3 + + + P23 + desc P23 + 3 + 3 + read-only + + + P24 + desc P24 + 4 + 4 + read-only + + + P25 + desc P25 + 5 + 5 + read-only + + + P26 + desc P26 + 6 + 6 + read-only + + + P27 + desc P27 + 7 + 7 + read-only + + + + + P2RIE + desc P2RIE + 0x1B8 + 32 + read-only + 0x0 + 0x3 + + + P23 + desc P23 + 3 + 3 + read-only + + + P24 + desc P24 + 4 + 4 + read-only + + + P25 + desc P25 + 5 + 5 + read-only + + + P26 + desc P26 + 6 + 6 + read-only + + + P27 + desc P27 + 7 + 7 + read-only + + + + + P2FIE + desc P2FIE + 0x1BC + 32 + read-only + 0x0 + 0x3 + + + P23 + desc P23 + 3 + 3 + read-only + + + P24 + desc P24 + 4 + 4 + read-only + + + P25 + desc P25 + 5 + 5 + read-only + + + P26 + desc P26 + 6 + 6 + read-only + + + P27 + desc P27 + 7 + 7 + read-only + + + + + P3DIR + desc P3DIR + 0x1C0 + 32 + read-write + 0xFFFFFFFF + 0x7E + + + P31 + desc P31 + 1 + 1 + read-write + + + P32 + desc P32 + 2 + 2 + read-write + + + P33 + desc P33 + 3 + 3 + read-write + + + P34 + desc P34 + 4 + 4 + read-write + + + P35 + desc P35 + 5 + 5 + read-write + + + P36 + desc P36 + 6 + 6 + read-write + + + + + P3IN + desc P3IN + 0x1C4 + 32 + read-only + 0x0 + 0x7E + + + P31 + desc P31 + 1 + 1 + read-only + + + P32 + desc P32 + 2 + 2 + read-only + + + P33 + desc P33 + 3 + 3 + read-only + + + P34 + desc P34 + 4 + 4 + read-only + + + P35 + desc P35 + 5 + 5 + read-only + + + P36 + desc P36 + 6 + 6 + read-only + + + + + P3OUT + desc P3OUT + 0x1C8 + 32 + read-write + 0x0 + 0x7E + + + P31 + desc P31 + 1 + 1 + read-write + + + P32 + desc P32 + 2 + 2 + read-write + + + P33 + desc P33 + 3 + 3 + read-write + + + P34 + desc P34 + 4 + 4 + read-write + + + P35 + desc P35 + 5 + 5 + read-write + + + P36 + desc P36 + 6 + 6 + read-write + + + + + P3ADS + desc P3ADS + 0x1CC + 32 + read-write + 0x0 + 0x7E + + + P31 + desc P31 + 1 + 1 + read-write + + + P32 + desc P32 + 2 + 2 + read-write + + + P33 + desc P33 + 3 + 3 + read-write + + + P34 + desc P34 + 4 + 4 + read-write + + + P35 + desc P35 + 5 + 5 + read-write + + + P36 + desc P36 + 6 + 6 + read-write + + + + + P3DR + desc P3DR + 0x1DC + 32 + read-write + 0x0 + 0x7E + + + P31 + desc P31 + 1 + 1 + read-write + + + P32 + desc P32 + 2 + 2 + read-write + + + P33 + desc P33 + 3 + 3 + read-write + + + P34 + desc P34 + 4 + 4 + read-write + + + P35 + desc P35 + 5 + 5 + read-write + + + P36 + desc P36 + 6 + 6 + read-write + + + + + P3PU + desc P3PU + 0x1E0 + 32 + read-write + 0x0 + 0x7E + + + P31 + desc P31 + 1 + 1 + read-write + + + P32 + desc P32 + 2 + 2 + read-write + + + P33 + desc P33 + 3 + 3 + read-write + + + P34 + desc P34 + 4 + 4 + read-write + + + P35 + desc P35 + 5 + 5 + read-write + + + P36 + desc P36 + 6 + 6 + read-write + + + + + P3PD + desc P3PD + 0x1E4 + 32 + read-write + 0x0 + 0x7E + + + P31 + desc P31 + 1 + 1 + read-write + + + P32 + desc P32 + 2 + 2 + read-write + + + P33 + desc P33 + 3 + 3 + read-write + + + P34 + desc P34 + 4 + 4 + read-write + + + P35 + desc P35 + 5 + 5 + read-write + + + P36 + desc P36 + 6 + 6 + read-write + + + + + P3OD + desc P3OD + 0x1EC + 32 + read-write + 0x0 + 0x7E + + + P31 + desc P31 + 1 + 1 + read-write + + + P32 + desc P32 + 2 + 2 + read-write + + + P33 + desc P33 + 3 + 3 + read-write + + + P34 + desc P34 + 4 + 4 + read-write + + + P35 + desc P35 + 5 + 5 + read-write + + + P36 + desc P36 + 6 + 6 + read-write + + + + + P3HIE + desc P3HIE + 0x1F0 + 32 + read-only + 0x0 + 0x7E + + + P31 + desc P31 + 1 + 1 + read-only + + + P32 + desc P32 + 2 + 2 + read-only + + + P33 + desc P33 + 3 + 3 + read-only + + + P34 + desc P34 + 4 + 4 + read-only + + + P35 + desc P35 + 5 + 5 + read-only + + + P36 + desc P36 + 6 + 6 + read-only + + + + + P3LIE + desc P3LIE + 0x1F4 + 32 + read-only + 0x0 + 0x7E + + + P31 + desc P31 + 1 + 1 + read-only + + + P32 + desc P32 + 2 + 2 + read-only + + + P33 + desc P33 + 3 + 3 + read-only + + + P34 + desc P34 + 4 + 4 + read-only + + + P35 + desc P35 + 5 + 5 + read-only + + + P36 + desc P36 + 6 + 6 + read-only + + + + + P3RIE + desc P3RIE + 0x1F8 + 32 + read-only + 0x0 + 0x7E + + + P31 + desc P31 + 1 + 1 + read-only + + + P32 + desc P32 + 2 + 2 + read-only + + + P33 + desc P33 + 3 + 3 + read-only + + + P34 + desc P34 + 4 + 4 + read-only + + + P35 + desc P35 + 5 + 5 + read-only + + + P36 + desc P36 + 6 + 6 + read-only + + + + + P3FIE + desc P3FIE + 0x1FC + 32 + read-only + 0x0 + 0x7E + + + P31 + desc P31 + 1 + 1 + read-only + + + P32 + desc P32 + 2 + 2 + read-only + + + P33 + desc P33 + 3 + 3 + read-only + + + P34 + desc P34 + 4 + 4 + read-only + + + P35 + desc P35 + 5 + 5 + read-only + + + P36 + desc P36 + 6 + 6 + read-only + + + + + P0STAT + desc P0STAT + 0x200 + 32 + read-only + 0x0 + 0xF + + + P00 + desc P00 + 0 + 0 + read-only + + + P01 + desc P01 + 1 + 1 + read-only + + + P02 + desc P02 + 2 + 2 + read-only + + + P03 + desc P03 + 3 + 3 + read-only + + + + + P0ICLR + desc P0ICLR + 0x210 + 32 + read-only + 0x0 + 0xF + + + P00 + desc P00 + 0 + 0 + read-only + + + P01 + desc P01 + 1 + 1 + read-only + + + P02 + desc P02 + 2 + 2 + read-only + + + P03 + desc P03 + 3 + 3 + read-only + + + + + P1STAT + desc P1STAT + 0x240 + 32 + read-only + 0x0 + 0x3 + + + P14 + desc P14 + 4 + 4 + read-only + + + P15 + desc P15 + 5 + 5 + read-only + + + + + P1ICLR + desc P1ICLR + 0x250 + 32 + read-only + 0x0 + 0x3 + + + P14 + desc P14 + 4 + 4 + read-only + + + P15 + desc P15 + 5 + 5 + read-only + + + + + P2STAT + desc P2STAT + 0x280 + 32 + read-only + 0x0 + 0x3 + + + P23 + desc P23 + 3 + 3 + read-only + + + P24 + desc P24 + 4 + 4 + read-only + + + P25 + desc P25 + 5 + 5 + read-only + + + P26 + desc P26 + 6 + 6 + read-only + + + P27 + desc P27 + 7 + 7 + read-only + + + + + P2ICLR + desc P2ICLR + 0x290 + 32 + read-only + 0x0 + 0x3 + + + P23 + desc P23 + 3 + 3 + read-only + + + P24 + desc P24 + 4 + 4 + read-only + + + P25 + desc P25 + 5 + 5 + read-only + + + P26 + desc P26 + 6 + 6 + read-only + + + P27 + desc P27 + 7 + 7 + read-only + + + + + P3STAT + desc P3STAT + 0x2C0 + 32 + read-only + 0x0 + 0x7E + + + P31 + desc P31 + 1 + 1 + read-only + + + P32 + desc P32 + 2 + 2 + read-only + + + P33 + desc P33 + 3 + 3 + read-only + + + P34 + desc P34 + 4 + 4 + read-only + + + P35 + desc P35 + 5 + 5 + read-only + + + P36 + desc P36 + 6 + 6 + read-only + + + + + P3ICLR + desc P3ICLR + 0x2D0 + 32 + read-only + 0x0 + 0x7E + + + P31 + desc P31 + 1 + 1 + read-only + + + P32 + desc P32 + 2 + 2 + read-only + + + P33 + desc P33 + 3 + 3 + read-only + + + P34 + desc P34 + 4 + 4 + read-only + + + P35 + desc P35 + 5 + 5 + read-only + + + P36 + desc P36 + 6 + 6 + read-only + + + + + CTRL0 + desc CTRL0 + 0x300 + 32 + read-write + 0x1 + 0x1 + + + IESEL + desc IESEL + 0 + 0 + read-write + + + + + CTRL1 + desc CTRL1 + 0x304 + 32 + read-write + 0x0 + 0xFFFF + + + EXT_CLK_SEL + desc EXT_CLK_SEL + 3 + 0 + read-write + + + SSN_SEL + desc SSN_SEL + 7 + 4 + read-write + + + PCLK_SEL + desc PCLK_SEL + 9 + 8 + read-write + + + HCLK_SEL + desc HCLK_SEL + 11 + 10 + read-write + + + PCLK_EN + desc PCLK_EN + 12 + 12 + read-write + + + HCLK_EN + desc HCLK_EN + 13 + 13 + read-write + + + IR_POL + desc IR_POL + 14 + 14 + read-write + + + + + CTRL2 + desc CTRL2 + 0x308 + 32 + read-write + 0x0 + 0x3FF + + + PCA_CAP0_SEL + desc PCA_CAP0_SEL + 1 + 0 + read-write + + + PCA_CAP1_SEL + desc PCA_CAP1_SEL + 3 + 2 + read-write + + + PCA_CAP2_SEL + desc PCA_CAP2_SEL + 5 + 4 + read-write + + + PCA_CAP3_SEL + desc PCA_CAP3_SEL + 7 + 6 + read-write + + + PCA_CAP4_SEL + desc PCA_CAP4_SEL + 9 + 8 + read-write + + + + + CTRL3 + desc CTRL3 + 0x30C + 32 + read-write + 0x0 + 0xFFF + + + TM4_B_SEL + desc TM4_B_SEL + 1 + 0 + read-write + + + TM5_B_SEL + desc TM5_B_SEL + 3 + 2 + read-write + + + TM6_B_SEL + desc TM6_B_SEL + 5 + 4 + read-write + + + TM4_A_SEL + desc TM4_A_SEL + 7 + 6 + read-write + + + TM5_A_SEL + desc TM5_A_SEL + 9 + 8 + read-write + + + TM6_A_SEL + desc TM6_A_SEL + 11 + 10 + read-write + + + + + CTRL4 + desc CTRL4 + 0x310 + 32 + read-write + 0x0 + 0xFF + + + TM0_GATE_SEL + desc TM0_GATE_SEL + 1 + 0 + read-write + + + TM1_GATE_SEL + desc TM1_GATE_SEL + 3 + 2 + read-write + + + TM2_GATE_SEL + desc TM2_GATE_SEL + 5 + 4 + read-write + + + TM3_GATE_SEL + desc TM3_GATE_SEL + 7 + 6 + read-write + + + + + + + I2C + desc I2C + 0x40000400 + + 0x0 + 0x18 + + + + TMRUN + desc TMRUN + 0x0 + 32 + read-write + 0x0 + 0x1 + + + TME + desc TME + 0 + 0 + read-write + + + + + TM + desc TM + 0x4 + 32 + read-write + 0x0 + 0xFF + + + TM + desc TM + 7 + 0 + read-write + + + + + CR + desc CR + 0x8 + 32 + read-write + 0x0 + 0x7D + + + H1M + desc H1M + 0 + 0 + read-write + + + AA + desc AA + 2 + 2 + read-write + + + SI + desc SI + 3 + 3 + read-write + + + STO + desc STO + 4 + 4 + read-write + + + STA + desc STA + 5 + 5 + read-write + + + ENS + desc ENS + 6 + 6 + read-write + + + + + DATA + desc DATA + 0xC + 32 + read-write + 0x0 + 0xFF + + + I2CDAT + desc I2CDAT + 7 + 0 + read-write + + + + + ADDR + desc ADDR + 0x10 + 32 + read-write + 0x0 + 0xFF + + + GC + desc GC + 0 + 0 + read-write + + + I2CADR + desc I2CADR + 7 + 1 + read-write + + + + + STAT + desc STAT + 0x14 + 32 + read-only + 0x0 + 0xFF + + + I2CSTA + desc I2CSTA + 7 + 0 + read-only + + + + + + + LPTIMER + desc LPTIMER + 0x40000C00 + BT0 + + 0x0 + 0x78 + + + + CNT + desc CNT + 0x60 + 32 + read-only + 0x0 + 0xFFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + + + ARR + desc ARR + 0x64 + 32 + read-write + 0x0 + 0xFFFF + + + ARR + desc ARR + 15 + 0 + read-write + + + + + CR + desc CR + 0x6C + 32 + read-write + 0x8 + 0x7BF + + + TR + desc TR + 0 + 0 + read-write + + + MD + desc MD + 1 + 1 + read-write + + + CT + desc CT + 2 + 2 + read-write + + + TOG_EN + desc TOG_EN + 3 + 3 + read-write + + + TCK_SEL + desc TCK_SEL + 5 + 4 + read-write + + + WT_FLAG + desc WT_FLAG + 7 + 7 + read-only + + + GATE + desc GATE + 8 + 8 + read-write + + + GATE_P + desc GATE_P + 9 + 9 + read-write + + + IE + desc IE + 10 + 10 + read-write + + + + + IFR + desc IFR + 0x70 + 32 + read-only + 0x0 + 0x1 + + + TF + desc TF + 0 + 0 + read-only + + + + + ICLR + desc ICLR + 0x74 + 32 + write-only + 0x0 + 0x1 + + + TFC + desc TFC + 0 + 0 + write-only + + + + + + + LPUART + desc LPUART + 0x40000200 + + 0x0 + 0x15 + + + + SBUF + desc SBUF + 0x0 + 32 + read-write + 0x0 + 0xFF + + + SBUF + desc SBUF + 7 + 0 + read-write + + + + + SCON + desc SCON + 0x4 + 32 + read-write + 0x0 + 0xFFFF + + + RIEN + desc RIEN + 0 + 0 + read-write + + + TIEN + desc TIEN + 1 + 1 + read-write + + + RB8 + desc RB8 + 2 + 2 + read-write + + + TB8 + desc TB8 + 3 + 3 + read-write + + + REN + desc REN + 4 + 4 + read-write + + + SM2 + desc SM2 + 5 + 5 + read-write + + + SM01 + desc SM01 + 7 + 6 + read-write + + + TEEN + desc TEEN + 8 + 8 + read-write + + + DBAUD + desc DBAUD + 9 + 9 + read-write + + + LPMODE + desc LPMODE + 10 + 10 + read-write + + + SCLKSEL + desc SCLKSEL + 12 + 11 + read-write + + + PRS + desc PRS + 15 + 13 + read-write + + + + + SADDR + desc SADDR + 0x8 + 32 + read-write + 0x0 + 0xFF + + + SADDR + desc SADDR + 7 + 0 + read-write + + + + + SADEN + desc SADEN + 0xC + 32 + read-write + 0x0 + 0xFF + + + SADEN + desc SADEN + 7 + 0 + read-write + + + + + ISR + desc ISR + 0x10 + 32 + read-only + 0x0 + 0xF + + + RI + desc RI + 0 + 0 + read-only + + + TI + desc TI + 1 + 1 + read-only + + + FE + desc FE + 2 + 2 + read-only + + + TE + desc TE + 3 + 3 + read-only + + + + + ICR + desc ICR + 0x14 + 32 + write-only + 0x0 + 0x7 + + + RICLR + desc RICLR + 0 + 0 + write-only + + + TICLR + desc TICLR + 1 + 1 + write-only + + + FECLR + desc FECLR + 2 + 2 + write-only + + + + + + + LVD + desc LVD + 0x40002400 + ADC + + 0x0 + 0x30 + + + + CR + desc CR + 0x28 + 32 + read-write + 0x100 + 0xFFFF + + + LVDEN + desc LVDEN + 0 + 0 + read-write + + + ACT + desc ACT + 1 + 1 + read-write + + + SOURCE_SEL + desc SOURCE_SEL + 3 + 2 + read-write + + + VTDS + desc VTDS + 7 + 4 + read-write + + + FLTEN + desc FLTEN + 8 + 8 + read-write + + + DEBOUNCE_TIME + desc DEBOUNCE_TIME + 11 + 9 + read-write + + + FTEN + desc FTEN + 12 + 12 + read-write + + + RTEN + desc RTEN + 13 + 13 + read-write + + + HTEN + desc HTEN + 14 + 14 + read-write + + + IE + desc IE + 15 + 15 + read-write + + + + + IFR + desc IFR + 0x2C + 32 + read-write + 0x0 + 0x1 + + + INTF + desc INTF + 0 + 0 + read-write + + + + + + + PCA + desc PCA + 0x40001000 + + 0x0 + 0x64 + + + + CCON + desc CCON + 0x0 + 32 + read-write + 0x0 + 0xDF + + + CCF0 + desc CCF0 + 0 + 0 + read-write + + + CCF1 + desc CCF1 + 1 + 1 + read-write + + + CCF2 + desc CCF2 + 2 + 2 + read-write + + + CCF3 + desc CCF3 + 3 + 3 + read-write + + + CCF4 + desc CCF4 + 4 + 4 + read-write + + + CR + desc CR + 6 + 6 + read-write + + + CF + desc CF + 7 + 7 + read-write + + + + + CMOD + desc CMOD + 0x4 + 32 + read-write + 0x0 + 0xDF + + + CFIE + desc CFIE + 0 + 0 + read-write + + + CPS + desc CPS + 3 + 1 + read-write + + + WDTE + desc WDTE + 6 + 6 + read-write + + + CIDL + desc CIDL + 7 + 7 + read-write + + + + + CNT + desc CNT + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + CNT + desc CNT + 15 + 0 + read-write + + + + + ICLR + desc ICLR + 0xC + 32 + write-only + 0x9F + 0x9F + + + CCF0 + desc CCF0 + 0 + 0 + write-only + + + CCF1 + desc CCF1 + 1 + 1 + write-only + + + CCF2 + desc CCF2 + 2 + 2 + write-only + + + CCF3 + desc CCF3 + 3 + 3 + write-only + + + CCF4 + desc CCF4 + 4 + 4 + write-only + + + CF + desc CF + 7 + 7 + write-only + + + + + CCAPM0 + desc CCAPM0 + 0x10 + 32 + read-write + 0x0 + 0x7F + + + CCIE + desc CCIE + 0 + 0 + read-write + + + PWM + desc PWM + 1 + 1 + read-write + + + TOG + desc TOG + 2 + 2 + read-write + + + MAT + desc MAT + 3 + 3 + read-write + + + CAPN + desc CAPN + 4 + 4 + read-write + + + CAPP + desc CAPP + 5 + 5 + read-write + + + ECOM + desc ECOM + 6 + 6 + read-write + + + + + CCAPM1 + desc CCAPM1 + 0x14 + 32 + read-write + 0x0 + 0x7F + + + CCIE + desc CCIE + 0 + 0 + read-write + + + PWM + desc PWM + 1 + 1 + read-write + + + TOG + desc TOG + 2 + 2 + read-write + + + MAT + desc MAT + 3 + 3 + read-write + + + CAPN + desc CAPN + 4 + 4 + read-write + + + CAPP + desc CAPP + 5 + 5 + read-write + + + ECOM + desc ECOM + 6 + 6 + read-write + + + + + CCAPM2 + desc CCAPM2 + 0x18 + 32 + read-write + 0x0 + 0x7F + + + CCIE + desc CCIE + 0 + 0 + read-write + + + PWM + desc PWM + 1 + 1 + read-write + + + TOG + desc TOG + 2 + 2 + read-write + + + MAT + desc MAT + 3 + 3 + read-write + + + CAPN + desc CAPN + 4 + 4 + read-write + + + CAPP + desc CAPP + 5 + 5 + read-write + + + ECOM + desc ECOM + 6 + 6 + read-write + + + + + CCAPM3 + desc CCAPM3 + 0x1C + 32 + read-write + 0x0 + 0x7F + + + CCIE + desc CCIE + 0 + 0 + read-write + + + PWM + desc PWM + 1 + 1 + read-write + + + TOG + desc TOG + 2 + 2 + read-write + + + MAT + desc MAT + 3 + 3 + read-write + + + CAPN + desc CAPN + 4 + 4 + read-write + + + CAPP + desc CAPP + 5 + 5 + read-write + + + ECOM + desc ECOM + 6 + 6 + read-write + + + + + CCAPM4 + desc CCAPM4 + 0x20 + 32 + read-write + 0x0 + 0x7F + + + CCIE + desc CCIE + 0 + 0 + read-write + + + PWM + desc PWM + 1 + 1 + read-write + + + TOG + desc TOG + 2 + 2 + read-write + + + MAT + desc MAT + 3 + 3 + read-write + + + CAPN + desc CAPN + 4 + 4 + read-write + + + CAPP + desc CAPP + 5 + 5 + read-write + + + ECOM + desc ECOM + 6 + 6 + read-write + + + + + CCAP0H + desc CCAP0H + 0x24 + 32 + read-write + 0x0 + 0xFF + + + CCAP0 + desc CCAP0 + 7 + 0 + read-write + + + + + CCAP0L + desc CCAP0L + 0x28 + 32 + read-write + 0x0 + 0xFF + + + CCAP0 + desc CCAP0 + 7 + 0 + read-write + + + + + CCAP1H + desc CCAP1H + 0x2C + 32 + read-write + 0x0 + 0xFF + + + CCAP1 + desc CCAP1 + 7 + 0 + read-write + + + + + CCAP1L + desc CCAP1L + 0x30 + 32 + read-write + 0x0 + 0xFF + + + CCAP1 + desc CCAP1 + 7 + 0 + read-write + + + + + CCAP2H + desc CCAP2H + 0x34 + 32 + read-write + 0x0 + 0xFF + + + CCAP2 + desc CCAP2 + 7 + 0 + read-write + + + + + CCAP2L + desc CCAP2L + 0x38 + 32 + read-write + 0x0 + 0xFF + + + CCAP2 + desc CCAP2 + 7 + 0 + read-write + + + + + CCAP3H + desc CCAP3H + 0x3C + 32 + read-write + 0x0 + 0xFF + + + CCAP3 + desc CCAP3 + 7 + 0 + read-write + + + + + CCAP3L + desc CCAP3L + 0x40 + 32 + read-write + 0x0 + 0xFF + + + CCAP3 + desc CCAP3 + 7 + 0 + read-write + + + + + CCAP4H + desc CCAP4H + 0x44 + 32 + read-write + 0x0 + 0xFF + + + CCAP4 + desc CCAP4 + 7 + 0 + read-write + + + + + CCAP4L + desc CCAP4L + 0x48 + 32 + read-write + 0x0 + 0xFF + + + CCAP4 + desc CCAP4 + 7 + 0 + read-write + + + + + CCAPO + desc CCAPO + 0x4C + 32 + read-write + 0x0 + 0x1F + + + CCAPO0 + desc CCAPO0 + 0 + 0 + read-write + + + CCAPO1 + desc CCAPO1 + 1 + 1 + read-write + + + CCAPO2 + desc CCAPO2 + 2 + 2 + read-write + + + CCAPO3 + desc CCAPO3 + 3 + 3 + read-write + + + CCAPO4 + desc CCAPO4 + 4 + 4 + read-write + + + + + CCAP0 + desc CCAP0 + 0x50 + 32 + read-write + 0x0 + 0xFFFF + + + CCAP0 + desc CCAP0 + 15 + 0 + read-write + + + + + CCAP1 + desc CCAP1 + 0x54 + 32 + read-write + 0x0 + 0xFFFF + + + CCAP1 + desc CCAP1 + 15 + 0 + read-write + + + + + CCAP2 + desc CCAP2 + 0x58 + 32 + read-write + 0x0 + 0xFFFF + + + CCAP2 + desc CCAP2 + 15 + 0 + read-write + + + + + CCAP3 + desc CCAP3 + 0x5C + 32 + read-write + 0x0 + 0xFFFF + + + CCAP3 + desc CCAP3 + 15 + 0 + read-write + + + + + CCAP4 + desc CCAP4 + 0x60 + 32 + read-write + 0x0 + 0xFFFF + + + CCAP4 + desc CCAP4 + 15 + 0 + read-write + + + + + + + RAM + desc RAM + 0x40020400 + + 0x0 + 0x10 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x3 + + + CHKEN + desc CHKEN + 0 + 0 + read-write + + + IE + desc IE + 1 + 1 + read-write + + + + + ERRADDR + desc ERRADDR + 0x4 + 32 + read-only + 0x0 + 0xFFF + + + ERRADDR + desc ERRADDR + 11 + 0 + read-only + + + + + IFR + desc IFR + 0x8 + 32 + read-only + 0x0 + 0x1 + + + ERR + desc ERR + 0 + 0 + read-only + + + + + ICLR + desc ICLR + 0xC + 32 + read-only + 0x0 + 0x1 + + + ERRCLR + desc ERRCLR + 0 + 0 + write-only + + + + + + + RESET + desc RESET + 0x4000201C + + 0x0 + 0xF + + + + RESET_FLAG + desc RESET_FLAG + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + POR5V + desc POR5V + 0 + 0 + read-write + + + POR15V + desc POR15V + 1 + 1 + read-write + + + LVD + desc LVD + 2 + 2 + read-write + + + WDT + desc WDT + 3 + 3 + read-write + + + PCA + desc PCA + 4 + 4 + read-write + + + LOCKUP + desc LOCKUP + 5 + 5 + read-write + + + SYSREQ + desc SYSREQ + 6 + 6 + read-write + + + RSTB + desc RSTB + 7 + 7 + read-write + + + + + PREI_RESET + desc PREI_RESET + 0xC + 32 + read-write + 0xFFFFFFFF + 0xBFFF7FFF + + + UART0 + desc UART0 + 0 + 0 + read-write + + + UART1 + desc UART1 + 1 + 1 + read-write + + + LPUART + desc LPUART + 2 + 2 + read-write + + + I2C + desc I2C + 4 + 4 + read-write + + + SPI + desc SPI + 6 + 6 + read-write + + + BASETIM + desc BASETIM + 8 + 8 + read-write + + + LPTIM + desc LPTIM + 9 + 9 + read-write + + + ADVTIM + desc ADVTIM + 10 + 10 + read-write + + + PCA + desc PCA + 14 + 14 + read-write + + + ADC + desc ADC + 16 + 16 + read-write + + + VC + desc VC + 17 + 17 + read-write + + + RTC + desc RTC + 20 + 20 + read-write + + + TRIM + desc TRIM + 21 + 21 + read-write + + + TICK + desc TICK + 24 + 24 + read-write + + + CRC + desc CRC + 26 + 26 + read-write + + + GPIO + desc GPIO + 28 + 28 + read-write + + + + + + + RTC + desc RTC + 0x40001400 + + 0x0 + 0x32 + + + + CR0 + desc CR0 + 0x0 + 32 + read-write + 0x0 + 0x7FEF + + + PRDS + desc PRDS + 2 + 0 + read-write + + + AMPM + desc AMPM + 3 + 3 + read-write + + + HZ1OE + desc HZ1OE + 5 + 5 + read-write + + + HZ1SEL + desc HZ1SEL + 6 + 6 + read-write + + + START + desc START + 7 + 7 + read-write + + + PRDX + desc PRDX + 13 + 8 + read-write + + + PRDSEL + desc PRDSEL + 14 + 14 + read-write + + + + + CR1 + desc CR1 + 0x4 + 32 + read-write + 0x0 + 0x7FB + + + WAIT + desc WAIT + 0 + 0 + read-write + + + WAITF + desc WAITF + 1 + 1 + read-write + + + PRDF + desc PRDF + 3 + 3 + read-write + + + ALMF + desc ALMF + 4 + 4 + read-write + + + ALMIE + desc ALMIE + 6 + 6 + read-write + + + ALMEN + desc ALMEN + 7 + 7 + read-write + + + CKSEL + desc CKSEL + 10 + 8 + read-write + + + + + SEC + desc SEC + 0x8 + 32 + read-write + 0x0 + 0x7F + + + SECL + desc SECL + 3 + 0 + read-write + + + SECH + desc SECH + 6 + 4 + read-write + + + + + MIN + desc MIN + 0xC + 32 + read-write + 0x0 + 0x7F + + + MINL + desc MINL + 3 + 0 + read-write + + + MINH + desc MINH + 6 + 4 + read-write + + + + + HOUR + desc HOUR + 0x10 + 32 + read-write + 0x0 + 0x7F + + + HOURL + desc HOURL + 3 + 0 + read-write + + + HOURH + desc HOURH + 5 + 4 + read-write + + + + + WEEK + desc WEEK + 0x14 + 32 + read-write + 0x0 + 0x7 + + + WEEK + desc WEEK + 2 + 0 + read-write + + + + + DAY + desc DAY + 0x18 + 32 + read-write + 0x0 + 0x3F + + + DAYL + desc DAYL + 3 + 0 + read-write + + + DAYH + desc DAYH + 5 + 4 + read-write + + + + + MON + desc MON + 0x1C + 32 + read-write + 0x0 + 0x1F + + + MON + desc MON + 4 + 0 + read-write + + + + + YEAR + desc YEAR + 0x20 + 32 + read-write + 0x0 + 0xFF + + + YEARL + desc YEARL + 3 + 0 + read-write + + + YEARH + desc YEARH + 7 + 4 + read-write + + + + + ALMMIN + desc ALMMIN + 0x24 + 32 + read-write + 0x0 + 0x7F + + + ALMMINL + desc ALMMINL + 3 + 0 + read-write + + + ALMMINH + desc ALMMINH + 6 + 4 + read-write + + + + + ALMHOUR + desc ALMHOUR + 0x28 + 32 + read-write + 0x0 + 0x3F + + + ALMHOURL + desc ALMHOURL + 3 + 0 + read-write + + + ALMHOURH + desc ALMHOURH + 5 + 4 + read-write + + + + + ALMWEEK + desc ALMWEEK + 0x2C + 32 + read-write + 0x0 + 0x7F + + + ALMWEEK + desc ALMWEEK + 6 + 0 + read-write + + + + + COMPEN + desc COMPEN + 0x30 + 32 + read-write + 0x20 + 0x81FF + + + CR + desc CR + 8 + 0 + read-write + + + EN + desc EN + 15 + 15 + read-write + + + + + + + SPI + desc SPI + 0x40000800 + + 0x0 + 0x10 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0xDF + + + SPR0 + desc SPR0 + 0 + 0 + read-write + + + SPR1 + desc SPR1 + 1 + 1 + read-write + + + CPHA + desc CPHA + 2 + 2 + read-write + + + CPOL + desc CPOL + 3 + 3 + read-write + + + MSTR + desc MSTR + 4 + 4 + read-write + + + SPEN + desc SPEN + 6 + 6 + read-write + + + SPR2 + desc SPR2 + 7 + 7 + read-write + + + + + SSN + desc SSN + 0x4 + 32 + read-write + 0x0 + 0x1 + + + SSN + desc SSN + 0 + 0 + read-write + + + + + STAT + desc STAT + 0x8 + 32 + read-only + 0x0 + 0xF0 + + + MDF + desc MDF + 4 + 4 + read-only + + + SSERR + desc SSERR + 5 + 5 + read-only + + + WCOL + desc WCOL + 6 + 6 + read-only + + + SPIF + desc SPIF + 7 + 7 + read-only + + + + + DATA + desc DATA + 0xC + 32 + read-write + 0x0 + 0xFF + + + SPDAT + desc SPDAT + 7 + 0 + read-write + + + + + + + UART0 + desc UART + 0x40000000 + + 0x0 + 0x15 + + + + SBUF + desc SBUF + 0x0 + 32 + read-write + 0x0 + 0xFF + + + SBUF + desc SBUF + 7 + 0 + read-write + + + + + SCON + desc SCON + 0x4 + 32 + read-write + 0x0 + 0x2FF + + + RIEN + desc RIEN + 0 + 0 + read-write + + + TIEN + desc TIEN + 1 + 1 + read-write + + + RB8 + desc RB8 + 2 + 2 + read-write + + + TB8 + desc TB8 + 3 + 3 + read-write + + + REN + desc REN + 4 + 4 + read-write + + + SM2 + desc SM2 + 5 + 5 + read-write + + + SM01 + desc SM01 + 7 + 6 + read-write + + + DBAUD + desc DBAUD + 9 + 9 + read-write + + + + + SADDR + desc SADDR + 0x8 + 32 + read-write + 0x0 + 0xFF + + + SADDR + desc SADDR + 7 + 0 + read-write + + + + + SADEN + desc SADEN + 0xC + 32 + read-write + 0x0 + 0xFF + + + SADEN + desc SADEN + 7 + 0 + read-write + + + + + ISR + desc ISR + 0x10 + 32 + read-only + 0x0 + 0xF + + + RI + desc RI + 0 + 0 + read-only + + + TI + desc TI + 1 + 1 + read-only + + + FE + desc FE + 2 + 2 + read-only + + + TE + desc TE + 3 + 3 + read-only + + + + + ICR + desc ICR + 0x14 + 32 + write-only + 0x0 + 0x7 + + + RICLR + desc RICLR + 0 + 0 + read-write + + + TICLR + desc TICLR + 1 + 1 + read-write + + + FECLR + desc FECLR + 2 + 2 + write-only + + + + + + + UART1 + desc UART + 0x40000100 + + 0x0 + 0x15 + + + + VC + desc VC + 0x40002400 + ADC + + 0x0 + 0x28 + + + + CR + desc CR + 0x10 + 32 + read-write + 0x20 + 0xFFFF + + + DIV + desc DIV + 5 + 0 + read-write + + + DIV_EN + desc DIV_EN + 6 + 6 + read-write + + + REF2P5_SEL + desc REF2P5_SEL + 7 + 7 + read-write + + + VC0_BIAS_SEL + desc VC0_BIAS_SEL + 9 + 8 + read-write + + + VC0_HYS_SEL + desc VC0_HYS_SEL + 11 + 10 + read-write + + + VC1_BIAS_SEL + desc VC1_BIAS_SEL + 13 + 12 + read-write + + + VC1_HYS_SEL + desc VC1_HYS_SEL + 15 + 14 + read-write + + + + + VC0_CR + desc VC0_CR + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + EN + desc EN + 0 + 0 + read-write + + + P_SEL + desc P_SEL + 3 + 1 + read-write + + + N_SEL + desc N_SEL + 7 + 4 + read-write + + + FLTEN + desc FLTEN + 8 + 8 + read-write + + + DEBOUNCE_TIME + desc DEBOUNCE_TIME + 11 + 9 + read-write + + + FALLING + desc FALLING + 12 + 12 + read-write + + + RISING + desc RISING + 13 + 13 + read-write + + + LEVEL + desc LEVEL + 14 + 14 + read-write + + + IE + desc IE + 15 + 15 + read-write + + + + + VC1_CR + desc VC1_CR + 0x18 + 32 + read-write + 0x0 + 0xFFFF + + + EN + desc EN + 0 + 0 + read-write + + + P_SEL + desc P_SEL + 3 + 1 + read-write + + + N_SEL + desc N_SEL + 7 + 4 + read-write + + + FLTEN + desc FLTEN + 8 + 8 + read-write + + + DEBOUNCE_TIME + desc DEBOUNCE_TIME + 11 + 9 + read-write + + + FALLING + desc FALLING + 12 + 12 + read-write + + + RISING + desc RISING + 13 + 13 + read-write + + + LEVEL + desc LEVEL + 14 + 14 + read-write + + + IE + desc IE + 15 + 15 + read-write + + + + + VC0_OUT_CFG + desc VC0_OUT_CFG + 0x1C + 32 + read-write + 0x0 + 0xFFFF + + + INV_TIMER + desc INV_TIMER + 0 + 0 + read-write + + + TIM0G + desc TIM0G + 1 + 1 + read-write + + + TIM1G + desc TIM1G + 2 + 2 + read-write + + + TIM2G + desc TIM2G + 3 + 3 + read-write + + + TIM3G + desc TIM3G + 4 + 4 + read-write + + + TIM3ECLK + desc TIM3ECLK + 5 + 5 + read-write + + + INV_PCA + desc INV_PCA + 6 + 6 + read-write + + + PCACAP0 + desc PCACAP0 + 7 + 7 + read-write + + + PCAECI + desc PCAECI + 8 + 8 + read-write + + + INV_TIM4 + desc INV_TIM4 + 9 + 9 + read-write + + + TIM4 + desc TIM4 + 10 + 10 + read-write + + + INV_TIM5 + desc INV_TIM5 + 11 + 11 + read-write + + + TIM5 + desc TIM5 + 12 + 12 + read-write + + + INV_TIM6 + desc INV_TIM6 + 13 + 13 + read-write + + + TIM6 + desc TIM6 + 14 + 14 + read-write + + + BRAKE + desc BRAKE + 15 + 15 + read-write + + + + + VC1_OUT_CFG + desc VC1_OUT_CFG + 0x20 + 32 + read-write + 0x0 + 0xFFFF + + + INV_TIMER + desc INV_TIMER + 0 + 0 + read-write + + + TIM0G + desc TIM0G + 1 + 1 + read-write + + + TIM1G + desc TIM1G + 2 + 2 + read-write + + + TIM2G + desc TIM2G + 3 + 3 + read-write + + + TIM3G + desc TIM3G + 4 + 4 + read-write + + + TIM3ECLK + desc TIM3ECLK + 5 + 5 + read-write + + + INV_PCA + desc INV_PCA + 6 + 6 + read-write + + + PCACAP0 + desc PCACAP0 + 7 + 7 + read-write + + + PCAECI + desc PCAECI + 8 + 8 + read-write + + + INV_TIM4 + desc INV_TIM4 + 9 + 9 + read-write + + + TIM4 + desc TIM4 + 10 + 10 + read-write + + + INV_TIM5 + desc INV_TIM5 + 11 + 11 + read-write + + + TIM5 + desc TIM5 + 12 + 12 + read-write + + + INV_TIM6 + desc INV_TIM6 + 13 + 13 + read-write + + + TIM6 + desc TIM6 + 14 + 14 + read-write + + + BRAKE + desc BRAKE + 15 + 15 + read-write + + + + + IFR + desc IFR + 0x24 + 32 + read-write + 0x0 + 0xF + + + VC0_INTF + desc VC0_INTF + 0 + 0 + read-write + + + VC1_INTF + desc VC1_INTF + 1 + 1 + read-write + + + VC0_FILTER + desc VC0_FILTER + 2 + 2 + read-only + + + VC1_FILTER + desc VC1_FILTER + 3 + 3 + read-only + + + + + + + WDT + desc WDT + 0x40000C00 + BT0 + + 0x0 + 0x86 + + + + RST + desc RST + 0x80 + 32 + write-only + 0x0 + 0xFF + + + WDTRST + desc WDTRST + 7 + 0 + write-only + + + + + CON + desc CON + 0x84 + 32 + read-write + 0xF + 0xFFBF + + + WOV + desc WOV + 3 + 0 + read-write + + + WDTR + desc WDTR + 4 + 4 + read-only + + + WINT_EN + desc WINT_EN + 5 + 5 + read-write + + + WDINT + desc WDINT + 7 + 7 + read-only + + + WCNTL + desc WCNTL + 15 + 8 + read-only + + + + + + + diff --git a/port/hdsc/hc32l110/src/hal.zig b/port/hdsc/hc32l110/src/hal.zig new file mode 100644 index 000000000..ead4d05d2 --- /dev/null +++ b/port/hdsc/hc32l110/src/hal.zig @@ -0,0 +1,38 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const cpu = microzig.cpu; +const chip = microzig.chip; + +pub const time = @import("hal/time.zig"); +pub const gpio = @import("hal/gpio.zig"); +pub const clocks = @import("hal/clocks.zig"); +pub const crc16 = @import("hal/crc16.zig"); +pub const spi = @import("hal/spi.zig"); +pub const uart = @import("hal/uart.zig"); +pub const i2c = @import("hal/i2c.zig"); +pub const drivers = @import("hal/drivers.zig"); + +pub inline fn init() void { + const CLOCK = chip.peripherals.CLOCK; + clocks.set_rch_frequency(.@"24MHz"); + clocks.enable(.InternalHighSpeed, true); + // TODO: hide pins on 20-pin mcu + + // TODO: move this to seprate function + CLOCK.PERI_CLKEN.modify(.{ + .TICK = 1, + }); + CLOCK.SYSTICK_CR.modify(.{ + .CLK_SEL = 0x2, // RCH + .NOREF = 1, + }); + cpu.peripherals.systick.LOAD.modify(.{ + .RELOAD = 4_000_000 / 1000, // 1ms tick rate + }); + cpu.peripherals.systick.VAL.modify(.{ + .CURRENT = 0, // 1ms tick rate + }); + cpu.peripherals.systick.CTRL.modify(.{ + .ENABLE = 1, + }); +} diff --git a/port/hdsc/hc32l110/src/hal/clocks.zig b/port/hdsc/hc32l110/src/hal/clocks.zig new file mode 100644 index 000000000..984eef46f --- /dev/null +++ b/port/hdsc/hc32l110/src/hal/clocks.zig @@ -0,0 +1,123 @@ +const microzig = @import("microzig"); +const chip = microzig.chip; + +const CLOCK = chip.peripherals.CLOCK; +const GPIO = chip.peripherals.GPIO; + +pub const RchFrequency = enum(u11) { + @"32768", + @"38_4K", + @"4MHz", + @"8MHz", + @"16MHz", + @"22_2MHz", + @"24MHz", + _, +}; + +pub const ClockSource = enum { + /// RCH + InternalHighSpeed, + /// XTH + ExternalHighSpeed, + /// RCL + InternalLowSpeed, + /// XTL + ExternalLowSpeed, +}; + +pub fn set_rch_frequency(frequency: RchFrequency) void { + const address: usize = switch (frequency) { + .@"32768" => 0x00100C22, + .@"38_4K" => 0x00100C20, + .@"4MHz" => 0x00100C08, + .@"8MHz" => 0x00100C06, + .@"16MHz" => 0x00100C04, + .@"22_2MHz" => 0x00100C02, + .@"24MHz" => 0x00100C00, + else => @panic("unsupported frequency"), + }; + const trim_ptr: *volatile u16 = @ptrFromInt(address); + + CLOCK.RCH_CR.modify(.{ + .TRIM = @as(u11, @truncate(trim_ptr.*)), + }); +} + +pub inline fn unlock() void { + CLOCK.SYSCTRL2.write(.{ .SYSCTRL2 = 0x5A5A }); + CLOCK.SYSCTRL2.write(.{ .SYSCTRL2 = 0xA5A5 }); +} + +pub fn enable(c: ClockSource, en: bool) void { + unlock(); + switch (c) { + .ExternalLowSpeed => { + CLOCK.PERI_CLKEN.modify(.{ + .GPIO = 1, + }); + GPIO.P1ADS.modify(.{ + .P14 = @intFromBool(en), + .P15 = @intFromBool(en), + }); + CLOCK.XTL_CR.modify(.{ + .DRIVER = 0xf, + }); + CLOCK.SYSCTRL0.modify(.{ + .XTL_EN = @intFromBool(en), + }); + }, + .InternalLowSpeed => { + CLOCK.SYSCTRL0.modify(.{ .RCL_EN = @intFromBool(en) }); + }, + .ExternalHighSpeed => { + CLOCK.PERI_CLKEN.modify(.{ + .GPIO = 1, + }); + GPIO.P1ADS.modify(.{ + .P14 = @intFromBool(en), + .P15 = @intFromBool(en), + }); + CLOCK.XTH_CR.modify(.{ + .DRIVER = 0xf, + }); + CLOCK.SYSCTRL0.modify(.{ + .XTH_EN = @intFromBool(en), + }); + }, + .InternalHighSpeed => { + CLOCK.SYSCTRL0.modify(.{ .RCH_EN = @intFromBool(en) }); + }, + } +} + +pub const gate = struct { + pub const ClockGate = enum(u5) { + Uart0 = 0, + Uart1 = 1, + LpUart = 2, + I2c = 4, + Spi = 6, + BaseTim = 8, + LpTim = 9, + Adt = 10, + Pca = 14, + Wdt = 15, + AdcBgr = 16, + VcLvd = 17, + Rtc = 20, + ClkTrim = 21, + Tick = 24, + Crc = 26, + Gpio = 28, + Flash = 31, + }; + + pub inline fn enable(clock_gate: ClockGate) void { + CLOCK.PERI_CLKEN.write_bit(@intFromEnum(clock_gate), 1); + } + + pub inline fn disable(clock_gate: ClockGate) void { + CLOCK.PERI_CLKEN.write_bit(@intFromEnum(clock_gate), 0); + } +}; diff --git a/port/hdsc/hc32l110/src/hal/crc16.zig b/port/hdsc/hc32l110/src/hal/crc16.zig new file mode 100644 index 000000000..ae408456f --- /dev/null +++ b/port/hdsc/hc32l110/src/hal/crc16.zig @@ -0,0 +1,37 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const chip = microzig.chip; + +const CRC = chip.peripherals.CRC; + +pub fn calculate(T: type, data: []const T) u16 { + switch (T) { + u8, u16, u32 => {}, + else => @compileError("unsupported type"), + } + + CRC.RESULT.write(.{ .RESULT = 0xffff, .FLAG = 0 }); + + const ptr: *volatile T = @ptrCast(&CRC.DATA); + for (data) |d| { + ptr.* = d; + } + + return CRC.RESULT.read().RESULT; +} + +pub fn check(T: type, data: []const T, value: u16) bool { + switch (T) { + u8, u16, u32 => {}, + else => @compileError("unsupported type"), + } + + CRC.RESULT.write(.{ .RESULT = value, .FLAG = 0 }); + + const ptr: *volatile T = @ptrCast(&CRC.DATA); + for (data) |d| { + ptr.* = d; + } + + return CRC.RESULT.read().FLAG == 1; +} diff --git a/port/hdsc/hc32l110/src/hal/drivers.zig b/port/hdsc/hc32l110/src/hal/drivers.zig new file mode 100644 index 000000000..d56853c09 --- /dev/null +++ b/port/hdsc/hc32l110/src/hal/drivers.zig @@ -0,0 +1,104 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const hal = @import("../hal.zig"); + +const drivers = microzig.drivers.base; +const time = microzig.drivers.time; + +const Datagram_Device = drivers.Datagram_Device; + +/// +/// A datagram device attached to an I²C bus. +/// +pub const I2C_Device = struct { + pub const ConnectError = Datagram_Device.ConnectError; + pub const WriteError = Datagram_Device.WriteError; + pub const ReadError = Datagram_Device.ReadError; + + /// Selects I²C bus should be used. + bus: hal.i2c.I2C, + + /// The address of our I²C device. + address: hal.i2c.Address, + + pub fn init(bus: hal.i2c.I2C, address: hal.i2c.Address) I2C_Device { + return .{ + .bus = bus, + .address = address, + }; + } + + pub fn datagram_device(dev: *I2C_Device) Datagram_Device { + return .{ + .ptr = dev, + .vtable = &vtable, + }; + } + + pub fn connect(dev: I2C_Device) ConnectError!void { + _ = dev; + } + + pub fn disconnect(dev: I2C_Device) void { + _ = dev; + } + + pub fn write(dev: I2C_Device, datagram: []const u8) !void { + try dev.bus.write_blocking(dev.address, datagram, null); + } + + pub fn writev(dev: I2C_Device, datagrams: []const []const u8) !void { + try dev.bus.writev_blocking(dev.address, datagrams, null); + } + + pub fn read(dev: I2C_Device, datagram: []u8) !usize { + try dev.bus.read_blocking(dev.address, datagram, null); + return datagram.len; + } + + pub fn readv(dev: I2C_Device, datagrams: []const []u8) !usize { + try dev.bus.readv_blocking(dev.address, datagrams, null); + return microzig.utilities.Slice_Vector([]u8).init(datagrams).size(); + } + + const vtable = Datagram_Device.VTable{ + .connect_fn = null, + .disconnect_fn = null, + .writev_fn = writev_fn, + .readv_fn = readv_fn, + }; + + fn writev_fn(dd: *anyopaque, chunks: []const []const u8) WriteError!void { + const dev: *I2C_Device = @ptrCast(@alignCast(dd)); + return dev.writev(chunks) catch |err| switch (err) { + error.DeviceNotPresent, + error.NoAcknowledge, + error.TargetAddressReserved, + => return error.Unsupported, + + error.UnknownAbort, + error.TxFifoFlushed, + => return error.IoError, + + error.Timeout => return error.Timeout, + error.NoData => {}, + }; + } + + fn readv_fn(dd: *anyopaque, chunks: []const []u8) ReadError!usize { + const dev: *I2C_Device = @ptrCast(@alignCast(dd)); + return dev.readv(chunks) catch |err| switch (err) { + error.DeviceNotPresent, + error.NoAcknowledge, + error.TargetAddressReserved, + => return error.Unsupported, + + error.UnknownAbort, + error.TxFifoFlushed, + => return error.IoError, + + error.Timeout => return error.Timeout, + error.NoData => return 0, + }; + } +}; diff --git a/port/hdsc/hc32l110/src/hal/gpio.zig b/port/hdsc/hc32l110/src/hal/gpio.zig new file mode 100644 index 000000000..fce2028af --- /dev/null +++ b/port/hdsc/hc32l110/src/hal/gpio.zig @@ -0,0 +1,115 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const Mmio = microzig.mmio.Mmio; +const chip = microzig.chip; + +pub const Direction = enum(u1) { + out = 0, + in = 1, +}; + +pub const Pull = enum { + up, + down, + disabled, +}; + +pub const Enabled = enum(u1) { + disabled = 0, + enabled = 1, +}; + +pub const DriveStrength = enum(u1) { + high = 0, + normal = 1, +}; + +const gpio_block_size = 64; +const gpio_port_count = 4; +const max_pin_number = 10; + +const GenericGpioBlock = extern struct { + reg: Mmio(u32) align(4), + padding: [gpio_block_size - @sizeOf(u32)]u8 align(4), +}; + +const SelGpioBlock = extern struct { + reg: [max_pin_number]Mmio(u32) align(4), + padding: [gpio_block_size - (@sizeOf(u32) * max_pin_number)]u8 align(4), +}; + +comptime { + std.debug.assert(@sizeOf(GenericGpioBlock) == gpio_block_size); + std.debug.assert(@sizeOf(SelGpioBlock) == gpio_block_size); +} + +const IN: *volatile [gpio_port_count]GenericGpioBlock align(4) = @ptrCast(&chip.peripherals.GPIO.P0IN); +const OUT: *volatile [gpio_port_count]GenericGpioBlock align(4) = @ptrCast(&chip.peripherals.GPIO.P0OUT); +const DIR: *volatile [gpio_port_count]GenericGpioBlock align(4) = @ptrCast(&chip.peripherals.GPIO.P0DIR); +const PU: *volatile [gpio_port_count]GenericGpioBlock align(4) = @ptrCast(&chip.peripherals.GPIO.P0PU); +const PD: *volatile [gpio_port_count]GenericGpioBlock align(4) = @ptrCast(&chip.peripherals.GPIO.P0PD); +const OD: *volatile [gpio_port_count]GenericGpioBlock align(4) = @ptrCast(&chip.peripherals.GPIO.P0OD); +const DR: *volatile [gpio_port_count]GenericGpioBlock align(4) = @ptrCast(&chip.peripherals.GPIO.P0DR); +const ADS: *volatile [gpio_port_count]GenericGpioBlock align(4) = @ptrCast(&chip.peripherals.GPIO.P0ADS); +// TODO: patch the svd instead of doing pointer math here +const SEL: *volatile [gpio_port_count]SelGpioBlock align(4) = @ptrFromInt(@intFromPtr(&chip.peripherals.GPIO.P01_SEL) - 4); + +pub const Pin = enum(u5) { + _, + + pub inline fn init(self: Pin, direction: Direction) void { + self.set_function(0); // gpio + self.set_direction(direction); + self.set_pull(.disabled); + self.set_open_drain(.disabled); + } + + pub inline fn put(self: Pin, value: u1) void { + OUT[self.port()].reg.write_bit(self.pin(), value); + } + + pub inline fn toggle(self: Pin) void { + OUT[self.port()].reg.toggle_bit(self.pin()); + } + + pub inline fn read(self: Pin) u1 { + return IN[self.port()].reg.read_bit(self.pin()); + } + + pub inline fn set_direction(self: Pin, direction: Direction) void { + DIR[self.port()].reg.write_bit(self.pin(), @intFromEnum(direction)); + } + + pub inline fn set_function(self: Pin, function: u5) void { + SEL[self.port()].reg[self.pin()].raw = function; + } + + pub inline fn set_pull(self: Pin, pull: Pull) void { + PU[self.port()].reg.write_bit(self.pin(), @intFromBool(pull == .up)); + PD[self.port()].reg.write_bit(self.pin(), @intFromBool(pull == .down)); + } + + pub inline fn set_open_drain(self: Pin, enabled: Enabled) void { + OD[self.port()].reg.write_bit(self.pin(), @intFromEnum(enabled)); + } + + pub inline fn set_drive_strength(self: Pin, drive_strength: DriveStrength) void { + DR[self.port()].reg.write_bit(self.pin(), @intFromEnum(drive_strength)); + } + + pub inline fn set_analog(self: Pin, enabled: Enabled) void { + ADS[self.port()].reg.write_bit(self.pin(), @intFromEnum(enabled)); + } + + inline fn port(self: Pin) u2 { + return @truncate(@intFromEnum(self) >> 3); + } + + inline fn pin(self: Pin) u3 { + return @truncate(@intFromEnum(self)); + } +}; + +pub fn num(port: u2, n: u3) Pin { + return @enumFromInt(@as(u5, port) << 3 | (n)); +} diff --git a/port/hdsc/hc32l110/src/hal/i2c.zig b/port/hdsc/hc32l110/src/hal/i2c.zig new file mode 100644 index 000000000..aa282aa41 --- /dev/null +++ b/port/hdsc/hc32l110/src/hal/i2c.zig @@ -0,0 +1,289 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const mdf = microzig.drivers; +const I2C_Device = microzig.hal.drivers.I2C_Device; +const peripherals = microzig.chip.peripherals; + +const I2C0 = peripherals.I2C; +const RESET = microzig.chip.peripherals.RESET; + +pub const Config = struct { + baud: u8, +}; + +/// +/// 7-bit I²C address, without the read/write bit. +/// +pub const Address = enum(u7) { + /// The general call addresses all devices on the bus using the I²C address 0. + pub const general_call: Address = @enumFromInt(0x00); + + _, + + pub fn new(addr: u7) Address { + const a: Address = @enumFromInt(addr); + std.debug.assert(!is_reserved(addr)); + return a; + } + + /// + /// Returns `true` if the Address is a reserved I²C address. + /// + /// Reserved addresses are ones that match `0b0000XXX` or `0b1111XXX`. + /// + /// See more here: https://www.i2c-bus.org/addressing/ + pub fn is_reserved(addr: u7) bool { + return ((addr & 0x78) == 0) or ((addr & 0x78) == 0x78); + } + + pub fn format(addr: Address, fmt: []const u8, options: std.fmt.FormatOptions, writer: anytype) !void { + _ = fmt; + _ = options; + try writer.print("I2C(0x{X:0>2})", .{@intFromEnum(addr)}); + } +}; + +const i2c = @This(); + +pub const instance = struct { + pub const I2C: i2c.I2C = @enumFromInt(0); + pub fn num(instance_number: u1) i2c.I2C { + std.debug.assert(instance_number == 0); + return @enumFromInt(instance_number); + } +}; + +pub const TransactionError = error{ + NoAcknowledge, + Timeout, + TargetAddressReserved, + NoData, +}; + +pub const ConfigError = error{ + UnsupportedBaudRate, +}; + +pub const I2C = enum(u1) { + _, + + pub fn apply(self: I2C, comptime config: Config) ConfigError!void { + self.reset(); + I2C0.TM.write(.{ .TM = config.baud }); + I2C0.ADDR.write(.{ + .I2CADR = 0, + .GC = 0, + }); + } + + pub inline fn reset(_: I2C) void { + RESET.PREI_RESET.modify(.{ + .I2C = 0, + }); + RESET.PREI_RESET.modify(.{ + .I2C = 1, + }); + } + + pub inline fn enable(_: I2C) void { + I2C0.TMRUN.write(.{ + // enable baudrate generation + .TME = 1, + }); + + I2C0.CR.modify(.{ + // enable i2c module + .ENS = 1, + // enable high speed mode + .H1M = 1, + }); + } + + pub inline fn disable(_: I2C) void { + I2C0.CR.modify(.{ + .TMRUN = 0, + .ENS = 0, + .H1M = 0, + }); + } + + pub fn writev_blocking(self: I2C, address: Address, buffers: []const []const u8, timeout: ?mdf.time.Duration) TransactionError!void { + // TODO: timeouts + _ = timeout; + + const write_vec = microzig.utilities.Slice_Vector([]const u8).init(buffers); + if (write_vec.size() == 0) + return TransactionError.NoData; + + self.set_start(); + + // send address + self.wait_for_irq(); + { + const state = self.get_state(); + switch (state) { + 0x08 => {}, // ACK + else => @panic("invalid i2c state"), + } + } + self.clear_start(); + self.write_data(@intFromEnum(address) << 1); + self.clear_irq(); + + // wait for ack/nack + self.wait_for_irq(); + { + const state = self.get_state(); + switch (state) { + 0x18 => {}, // ACK + 0x20 => return error.NoAcknowledge, + else => @panic("invalid i2c state"), + } + } + + var iter = write_vec.iterator(); + while (iter.next_element()) |element| { + self.write_data(element.value); + self.clear_irq(); + + self.wait_for_irq(); + const state = self.get_state(); + switch (state) { + 0x28 => {}, // ACK + 0x20 => return error.NoAcknowledge, + else => @panic("invalid i2c state"), + } + } + + self.set_stop(); + self.clear_irq(); + } + + pub fn write_blocking(self: I2C, address: Address, data: []const u8, timeout: ?mdf.time.Duration) TransactionError!void { + return self.writev_blocking(address, &.{data}, timeout); + } + + pub fn readv_blocking(self: I2C, address: Address, buffers: []const []u8, timeout: ?mdf.time.Duration) TransactionError!void { + // TODO: timeouts + _ = timeout; + + const write_vec = microzig.utilities.Slice_Vector([]u8).init(buffers); + const total_size = write_vec.size(); + if (total_size == 0) + return TransactionError.NoData; + + self.set_start(); + + // send address + self.wait_for_irq(); + { + const state = self.get_state(); + switch (state) { + 0x08 => {}, + else => @panic("invalid i2c state"), + } + } + self.clear_start(); + self.write_data((@intFromEnum(address) << 1) | 0x01); + self.clear_irq(); + + // wait for ack/nack + self.wait_for_irq(); + { + const state = self.get_state(); + switch (state) { + 0x40 => {}, // ACK + 0x48 => return error.NoAcknowledge, + else => @panic("invalid i2c state"), + } + } + + if (total_size > 1) { + self.set_ack(); + } + self.clear_irq(); + + var iter = write_vec.iterator(); + var offset: usize = 0; + while (iter.next_element_ptr()) |element| { + self.wait_for_irq(); + const state = self.get_state(); + + element.value_ptr.* = self.read_data(); + + switch (state) { + 0x50 => { + // clear ack after second to last element + if (total_size > 1 and offset == total_size - 2) { + self.clear_ack(); + } + }, + 0x58 => { + if (element.last) { + self.set_stop(); + } + }, + // TODO: find out which value corresponds to NACK + else => @panic("invalid i2c state"), + } + self.clear_irq(); + offset += 1; + } + } + + pub fn read_blocking(self: I2C, address: Address, dst: []u8, timeout: ?mdf.time.Duration) TransactionError!void { + return try self.readv_blocking(address, &.{dst}, timeout); + } + + pub inline fn device(self: I2C, address: Address) I2C_Device { + return I2C_Device.init(self, address); + } + + inline fn set_start(_: I2C) void { + I2C0.CR.modify(.{ .STA = 1 }); + } + + inline fn clear_start(_: I2C) void { + I2C0.CR.modify(.{ .STA = 0 }); + } + + inline fn set_stop(_: I2C) void { + I2C0.CR.modify(.{ .STO = 1 }); + } + + inline fn clear_stop(_: I2C) void { + I2C0.CR.modify(.{ .STO = 0 }); + } + + inline fn set_ack(_: I2C) void { + I2C0.CR.modify(.{ .AA = 1 }); + } + + inline fn clear_ack(_: I2C) void { + I2C0.CR.modify(.{ .AA = 0 }); + } + + inline fn write_data(_: I2C, data: u8) void { + I2C0.DATA.write(.{ .I2CDAT = data }); + } + + inline fn read_data(_: I2C) u8 { + return I2C0.DATA.read().I2CDAT; + } + + inline fn get_state(_: I2C) u8 { + return I2C0.STAT.read().I2CSTA; + } + + fn wait_for_irq(self: I2C) void { + while (!self.is_irq_set()) {} + } + + inline fn is_irq_set(_: I2C) bool { + return I2C0.CR.read().SI == 1; + } + + inline fn clear_irq(_: I2C) void { + I2C0.CR.modify(.{ .SI = 0 }); + } +};