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1 parent d1d8e29 commit 6cd3e1cCopy full SHA for 6cd3e1c
tests/test_wishbone_sram.py
@@ -91,7 +91,6 @@ async def testbench(ctx):
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ctx.set(dut.wb_bus.dat_w, (i << 24) | 0x00ffff00)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.wb_bus.ack), 1)
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- self.assertEqual(ctx.get(dut.wb_bus.dat_r), i)
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self.assertEqual(ctx.get(dut.wb_bus.ack), 0)
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ctx.set(dut.wb_bus.cyc, 0)
@@ -115,7 +114,6 @@ async def testbench(ctx):
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ctx.set(dut.wb_bus.dat_w, i | 0x00ffff00)
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- self.assertEqual(ctx.get(dut.wb_bus.dat_r), i << 24)
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