library/spi_engine: update quartus tcl

Update scripts for generating the spi engine for quartus projects. Also
updated Makefile that had a missing fifo asym library for quartus.

Signed-off-by: Carlos Souza <[email protected]>

Author: caosjr

library/spi_engine/axi_spi_engine/Makefile

@@ -28,6 +28,7 @@ XILINX_INTERFACE_DEPS += spi_engine/interfaces
 INTEL_DEPS += ../../common/ad_mem.v
 INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
 INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v
+INTEL_DEPS += ../../util_axis_fifo_asym/util_axis_fifo_asym.v
 INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo_address_generator.v
 INTEL_DEPS += ../../util_cdc/sync_bits.v
 INTEL_DEPS += ../../util_cdc/sync_gray.v
@@ -36,6 +37,7 @@ INTEL_DEPS += axi_spi_engine_hw.tcl
 
 LATTICE_DEPS += ../../common/ad_mem.v
 LATTICE_DEPS += ../../util_axis_fifo/util_axis_fifo.v
+LATTICE_DEPS += ../../util_axis_fifo_asym/util_axis_fifo_asym.v
 LATTICE_DEPS += ../../util_axis_fifo/util_axis_fifo_address_generator.v
 LATTICE_DEPS += ../../util_cdc/sync_bits.v
 LATTICE_DEPS += ../../util_cdc/sync_gray.v

library/spi_engine/axi_spi_engine/axi_spi_engine_constr.sdc

@@ -3,6 +3,8 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-set_false_path  \
-  -to [get_registers  *cdc_sync_stage1*]
+set_false_path -to [get_registers *cdc_sync_stage1*]
 
+set_false_path \
+  -from [get_registers *i_sdi_level_sync*|cdc_hold[*]] \
+  -to   [get_registers *i_sdi_level_sync*|out_data[*]]

library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl

@@ -14,6 +14,7 @@ ad_ip_files axi_spi_engine [list\
   $ad_hdl_dir/library/util_cdc/sync_bits.v \
   $ad_hdl_dir/library/util_cdc/sync_gray.v \
   $ad_hdl_dir/library/common/ad_mem.v \
+  $ad_hdl_dir/library/util_axis_fifo_asym/util_axis_fifo_asym.v \
   $ad_hdl_dir/library/common/up_axi.v \
   $ad_hdl_dir/library/common/ad_rst.v \
   $ad_hdl_dir/library/intel/common/up_rst_constr.sdc \

library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl

@@ -52,6 +52,13 @@ proc p_elaboration {} {
   set_interface_property cmd associatedClock if_clk
   set_interface_property cmd associatedReset if_resetn
 
+  # offload active interface
+
+  add_interface s_offload_active_ctrl conduit end
+  add_interface_port s_offload_active_ctrl s_offload_active interconnect_dir input 1
+  set_interface_property s_offload_active_ctrl associatedClock if_clk
+  set_interface_property s_offload_active_ctrl associatedReset if_resetn
+
   # SDO data interface
 
   add_interface sdo_data axi4stream end

library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl

@@ -43,6 +43,13 @@ proc p_elaboration {} {
   set_interface_property m_cmd associatedClock if_clk
   set_interface_property m_cmd associatedReset if_resetn
 
+  # offload active master interface
+
+  add_interface m_offload_active_ctrl conduit end
+  add_interface_port m_offload_active_ctrl m_offload_active interconnect_dir output 1
+  set_interface_property m_offload_active_ctrl associatedClock if_clk
+  set_interface_property m_offload_active_ctrl associatedReset if_resetn
+
   # SDO data master interface
 
   add_interface m_sdo axi4stream start