diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_rx/Makefile b/library/intel/jesd204c/jesd204_f_tile_adapter_rx/Makefile
index 2e81c080c15..1c5decca141 100644
--- a/library/intel/jesd204c/jesd204_f_tile_adapter_rx/Makefile
+++ b/library/intel/jesd204c/jesd204_f_tile_adapter_rx/Makefile
@@ -8,8 +8,8 @@ LIBRARY_NAME := jesd204_f_tile_adapter_rx
 
 INTEL_DEPS += ../../../util_cdc/sync_bits.v
 INTEL_DEPS += ../../../jesd204/jesd204_common/sync_header_align.v
-INTEL_DEPS += bitslip.v
-INTEL_DEPS += gearbox_64b66b.v
+INTEL_DEPS += ../../../jesd204/jesd204_common/bitslip.v
+INTEL_DEPS += ../../../jesd204/jesd204_common/gearbox_64b66b.v
 INTEL_DEPS += jesd204_f_tile_adapter_rx.v
 INTEL_DEPS += jesd204_f_tile_adapter_rx_constr.sdc
 
diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_rx/jesd204_f_tile_adapter_rx_hw.tcl b/library/intel/jesd204c/jesd204_f_tile_adapter_rx/jesd204_f_tile_adapter_rx_hw.tcl
index 582985f7c97..02ba1bd86f6 100644
--- a/library/intel/jesd204c/jesd204_f_tile_adapter_rx/jesd204_f_tile_adapter_rx_hw.tcl
+++ b/library/intel/jesd204c/jesd204_f_tile_adapter_rx/jesd204_f_tile_adapter_rx_hw.tcl
@@ -19,8 +19,8 @@ ad_ip_parameter DEVICE STRING "Agilex 7" false
 ad_ip_files jesd204_f_tile_adapter_rx [list \
   $ad_hdl_dir/library/util_cdc/sync_bits.v \
   $ad_hdl_dir/library/jesd204/jesd204_common/sync_header_align.v \
-  bitslip.v \
-  gearbox_64b66b.v \
+  $ad_hdl_dir/library/jesd204/jesd204_common/bitslip.v \
+  $ad_hdl_dir/library/jesd204/jesd204_common/gearbox_64b66b.v \
   jesd204_f_tile_adapter_rx.v \
   jesd204_f_tile_adapter_rx_constr.sdc \
 ]
diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_tx/Makefile b/library/intel/jesd204c/jesd204_f_tile_adapter_tx/Makefile
index bba3e6ea5d2..82527ca0b61 100644
--- a/library/intel/jesd204c/jesd204_f_tile_adapter_tx/Makefile
+++ b/library/intel/jesd204c/jesd204_f_tile_adapter_tx/Makefile
@@ -7,7 +7,7 @@
 LIBRARY_NAME := jesd204_f_tile_adapter_tx
 
 INTEL_DEPS += ../../../util_cdc/sync_bits.v
-INTEL_DEPS += gearbox_66b64b.v
+INTEL_DEPS += ../../../jesd204/jesd204_common/gearbox_66b64b.v
 INTEL_DEPS += jesd204_f_tile_adapter_tx.v
 INTEL_DEPS += jesd204_f_tile_adapter_tx_constr.sdc
 
diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_tx/jesd204_f_tile_adapter_tx_hw.tcl b/library/intel/jesd204c/jesd204_f_tile_adapter_tx/jesd204_f_tile_adapter_tx_hw.tcl
index ec3850e3460..67e3217e2b7 100644
--- a/library/intel/jesd204c/jesd204_f_tile_adapter_tx/jesd204_f_tile_adapter_tx_hw.tcl
+++ b/library/intel/jesd204c/jesd204_f_tile_adapter_tx/jesd204_f_tile_adapter_tx_hw.tcl
@@ -18,7 +18,7 @@ ad_ip_parameter DEVICE STRING "Agilex 7" false
 
 ad_ip_files jesd204_f_tile_adapter_tx [list \
   $ad_hdl_dir/library/util_cdc/sync_bits.v \
-  gearbox_66b64b.v \
+  $ad_hdl_dir/library/jesd204/jesd204_common/gearbox_66b64b.v \
   jesd204_f_tile_adapter_tx.v \
   jesd204_f_tile_adapter_tx_constr.sdc \
 ]
diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_rx/bitslip.v b/library/jesd204/jesd204_common/bitslip.v
similarity index 100%
rename from library/intel/jesd204c/jesd204_f_tile_adapter_rx/bitslip.v
rename to library/jesd204/jesd204_common/bitslip.v
diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_rx/gearbox_64b66b.v b/library/jesd204/jesd204_common/gearbox_64b66b.v
similarity index 100%
rename from library/intel/jesd204c/jesd204_f_tile_adapter_rx/gearbox_64b66b.v
rename to library/jesd204/jesd204_common/gearbox_64b66b.v
diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_tx/gearbox_66b64b.v b/library/jesd204/jesd204_common/gearbox_66b64b.v
similarity index 100%
rename from library/intel/jesd204c/jesd204_f_tile_adapter_tx/gearbox_66b64b.v
rename to library/jesd204/jesd204_common/gearbox_66b64b.v
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/Makefile b/library/jesd204/jesd204_versal_gt_adapter_rx/Makefile
index 6979a6606ff..a1a713654c6 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_rx/Makefile
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/Makefile
@@ -8,8 +8,13 @@ LIBRARY_NAME := jesd204_versal_gt_adapter_rx
 
 GENERIC_DEPS += jesd204_versal_gt_adapter_rx.v
 GENERIC_DEPS += lane_align.v
+GENERIC_DEPS += ../jesd204_common/sync_header_align.v
+GENERIC_DEPS += ../jesd204_common/gearbox_64b66b.v
+GENERIC_DEPS += ../jesd204_common/bitslip.v
+GENERIC_DEPS += ../jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
+GENERIC_DEPS += ../jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v
+GENERIC_DEPS += ../jesd204_soft_pcs_rx/jesd204_pattern_align.v
 
-XILINX_DEPS += ../jesd204_common/sync_header_align.v
 XILINX_DEPS += jesd204_versal_gt_adapter_rx_ip.tcl
 
 include ../../scripts/library.mk
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
index f49278fd2f8..19416c24a24 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2017, 2018, 2020-2022, 2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2017, 2018, 2020-2022, 2024-2025 Analog Devices, Inc. All rights reserved.
 // SPDX short identifier: ADIJESD204
 // ***************************************************************************
 // ***************************************************************************
@@ -8,6 +8,7 @@
 `timescale 1ns/100ps
 
 module  jesd204_versal_gt_adapter_rx #(
+  parameter TRANSCEIVER = "GTY",
   parameter LINK_MODE = 2 // 1 - 8B10B, 2 - 64B66B
 ) (
   // Interface to Physical Layer
@@ -21,6 +22,9 @@ module  jesd204_versal_gt_adapter_rx #(
   input  [  1 : 0] rxheadervalid,
   output           rxslide,
 
+  input            phy_clk,
+  input            phy_rstn,
+
   // Interface to Link layer core
   output [ 63 : 0]  rx_data,
   output [  3 : 0]  rx_charisk,
@@ -33,71 +37,220 @@ module  jesd204_versal_gt_adapter_rx #(
   input             usr_clk
 );
 
-  reg [63:0] rxdata_d;
-  reg [ 1:0] rxheader_d;
-  reg        rxgearboxslip_d;
-  reg [ 1:0] rxheadervalid_d;
-  reg [15:0] rxctrl0_d;
-  reg [15:0] rxctrl1_d;
-  reg [ 7:0] rxctrl3_d;
-  wire       rxgearboxslip_s;
-
-  always @(posedge usr_clk) begin
-    rxdata_d <= rxdata[63:0];
-    rxheader_d <= rxheader[1:0];
-    rxgearboxslip_d <= rxgearboxslip_s;
-    rxheadervalid_d <= rxheadervalid;
-    rxctrl0_d <= rxctrl0;
-    rxctrl1_d <= rxctrl1;
-    rxctrl3_d <= rxctrl3;
-  end
+  wire i_reset;
+  wire o_reset;
 
-  generate if (LINK_MODE == 2) begin
-    // Sync header alignment
-    wire rx_bitslip_req_s;
-    reg [5:0] rx_bitslip_done_cnt = 'h0;
-    always @(posedge usr_clk) begin
-      if (rx_bitslip_done_cnt[5]) begin
-        rx_bitslip_done_cnt <= 'b0;
-      end else if (rx_bitslip_req_s & ~rx_bitslip_done_cnt[5]) begin
-        rx_bitslip_done_cnt <= rx_bitslip_done_cnt + 1;
+  sync_bits #(
+    .NUM_OF_BITS(1),
+    .ASYNC_CLK(1)
+  ) i_sync_i_reset (
+    .in_bits(~phy_rstn),
+    .out_clk(phy_clk),
+    .out_resetn(1'b1),
+    .out_bits(i_reset));
+
+  sync_bits #(
+    .NUM_OF_BITS(1),
+    .ASYNC_CLK(1)
+  ) i_sync_o_reset (
+    .in_bits(~phy_rstn),
+    .out_clk(usr_clk),
+    .out_resetn(1'b1),
+    .out_bits(o_reset));
+
+  generate if (TRANSCEIVER == "GTM") begin
+    if (LINK_MODE == 2) begin
+      reg  [63:0] i_data;
+      wire        rd_rst_busy;
+      wire        wr_rst_busy;
+      wire        fifo_wr_en;
+      wire        i_fifo_full;
+      wire [65:0] fifo_rd_data;
+      wire        fifo_rd_en;
+      wire        fifo_empty;
+
+      wire [65:0] i_gb_data;
+      wire        i_gb_valid;
+
+      wire [63:0] o_data_aligned;
+      wire [ 1:0] o_header_aligned;
+      wire [63:0] o_data_rev;
+      wire [ 1:0] o_header_rev;
+      wire        o_bitslip;
+      wire        o_bitslip_done;
+
+      always @(posedge phy_clk) begin
+        i_data <= rxdata[63:0];
       end
-    end
 
-    reg rx_bitslip_req_s_d = 1'b0;
-    always @(posedge usr_clk) begin
-      rx_bitslip_req_s_d <= rx_bitslip_req_s;
-    end
+      gearbox_64b66b i_gearbox (
+        .clk (phy_clk),
+        .reset (i_reset),
+        .i_data (i_data),
+        .o_data (i_gb_data),
+        .o_valid (i_gb_valid));
 
-    assign rxgearboxslip_s = rx_bitslip_req_s & ~rx_bitslip_req_s_d;
-    assign rxgearboxslip = rxgearboxslip_d;
+      // CDC from LR / 64 to LR / 66
+      assign fifo_wr_en = i_gb_valid & ~i_fifo_full & ~wr_rst_busy;
+      assign fifo_rd_en = ~fifo_empty & ~rd_rst_busy;
 
-    wire [63:0] rxdata_flip;
-    wire [ 1:0] rxheader_flip;
-    genvar i;
-    for (i = 0; i < 64; i=i+1) begin
-      assign rxdata_flip[63-i] = rxdata_d[i];
-    end
-    assign rxheader_flip = {rxheader_d[0], rxheader_d[1]};
-
-    // Sync header alignment
-    sync_header_align i_sync_header_align (
-      .clk(usr_clk),
-      .reset(~rxheadervalid_d[0]),
-      // Flip header bits and data
-      .i_data({rxheader_flip, rxdata_flip}),
-      .i_slip(rx_bitslip_req_s),
-      .i_slip_done(rx_bitslip_done_cnt[5]),
-      .o_data(rx_data),
-      .o_header(rx_header),
-      .o_block_sync(rx_block_sync));
+      xpm_fifo_async #(
+        .CASCADE_HEIGHT(0),
+        .CDC_SYNC_STAGES(2),
+        .DOUT_RESET_VALUE("0"),
+        .ECC_MODE("no_ecc"),
+        .EN_SIM_ASSERT_ERR("warning"),
+        .FIFO_MEMORY_TYPE("auto"),
+        .FIFO_READ_LATENCY(1),
+        .FIFO_WRITE_DEPTH(32),
+        .FULL_RESET_VALUE(0),
+        .PROG_EMPTY_THRESH(10),
+        .PROG_FULL_THRESH(10),
+        .RD_DATA_COUNT_WIDTH(1),
+        .READ_DATA_WIDTH(66),
+        .READ_MODE("std"),
+        .RELATED_CLOCKS(0),
+        .SIM_ASSERT_CHK(0),
+        .USE_ADV_FEATURES("0707"),
+        .WAKEUP_TIME(0),
+        .WRITE_DATA_WIDTH(66),
+        .WR_DATA_COUNT_WIDTH(1)
+      ) i_async_fifo (
+        .sleep (1'b0),
+        .injectdbiterr (1'b0),
+        .injectsbiterr (1'b0),
+        .rd_rst_busy (rd_rst_busy),
+        .rd_clk (usr_clk),
+        .rd_en (fifo_rd_en),
+        .dout (fifo_rd_data),
+        .empty (fifo_empty),
+        .wr_rst_busy (wr_rst_busy),
+        .wr_clk (phy_clk),
+        .wr_en (fifo_wr_en),
+        .din (i_gb_data),
+        .full (i_fifo_full),
+        .rst (i_reset));
+
+      // In LR / 66 domain
+      bitslip i_bitslip (
+        .clk (usr_clk),
+        .reset (o_reset),
+        .bitslip (o_bitslip),
+        .data_in (fifo_rd_data),
+        .bitslip_done (o_bitslip_done),
+        .data_out ({o_data_aligned, o_header_aligned}));
+
+      genvar i;
+      for (i=0; i < 64; i=i+1) begin
+        assign o_data_rev[63-i] = o_data_aligned[i];
+      end
+      assign o_header_rev = {o_header_aligned[0], o_header_aligned[1]};
+
+      sync_header_align i_header_align (
+        .clk (usr_clk),
+        .reset (o_reset),
+        .i_data ({o_header_rev, o_data_rev}),
+        .i_slip (o_bitslip),
+        .i_slip_done (o_bitslip_done),
+        .o_data (rx_data),
+        .o_header (rx_header),
+        .o_block_sync (rx_block_sync));
 
       assign rx_disperr    = 4'b0;
       assign rx_charisk    = 4'b0;
       assign rx_notintable = 4'b0;
       assign rxslide       = 1'b0;
+      assign rxgearboxslip = 1'b0;
     end else begin
-      assign rx_data       = {32'b0, rxdata_d[31:0]};
+      wire [39:0] rx_data_40b;
+
+      jesd204_soft_pcs_rx #(
+        .NUM_LANES (1),
+        .DATA_PATH_WIDTH (4),
+        .REGISTER_INPUTS (1),
+        .INVERT_INPUTS (0),
+        .IFC_TYPE (0)
+      ) i_jesd204_soft_pcs_rx (
+        .clk (usr_clk),
+        .reset (o_reset),
+        .patternalign_en (en_char_align),
+        .data (rxdata[39:0]),
+        .char (rx_data_40b),
+        .charisk (rx_charisk),
+        .notintable (rx_notintable),
+        .disperr (rx_disperr));
+
+      assign rx_data = {24'b0, rx_data_40b};
+      assign rx_block_sync = 'b0;
+      assign rxslide = 1'b0;
+      assign rxgearboxslip = 1'b0;
+    end
+  end else begin
+    reg [63:0] rxdata_d;
+    reg [ 1:0] rxheader_d;
+    reg        rxgearboxslip_d;
+    reg [ 1:0] rxheadervalid_d;
+    reg [15:0] rxctrl0_d;
+    reg [15:0] rxctrl1_d;
+    reg [ 7:0] rxctrl3_d;
+    wire       rxgearboxslip_s;
+
+    always @(posedge usr_clk) begin
+      rxdata_d <= rxdata[63:0];
+      rxheader_d <= rxheader[1:0];
+      rxgearboxslip_d <= rxgearboxslip_s;
+      rxheadervalid_d <= rxheadervalid;
+      rxctrl0_d <= rxctrl0;
+      rxctrl1_d <= rxctrl1;
+      rxctrl3_d <= rxctrl3;
+    end
+
+    if (LINK_MODE == 2) begin
+      // Sync header alignment
+      wire rx_bitslip_req_s;
+      reg [5:0] rx_bitslip_done_cnt = 'h0;
+      always @(posedge usr_clk) begin
+        if (rx_bitslip_done_cnt[5]) begin
+          rx_bitslip_done_cnt <= 'b0;
+        end else if (rx_bitslip_req_s & ~rx_bitslip_done_cnt[5]) begin
+          rx_bitslip_done_cnt <= rx_bitslip_done_cnt + 1;
+        end
+      end
+
+      reg rx_bitslip_req_s_d = 1'b0;
+      always @(posedge usr_clk) begin
+        rx_bitslip_req_s_d <= rx_bitslip_req_s;
+      end
+
+      assign rxgearboxslip_s = rx_bitslip_req_s & ~rx_bitslip_req_s_d;
+      assign rxgearboxslip = rxgearboxslip_d;
+
+      wire [63:0] rxdata_flip;
+      wire [ 1:0] rxheader_flip;
+      genvar i;
+      for (i = 0; i < 64; i=i+1) begin
+        assign rxdata_flip[63-i] = rxdata_d[i];
+      end
+      assign rxheader_flip = {rxheader_d[0], rxheader_d[1]};
+
+      // Sync header alignment
+      sync_header_align i_sync_header_align (
+        .clk(usr_clk),
+        .reset(~rxheadervalid_d[0]),
+        // Flip header bits and data
+        .i_data({rxheader_flip, rxdata_flip}),
+        .i_slip(rx_bitslip_req_s),
+        .i_slip_done(rx_bitslip_done_cnt[5]),
+        .o_data(rx_data),
+        .o_header(rx_header),
+        .o_block_sync(rx_block_sync));
+
+        assign rx_disperr    = 4'b0;
+        assign rx_charisk    = 4'b0;
+        assign rx_notintable = 4'b0;
+        assign rxslide       = 1'b0;
+    end else begin
+      assign rx_data       = rxdata_d[31:0];
       assign rx_header     = rxheader_d[1:0];
 
       assign rx_charisk    = rxctrl0_d[3:0];
@@ -112,6 +265,7 @@ module  jesd204_versal_gt_adapter_rx #(
         .rx_slide (rxslide),
         .en_char_align (en_char_align));
     end
+  end
   endgenerate
 
 endmodule
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_constr.ttcl b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_constr.ttcl
new file mode 100644
index 00000000000..fbd39814bd6
--- /dev/null
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_constr.ttcl
@@ -0,0 +1,41 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName [ttcl_add $ComponentName "_constr"] :>
+<: setFileExtension ".xdc" :>
+<: setFileProcessingOrder late :>
+
+set usr_clk [get_clocks -of_objects [get_ports -quiet {usr_clk}]]
+set phy_clk [get_clocks -of_objects [get_ports -quiet {phy_clk}]]
+
+# sync bits i_reset
+set_false_path \
+  -from $phy_clk \
+  -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_i_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_i_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_sync_i_reset* && IS_SEQUENTIAL}]
+
+# sync bits o_reset
+set_false_path \
+  -from $usr_clk \
+  -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_o_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_o_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_sync_o_reset* && IS_SEQUENTIAL}]
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
index 97e945cbd03..579274f3ced 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIJESD204
 ###############################################################################
 
@@ -11,9 +11,19 @@ adi_ip_files jesd204_versal_gt_adapter_rx [list \
   jesd204_versal_gt_adapter_rx.v \
   lane_align.v \
   ../jesd204_common/sync_header_align.v \
-  ]
+  ../jesd204_common/gearbox_64b66b.v \
+  ../jesd204_common/bitslip.v \
+  ../jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v \
+  ../jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v \
+  ../jesd204_soft_pcs_rx/jesd204_pattern_align.v \
+  $ad_hdl_dir/library/util_cdc/sync_bits.v \
+  jesd204_versal_gt_adapter_rx_constr.ttcl \
+  jesd204_versal_gt_adapter_rx_ooc.ttcl \
+]
 
 adi_ip_properties_lite jesd204_versal_gt_adapter_rx
+adi_ip_ttcl jesd204_versal_gt_adapter_rx "jesd204_versal_gt_adapter_rx_constr.ttcl"
+adi_ip_ttcl jesd204_versal_gt_adapter_rx "jesd204_versal_gt_adapter_rx_ooc.ttcl"
 
 set_property display_name "ADI JESD204 Versal Transceiver Rx Lane Adapter" [ipx::current_core]
 set_property description "ADI JESD204 Versal Transceiver Rx Lane Adapter" [ipx::current_core]
@@ -45,4 +55,14 @@ adi_add_bus "RX_GT_IP_Interface" "master" \
    { "rxgearboxslip" "ch_rxgearboxslip" } \
   }
 
+set_property -dict [list \
+  value_validation_type list \
+  value_validation_list {GT GTY GTM} \
+] [ipx::get_user_parameters TRANSCEIVER -of_objects [ipx::current_core]]
+
+set_property -dict [list \
+  value_validation_type pairs \
+  value_validation_pairs {64B66B 2 8B10B 1} \
+] [ipx::get_user_parameters LINK_MODE -of_objects [ipx::current_core]]
+
 ipx::save_core [ipx::current_core]
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ooc.ttcl b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ooc.ttcl
new file mode 100644
index 00000000000..70abd7ffd03
--- /dev/null
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ooc.ttcl
@@ -0,0 +1,21 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
+<: setFileUsedIn { out_of_context synthesis implementation } :>
+<: ;#Component and file information :>
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName $ComponentName :>
+<: setFileExtension "_ooc.xdc" :>
+
+# This XDC is used only for OOC mode of synthesis, implementation.
+# These are default values for timing driven synthesis during OOC flow.
+# These values will be overwritten during implementation with information
+# from top level.
+
+create_clock -name usr_clk -period 2.5000 [get_ports usr_clk]
+create_clock -name phy_clk -period 2.4242 [get_ports phy_clk]
+
+################################################################################
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/Makefile b/library/jesd204/jesd204_versal_gt_adapter_tx/Makefile
index 0baea0f93e9..12dd475e3e0 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_tx/Makefile
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/Makefile
@@ -7,6 +7,9 @@
 LIBRARY_NAME := jesd204_versal_gt_adapter_tx
 
 GENERIC_DEPS += jesd204_versal_gt_adapter_tx.v
+GENERIC_DEPS += ../jesd204_common/gearbox_66b64b.v
+GENERIC_DEPS += ../jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
+GENERIC_DEPS += ../jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v
 
 XILINX_DEPS += jesd204_versal_gt_adapter_tx_ip.tcl
 
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v
index 0f71804d0fb..9f3b50a9087 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2017-2019, 2021, 2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2017-2019, 2021, 2024-2025 Analog Devices, Inc. All rights reserved.
 // SPDX short identifier: ADIJESD204
 // ***************************************************************************
 // ***************************************************************************
@@ -8,6 +8,7 @@
 `timescale 1ns/100ps
 
 module  jesd204_versal_gt_adapter_tx #(
+  parameter TRANSCEIVER = "GTY",
   parameter LINK_MODE = 2 // 1 - 8B10B, 2 - 64B66B
 ) (
   output  [127 : 0] txdata,
@@ -15,6 +16,10 @@ module  jesd204_versal_gt_adapter_tx #(
   output  [ 15 : 0] txctrl0,
   output  [ 15 : 0] txctrl1,
   output  [  7 : 0] txctrl2,
+
+  input             phy_clk,
+  input             phy_rstn,
+
   // Interface to Link layer core
   input   [ 63 : 0] tx_data,
   input   [  1 : 0] tx_header,
@@ -22,39 +27,182 @@ module  jesd204_versal_gt_adapter_tx #(
 
   input             usr_clk
 );
+  wire i_reset;
+  wire o_reset;
 
-  reg [63:0]   txdata_d;
-  reg [ 1:0]   txheader_d;
-  reg [ 3:0]   txcharisk_d;
+  sync_bits #(
+    .NUM_OF_BITS(1),
+    .ASYNC_CLK(1)
+  ) i_sync_i_reset (
+    .in_bits(~phy_rstn),
+    .out_clk(phy_clk),
+    .out_resetn(1'b1),
+    .out_bits(i_reset));
 
-  always @(posedge usr_clk) begin
-    txdata_d <= tx_data;
-    txheader_d <= tx_header;
-    txcharisk_d <= tx_charisk;
-  end
+  sync_bits #(
+    .NUM_OF_BITS(1),
+    .ASYNC_CLK(1)
+  ) i_sync_o_reset (
+    .in_bits(~phy_rstn),
+    .out_clk(usr_clk),
+    .out_resetn(1'b1),
+    .out_bits(o_reset));
 
-  generate if (LINK_MODE == 2) begin
-    wire [63:0] tx_data_flip;
-    wire [ 1:0] tx_header_flip;
-    genvar i;
-    for (i = 0; i < 64; i=i+1) begin
-      assign tx_data_flip[63-i] = txdata_d[i];
-    end
-    assign tx_header_flip = {txheader_d[0], txheader_d[1]};
+  generate if (TRANSCEIVER == "GTM") begin
+    if (LINK_MODE == 2) begin
+      wire        i_fifo_empty;
+      wire        i_gb_read;
+      wire [63:0] o_gb_data;
+      wire [63:0] o_data;
+      wire [ 1:0] o_header;;
+
+      wire        o_fifo_full;
+      reg  [63:0] o_phy_data_r;
+      reg  [ 1:0] o_phy_header_r;
+      wire [63:0] o_phy_data_rev;
+      wire [ 1:0] o_phy_header_rev;
+
+      wire         wr_rst_busy;
+      wire         rd_rst_busy;
+      wire  [65:0] rd_data;
+
+      wire  [65:0] wr_data;
+      wire         wr_en;
+      wire         rd_en;
+
+      reg   [63:0] txdata_d;
+
+      // Register the input data to ease timing
+      always @(posedge usr_clk) begin
+        o_phy_data_r <= tx_data;
+        o_phy_header_r <= tx_header;
+      end
+
+      genvar i;
+      for (i=0; i < 64; i=i+1) begin
+        assign o_phy_data_rev[63-i] = o_phy_data_r[i];
+      end
+      assign o_phy_header_rev = {o_phy_header_r[0], o_phy_header_r[1]};
+
+      // CDC from LR / 66 to LR / 64
+      assign wr_en = ~o_fifo_full & ~wr_rst_busy;
+      assign rd_en = i_gb_read & ~i_fifo_empty & ~rd_rst_busy;
+
+      xpm_fifo_async #(
+        .CASCADE_HEIGHT(0),
+        .CDC_SYNC_STAGES(2),
+        .DOUT_RESET_VALUE("0"),
+        .ECC_MODE("no_ecc"),
+        .EN_SIM_ASSERT_ERR("warning"),
+        .FIFO_MEMORY_TYPE("auto"),
+        .FIFO_READ_LATENCY(1),
+        .FIFO_WRITE_DEPTH(32),
+        .FULL_RESET_VALUE(0),
+        .PROG_EMPTY_THRESH(10),
+        .PROG_FULL_THRESH(10),
+        .RD_DATA_COUNT_WIDTH(1),
+        .READ_DATA_WIDTH(66),
+        .READ_MODE("std"),
+        .RELATED_CLOCKS(0),
+        .SIM_ASSERT_CHK(0),
+        .USE_ADV_FEATURES("0707"),
+        .WAKEUP_TIME(0),
+        .WRITE_DATA_WIDTH(66),
+        .WR_DATA_COUNT_WIDTH(1)
+      ) i_async_fifo (
+        .sleep (1'b0),
+        .injectdbiterr (1'b0),
+        .injectsbiterr (1'b0),
+        .rd_rst_busy (rd_rst_busy),
+        .rd_clk (phy_clk),
+        .rd_en (rd_en),
+        .dout(rd_data),
+        .empty (i_fifo_empty),
+        .wr_rst_busy (wr_rst_busy),
+        .wr_clk (usr_clk),
+        .wr_en (wr_en),
+        .din ({o_phy_data_rev, o_phy_header_rev}),
+        .full (o_fifo_full),
+        .rst (o_reset));
 
-    // Flip header bits and data
-    assign txdata   = {64'b0, tx_data_flip};
-    assign txheader = {4'b0, tx_header_flip};
+      // In LR / 64 domain
+      gearbox_66b64b i_gearbox (
+        .clk (phy_clk),
+        .reset (i_reset),
+        .i_data (rd_data),
+        .i_valid (~i_fifo_empty & i_gb_read),
+        .o_data (o_gb_data),
+        .o_rd_en (i_gb_read));
 
-    assign txctrl0  = 16'b0;
-    assign txctrl1  = 16'b0;
-    assign txctrl2  = 16'b0;
+      always @(posedge phy_clk) begin
+        txdata_d <= o_gb_data;
+      end
+
+      assign txdata = txdata_d;
+      assign txheader = 'b0;
+      assign txctrl0 = 'b0;
+      assign txctrl1 = 'b0;
+      assign txctrl2 = 'b0;
+    end else begin
+      wire [39:0] tx_data_40b;
+      reg  [39:0] txdata_d;
+
+      jesd204_soft_pcs_tx #(
+        .NUM_LANES (1),
+        .DATA_PATH_WIDTH (4),
+        .INVERT_OUTPUTS (0),
+        .IFC_TYPE (0)
+      ) i_jesd204_soft_pcs_tx (
+        .clk (usr_clk),
+        .reset (o_reset),
+        .char (tx_data),
+        .charisk (tx_charisk),
+        .data (tx_data_40b));
+
+      always @(posedge usr_clk) begin
+        txdata_d <= tx_data_40b;
+      end
+
+      assign txdata = txdata_d;
+      assign txheader = 'b0;
+      assign txctrl0 = 'b0;
+      assign txctrl1 = 'b0;
+      assign txctrl2 = 'b0;
+    end
   end else begin
-    assign txdata   = {96'b0, txdata_d[31:0]};
-    assign txheader = {4'b0, txheader_d};
-    assign txctrl2  = {4'b0, txcharisk_d};
-    assign txctrl0  = 16'b0;
-    assign txctrl1  = 16'b0;
+    reg [63:0]   txdata_d;
+    reg [ 1:0]   txheader_d;
+    reg [ 3:0]   txcharisk_d;
+
+    always @(posedge usr_clk) begin
+      txdata_d <= tx_data;
+      txheader_d <= tx_header;
+      txcharisk_d <= tx_charisk;
+    end
+
+    if (LINK_MODE == 2) begin
+      wire [63:0] tx_data_flip;
+      wire [ 1:0] tx_header_flip;
+      genvar i;
+      for (i = 0; i < 64; i=i+1) begin
+        assign tx_data_flip[63-i] = txdata_d[i];
+      end
+      assign tx_header_flip = {txheader_d[0], txheader_d[1]};
+
+      // Flip header bits and data
+      assign txdata   = {64'b0, tx_data_flip};
+      assign txheader = {4'b0, tx_header_flip};
+
+      assign txctrl0  = 16'b0;
+      assign txctrl1  = 16'b0;
+      assign txctrl2  = 16'b0;
+    end else begin
+      assign txdata   = {96'b0, txdata_d[31:0]};
+      assign txheader = {4'b0, txheader_d};
+      assign txctrl2  = {4'b0, txcharisk_d};
+      assign txctrl0  = 16'b0;
+      assign txctrl1  = 16'b0;
+    end
   end
   endgenerate
 
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_constr.ttcl b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_constr.ttcl
new file mode 100644
index 00000000000..fbd39814bd6
--- /dev/null
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_constr.ttcl
@@ -0,0 +1,41 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName [ttcl_add $ComponentName "_constr"] :>
+<: setFileExtension ".xdc" :>
+<: setFileProcessingOrder late :>
+
+set usr_clk [get_clocks -of_objects [get_ports -quiet {usr_clk}]]
+set phy_clk [get_clocks -of_objects [get_ports -quiet {phy_clk}]]
+
+# sync bits i_reset
+set_false_path \
+  -from $phy_clk \
+  -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_i_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_i_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_sync_i_reset* && IS_SEQUENTIAL}]
+
+# sync bits o_reset
+set_false_path \
+  -from $usr_clk \
+  -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_o_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_o_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_sync_o_reset* && IS_SEQUENTIAL}]
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl
index 91ce07e6c1d..51387b6d4a0 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIJESD204
 ###############################################################################
 
@@ -8,10 +8,18 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
 
 adi_ip_create jesd204_versal_gt_adapter_tx
 adi_ip_files jesd204_versal_gt_adapter_tx [list \
-  jesd204_versal_gt_adapter_tx.v
-  ]
+  jesd204_versal_gt_adapter_tx.v \
+  ../jesd204_common/gearbox_66b64b.v \
+  ../jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v \
+  ../jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v \
+  $ad_hdl_dir/library/util_cdc/sync_bits.v \
+  jesd204_versal_gt_adapter_tx_constr.ttcl \
+  jesd204_versal_gt_adapter_tx_ooc.ttcl \
+]
 
 adi_ip_properties_lite jesd204_versal_gt_adapter_tx
+adi_ip_ttcl jesd204_versal_gt_adapter_tx "jesd204_versal_gt_adapter_tx_constr.ttcl"
+adi_ip_ttcl jesd204_versal_gt_adapter_tx "jesd204_versal_gt_adapter_tx_ooc.ttcl"
 
 set_property display_name "ADI JESD204 Versal Transceiver Tx Lane Adapter" [ipx::current_core]
 set_property description "ADI JESD204 Versal Transceiver Tx Lane Adapter" [ipx::current_core]
@@ -36,4 +44,14 @@ adi_add_bus "TX" "slave" \
    { "tx_charisk" "txcharisk" } \
   }
 
+set_property -dict [list \
+  value_validation_type list \
+  value_validation_list {GT GTY GTM} \
+] [ipx::get_user_parameters TRANSCEIVER -of_objects [ipx::current_core]]
+
+set_property -dict [list \
+  value_validation_type pairs \
+  value_validation_pairs {64B66B 2 8B10B 1} \
+] [ipx::get_user_parameters LINK_MODE -of_objects [ipx::current_core]]
+
 ipx::save_core [ipx::current_core]
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ooc.ttcl b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ooc.ttcl
new file mode 100644
index 00000000000..70abd7ffd03
--- /dev/null
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ooc.ttcl
@@ -0,0 +1,21 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
+<: setFileUsedIn { out_of_context synthesis implementation } :>
+<: ;#Component and file information :>
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName $ComponentName :>
+<: setFileExtension "_ooc.xdc" :>
+
+# This XDC is used only for OOC mode of synthesis, implementation.
+# These are default values for timing driven synthesis during OOC flow.
+# These values will be overwritten during implementation with information
+# from top level.
+
+create_clock -name usr_clk -period 2.5000 [get_ports usr_clk]
+create_clock -name phy_clk -period 2.4242 [get_ports phy_clk]
+
+################################################################################
diff --git a/library/xilinx/scripts/versal_xcvr_subsystem.tcl b/library/xilinx/scripts/versal_xcvr_subsystem.tcl
index 3fa4e612f85..759ee627df0 100644
--- a/library/xilinx/scripts/versal_xcvr_subsystem.tcl
+++ b/library/xilinx/scripts/versal_xcvr_subsystem.tcl
@@ -3,8 +3,6 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-source ../../../projects/scripts/adi_board.tcl
-
 # Parameter description:
 #   ip_name : The name of the created ip
 #   jesd_mode : Used physical layer encoder mode
@@ -28,8 +26,16 @@ proc create_xcvr_subsystem {
   {ref_clock 375}
   {transceiver GTY}
   {direction RX}
+  {internal_link_clk {}}
 } {
+  # set_property CONFIG.INTF0_GT_SETTINGS(LR0_SETTINGS) {RX_LINE_RATE 10 RX_REFCLK_FREQUENCY 250 RX_USER_DATA_WIDTH 40 TXPROGDIV_FREQ_VAL 250.000 TX_LINE_RATE 10 TX_REFCLK_FREQUENCY 250 TX_USER_DATA_WIDTH 40 RXPROGDIV_FREQ_VAL 500.000} [get_bd_cells gtwiz_versal_0]
+
+  set preset                   ${transceiver}-JESD204_${jesd_mode}
   set clk_divider              [expr {$jesd_mode == "64B66B" ? 66 : 40}]
+  if {$transceiver == "GTM"} {
+    set preset                 ${transceiver}-NRZ_JESD
+    set clk_divider            [expr {$jesd_mode == "64B66B" ? 64 : 40}]
+  }
   set datapath_width           [expr {$jesd_mode == "64B66B" ? 64 : 32}]
   set internal_datapath_width  [expr {$jesd_mode == "64B66B" ? 64 : 40}]
   set data_encoding            [expr {$jesd_mode == "64B66B" ? "64B66B_ASYNC" : "8B10B"}]
@@ -54,10 +60,12 @@ proc create_xcvr_subsystem {
 
   # RX parameters
   dict set xcvr_param RX_LINE_RATE ${rx_lane_rate}
-  dict set xcvr_param RX_DATA_DECODING ${data_encoding}
+  dict set xcvr_param RX_DATA_DECODING [expr {$transceiver != "GTM" ? $data_encoding : "RAW"}]
+  dict set xcvr_param RX_USER_DATA_WIDTH [expr {$transceiver != "GTM" ? $datapath_width : $internal_datapath_width}]
   dict set xcvr_param RX_REFCLK_FREQUENCY ${ref_clock}
-  dict set xcvr_param RX_USER_DATA_WIDTH ${datapath_width}
-  dict set xcvr_param RX_INT_DATA_WIDTH ${internal_datapath_width}
+  if {$transceiver != "GTM"} {
+    dict set xcvr_param RX_INT_DATA_WIDTH ${internal_datapath_width}
+  }
   dict set xcvr_param RX_OUTCLK_SOURCE {RXPROGDIVCLK}
   dict set xcvr_param RXRECCLK_FREQ_VAL ${rx_progdiv_clock}
   dict set xcvr_param RXPROGDIV_FREQ_VAL ${rx_progdiv_clock}
@@ -71,21 +79,24 @@ proc create_xcvr_subsystem {
 
   # Tx parameters
   dict set xcvr_param TX_LINE_RATE ${tx_lane_rate}
-  dict set xcvr_param TX_DATA_ENCODING ${data_encoding}
+  dict set xcvr_param TX_DATA_ENCODING [expr {$transceiver != "GTM" ? $data_encoding : "RAW"}]
+  dict set xcvr_param TX_USER_DATA_WIDTH [expr {$transceiver != "GTM" ? $datapath_width : $internal_datapath_width}]
   dict set xcvr_param TX_REFCLK_FREQUENCY ${ref_clock}
-  dict set xcvr_param TX_USER_DATA_WIDTH ${datapath_width}
-  dict set xcvr_param TX_INT_DATA_WIDTH ${internal_datapath_width}
-  dict set xcvr_param TXPROGDIV_FREQ_VAL ${tx_progdiv_clock}
+  if {$transceiver != "GTM"} {
+    dict set xcvr_param TX_INT_DATA_WIDTH ${internal_datapath_width}
+  }
   dict set xcvr_param TX_OUTCLK_SOURCE {TXPROGDIVCLK}
+  dict set xcvr_param TXPROGDIV_FREQ_VAL ${tx_progdiv_clock}
   dict set xcvr_param TX_PLL_TYPE {LCPLL}
 
   set phy_params [dict create]
   dict set phy_params CONFIG.ENABLE_REG_INTERFACE {true}
   dict set phy_params CONFIG.REG_CONF_INTF {AXI_LITE}
+  dict set phy_params CONFIG.GT_TYPE ${transceiver}
   dict set phy_params CONFIG.NO_OF_QUADS ${num_quads}
   dict set phy_params CONFIG.NO_OF_INTERFACE {1}
   dict set phy_params CONFIG.LOCATE_BUFG {CORE}
-  dict set phy_params CONFIG.INTF0_PRESET ${transceiver}-JESD204_${jesd_mode}
+  dict set phy_params CONFIG.INTF0_PRESET ${preset}
   dict set phy_params CONFIG.INTF0_GT_SETTINGS(LR0_SETTINGS) ${xcvr_param}
   if {$direction != "RXTX"} {
     dict set phy_params CONFIG.INTF0_GT_DIRECTION SIMPLEX_${direction}
@@ -100,7 +111,7 @@ proc create_xcvr_subsystem {
     dict set phy_params CONFIG.INTF1_GT_DIRECTION {SIMPLEX_TX}
     dict set phy_params CONFIG.INTF0_NO_OF_LANES $rx_no_lanes
     dict set phy_params CONFIG.INTF1_NO_OF_LANES $tx_no_lanes
-    dict set phy_params CONFIG.INTF1_PRESET ${transceiver}-JESD204_${jesd_mode}
+    dict set phy_params CONFIG.INTF1_PRESET ${preset}
     dict set phy_params CONFIG.INTF1_GT_SETTINGS(LR0_SETTINGS) ${xcvr_param}
   }
 
@@ -180,6 +191,10 @@ proc create_xcvr_subsystem {
 #       RXTX : Duplex mode
 #       RX   : Rx link only
 #       TX   : Tx link only
+#   external_link_clk : applies to GTM and JESD204C:
+#       - when not set a clk_wizard is added to generate the LR / 66 clock for the gearbox
+#       - when set the LR / 66 clock is expected to be external to the subsystem and connected from the BD
+#
 proc create_versal_jesd_xcvr_subsystem {
   {ip_name versal_phy}
   {jesd_mode 64B66B}
@@ -190,6 +205,7 @@ proc create_versal_jesd_xcvr_subsystem {
   {ref_clock 375}
   {transceiver GTY}
   {intf_cfg RXTX}
+  {external_link_clk 0}
 } {
   set rx_quads                 [expr int(ceil(1.0 * $rx_no_lanes / 4))]
   set tx_quads                 [expr int(ceil(1.0 * $tx_no_lanes / 4))]
@@ -210,6 +226,7 @@ proc create_versal_jesd_xcvr_subsystem {
   create_bd_pin -dir I ${ip_name}/GT_REFCLK -type clk
   create_bd_pin -dir I ${ip_name}/s_axi_clk
   create_bd_pin -dir I ${ip_name}/s_axi_resetn
+
   if {$intf_cfg != "TX"} {
     create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk
     create_bd_pin -dir I ${ip_name}/en_char_align
@@ -228,8 +245,24 @@ proc create_versal_jesd_xcvr_subsystem {
   if {$intf_cfg != "TX"} {
     ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx
     ad_connect ${ip_name}/xcvr/INTF${rx_intf}_rx_clr_out ${ip_name}/bufg_gt_rx/gt_bufgtclr
-    ad_connect ${ip_name}/xcvr/QUAD0_RX0_outclk          ${ip_name}/bufg_gt_rx/outclk
-    ad_connect ${ip_name}/bufg_gt_rx/usrclk              ${ip_name}/rxusrclk_out
+    ad_connect ${ip_name}/xcvr/INTF${rx_intf}_RX_USRCLK  ${ip_name}/bufg_gt_rx/outclk
+    if {$transceiver != "GTM" || $link_mode == 1} {
+      ad_connect ${ip_name}/bufg_gt_rx/usrclk              ${ip_name}/rxusrclk_out
+    } else {
+      if {$external_link_clk} {
+        create_bd_pin -dir I ${ip_name}/rx_usrclk_in
+        ad_connect ${ip_name}/rx_usrclk_in ${ip_name}/rxusrclk_out
+      } else {
+        ad_ip_instance clk_wizard ${ip_name}/rx_clkwiz
+        # ad_ip_parameter ${ip_name}/rx_clkwiz CONFIG.PRIM_IN_FREQ.VALUE_SRC {USER}
+        # ad_ip_parameter ${ip_name}/rx_clkwiz CONFIG.PRIM_IN_FREQ [format %.5f [expr $rx_lane_rate * 1000.0 / 64]]
+        ad_ip_parameter ${ip_name}/rx_clkwiz CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY [format %.5f [expr $rx_lane_rate * 1000.0 / 66]]
+        ad_ip_parameter ${ip_name}/rx_clkwiz CONFIG.USE_PHASE_ALIGNMENT {true}
+        ad_ip_parameter ${ip_name}/rx_clkwiz CONFIG.USE_LOCKED {true}
+        ad_connect ${ip_name}/bufg_gt_rx/usrclk   ${ip_name}/rx_clkwiz/clk_in1
+        ad_connect ${ip_name}/rx_clkwiz/clk_out1  ${ip_name}/rxusrclk_out
+      }
+    }
 
     for {set j 0} {$j < $rx_quads} {incr j} {
       create_bd_pin -dir I -from 3 -to 0 ${ip_name}/rx_${j}_p
@@ -240,22 +273,53 @@ proc create_versal_jesd_xcvr_subsystem {
 
     for {set j 0} {$j < $rx_no_lanes} {incr j} {
       ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/rx_adapt_${j} [list \
+        TRANSCEIVER $transceiver \
         LINK_MODE $link_mode \
       ]
       ad_connect ${ip_name}/rx_adapt_${j}/RX_GT_IP_Interface ${ip_name}/xcvr/INTF${rx_intf}_RX${j}_GT_IP_Interface
 
       create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j}
       ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX
-      ad_connect ${ip_name}/rx_adapt_${j}/usr_clk ${ip_name}/xcvr/INTF${rx_intf}_rx_usrclk
       ad_connect ${ip_name}/rx_adapt_${j}/en_char_align ${ip_name}/en_char_align
+
+      if {$transceiver != "GTM" || $link_mode == 1} {
+        ad_connect ${ip_name}/xcvr/INTF${rx_intf}_rx_usrclk ${ip_name}/rx_adapt_${j}/usr_clk
+        ad_connect ${ip_name}/xcvr/INTF${rx_intf}_rx_usrclk ${ip_name}/rx_adapt_${j}/phy_clk
+        ad_connect ${ip_name}/xcvr/INTF${rx_intf}_rst_rx_done_out ${ip_name}/rx_adapt_${j}/phy_rstn
+      } else {
+        ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/rx_adapt_${j}/phy_clk
+        if {$external_link_clk} {
+          ad_connect ${ip_name}/rx_usrclk_in ${ip_name}/rx_adapt_${j}/usr_clk
+          ad_connect ${ip_name}/xcvr/INTF${rx_intf}_rst_rx_done_out ${ip_name}/rx_adapt_${j}/phy_rstn
+        } else {
+          ad_connect ${ip_name}/rx_clkwiz/clk_out1 ${ip_name}/rx_adapt_${j}/usr_clk
+          ad_connect ${ip_name}/rx_clkwiz/locked ${ip_name}/rx_adapt_${j}/phy_rstn
+        }
+      }
     }
   }
 
   if {$intf_cfg != "RX"} {
     ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx
     ad_connect ${ip_name}/xcvr/INTF${tx_intf}_tx_clr_out ${ip_name}/bufg_gt_tx/gt_bufgtclr
-    ad_connect ${ip_name}/xcvr/QUAD0_TX0_outclk          ${ip_name}/bufg_gt_tx/outclk
-    ad_connect ${ip_name}/bufg_gt_tx/usrclk              ${ip_name}/txusrclk_out
+    ad_connect ${ip_name}/xcvr/INTF${tx_intf}_TX_USRCLK  ${ip_name}/bufg_gt_tx/outclk
+    if {$transceiver != "GTM" || $link_mode == 1} {
+      ad_connect ${ip_name}/bufg_gt_tx/usrclk            ${ip_name}/txusrclk_out
+    } else {
+      if {$external_link_clk} {
+        create_bd_pin -dir I ${ip_name}/tx_usrclk_in
+        ad_connect ${ip_name}/tx_usrclk_in ${ip_name}/txusrclk_out
+      } else {
+        ad_ip_instance clk_wizard ${ip_name}/tx_clkwiz
+        # ad_ip_parameter ${ip_name}/tx_clkwiz CONFIG.PRIM_IN_FREQ.VALUE_SRC {USER}
+        # ad_ip_parameter ${ip_name}/tx_clkwiz CONFIG.PRIM_IN_FREQ [format %.5f [expr $tx_lane_rate * 1000.0 / 64]]
+        ad_ip_parameter ${ip_name}/tx_clkwiz CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY [format %.5f [expr $tx_lane_rate * 1000.0 / 66]]
+        ad_ip_parameter ${ip_name}/tx_clkwiz CONFIG.USE_PHASE_ALIGNMENT {true}
+        ad_ip_parameter ${ip_name}/tx_clkwiz CONFIG.USE_LOCKED {true}
+        ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/tx_clkwiz/clk_in1
+        ad_connect ${ip_name}/tx_clkwiz/clk_out1 ${ip_name}/txusrclk_out
+      }
+    }
 
     for {set j 0} {$j < $tx_quads} {incr j} {
       create_bd_pin -dir O -from 3 -to 0 ${ip_name}/tx_${j}_p
@@ -266,13 +330,28 @@ proc create_versal_jesd_xcvr_subsystem {
 
     for {set j 0} {$j < $tx_no_lanes} {incr j} {
       ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/tx_adapt_${j} [list \
+        TRANSCEIVER $transceiver \
         LINK_MODE $link_mode \
       ]
       ad_connect ${ip_name}/tx_adapt_${j}/TX_GT_IP_Interface ${ip_name}/xcvr/INTF${tx_intf}_TX${j}_GT_IP_Interface
 
       create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j}
       ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX
-      ad_connect ${ip_name}/tx_adapt_${j}/usr_clk ${ip_name}/xcvr/INTF${tx_intf}_tx_usrclk
+
+      if {$transceiver != "GTM" || $link_mode == 1} {
+        ad_connect ${ip_name}/xcvr/INTF${tx_intf}_tx_usrclk ${ip_name}/tx_adapt_${j}/usr_clk
+        ad_connect ${ip_name}/xcvr/INTF${tx_intf}_tx_usrclk ${ip_name}/tx_adapt_${j}/phy_clk
+        ad_connect ${ip_name}/xcvr/INTF${tx_intf}_rst_tx_done_out ${ip_name}/tx_adapt_${j}/phy_rstn
+      } else {
+        ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/tx_adapt_${j}/phy_clk
+        if {$external_link_clk} {
+          ad_connect ${ip_name}/tx_usrclk_in ${ip_name}/tx_adapt_${j}/usr_clk
+          ad_connect ${ip_name}/xcvr/INTF${tx_intf}_rst_tx_done_out ${ip_name}/tx_adapt_${j}/phy_rstn
+        } else {
+          ad_connect ${ip_name}/tx_clkwiz/clk_out1 ${ip_name}/tx_adapt_${j}/usr_clk
+          ad_connect ${ip_name}/tx_clkwiz/locked ${ip_name}/tx_adapt_${j}/phy_rstn
+        }
+      }
     }
   }
 
diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
index c95272d5a58..3a9b6e91be5 100644
--- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
+++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
@@ -36,6 +36,10 @@ if {![info exists TRANSCEIVER_TYPE]} {
   set TRANSCEIVER_TYPE GTY
 }
 
+if {![info exists EXTERNAL_LINK_CLK]} {
+  set EXTERNAL_LINK_CLK 0
+}
+
 # Common parameter for TX and RX
 set JESD_MODE  $ad_project_params(JESD_MODE)
 set RX_LANE_RATE $ad_project_params(RX_LANE_RATE)
@@ -157,6 +161,8 @@ if {!$ADI_PHY_SEL} {
   create_bd_port -dir I tx_sysref_0
   create_bd_port -dir O rx_sync_0
   create_bd_port -dir I tx_sync_0
+  create_bd_port -dir I rx_usrclk_in
+  create_bd_port -dir I tx_usrclk_in
 }
 
 # common xcvr
@@ -209,7 +215,7 @@ if {$ADI_PHY_SEL == 1} {
 
   switch $INTF_CFG {
     "RXTX" {
-      create_versal_jesd_xcvr_subsystem jesd204_phy_rxtx $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
+      create_versal_jesd_xcvr_subsystem jesd204_phy_rxtx $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG $EXTERNAL_LINK_CLK
       set rx_phy jesd204_phy_rxtx
       set tx_phy jesd204_phy_rxtx
       ad_connect ref_clk_q0      ${rx_phy}/GT_REFCLK
@@ -223,9 +229,13 @@ if {$ADI_PHY_SEL == 1} {
       ad_connect ${rx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath
       ad_connect ${rx_phy}/rx_resetdone rx_resetdone
       ad_connect ${rx_phy}/tx_resetdone tx_resetdone
+      if {$EXTERNAL_LINK_CLK && $JESD_MODE == "64B66B"} {
+        ad_connect rx_usrclk_in     ${rx_phy}/rx_usrclk_in
+        ad_connect tx_usrclk_in     ${tx_phy}/tx_usrclk_in
+      }
     }
     "RX" {
-      create_versal_jesd_xcvr_subsystem jesd204_phy_rx $JESD_MODE $RX_NUM_OF_LANES 0 $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
+      create_versal_jesd_xcvr_subsystem jesd204_phy_rx $JESD_MODE $RX_NUM_OF_LANES 0 $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG $EXTERNAL_LINK_CLK
       set rx_phy jesd204_phy_rx
       ad_connect ref_clk_q0      ${rx_phy}/GT_REFCLK
       ad_connect gt_reset        ${rx_phy}/gtreset_in
@@ -235,9 +245,12 @@ if {$ADI_PHY_SEL == 1} {
       ad_connect ${rx_phy}/gtreset_rx_datapath gt_reset_rx_datapath
       ad_connect ${rx_phy}/gtreset_rx_pll_and_datapath gt_reset_rx_pll_and_datapath
       ad_connect ${rx_phy}/rx_resetdone rx_resetdone
+      if {$EXTERNAL_LINK_CLK && $JESD_MODE == "64B66B"} {
+        ad_connect rx_usrclk_in     ${rx_phy}/rx_usrclk_in
+      }
     }
     "TX" {
-      create_versal_jesd_xcvr_subsystem jesd204_phy_tx $JESD_MODE 0 $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
+      create_versal_jesd_xcvr_subsystem jesd204_phy_tx $JESD_MODE 0 $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG $EXTERNAL_LINK_CLK
       set tx_phy jesd204_phy_tx
       ad_connect ref_clk_q0      ${tx_phy}/GT_REFCLK
       ad_connect gt_reset        ${tx_phy}/gtreset_in
@@ -247,6 +260,9 @@ if {$ADI_PHY_SEL == 1} {
       ad_connect ${tx_phy}/gtreset_tx_datapath gt_reset_tx_datapath
       ad_connect ${tx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath
       ad_connect ${tx_phy}/tx_resetdone tx_resetdone
+      if {$EXTERNAL_LINK_CLK && $JESD_MODE == "64B66B"} {
+        ad_connect tx_usrclk_in     ${tx_phy}/tx_usrclk_in
+      }
     }
   }
 }