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testbenches/project/ad738x: Update testbench
Testbench was updated to use the new features related to the spi lane mask. Signed-off-by: Carlos Souza <[email protected]>
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6 files changed

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6 files changed

+671
-434
lines changed
Lines changed: 59 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,61 @@
11
global ad_project_params
22

3-
set ad_project_params(ALERT_SPI_N) 0
4-
set ad_project_params(NUM_OF_SDI) 2
3+
# SPI Engine DUT parameters
4+
set ad_project_params(ALERT_SPI_N) 0
5+
set ad_project_params(DATA_WIDTH) 32
6+
set ad_project_params(NUM_OF_CS) 1
7+
set ad_project_params(NUM_OF_SDIO) 4
8+
set ad_project_params(NUM_OF_SDO) 4
9+
set ad_project_params(CMD_MEM_ADDR_WIDTH) 4
10+
set ad_project_params(DATA_MEM_ADDR_WIDTH) 5
11+
set ad_project_params(SDI_FIFO_ADDR_WIDTH) 7
12+
set ad_project_params(SDO_FIFO_ADDR_WIDTH) 7
13+
set ad_project_params(SYNC_FIFO_ADDR_WIDTH) 4
14+
set ad_project_params(CMD_FIFO_ADDR_WIDTH) 4
15+
set ad_project_params(SDO_STREAMING) 0
16+
17+
# Test parameters
18+
set ad_project_params(DATA_DLENGTH) 16
19+
set ad_project_params(THREE_WIRE) 0
20+
set ad_project_params(CPOL) 1
21+
set ad_project_params(CPHA) 1
22+
set ad_project_params(SDO_IDLE_STATE) 0
23+
set ad_project_params(SLAVE_TIN) 0
24+
set ad_project_params(SLAVE_TOUT) 7
25+
set ad_project_params(MASTER_TIN) 0
26+
set ad_project_params(MASTER_TOUT) 0
27+
set ad_project_params(CS_TO_MISO) 0
28+
set ad_project_params(CLOCK_DIVIDER) 0
29+
set ad_project_params(NUM_OF_WORDS) 2
30+
set ad_project_params(NUM_OF_TRANSFERS) 10
31+
set ad_project_params(SDI_LANE_MASK) 'h0f
32+
set ad_project_params(SDO_LANE_MASK) 'h01
33+
set ad_project_params(CS_ACTIVE_HIGH) 0
34+
35+
set spi_s_vip_cfg [ list \
36+
MODE 0 \
37+
CPOL $ad_project_params(CPOL) \
38+
CPHA $ad_project_params(CPHA) \
39+
INV_CS $ad_project_params(CS_ACTIVE_HIGH) \
40+
SLAVE_TIN $ad_project_params(SLAVE_TIN) \
41+
SLAVE_TOUT $ad_project_params(SLAVE_TOUT) \
42+
MASTER_TIN $ad_project_params(MASTER_TIN) \
43+
MASTER_TOUT $ad_project_params(MASTER_TOUT) \
44+
CS_TO_MISO $ad_project_params(CS_TO_MISO) \
45+
DATA_DLENGTH $ad_project_params(DATA_DLENGTH) \
46+
NUM_OF_SDI $ad_project_params(NUM_OF_SDIO) \
47+
NUM_OF_SDO $ad_project_params(NUM_OF_SDO) \
48+
SDI_LANE_MASK $ad_project_params(SDI_LANE_MASK) \
49+
SDO_LANE_MASK $ad_project_params(SDO_LANE_MASK) \
50+
]
51+
set ad_project_params(spi_s_vip_cfg) $spi_s_vip_cfg
52+
53+
set axis_sdo_src_vip_cfg [ list \
54+
INTERFACE_MODE {MASTER} \
55+
HAS_TREADY 1 \
56+
HAS_TLAST 0 \
57+
TDATA_NUM_BYTES [expr $ad_project_params(DATA_WIDTH)/8] \
58+
TDEST_WIDTH 0 \
59+
TID_WIDTH 0 \
60+
]
61+
set ad_project_params(axis_sdo_src_vip_cfg) $axis_sdo_src_vip_cfg
Lines changed: 134 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,134 @@
1+
// ***************************************************************************
2+
// ***************************************************************************
3+
// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
4+
//
5+
// In this HDL repository, there are many different and unique modules, consisting
6+
// of various HDL (Verilog or VHDL) components. The individual modules are
7+
// developed independently, and may be accompanied by separate and unique license
8+
// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
27+
// 2. An ADI specific BSD license, which can be found in the top level directory
28+
// of this repository (LICENSE_ADIBSD), and also on-line at:
29+
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
30+
// This will allow to generate bit files and not release the source code,
31+
// as long as it attaches to an ADI device.
32+
//
33+
// ***************************************************************************
34+
// ***************************************************************************
35+
36+
`include "utils.svh"
37+
`include "axis_definitions.svh"
38+
39+
package spi_environment_pkg;
40+
41+
import logger_pkg::*;
42+
import adi_environment_pkg::*;
43+
44+
import m_axis_sequencer_pkg::*;
45+
import adi_axis_agent_pkg::*;
46+
import adi_spi_vip_pkg::*;
47+
import adi_spi_vip_if_base_pkg::*;
48+
49+
`ifdef DEF_SDO_STREAMING
50+
import `PKGIFY(test_harness, sdo_src)::*;
51+
`endif
52+
53+
class spi_environment extends adi_environment;
54+
55+
// Agents
56+
adi_spi_agent spi_agent;
57+
`ifdef DEF_SDO_STREAMING
58+
adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(test_harness_sdo_src_0)) sdo_src_agent;
59+
`endif
60+
61+
//============================================================================
62+
// Constructor
63+
//============================================================================
64+
function new(
65+
input string name,
66+
67+
`ifdef DEF_SDO_STREAMING
68+
virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness_sdo_src_0)) sdo_src_axis_vip_if,
69+
`endif
70+
adi_spi_vip_if_base spi_s_vip_if);
71+
72+
super.new(name);
73+
74+
// Creating the agents
75+
this.spi_agent = new("SPI VIP Agent", spi_s_vip_if, this);
76+
`ifdef DEF_SDO_STREAMING
77+
this.sdo_src_agent = new("SDO Source AXI Stream Agent", sdo_src_axis_vip_if);
78+
`endif
79+
80+
// downgrade reset check: we are currently using a clock generator for the SPI clock,
81+
// so it will come a bit after the reset and trigger the default error.
82+
// This is harmless for this test (we don't want to test any reset scheme)
83+
`ifdef DEF_SDO_STREAMING
84+
sdo_src_axis_vip_if.set_xilinx_reset_check_to_warn();
85+
`endif
86+
endfunction
87+
88+
//============================================================================
89+
// Configure environment
90+
// - Configure the sequencers with an initial configuration before starting
91+
//============================================================================
92+
task configure();
93+
`ifdef DEF_SDO_STREAMING
94+
this.sdo_src_agent.sequencer.set_stop_policy(STOP_POLICY_PACKET);
95+
this.sdo_src_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_TEST_DATA);
96+
`endif
97+
endtask
98+
99+
//============================================================================
100+
// Start environment
101+
// - Connect all the agents to the scoreboard
102+
// - Start the agents
103+
//============================================================================
104+
task start();
105+
this.spi_agent.start();
106+
`ifdef DEF_SDO_STREAMING
107+
this.sdo_src_agent.start();
108+
`endif
109+
endtask
110+
111+
//============================================================================
112+
// Run subroutine
113+
//============================================================================
114+
task run();
115+
fork
116+
`ifdef DEF_SDO_STREAMING
117+
this.sdo_src_agent.run();
118+
`endif
119+
join_none
120+
endtask
121+
122+
//============================================================================
123+
// Stop subroutine
124+
//============================================================================
125+
task stop();
126+
this.spi_agent.stop();
127+
`ifdef DEF_SDO_STREAMING
128+
this.sdo_src_agent.stop();
129+
`endif
130+
endtask
131+
132+
endclass
133+
134+
endpackage

testbenches/project/ad738x/system_bd.tcl

Lines changed: 33 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -41,11 +41,36 @@ global ad_project_params
4141

4242
source $ad_hdl_dir/projects/ad738x_fmc/common/ad738x_bd.tcl
4343

44-
create_bd_port -dir O ad738x_spi_clk
45-
create_bd_port -dir O ad738x_irq
44+
# Add test-specific VIPs
45+
puts "CPOL: "
46+
puts [$ad_project_params(CPOL)]
47+
puts "CPHA: "
48+
puts [$ad_project_params(CPHA)]
4649

47-
ad_connect ad738x_spi_clk spi_clkgen/clk_0
48-
ad_connect ad738x_irq spi_ad738x_adc/irq
50+
ad_ip_instance adi_spi_vip spi_s_vip $ad_project_params(spi_s_vip_cfg)
51+
adi_sim_add_define "SPI_S=spi_s_vip"
52+
53+
# Create a new interface with Monitor mode
54+
create_bd_intf_port -mode Monitor -vlnv analog.com:interface:spi_engine_rtl:1.0 ad738x_spi_vip
55+
56+
# it is necessary to remove the connection with the master interface of the quad_ada77681_bd
57+
ad_disconnect ad738x_spi $hier_spi_engine/m_spi
58+
ad_connect spi_s_vip/s_spi $hier_spi_engine/m_spi
59+
ad_connect ad738x_spi_vip $hier_spi_engine/m_spi
60+
61+
if ($ad_project_params(SDO_STREAMING)) {
62+
ad_ip_instance axi4stream_vip sdo_src $ad_project_params(axis_sdo_src_vip_cfg)
63+
adi_sim_add_define "SDO_SRC=sdo_src"
64+
ad_connect spi_clk sdo_src/aclk
65+
ad_connect sys_cpu_resetn sdo_src/aresetn
66+
ad_connect sdo_src/m_axis $hier_spi_engine/s_axis_sample
67+
}
68+
69+
create_bd_port -dir O ad738x_spi_vip_clk
70+
create_bd_port -dir O ad738x_irq
71+
72+
ad_connect ad738x_spi_vip_clk spi_clkgen/clk_0
73+
ad_connect ad738x_irq $hier_spi_engine/irq
4974

5075
set BA_SPI_REGMAP 0x44A00000
5176
set_property offset $BA_SPI_REGMAP [get_bd_addr_segs {mng_axi_vip/Master_AXI/spi_ad738x_adc_axi_regmap}]
@@ -55,10 +80,10 @@ set BA_DMA 0x44A30000
5580
set_property offset $BA_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad738x_dma}]
5681
adi_sim_add_define "AD738x_DMA_BA=[format "%d" ${BA_DMA}]"
5782

58-
set BA_PWM 0x44B00000
59-
set_property offset $BA_PWM [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_spi_trigger_gen}]
60-
adi_sim_add_define "AD738x_PWM_GEN_BA=[format "%d" ${BA_PWM}]"
61-
6283
set BA_CLKGEN 0x44A70000
6384
set_property offset $BA_CLKGEN [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_spi_clkgen}]
6485
adi_sim_add_define "AD738x_AXI_CLKGEN_BA=[format "%d" ${BA_CLKGEN}]"
86+
87+
set BA_PWM 0x44B00000
88+
set_property offset $BA_PWM [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_spi_trigger_gen}]
89+
adi_sim_add_define "AD738x_PWM_GEN_BA=[format "%d" ${BA_PWM}]"

testbenches/project/ad738x/system_project.tcl

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,13 +31,15 @@ if {[expr {![info exists use_smartconnect]}]} {
3131
# Create the project
3232
adi_sim_project_xilinx $project_name "xc7z007sclg400-1"
3333

34+
source $ad_tb_dir/library/includes/sp_include_axis.tcl
3435
source $ad_tb_dir/library/includes/sp_include_dmac.tcl
3536
source $ad_tb_dir/library/includes/sp_include_spi_engine.tcl
37+
source $ad_tb_dir/library/includes/sp_include_pwm_gen.tcl
38+
source $ad_tb_dir/library/includes/sp_include_clk_gen.tcl
3639

3740
# Add test files to the project
3841
adi_sim_project_files [list \
39-
"$ad_tb_dir/library/regmaps/adi_regmap_clkgen_pkg.sv" \
40-
"$ad_tb_dir/library/regmaps/adi_regmap_pwm_gen_pkg.sv" \
42+
"spi_environment.sv" \
4143
"tests/test_program.sv" \
4244
]
4345

testbenches/project/ad738x/system_tb.sv

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -37,27 +37,27 @@
3737

3838
module system_tb();
3939

40-
wire ad738x_spi_sclk;
41-
wire ad738x_spi_sdo;
42-
wire [`NUM_OF_SDI-1:0] ad738x_spi_sdi;
43-
wire ad738x_spi_cs;
44-
wire ad738x_spi_clk;
45-
wire ad738x_irq;
40+
wire ad738x_irq;
41+
wire ad738x_spi_sclk;
42+
wire [(`NUM_OF_CS - 1):0] ad738x_spi_cs;
43+
wire ad738x_spi_clk;
44+
wire ad738x_spi_sdo;
45+
wire [`NUM_OF_SDIO-1:0] ad738x_spi_sdi;
4646

4747
`TEST_PROGRAM test(
48-
.ad738x_spi_clk (ad738x_spi_clk),
4948
.ad738x_irq (ad738x_irq),
50-
.ad738x_spi_sdi(ad738x_spi_sdi),
49+
.ad738x_spi_sclk (ad738x_spi_sclk),
5150
.ad738x_spi_cs (ad738x_spi_cs),
52-
.ad738x_spi_sclk (ad738x_spi_sclk));
51+
.ad738x_spi_clk (ad738x_spi_clk),
52+
.ad738x_spi_sdi(ad738x_spi_sdi));
5353

5454
test_harness `TH (
55-
.ad738x_spi_clk (ad738x_spi_clk),
5655
.irq (),
5756
.ad738x_irq(ad738x_irq),
58-
.ad738x_spi_sdo (ad738x_spi_sdo),
59-
.ad738x_spi_sdi (ad738x_spi_sdi),
60-
.ad738x_spi_cs (ad738x_spi_cs),
61-
.ad738x_spi_sclk (ad738x_spi_sclk));
57+
.ad738x_spi_vip_sclk (ad738x_spi_sclk),
58+
.ad738x_spi_vip_cs (ad738x_spi_cs),
59+
.ad738x_spi_vip_clk (ad738x_spi_clk),
60+
.ad738x_spi_vip_sdo (ad738x_spi_sdo),
61+
.ad738x_spi_vip_sdi (ad738x_spi_sdi));
6262

6363
endmodule

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