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@IstvanZsSzekely IstvanZsSzekely commented May 24, 2024

  • Updated test_harness naming to the new convention found in HDL repository
  • Updated adrv9009 block design to connect to the 2nd interconnect

Use this PR together with this PR. The system is now built properly, but the testbenches are still failing.

@IstvanZsSzekely IstvanZsSzekely added the bug Something isn't working label May 24, 2024
@IstvanZsSzekely IstvanZsSzekely requested a review from FilipG24 May 24, 2024 11:27
@IstvanZsSzekely IstvanZsSzekely self-assigned this May 24, 2024
@IstvanZsSzekely IstvanZsSzekely marked this pull request as ready for review May 24, 2024 12:33
@IstvanZsSzekely IstvanZsSzekely marked this pull request as draft September 6, 2024 07:05
@IstvanZsSzekely IstvanZsSzekely marked this pull request as ready for review September 9, 2024 11:11
- Changed the interconnect cascading option to automatically cascade in testbenches
- Updated test_harness naming to the new convention
- Updated ADRV9009 block design

Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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