From f1e88cc387275c769479a406224be166d1528405 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 16 Dec 2024 11:05:22 +0200 Subject: [PATCH 01/37] infrastructure refactorization Signed-off-by: Istvan-Zsolt Szekely --- library/drivers/common/mailbox.sv | 67 ----- library/drivers/common/scoreboard.sv | 239 ++++++---------- library/drivers/common/watchdog.sv | 1 + library/drivers/common/x_monitor.sv | 182 ++++-------- library/includes/Makeinclude_axi.mk | 3 + library/includes/Makeinclude_axis.mk | 3 + library/includes/Makeinclude_common.mk | 1 + library/includes/Makeinclude_scoreboard.mk | 3 +- library/includes/sp_include_axi.tcl | 3 + library/includes/sp_include_axis.tcl | 3 + library/includes/sp_include_common.tcl | 1 + library/includes/sp_include_scoreboard.tcl | 3 +- library/regmaps/adi_peripheral_pkg.sv | 1 + library/regmaps/reg_accessor.sv | 2 +- library/utilities/adi_common_pkg.sv | 161 +++++++++++ library/utilities/logger_pkg.sv | 50 ---- library/utilities/test_harness_env.sv | 103 ++----- library/utilities/utils.svh | 223 +++++++-------- library/vip/adi/base/pub_sub_pkg.sv | 97 +++++++ library/vip/amd/adi_axi_agent.sv | 108 +++++++ library/vip/amd/adi_axis_agent.sv | 108 +++++++ library/vip/amd/m_axi_sequencer.sv | 9 +- library/vip/amd/m_axis_sequencer.sv | 26 +- library/vip/amd/s_axi_sequencer.sv | 16 +- library/vip/amd/s_axis_sequencer.sv | 35 +-- testbenches/ip/base/environment.sv | 91 ------ testbenches/ip/base/tests/test_program.sv | 15 +- testbenches/ip/scoreboard/environment.sv | 263 ++++-------------- testbenches/ip/scoreboard/system_bd.tcl | 2 +- .../ip/scoreboard/tests/test_program.sv | 142 ++++++---- 30 files changed, 942 insertions(+), 1019 deletions(-) delete mode 100644 library/drivers/common/mailbox.sv create mode 100644 library/utilities/adi_common_pkg.sv create mode 100644 library/vip/adi/base/pub_sub_pkg.sv create mode 100644 library/vip/amd/adi_axi_agent.sv create mode 100644 library/vip/amd/adi_axis_agent.sv delete mode 100644 testbenches/ip/base/environment.sv diff --git a/library/drivers/common/mailbox.sv b/library/drivers/common/mailbox.sv deleted file mode 100644 index 4f468bc2..00000000 --- a/library/drivers/common/mailbox.sv +++ /dev/null @@ -1,67 +0,0 @@ -`include "utils.svh" - -package mailbox_pkg; - - import logger_pkg::*; - - class mailbox_c #(type T) extends adi_component; - - T queue[$]; - - int size_max; - - event q_event; - - // constructor - function new( - input string name, - input int size_max = 0, - input adi_component parent = null); - - super.new(name, parent); - - this.size_max = size_max; - endfunction - - function int num(); - return this.queue.size(); - endfunction - - task get(ref T element); - if (this.num() == 0) - @this.q_event; - element = this.queue.pop_back(); - ->this.q_event; - endtask - - function int try_get(ref T element); - if (this.num() == 0) - return 0; - element = this.queue.pop_back(); - ->this.q_event; - return 1; - endfunction - - task put(input T element); - if (this.size_max == this.num() && this.size_max != 0) - @this.q_event; - this.queue.push_front(element); - ->this.q_event; - endtask - - function int try_put(input T element); - if (this.size_max == this.num() && this.size_max != 0) - return 0; - this.queue.push_front(element); - ->this.q_event; - return 1; - endfunction - - task flush(); - T element; - while(this.try_get(element)); - endtask - - endclass - -endpackage diff --git a/library/drivers/common/scoreboard.sv b/library/drivers/common/scoreboard.sv index 640dabab..f5fe568a 100644 --- a/library/drivers/common/scoreboard.sv +++ b/library/drivers/common/scoreboard.sv @@ -6,23 +6,62 @@ package scoreboard_pkg; import axi4stream_vip_pkg::*; import axi_vip_pkg::*; import logger_pkg::*; - import x_monitor_pkg::*; - import mailbox_pkg::*; + import adi_common_pkg::*; + import pub_sub_pkg::*; class scoreboard extends adi_component; - typedef enum bit { CYCLIC=0, ONESHOT } sink_type_t; - protected sink_type_t sink_type; + class subscriber_class extends adi_subscriber #(logic [7:0]); + + protected scoreboard scoreboard_ref; + + protected logic [7:0] byte_stream [$]; + + function new( + input string name, + input scoreboard scoreboard_ref, + input adi_component parent = null); + + super.new(name, parent); + + this.scoreboard_ref = scoreboard_ref; + endfunction: new + + virtual function void update(input data_type data [$]); + this.info($sformatf("Data received: %d", data.size()), ADI_VERBOSITY_MEDIUM); + while (data.size()) begin + this.byte_stream.push_back(data.pop_front); + end + + if (this.scoreboard_ref.enabled) begin + this.scoreboard_ref.compare_transaction(); + end + endfunction: update + + function logic [7:0] get_data(); + return this.byte_stream.pop_front(); + endfunction: get_data + + function void put_data(logic [7:0] data); + this.byte_stream.push_back(data); + endfunction: put_data + + function int get_size(); + return this.byte_stream.size(); + endfunction: get_size - // List of analysis ports from the monitors - protected x_monitor source_monitor; - protected x_monitor sink_monitor; + function void clear_stream(); + this.byte_stream.delete(); + endfunction: clear_stream - protected logic [7:0] source_byte_stream [$]; - protected logic [7:0] sink_byte_stream [$]; + endclass: subscriber_class - protected int source_byte_stream_size; - protected int sink_byte_stream_size; + + subscriber_class subscriber_source; + subscriber_class subscriber_sink; + + typedef enum bit { CYCLIC=0, ONESHOT } sink_type_t; + protected sink_type_t sink_type; // counters and synchronizers protected bit enabled; @@ -31,8 +70,6 @@ package scoreboard_pkg; // protected event end_of_first_cycle; protected event byte_streams_empty; protected event stop_scoreboard; - protected event source_transaction_event; - protected event sink_transaction_event; // constructor function new( @@ -41,186 +78,82 @@ package scoreboard_pkg; super.new(name, parent); + this.subscriber_source = new("Subscriber Source", this); + this.subscriber_sink = new("Subscriber Sink", this); + this.enabled = 0; this.sink_type = ONESHOT; - this.source_byte_stream_size = 0; - this.sink_byte_stream_size = 0; this.byte_streams_empty_sig = 1; - endfunction: new - // connect the analysis ports of the monitor to the scoreboard - function void set_source_stream( - x_monitor source_monitor); - - this.source_monitor = source_monitor; - - endfunction: set_source_stream - - function void set_sink_stream( - x_monitor sink_monitor); - - this.sink_monitor = sink_monitor; - - endfunction: set_sink_stream - // run task task run(); - - fork - this.enabled = 1; - this.get_source_transaction(); - this.get_sink_transaction(); - this.compare_transaction(); - join_none - + this.enabled = 1; + + this.info($sformatf("Scoreboard enabled"), ADI_VERBOSITY_MEDIUM); endtask: run // stop scoreboard task stop(); this.enabled = 0; - ->>stop_scoreboard; this.clear_streams(); - #1step; + this.byte_streams_empty_sig = 1; endtask: stop // set sink type function void set_sink_type(input bit sink_type); - if (!this.enabled) begin this.sink_type = sink_type_t'(sink_type); end else begin this.error($sformatf("Can not configure sink_type while scoreboard is running.")); end - endfunction: set_sink_type - // clear source and sink byte streams - function void clear_streams(); - this.source_byte_stream.delete(); - this.sink_byte_stream.delete(); - - this.source_byte_stream_size = 0; - this.sink_byte_stream_size = 0; - endfunction: clear_streams - // get sink type function bit get_sink_type(); return this.sink_type; - endfunction + endfunction: get_sink_type + + // clear source and sink byte streams + protected function void clear_streams(); + this.subscriber_source.clear_stream(); + this.subscriber_source.clear_stream(); + endfunction: clear_streams // wait until source and sink byte streams are empty, full check task wait_until_complete(); if (this.byte_streams_empty_sig) return; - @byte_streams_empty; - endtask - - // get transaction data from source monitor - task get_source_transaction(); - - logic [7:0] source_byte; - - forever begin - fork begin - fork - this.source_monitor.wait_for_transaction_event(); - @stop_scoreboard; - join_any - disable fork; - end join - if (this.enabled == 0) - break; - - this.source_monitor.get_key(); - for (int i=0; i>source_transaction_event; - this.source_monitor.put_key(); - end - - endtask: get_source_transaction - - // get transaction data from sink monitor - task get_sink_transaction(); - - logic [7:0] sink_byte; - - forever begin - fork begin - fork - this.sink_monitor.wait_for_transaction_event(); - @stop_scoreboard; - join_any - disable fork; - end join - - if (this.enabled == 0) - break; - - this.sink_monitor.get_key(); - for (int i=0; i>sink_transaction_event; - this.sink_monitor.put_key(); - end - - endtask: get_sink_transaction + @this.byte_streams_empty; + endtask: wait_until_complete // compare the collected data - virtual task compare_transaction(); - + virtual function void compare_transaction(); logic [7:0] source_byte; logic [7:0] sink_byte; - this.info($sformatf("Started"), ADI_VERBOSITY_MEDIUM); - - forever begin : tx_path - if (this.enabled == 0) - break; - if ((this.source_byte_stream_size > 0) && - (this.sink_byte_stream_size > 0)) begin - byte_streams_empty_sig = 0; - source_byte = this.source_byte_stream.pop_back(); - if (this.sink_type == CYCLIC) - this.source_byte_stream.push_front(source_byte); - else - this.source_byte_stream_size--; - sink_byte = this.sink_byte_stream.pop_back(); - this.sink_byte_stream_size--; - this.info($sformatf("Source-sink data: exp %h - rcv %h", source_byte, sink_byte), ADI_VERBOSITY_MEDIUM); - if (source_byte != sink_byte) begin - this.error($sformatf("Failed at: exp %h - rcv %h", source_byte, sink_byte)); - end - end else begin - if ((this.source_byte_stream_size == 0) && - (this.sink_byte_stream_size == 0)) begin - byte_streams_empty_sig = 1; - ->>byte_streams_empty; - end - fork begin - fork - @source_transaction_event; - @sink_transaction_event; - @stop_scoreboard; - join_any - byte_streams_empty_sig = 0; - disable fork; - end join + if (this.enabled == 0) + return; + + while ((this.subscriber_source.get_size() > 0) && + (this.subscriber_sink.get_size() > 0)) begin + byte_streams_empty_sig = 0; + source_byte = this.subscriber_source.get_data(); + if (this.sink_type == CYCLIC) + this.subscriber_source.put_data(source_byte); + sink_byte = this.subscriber_sink.get_data(); + this.info($sformatf("Source-sink data: exp %h - rcv %h", source_byte, sink_byte), ADI_VERBOSITY_MEDIUM); + if (source_byte != sink_byte) begin + this.error($sformatf("Failed at: exp %h - rcv %h", source_byte, sink_byte)); end end - endtask /* compare_transaction */ + if ((this.subscriber_source.get_size() == 0) && + (this.subscriber_sink.get_size() == 0)) begin + this.byte_streams_empty_sig = 1; + ->this.byte_streams_empty; + end + endfunction: compare_transaction endclass diff --git a/library/drivers/common/watchdog.sv b/library/drivers/common/watchdog.sv index 917f3a32..ed09fda6 100644 --- a/library/drivers/common/watchdog.sv +++ b/library/drivers/common/watchdog.sv @@ -37,6 +37,7 @@ package watchdog_pkg; import logger_pkg::*; + import adi_common_pkg::*; class watchdog extends adi_component; diff --git a/library/drivers/common/x_monitor.sv b/library/drivers/common/x_monitor.sv index 2852b789..3eee77a0 100644 --- a/library/drivers/common/x_monitor.sv +++ b/library/drivers/common/x_monitor.sv @@ -6,202 +6,138 @@ package x_monitor_pkg; import axi4stream_vip_pkg::*; import axi_vip_pkg::*; import logger_pkg::*; - import mailbox_pkg::*; + import adi_common_pkg::*; + import pub_sub_pkg::*; - class x_monitor extends adi_component; - - mailbox_c #(logic [7:0]) mailbox; - protected semaphore semaphore_key; - protected event transaction_event; + class x_monitor extends adi_monitor; protected bit enabled; // constructor function new( input string name, - input adi_component parent = null); + input adi_agent parent = null); super.new(name, parent); - this.mailbox = new("Mailbox", 0, this); - this.semaphore_key = new(1); + this.enabled = 0; endfunction - // semaphore functions - task get_key(); - this.semaphore_key.get(); - endtask - - task put_key(); - this.semaphore_key.put(); - endtask - - // event functions - task transaction_captured(); - ->>this.transaction_event; - endtask - - task wait_for_transaction_event(); - @this.transaction_event; - endtask - - // run task task run(); + if (this.enabled) begin + this.error($sformatf("Monitor is already running!")); + return; + end fork - this.enabled = 1; - get_transaction(); + this.get_transaction(); join_none - endtask /* run */ + this.enabled = 1; + this.info($sformatf("Monitor enabled"), ADI_VERBOSITY_MEDIUM); + endtask: run // virtual functions - virtual function void set_sink_type(input bit sink_type); - endfunction - - virtual function bit get_sink_type(); - endfunction - virtual task get_transaction(); endtask endclass - typedef enum bit { - READ_OP = 1'b0, - WRITE_OP = 1'b1 - } operation_type_t; - class x_axi_monitor #( type T, operation_type_t operation_type ) extends x_monitor; - // operation type: 1 - write - // 0 - read + class x_axi_monitor #(int `AXI_VIP_PARAM_ORDER(axi)) extends x_monitor; // analysis port from the monitor + protected axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor; protected xil_analysis_port #(axi_monitor_transaction) axi_ap; - protected T agent; - - protected int axi_byte_stream_size; + adi_publisher #(logic [7:0]) publisher_tx; + adi_publisher #(logic [7:0]) publisher_rx; // constructor function new( input string name, - input T agent, - input adi_component parent = null); + input axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor, + input adi_agent parent = null); super.new(name, parent); - this.enabled = 0; - - this.agent = agent; - this.axi_ap = this.agent.monitor.item_collected_port; - - this.axi_byte_stream_size = 0; + this.monitor = monitor; + this.axi_ap = monitor.item_collected_port; - endfunction /* new */ + this.publisher_tx = new("Publisher TX", this); + this.publisher_rx = new("Publisher RX", this); + endfunction // collect data from the DDR interface, all WRITE transaction are coming // from the ADC and all READ transactions are going to the DAC virtual task get_transaction(); - axi_monitor_transaction transaction; xil_axi_data_beat data_beat; xil_axi_strb_beat strb_beat; int num_bytes; logic [7:0] axi_byte; + logic [7:0] data_queue [$]; forever begin - this.get_key(); this.axi_ap.get(transaction); - if (bit'(transaction.get_cmd_type()) == operation_type) begin - this.put_key(); - num_bytes = transaction.get_data_width()/8; - for (int i=0; i<(transaction.get_len()+1); i++) begin - data_beat = transaction.get_data_beat(i); - strb_beat = transaction.get_strb_beat(i); - for (int j=0; j +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +package adi_common_pkg; + + import logger_pkg::*; + + class adi_reporter; + string name; + adi_reporter parent; + + function new( + input string name, + input adi_reporter parent = null); + + this.name = name; + this.parent = parent; + endfunction + + function string get_path(); + if (this.parent == null) + return this.name; + else + return $sformatf("%s.%s", this.parent.get_path(), this.name); + endfunction: get_path + + function void info( + input string message, + input adi_verbosity_t verbosity); + + `INFO(("[%s] %s", this.get_path(), message), verbosity); + endfunction: info + + function void warning(input string message); + `WARNING(("[%s] %s", this.get_path(), message)); + endfunction: warning + + function void error(input string message); + `ERROR(("[%s] %s", this.get_path(), message)); + endfunction: error + + function void fatal(input string message); + `FATAL(("[%s] %s", this.get_path(), message)); + endfunction: fatal + endclass: adi_reporter + + + class adi_component extends adi_reporter; + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_component + + + class adi_environment extends adi_component; + function new( + input string name, + input adi_environment parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_environment + + + class adi_api extends adi_component; + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_api + + + class adi_regmap extends adi_component; + function new( + input string name, + input adi_api parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_regmap + + + class adi_agent extends adi_component; + function new( + input string name, + input adi_environment parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_agent + + + class adi_driver extends adi_component; + function new( + input string name, + input adi_agent parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_driver + + + class adi_sequencer extends adi_component; + function new( + input string name, + input adi_agent parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_sequencer + + + class adi_monitor extends adi_component; + function new( + input string name, + input adi_agent parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_monitor + +endpackage diff --git a/library/utilities/logger_pkg.sv b/library/utilities/logger_pkg.sv index 0b2b64d2..6db5d3cb 100644 --- a/library/utilities/logger_pkg.sv +++ b/library/utilities/logger_pkg.sv @@ -71,54 +71,4 @@ package logger_pkg; verbosity = value; endfunction: setLoggerVerbosity - - class adi_reporter; - string name; - adi_reporter parent; - - function new( - input string name, - input adi_reporter parent = null); - - this.name = name; - this.parent = parent; - endfunction - - function string get_path(); - if (this.parent == null) - return this.name; - else - return $sformatf("%s.%s", this.parent.get_path(), this.name); - endfunction: get_path - - function void info( - input string message, - input adi_verbosity_t verbosity); - - PrintInfo($sformatf("[%s] %s", this.get_path(), message), verbosity); - endfunction: info - - function void warning(input string message); - PrintWarning($sformatf("[%s] %s", this.get_path(), message)); - endfunction: warning - - function void error(input string message); - PrintError($sformatf("[%s] %s", this.get_path(), message)); - endfunction: error - - function void fatal(input string message); - PrintFatal($sformatf("[%s] %s", this.get_path(), message)); - endfunction: fatal - endclass: adi_reporter - - - class adi_component extends adi_reporter; - function new( - input string name, - input adi_component parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_component - endpackage diff --git a/library/utilities/test_harness_env.sv b/library/utilities/test_harness_env.sv index 2850c1b0..042070ea 100644 --- a/library/utilities/test_harness_env.sv +++ b/library/utilities/test_harness_env.sv @@ -38,25 +38,18 @@ package test_harness_env_pkg; import logger_pkg::*; + import adi_common_pkg::*; import axi_vip_pkg::*; - import axi4stream_vip_pkg::*; import m_axi_sequencer_pkg::*; import s_axi_sequencer_pkg::*; - import `PKGIFY(test_harness, mng_axi_vip)::*; - import `PKGIFY(test_harness, ddr_axi_vip)::*; + import adi_axi_agent_pkg::*; - class test_harness_env extends adi_component; - // Agents - `AGENT(test_harness, mng_axi_vip, mst_t) mng_agent; - `AGENT(test_harness, ddr_axi_vip, slv_mem_t) ddr_axi_agent; - - // Sequencers - m_axi_sequencer #(`AGENT(test_harness, mng_axi_vip, mst_t)) mng; - s_axi_sequencer #(`AGENT(test_harness, ddr_axi_vip, slv_mem_t)) ddr_axi_seq; + class test_harness_env #(int `AXI_VIP_PARAM_ORDER(mng), int `AXI_VIP_PARAM_ORDER(ddr)) extends adi_environment; - // Register accessors - bit done = 0; + // Agents + adi_axi_master_agent #(`AXI_VIP_PARAM_ORDER(mng)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAM_ORDER(ddr)) ddr; virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if; virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if; @@ -76,9 +69,8 @@ package test_harness_env_pkg; virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if - ); + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(mng)) mng_vip_if, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(ddr)) ddr_vip_if); super.new(name); @@ -88,13 +80,8 @@ package test_harness_env_pkg; this.sys_rst_vip_if = sys_rst_vip_if; // Creating the agents - mng_agent = new("AXI Manager agent", mng_vip_if); - ddr_axi_agent = new("AXI DDR stub agent", ddr_vip_if); - - // Creating the sequencers - mng = new("AXI Manager sequencer", mng_agent, this); - ddr_axi_seq = new("AXI DDR stub sequencer", ddr_axi_agent, this); - + this.mng = new("AXI Manager agent", mng_vip_if, this); + this.ddr = new("AXI DDR stub agent", ddr_vip_if, this); endfunction //============================================================================ @@ -103,76 +90,34 @@ package test_harness_env_pkg; // - Start the agents //============================================================================ task start(); - mng_agent.start_master(); - ddr_axi_agent.start_slave(); - - sys_clk_vip_if.start_clock; - dma_clk_vip_if.start_clock; - ddr_clk_vip_if.start_clock; - endtask - - //============================================================================ - // Start the test - // - start the scoreboard - // - start the sequencers - //============================================================================ - task test(); - fork - - join_none - endtask - - //============================================================================ - // Post test subroutine - //============================================================================ - task post_test(); - // wait until done - wait_done(); - endtask + this.mng.agent.start_master(); + this.ddr.agent.start_slave(); - //============================================================================ - // Run subroutine - //============================================================================ - task run; - test(); - post_test(); + this.sys_clk_vip_if.start_clock; + this.dma_clk_vip_if.start_clock; + this.ddr_clk_vip_if.start_clock; endtask //============================================================================ // Stop subroutine //============================================================================ - task stop; - mng_agent.stop_master(); - ddr_axi_agent.stop_slave(); - - sys_clk_vip_if.stop_clock; - dma_clk_vip_if.stop_clock; - ddr_clk_vip_if.stop_clock; - endtask + task stop(); + this.mng.agent.stop_master(); + this.ddr.agent.stop_slave(); - //============================================================================ - // Wait until all component are done - //============================================================================ - task wait_done; - wait (done == 1); - //`INFO(("Shutting down")); - endtask - - //============================================================================ - // Test controller routine - //============================================================================ - task test_c_run(); - done = 1; + this.sys_clk_vip_if.stop_clock; + this.dma_clk_vip_if.stop_clock; + this.ddr_clk_vip_if.stop_clock; endtask //============================================================================ // System reset routine //============================================================================ - task sys_reset; + task sys_reset(); //asserts all the resets for 100 ns - sys_rst_vip_if.assert_reset; + this.sys_rst_vip_if.assert_reset; #200; - sys_rst_vip_if.deassert_reset; + this.sys_rst_vip_if.deassert_reset; #800; endtask diff --git a/library/utilities/utils.svh b/library/utilities/utils.svh index a14e3493..d021994c 100644 --- a/library/utilities/utils.svh +++ b/library/utilities/utils.svh @@ -48,126 +48,103 @@ // Help build VIP parameter name e.g. test_harness_dst_axis_vip_0_VIP_DATA_WIDTH `define GETPARAM(th,vip,param) th``_``vip``_0_``param -`define DMAC_PARAMS(th,vip) th``_``vip``_0_ID, \ - th``_``vip``_0_DMA_DATA_WIDTH_SRC, \ - th``_``vip``_0_DMA_DATA_WIDTH_DEST, \ - th``_``vip``_0_DMA_LENGTH_WIDTH, \ - th``_``vip``_0_DMA_2D_TRANSFER, \ - th``_``vip``_0_DMA_2D_TLAST_MODE, \ - th``_``vip``_0_ASYNC_CLK_REQ_SRC, \ - th``_``vip``_0_ASYNC_CLK_SRC_DEST, \ - th``_``vip``_0_ASYNC_CLK_DEST_REQ, \ - th``_``vip``_0_AXI_SLICE_DEST, \ - th``_``vip``_0_AXI_SLICE_SRC, \ - th``_``vip``_0_SYNC_TRANSFER_START, \ - th``_``vip``_0_CYCLIC, \ - th``_``vip``_0_DMA_AXI_PROTOCOL_DEST, \ - th``_``vip``_0_DMA_AXI_PROTOCOL_SRC, \ - th``_``vip``_0_DMA_TYPE_DEST, \ - th``_``vip``_0_DMA_TYPE_SRC, \ - th``_``vip``_0_DMA_AXI_ADDR_WIDTH, \ - th``_``vip``_0_MAX_BYTES_PER_BURST, \ - th``_``vip``_0_FIFO_SIZE, \ - th``_``vip``_0_AXI_ID_WIDTH_SRC, \ - th``_``vip``_0_AXI_ID_WIDTH_DEST, \ - th``_``vip``_0_DISABLE_DEBUG_REGISTERS, \ - th``_``vip``_0_ENABLE_DIAGNOSTICS_IF, \ - th``_``vip``_0_ENABLE_FRAME_LOCK, \ - th``_``vip``_0_MAX_NUM_FRAMES_WIDTH, \ - th``_``vip``_0_USE_EXT_SYNC, \ - th``_``vip``_0_HAS_AUTORUN - // Help build VIP Interface parameters name -`define AXI_VIP_IF_PARAMS(th,vip) th``_``vip``_0_VIP_PROTOCOL,\ - th``_``vip``_0_VIP_ADDR_WIDTH,\ - th``_``vip``_0_VIP_DATA_WIDTH,\ - th``_``vip``_0_VIP_DATA_WIDTH,\ - th``_``vip``_0_VIP_ID_WIDTH,\ - th``_``vip``_0_VIP_ID_WIDTH,\ - th``_``vip``_0_VIP_AWUSER_WIDTH,\ - th``_``vip``_0_VIP_WUSER_WIDTH,\ - th``_``vip``_0_VIP_BUSER_WIDTH,\ - th``_``vip``_0_VIP_ARUSER_WIDTH,\ - th``_``vip``_0_VIP_RUSER_WIDTH,\ - th``_``vip``_0_VIP_SUPPORTS_NARROW,\ - th``_``vip``_0_VIP_HAS_BURST,\ - th``_``vip``_0_VIP_HAS_LOCK,\ - th``_``vip``_0_VIP_HAS_CACHE,\ - th``_``vip``_0_VIP_HAS_REGION,\ - th``_``vip``_0_VIP_HAS_PROT,\ - th``_``vip``_0_VIP_HAS_QOS,\ - th``_``vip``_0_VIP_HAS_WSTRB,\ - th``_``vip``_0_VIP_HAS_BRESP,\ - th``_``vip``_0_VIP_HAS_RRESP,\ - th``_``vip``_0_VIP_HAS_ARESETN - -`define AXIS_VIP_IF_PARAMS(th,vip) th``_``vip``_0_VIP_SIGNAL_SET,\ - th``_``vip``_0_VIP_DEST_WIDTH,\ - th``_``vip``_0_VIP_DATA_WIDTH,\ - th``_``vip``_0_VIP_ID_WIDTH,\ - th``_``vip``_0_VIP_USER_WIDTH,\ - th``_``vip``_0_VIP_USER_BITS_PER_BYTE,\ - th``_``vip``_0_VIP_HAS_ARESETN - -`define AXI_VIP_PARAM_DECL int AXI_VIP_PROTOCOL=0,\ - AXI_VIP_ADDR_WIDTH=32,\ - AXI_VIP_WDATA_WIDTH=32,\ - AXI_VIP_RDATA_WIDTH=32,\ - AXI_VIP_WID_WIDTH = 0,\ - AXI_VIP_RID_WIDTH = 0,\ - AXI_VIP_AWUSER_WIDTH=0,\ - AXI_VIP_WUSER_WIDTH=0,\ - AXI_VIP_BUSER_WIDTH=0,\ - AXI_VIP_ARUSER_WIDTH=0,\ - AXI_VIP_RUSER_WIDTH=0,\ - AXI_VIP_SUPPORTS_NARROW = 1,\ - AXI_VIP_HAS_BURST = 1,\ - AXI_VIP_HAS_LOCK = 1,\ - AXI_VIP_HAS_CACHE= 1,\ - AXI_VIP_HAS_REGION = 1,\ - AXI_VIP_HAS_PROT= 1,\ - AXI_VIP_HAS_QOS= 1,\ - AXI_VIP_HAS_WSTRB= 1,\ - AXI_VIP_HAS_BRESP= 1,\ - AXI_VIP_HAS_RRESP= 1,\ - AXI_VIP_HAS_ARESETN = 1 - -`define AXI_VIP_PARAM_ORDER AXI_VIP_PROTOCOL,\ - AXI_VIP_ADDR_WIDTH,\ - AXI_VIP_WDATA_WIDTH,\ - AXI_VIP_RDATA_WIDTH,\ - AXI_VIP_WID_WIDTH,\ - AXI_VIP_RID_WIDTH,\ - AXI_VIP_AWUSER_WIDTH,\ - AXI_VIP_WUSER_WIDTH,\ - AXI_VIP_BUSER_WIDTH,\ - AXI_VIP_ARUSER_WIDTH,\ - AXI_VIP_RUSER_WIDTH,\ - AXI_VIP_SUPPORTS_NARROW,\ - AXI_VIP_HAS_BURST,\ - AXI_VIP_HAS_LOCK,\ - AXI_VIP_HAS_CACHE,\ - AXI_VIP_HAS_REGION,\ - AXI_VIP_HAS_PROT,\ - AXI_VIP_HAS_QOS,\ - AXI_VIP_HAS_WSTRB,\ - AXI_VIP_HAS_BRESP,\ - AXI_VIP_HAS_RRESP,\ - AXI_VIP_HAS_ARESETN - -`define AXIS_VIP_PARAM_DECL int AXIS_VIP_INTERFACE_MODE = 2,\ - AXIS_VIP_SIGNAL_SET = 8'b00000011,\ - AXIS_VIP_DATA_WIDTH = 8,\ - AXIS_VIP_ID_WIDTH = 0,\ - AXIS_VIP_DEST_WIDTH = 0,\ - AXIS_VIP_USER_WIDTH = 0,\ - AXIS_VIP_USER_BITS_PER_BYTE = 0,\ - AXIS_VIP_HAS_TREADY = 1,\ - AXIS_VIP_HAS_TSTRB = 0,\ - AXIS_VIP_HAS_TKEEP = 0,\ - AXIS_VIP_HAS_TLAST = 0,\ - AXIS_VIP_HAS_ACLKEN = 0,\ - AXIS_VIP_HAS_ARESETN = 1 +`define AXI_VIP_IF_PARAMS(n) n``_VIP_PROTOCOL,\ + n``_VIP_ADDR_WIDTH,\ + n``_VIP_WDATA_WIDTH,\ + n``_VIP_RDATA_WIDTH,\ + n``_VIP_WID_WIDTH,\ + n``_VIP_RID_WIDTH,\ + n``_VIP_AWUSER_WIDTH,\ + n``_VIP_WUSER_WIDTH,\ + n``_VIP_BUSER_WIDTH,\ + n``_VIP_ARUSER_WIDTH,\ + n``_VIP_RUSER_WIDTH,\ + n``_VIP_SUPPORTS_NARROW,\ + n``_VIP_HAS_BURST,\ + n``_VIP_HAS_LOCK,\ + n``_VIP_HAS_CACHE,\ + n``_VIP_HAS_REGION,\ + n``_VIP_HAS_PROT,\ + n``_VIP_HAS_QOS,\ + n``_VIP_HAS_WSTRB,\ + n``_VIP_HAS_BRESP,\ + n``_VIP_HAS_RRESP,\ + n``_VIP_HAS_ARESETN + +`define AXI_VIP_PARAM_ORDER(n) n``_VIP_PROTOCOL,\ + n``_VIP_ADDR_WIDTH,\ + n``_VIP_WDATA_WIDTH,\ + n``_VIP_RDATA_WIDTH,\ + n``_VIP_WID_WIDTH,\ + n``_VIP_RID_WIDTH,\ + n``_VIP_AWUSER_WIDTH,\ + n``_VIP_WUSER_WIDTH,\ + n``_VIP_BUSER_WIDTH,\ + n``_VIP_ARUSER_WIDTH,\ + n``_VIP_RUSER_WIDTH,\ + n``_VIP_SUPPORTS_NARROW,\ + n``_VIP_HAS_BURST,\ + n``_VIP_HAS_LOCK,\ + n``_VIP_HAS_CACHE,\ + n``_VIP_HAS_REGION,\ + n``_VIP_HAS_PROT,\ + n``_VIP_HAS_QOS,\ + n``_VIP_HAS_WSTRB,\ + n``_VIP_HAS_BRESP,\ + n``_VIP_HAS_RRESP,\ + n``_VIP_HAS_ARESETN + +`define AXI_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_PROTOCOL,\ + th``_``vip``_0_VIP_ADDR_WIDTH,\ + th``_``vip``_0_VIP_DATA_WIDTH,\ + th``_``vip``_0_VIP_DATA_WIDTH,\ + th``_``vip``_0_VIP_ID_WIDTH,\ + th``_``vip``_0_VIP_ID_WIDTH,\ + th``_``vip``_0_VIP_AWUSER_WIDTH,\ + th``_``vip``_0_VIP_WUSER_WIDTH,\ + th``_``vip``_0_VIP_BUSER_WIDTH,\ + th``_``vip``_0_VIP_ARUSER_WIDTH,\ + th``_``vip``_0_VIP_RUSER_WIDTH,\ + th``_``vip``_0_VIP_SUPPORTS_NARROW,\ + th``_``vip``_0_VIP_HAS_BURST,\ + th``_``vip``_0_VIP_HAS_LOCK,\ + th``_``vip``_0_VIP_HAS_CACHE,\ + th``_``vip``_0_VIP_HAS_REGION,\ + th``_``vip``_0_VIP_HAS_PROT,\ + th``_``vip``_0_VIP_HAS_QOS,\ + th``_``vip``_0_VIP_HAS_WSTRB,\ + th``_``vip``_0_VIP_HAS_BRESP,\ + th``_``vip``_0_VIP_HAS_RRESP,\ + th``_``vip``_0_VIP_HAS_ARESETN + +`define AXIS_VIP_PARAM_DECL AXIS_VIP_INTERFACE_MODE = 2,\ + AXIS_VIP_SIGNAL_SET = 8'b00000011,\ + AXIS_VIP_DATA_WIDTH = 8,\ + AXIS_VIP_ID_WIDTH = 0,\ + AXIS_VIP_DEST_WIDTH = 0,\ + AXIS_VIP_USER_WIDTH = 0,\ + AXIS_VIP_USER_BITS_PER_BYTE = 0,\ + AXIS_VIP_HAS_TREADY = 1,\ + AXIS_VIP_HAS_TSTRB = 0,\ + AXIS_VIP_HAS_TKEEP = 0,\ + AXIS_VIP_HAS_TLAST = 0,\ + AXIS_VIP_HAS_ACLKEN = 0,\ + AXIS_VIP_HAS_ARESETN = 1 + +`define AXIS_VIP_PARAM_ORDER(n) n``_VIP_INTERFACE_MODE,\ + n``_VIP_SIGNAL_SET,\ + n``_VIP_DATA_WIDTH,\ + n``_VIP_ID_WIDTH,\ + n``_VIP_DEST_WIDTH,\ + n``_VIP_USER_WIDTH,\ + n``_VIP_USER_BITS_PER_BYTE,\ + n``_VIP_HAS_TREADY,\ + n``_VIP_HAS_TSTRB,\ + n``_VIP_HAS_TKEEP,\ + n``_VIP_HAS_TLAST,\ + n``_VIP_HAS_ACLKEN,\ + n``_VIP_HAS_ARESETN `define AXIS_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_INTERFACE_MODE,\ th``_``vip``_0_VIP_SIGNAL_SET,\ @@ -183,6 +160,14 @@ th``_``vip``_0_VIP_HAS_ACLKEN,\ th``_``vip``_0_VIP_HAS_ARESETN +`define AXIS_VIP_IF_PARAMS(n) n``_VIP_SIGNAL_SET,\ + n``_VIP_DEST_WIDTH,\ + n``_VIP_DATA_WIDTH,\ + n``_VIP_ID_WIDTH,\ + n``_VIP_USER_WIDTH,\ + n``_VIP_USER_BITS_PER_BYTE,\ + n``_VIP_HAS_ARESETN + `define AXI 0 `define AXIS 1 `define FIFO 2 diff --git a/library/vip/adi/base/pub_sub_pkg.sv b/library/vip/adi/base/pub_sub_pkg.sv new file mode 100644 index 00000000..570395a6 --- /dev/null +++ b/library/vip/adi/base/pub_sub_pkg.sv @@ -0,0 +1,97 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +package pub_sub_pkg; + + import logger_pkg::*; + import adi_common_pkg::*; + + class adi_subscriber #(type data_type = int) extends adi_component; + + protected static bit [15:0] last_id = 'd0; + bit [15:0] id; + + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + + this.last_id++; + this.id = this.last_id; + endfunction: new + + virtual function void update(input data_type data [$]); + this.fatal($sformatf("This function is not implemented!")); + endfunction: update + + endclass: adi_subscriber + + + class adi_publisher #(type data_type = int) extends adi_component; + + protected adi_subscriber #(data_type) subscriber_list[bit[15:0]]; + + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + endfunction: new + + function void subscribe(input adi_subscriber #(data_type) subscriber); + if (this.subscriber_list.exists(subscriber.id)) + this.error($sformatf("Subscriber already on the list!")); + else + this.subscriber_list[subscriber.id] = subscriber; + endfunction: subscribe + + function void unsubscribe(input adi_subscriber #(data_type) subscriber); + if (!this.subscriber_list.exists(subscriber.id)) + this.error($sformatf("Subscriber does not exist on list!")); + else + this.subscriber_list.delete(subscriber.id); + endfunction: unsubscribe + + function void notify(input data_type data [$]); + foreach (this.subscriber_list[i]) + this.subscriber_list[i].update(data); + endfunction: notify + + endclass: adi_publisher + +endpackage diff --git a/library/vip/amd/adi_axi_agent.sv b/library/vip/amd/adi_axi_agent.sv new file mode 100644 index 00000000..db83d451 --- /dev/null +++ b/library/vip/amd/adi_axi_agent.sv @@ -0,0 +1,108 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +package adi_axi_agent_pkg; + + import logger_pkg::*; + import adi_common_pkg::*; + import axi_vip_pkg::*; + import m_axi_sequencer_pkg::*; + import s_axi_sequencer_pkg::*; + import x_monitor_pkg::*; + + + class adi_axi_master_agent #(int `AXI_VIP_PARAM_ORDER(master)) extends adi_agent; + + axi_mst_agent #(`AXI_VIP_PARAM_ORDER(master)) agent; + m_axi_sequencer #(`AXI_VIP_PARAM_ORDER(master)) sequencer; + x_axi_monitor #(`AXI_VIP_PARAM_ORDER(master)) monitor; + + function new( + input string name, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(master)) master_vip_if, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent = new("Agent", master_vip_if); + this.sequencer = new("Sequencer", this.agent, this); + this.monitor = new("Monitor TX", this.agent.monitor, this); + endfunction: new + + endclass: adi_axi_master_agent + + + class adi_axi_slave_mem_agent #(int `AXI_VIP_PARAM_ORDER(slave)) extends adi_agent; + + axi_slv_mem_agent #(`AXI_VIP_PARAM_ORDER(slave)) agent; + s_axi_sequencer #(`AXI_VIP_PARAM_ORDER(slave)) sequencer; + x_axi_monitor #(`AXI_VIP_PARAM_ORDER(slave)) monitor; + + function new( + input string name, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(slave)) slave_vip_if, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent = new("Agent", slave_vip_if); + this.sequencer = new("Sequencer", this.agent.mem_model, this); + this.monitor = new("Monitor TX", this.agent.monitor, this); + endfunction: new + + endclass: adi_axi_slave_mem_agent + + + class adi_axi_passthrough_mem_agent #(int `AXI_VIP_PARAM_ORDER(passthrough)) extends adi_agent; + + axi_passthrough_mem_agent #(`AXI_VIP_PARAM_ORDER(passthrough)) agent; + x_axi_monitor #(`AXI_VIP_PARAM_ORDER(passthrough)) monitor; + + function new( + input string name, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(passthrough)) passthrough_vip_if, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent = new("Agent", passthrough_vip_if); + this.monitor = new("Monitor TX", this.agent.monitor, this); + endfunction: new + + endclass: adi_axi_passthrough_mem_agent + +endpackage diff --git a/library/vip/amd/adi_axis_agent.sv b/library/vip/amd/adi_axis_agent.sv new file mode 100644 index 00000000..65801c1a --- /dev/null +++ b/library/vip/amd/adi_axis_agent.sv @@ -0,0 +1,108 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +package adi_axis_agent_pkg; + + import logger_pkg::*; + import adi_common_pkg::*; + import axi4stream_vip_pkg::*; + import m_axis_sequencer_pkg::*; + import s_axis_sequencer_pkg::*; + import x_monitor_pkg::*; + + + class adi_axis_master_agent #(int `AXIS_VIP_PARAM_ORDER(master)) extends adi_agent; + + axi4stream_mst_agent #(`AXIS_VIP_IF_PARAMS(master)) agent; + m_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(master)) sequencer; + x_axis_monitor #(`AXIS_VIP_PARAM_ORDER(master)) monitor; + + function new( + input string name, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(master)) master_vip_if, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent = new("Agent", master_vip_if); + this.sequencer = new("Sequencer", this.agent.driver, this); + this.monitor = new("Monitor", this.agent.monitor, this); + endfunction: new + + endclass: adi_axis_master_agent + + + class adi_axis_slave_agent #(int `AXIS_VIP_PARAM_ORDER(slave)) extends adi_agent; + + axi4stream_slv_agent #(`AXIS_VIP_IF_PARAMS(slave)) agent; + s_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(slave)) sequencer; + x_axis_monitor #(`AXIS_VIP_PARAM_ORDER(slave)) monitor; + + function new( + input string name, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(slave)) slave_vip_if, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent = new("Agent", slave_vip_if); + this.sequencer = new("Sequencer", this.agent.driver, this); + this.monitor = new("Monitor", this.agent.monitor, this); + endfunction: new + + endclass: adi_axis_slave_agent + + + class adi_axis_passthrough_mem_agent #(int `AXIS_VIP_PARAM_ORDER(passthrough)) extends adi_agent; + + axi4stream_passthrough_agent #(`AXIS_VIP_IF_PARAMS(passthrough)) agent; + x_axis_monitor #(`AXIS_VIP_PARAM_ORDER(passthrough)) monitor; + + function new( + input string name, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(passthrough)) passthrough_vip_if, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent = new("Agent", passthrough_vip_if); + this.monitor = new("Monitor", this.agent.monitor, this); + endfunction: new + + endclass: adi_axis_passthrough_mem_agent + +endpackage diff --git a/library/vip/amd/m_axi_sequencer.sv b/library/vip/amd/m_axi_sequencer.sv index eb25855d..7e917b0a 100644 --- a/library/vip/amd/m_axi_sequencer.sv +++ b/library/vip/amd/m_axi_sequencer.sv @@ -39,19 +39,20 @@ package m_axi_sequencer_pkg; import axi_vip_pkg::*; import logger_pkg::*; + import adi_common_pkg::*; import reg_accessor_pkg::*; - class m_axi_sequencer #( type T ) extends reg_accessor; + class m_axi_sequencer #(int `AXI_VIP_PARAM_ORDER(m)) extends reg_accessor; - T agent; + axi_mst_agent #(`AXI_VIP_PARAM_ORDER(m)) agent; semaphore reader_s; semaphore writer_s; function new( input string name, - input T agent, - input adi_component parent = null); + input axi_mst_agent #(`AXI_VIP_PARAM_ORDER(m)) agent, + input adi_agent parent = null); super.new(name, parent); diff --git a/library/vip/amd/m_axis_sequencer.sv b/library/vip/amd/m_axis_sequencer.sv index 91fc876e..6a319870 100644 --- a/library/vip/amd/m_axis_sequencer.sv +++ b/library/vip/amd/m_axis_sequencer.sv @@ -38,6 +38,7 @@ package m_axis_sequencer_pkg; import axi4stream_vip_pkg::*; + import adi_common_pkg::*; import logger_pkg::*; typedef enum { @@ -97,7 +98,7 @@ package m_axis_sequencer_pkg; // new function new( input string name, - input adi_component parent = null); + input adi_agent parent = null); super.new(name, parent); @@ -310,20 +311,21 @@ package m_axis_sequencer_pkg; endclass: m_axis_sequencer_base - class m_axis_sequencer #( type T, `AXIS_VIP_PARAM_DECL) extends m_axis_sequencer_base; + class m_axis_sequencer #(int `AXIS_VIP_PARAM_ORDER(AXIS)) extends m_axis_sequencer_base; - protected T agent; + protected axi4stream_mst_driver #(`AXIS_VIP_IF_PARAMS(AXIS)) driver; function new( input string name, - input T agent, - input adi_component parent = null); + input axi4stream_mst_driver #(`AXIS_VIP_IF_PARAMS(AXIS)) driver, + input adi_agent parent = null); super.new(name, parent); - this.agent = agent; - this.agent.vif_proxy.set_no_insert_x_when_keep_low(1); + this.driver = driver; + + this.driver.vif_proxy.set_no_insert_x_when_keep_low(1); endfunction: new @@ -338,19 +340,19 @@ package m_axis_sequencer_pkg; // set vif proxy to drive outputs with 0 when inactive virtual task set_inactive_drive_output_0(); - agent.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); + this.driver.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); this.wait_clk_count(2); endtask: set_inactive_drive_output_0 // check if ready is asserted virtual function bit check_ready_asserted(); - return agent.vif_proxy.is_ready_asserted(); + return this.driver.vif_proxy.is_ready_asserted(); endfunction: check_ready_asserted // wait for set amount of clock cycles virtual task wait_clk_count(input int wait_clocks); - agent.vif_proxy.wait_aclks(wait_clocks); + this.driver.vif_proxy.wait_aclks(wait_clocks); endtask: wait_clk_count // pack the byte stream into transfers(beats) then in packets by setting the tlast @@ -421,7 +423,7 @@ package m_axis_sequencer_pkg; end this.info($sformatf("generating axis transaction"), ADI_VERBOSITY_HIGH); - trans = agent.driver.create_transaction(); + trans = this.driver.create_transaction(); trans.set_data(data); trans.set_id('h0); trans.set_dest('h0); @@ -465,7 +467,7 @@ package m_axis_sequencer_pkg; forever begin @data_av_ev; this.info($sformatf("sending axis transaction"), ADI_VERBOSITY_HIGH); - agent.driver.send(trans); + this.driver.send(trans); ->> beat_done; end join_any diff --git a/library/vip/amd/s_axi_sequencer.sv b/library/vip/amd/s_axi_sequencer.sv index a097ece3..b03b2f40 100644 --- a/library/vip/amd/s_axi_sequencer.sv +++ b/library/vip/amd/s_axi_sequencer.sv @@ -37,28 +37,28 @@ package s_axi_sequencer_pkg; - import xil_common_vip_pkg::*; import axi_vip_pkg::*; + import adi_common_pkg::*; import logger_pkg::*; - class s_axi_sequencer #( type T ) extends adi_component; + class s_axi_sequencer #(int `AXI_VIP_PARAM_ORDER(s)) extends adi_component; - T agent; + xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(s)) mem_model; function new( input string name, - input T agent, - input adi_component parent = null); + input xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(s)) mem_model, + input adi_agent parent = null); super.new(name, parent); - this.agent = agent; + this.mem_model = mem_model; endfunction task get_byte_from_mem(input xil_axi_ulong addr, output bit [7:0] data); bit [31:0] four_bytes; - four_bytes = agent.mem_model.backdoor_memory_read_4byte(addr); + four_bytes = this.mem_model.backdoor_memory_read_4byte(addr); case (addr[1:0]) 2'b00: data = four_bytes[0+:8]; 2'b01: data = four_bytes[8+:8]; @@ -76,7 +76,7 @@ package s_axi_sequencer_pkg; 2'b10: strb = 'b0100; 2'b11: strb = 'b1000; endcase - agent.mem_model.backdoor_memory_write_4byte(.addr(addr), + this.mem_model.backdoor_memory_write_4byte(.addr(addr), .payload({4{data}}), .strb(strb)); endtask diff --git a/library/vip/amd/s_axis_sequencer.sv b/library/vip/amd/s_axis_sequencer.sv index 35418e6c..dc09e5ba 100644 --- a/library/vip/amd/s_axis_sequencer.sv +++ b/library/vip/amd/s_axis_sequencer.sv @@ -38,6 +38,7 @@ package s_axis_sequencer_pkg; import axi4stream_vip_pkg::*; + import adi_common_pkg::*; import logger_pkg::*; class s_axis_sequencer_base extends adi_component; @@ -60,7 +61,7 @@ package s_axis_sequencer_pkg; // new function new( input string name, - input adi_component parent = null); + input adi_agent parent = null); super.new(name, parent); @@ -156,26 +157,26 @@ package s_axis_sequencer_pkg; endclass: s_axis_sequencer_base - class s_axis_sequencer #( type T ) extends s_axis_sequencer_base; + class s_axis_sequencer #(int `AXIS_VIP_PARAM_ORDER(AXIS)) extends s_axis_sequencer_base; - protected T agent; + protected axi4stream_slv_driver #(`AXIS_VIP_IF_PARAMS(AXIS)) driver; function new( input string name, - input T agent, - input adi_component parent = null); + input axi4stream_slv_driver #(`AXIS_VIP_IF_PARAMS(AXIS)) driver, + input adi_agent parent = null); super.new(name, parent); - this.agent = agent; + this.driver = driver; endfunction virtual task user_gen_tready(); axi4stream_ready_gen tready_gen; - tready_gen = agent.driver.create_ready("TREADY"); + tready_gen = this.driver.create_ready("TREADY"); tready_gen.set_ready_policy(this.mode); @@ -191,27 +192,9 @@ package s_axis_sequencer_pkg; tready_gen.set_low_time_range(this.low_time_min, this.low_time_max); tready_gen.set_high_time_range(this.high_time_min, this.high_time_max); end - agent.driver.send_tready(tready_gen); + this.driver.send_tready(tready_gen); endtask - // Get transfer from the monitor and serialize data into a byte stream - // Assumption: all bytes from beat are valid (no position or null bytes) - virtual task get_transfer(); - - axi4stream_monitor_transaction mytrans; - xil_axi4stream_data_beat data_beat; - - agent.monitor.item_collected_port.get(mytrans); - - //$display(mytrans.convert2string); - - data_beat = mytrans.get_data_beat(); - - for (int i=0; i Date: Mon, 16 Dec 2024 11:19:54 +0200 Subject: [PATCH 02/37] infrastructure refactorization: Fixes Signed-off-by: Istvan-Zsolt Szekely --- library/vip/adi/io_vip/io_vip_ip.tcl | 2 +- library/vip/adi/spi_vip/adi_spi_vip_ip.tcl | 2 +- testbenches/ip/base/Makefile | 1 - testbenches/ip/base/system_project.tcl | 1 - 4 files changed, 2 insertions(+), 4 deletions(-) diff --git a/library/vip/adi/io_vip/io_vip_ip.tcl b/library/vip/adi/io_vip/io_vip_ip.tcl index 46f5fcad..a99e8474 100644 --- a/library/vip/adi/io_vip/io_vip_ip.tcl +++ b/library/vip/adi/io_vip/io_vip_ip.tcl @@ -3,7 +3,7 @@ ### SPDX short identifier: ADIBSD ############################################################################### -source ../../../../../scripts/adi_env.tcl +source ../../../../scripts/adi_tb_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl adi_ip_create io_vip diff --git a/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl b/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl index d6748352..1e745e88 100644 --- a/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl +++ b/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl @@ -3,7 +3,7 @@ ### SPDX short identifier: ADIBSD ############################################################################### -source ../../../../../scripts/adi_env.tcl +source ../../../../scripts/adi_tb_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl adi_ip_create adi_spi_vip diff --git a/testbenches/ip/base/Makefile b/testbenches/ip/base/Makefile index 6c2e0bea..845120e2 100644 --- a/testbenches/ip/base/Makefile +++ b/testbenches/ip/base/Makefile @@ -9,7 +9,6 @@ include ../../../scripts/make_tb_path.mk include $(TB_LIBRARY_PATH)/includes/Makeinclude_common.mk # Remaining test-bench dependencies except test programs -SV_DEPS += environment.sv # default test program TP := test_program diff --git a/testbenches/ip/base/system_project.tcl b/testbenches/ip/base/system_project.tcl index d86009f2..cc9ad709 100644 --- a/testbenches/ip/base/system_project.tcl +++ b/testbenches/ip/base/system_project.tcl @@ -18,7 +18,6 @@ adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" # Add test files to the project adi_sim_project_files [list \ - "environment.sv" \ "tests/test_program.sv" \ ] From 836fbe3d0bd8b48fcbbb9b27c491c805932f744d Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 16 Dec 2024 14:18:13 +0200 Subject: [PATCH 03/37] infrastructure refactorization: Refactoring Signed-off-by: Istvan-Zsolt Szekely --- library/includes/Makeinclude_axi.mk | 11 +- library/includes/Makeinclude_axis.mk | 11 +- library/includes/Makeinclude_scoreboard.mk | 2 +- library/includes/sp_include_axi.tcl | 11 +- library/includes/sp_include_axis.tcl | 11 +- library/includes/sp_include_scoreboard.tcl | 2 +- .../adi/base => utilities}/pub_sub_pkg.sv | 0 library/utilities/test_harness_env.sv | 4 +- library/utilities/utils.svh | 124 ------------------ library/vip/amd/{ => axi}/adi_axi_agent.sv | 9 +- .../amd/axi/adi_axi_monitor.sv} | 107 +++------------ library/vip/amd/axi/axi_definitions.svh | 112 ++++++++++++++++ library/vip/amd/{ => axi}/m_axi_sequencer.sv | 1 + library/vip/amd/{ => axi}/s_axi_sequencer.sv | 1 + library/vip/amd/{ => axis}/adi_axis_agent.sv | 9 +- library/vip/amd/axis/adi_axis_monitor.sv | 77 +++++++++++ library/vip/amd/axis/axis_definitions.svh | 93 +++++++++++++ .../vip/amd/{ => axis}/m_axis_sequencer.sv | 1 + .../vip/amd/{ => axis}/s_axis_sequencer.sv | 1 + testbenches/ip/base/tests/test_program.sv | 1 + testbenches/ip/scoreboard/environment.sv | 2 + .../ip/scoreboard/tests/test_program.sv | 4 +- 22 files changed, 345 insertions(+), 249 deletions(-) rename library/{vip/adi/base => utilities}/pub_sub_pkg.sv (100%) rename library/vip/amd/{ => axi}/adi_axi_agent.sv (93%) rename library/{drivers/common/x_monitor.sv => vip/amd/axi/adi_axi_monitor.sv} (50%) create mode 100644 library/vip/amd/axi/axi_definitions.svh rename library/vip/amd/{ => axi}/m_axi_sequencer.sv (99%) rename library/vip/amd/{ => axi}/s_axi_sequencer.sv (99%) rename library/vip/amd/{ => axis}/adi_axis_agent.sv (93%) create mode 100644 library/vip/amd/axis/adi_axis_monitor.sv create mode 100644 library/vip/amd/axis/axis_definitions.svh rename library/vip/amd/{ => axis}/m_axis_sequencer.sv (99%) rename library/vip/amd/{ => axis}/s_axis_sequencer.sv (99%) diff --git a/library/includes/Makeinclude_axi.mk b/library/includes/Makeinclude_axi.mk index 6df5de65..8a1b27c8 100644 --- a/library/includes/Makeinclude_axi.mk +++ b/library/includes/Makeinclude_axi.mk @@ -3,9 +3,10 @@ #################################################################################### # All test-bench dependencies except test programs -SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/adi_axi_agent.sv -SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/m_axi_sequencer.sv -SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/s_axi_sequencer.sv -SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/x_monitor.sv -SV_DEPS += $(TB_LIBRARY_PATH)/vip/adi/base/pub_sub_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/adi_axi_agent.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/m_axi_sequencer.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/s_axi_sequencer.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/adi_axi_monitor.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/axi_definitions.svh +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/reg_accessor.sv diff --git a/library/includes/Makeinclude_axis.mk b/library/includes/Makeinclude_axis.mk index d663d17c..5810ebd7 100644 --- a/library/includes/Makeinclude_axis.mk +++ b/library/includes/Makeinclude_axis.mk @@ -3,8 +3,9 @@ #################################################################################### # All test-bench dependencies except test programs -SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/adi_axis_agent.sv -SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/m_axis_sequencer.sv -SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/s_axis_sequencer.sv -SV_DEPS += $(TB_LIBRARY_PATH)/vip/adi/base/pub_sub_pkg.sv -SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/x_monitor.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/adi_axis_agent.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/m_axis_sequencer.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/s_axis_sequencer.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/adi_axis_monitor.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/axis_definitions.svh +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv diff --git a/library/includes/Makeinclude_scoreboard.mk b/library/includes/Makeinclude_scoreboard.mk index 46c408f1..3fd4e67a 100644 --- a/library/includes/Makeinclude_scoreboard.mk +++ b/library/includes/Makeinclude_scoreboard.mk @@ -3,6 +3,6 @@ #################################################################################### # All test-bench dependencies except test programs -SV_DEPS += $(TB_LIBRARY_PATH)/vip/adi/base/pub_sub_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/scoreboard.sv SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/scoreboard_pack.sv diff --git a/library/includes/sp_include_axi.tcl b/library/includes/sp_include_axi.tcl index 35a46f99..89aaa064 100644 --- a/library/includes/sp_include_axi.tcl +++ b/library/includes/sp_include_axi.tcl @@ -35,10 +35,11 @@ # Add test files to the project adi_sim_project_files [list \ - "$ad_tb_dir/library/vip/amd/adi_axi_agent.sv" \ - "$ad_tb_dir/library/vip/amd/m_axi_sequencer.sv" \ - "$ad_tb_dir/library/vip/amd/s_axi_sequencer.sv" \ - "$ad_tb_dir/library/drivers/common/x_monitor.sv" \ - "$ad_tb_dir/library/vip/adi/base/pub_sub_pkg.sv" \ + "$ad_tb_dir/library/vip/amd/axi/adi_axi_agent.sv" \ + "$ad_tb_dir/library/vip/amd/axi/m_axi_sequencer.sv" \ + "$ad_tb_dir/library/vip/amd/axi/s_axi_sequencer.sv" \ + "$ad_tb_dir/library/vip/amd/axi/adi_axi_monitor.sv" \ + "$ad_tb_dir/library/vip/amd/axi/axi_definitions.svh" \ + "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ "$ad_tb_dir/library/regmaps/reg_accessor.sv" \ ] diff --git a/library/includes/sp_include_axis.tcl b/library/includes/sp_include_axis.tcl index dc284e77..50532616 100644 --- a/library/includes/sp_include_axis.tcl +++ b/library/includes/sp_include_axis.tcl @@ -35,9 +35,10 @@ # Add test files to the project adi_sim_project_files [list \ - "$ad_tb_dir/library/vip/amd/adi_axis_agent.sv" \ - "$ad_tb_dir/library/vip/amd/m_axis_sequencer.sv" \ - "$ad_tb_dir/library/vip/amd/s_axis_sequencer.sv" \ - "$ad_tb_dir/library/drivers/common/x_monitor.sv" \ - "$ad_tb_dir/library/vip/adi/base/pub_sub_pkg.sv" \ + "$ad_tb_dir/library/vip/amd/axis/adi_axis_agent.sv" \ + "$ad_tb_dir/library/vip/amd/axis/m_axis_sequencer.sv" \ + "$ad_tb_dir/library/vip/amd/axis/s_axis_sequencer.sv" \ + "$ad_tb_dir/library/vip/amd/axis/adi_axis_monitor.sv" \ + "$ad_tb_dir/library/vip/amd/axis/axis_definitions.svh" \ + "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ ] diff --git a/library/includes/sp_include_scoreboard.tcl b/library/includes/sp_include_scoreboard.tcl index cd47bdd7..03ac1a8b 100644 --- a/library/includes/sp_include_scoreboard.tcl +++ b/library/includes/sp_include_scoreboard.tcl @@ -35,7 +35,7 @@ # Add test files to the project adi_sim_project_files [list \ - "$ad_tb_dir/library/vip/adi/base/pub_sub_pkg.sv" \ + "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ "$ad_tb_dir/library/drivers/common/scoreboard.sv" \ "$ad_tb_dir/library/drivers/common/scoreboard_pack.sv" \ ] diff --git a/library/vip/adi/base/pub_sub_pkg.sv b/library/utilities/pub_sub_pkg.sv similarity index 100% rename from library/vip/adi/base/pub_sub_pkg.sv rename to library/utilities/pub_sub_pkg.sv diff --git a/library/utilities/test_harness_env.sv b/library/utilities/test_harness_env.sv index 042070ea..3f05d8b2 100644 --- a/library/utilities/test_harness_env.sv +++ b/library/utilities/test_harness_env.sv @@ -34,14 +34,12 @@ // *************************************************************************** `include "utils.svh" +`include "axi_definitions.svh" package test_harness_env_pkg; import logger_pkg::*; import adi_common_pkg::*; - import axi_vip_pkg::*; - import m_axi_sequencer_pkg::*; - import s_axi_sequencer_pkg::*; import adi_axi_agent_pkg::*; diff --git a/library/utilities/utils.svh b/library/utilities/utils.svh index d021994c..03a240df 100644 --- a/library/utilities/utils.svh +++ b/library/utilities/utils.svh @@ -48,130 +48,6 @@ // Help build VIP parameter name e.g. test_harness_dst_axis_vip_0_VIP_DATA_WIDTH `define GETPARAM(th,vip,param) th``_``vip``_0_``param -// Help build VIP Interface parameters name -`define AXI_VIP_IF_PARAMS(n) n``_VIP_PROTOCOL,\ - n``_VIP_ADDR_WIDTH,\ - n``_VIP_WDATA_WIDTH,\ - n``_VIP_RDATA_WIDTH,\ - n``_VIP_WID_WIDTH,\ - n``_VIP_RID_WIDTH,\ - n``_VIP_AWUSER_WIDTH,\ - n``_VIP_WUSER_WIDTH,\ - n``_VIP_BUSER_WIDTH,\ - n``_VIP_ARUSER_WIDTH,\ - n``_VIP_RUSER_WIDTH,\ - n``_VIP_SUPPORTS_NARROW,\ - n``_VIP_HAS_BURST,\ - n``_VIP_HAS_LOCK,\ - n``_VIP_HAS_CACHE,\ - n``_VIP_HAS_REGION,\ - n``_VIP_HAS_PROT,\ - n``_VIP_HAS_QOS,\ - n``_VIP_HAS_WSTRB,\ - n``_VIP_HAS_BRESP,\ - n``_VIP_HAS_RRESP,\ - n``_VIP_HAS_ARESETN - -`define AXI_VIP_PARAM_ORDER(n) n``_VIP_PROTOCOL,\ - n``_VIP_ADDR_WIDTH,\ - n``_VIP_WDATA_WIDTH,\ - n``_VIP_RDATA_WIDTH,\ - n``_VIP_WID_WIDTH,\ - n``_VIP_RID_WIDTH,\ - n``_VIP_AWUSER_WIDTH,\ - n``_VIP_WUSER_WIDTH,\ - n``_VIP_BUSER_WIDTH,\ - n``_VIP_ARUSER_WIDTH,\ - n``_VIP_RUSER_WIDTH,\ - n``_VIP_SUPPORTS_NARROW,\ - n``_VIP_HAS_BURST,\ - n``_VIP_HAS_LOCK,\ - n``_VIP_HAS_CACHE,\ - n``_VIP_HAS_REGION,\ - n``_VIP_HAS_PROT,\ - n``_VIP_HAS_QOS,\ - n``_VIP_HAS_WSTRB,\ - n``_VIP_HAS_BRESP,\ - n``_VIP_HAS_RRESP,\ - n``_VIP_HAS_ARESETN - -`define AXI_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_PROTOCOL,\ - th``_``vip``_0_VIP_ADDR_WIDTH,\ - th``_``vip``_0_VIP_DATA_WIDTH,\ - th``_``vip``_0_VIP_DATA_WIDTH,\ - th``_``vip``_0_VIP_ID_WIDTH,\ - th``_``vip``_0_VIP_ID_WIDTH,\ - th``_``vip``_0_VIP_AWUSER_WIDTH,\ - th``_``vip``_0_VIP_WUSER_WIDTH,\ - th``_``vip``_0_VIP_BUSER_WIDTH,\ - th``_``vip``_0_VIP_ARUSER_WIDTH,\ - th``_``vip``_0_VIP_RUSER_WIDTH,\ - th``_``vip``_0_VIP_SUPPORTS_NARROW,\ - th``_``vip``_0_VIP_HAS_BURST,\ - th``_``vip``_0_VIP_HAS_LOCK,\ - th``_``vip``_0_VIP_HAS_CACHE,\ - th``_``vip``_0_VIP_HAS_REGION,\ - th``_``vip``_0_VIP_HAS_PROT,\ - th``_``vip``_0_VIP_HAS_QOS,\ - th``_``vip``_0_VIP_HAS_WSTRB,\ - th``_``vip``_0_VIP_HAS_BRESP,\ - th``_``vip``_0_VIP_HAS_RRESP,\ - th``_``vip``_0_VIP_HAS_ARESETN - -`define AXIS_VIP_PARAM_DECL AXIS_VIP_INTERFACE_MODE = 2,\ - AXIS_VIP_SIGNAL_SET = 8'b00000011,\ - AXIS_VIP_DATA_WIDTH = 8,\ - AXIS_VIP_ID_WIDTH = 0,\ - AXIS_VIP_DEST_WIDTH = 0,\ - AXIS_VIP_USER_WIDTH = 0,\ - AXIS_VIP_USER_BITS_PER_BYTE = 0,\ - AXIS_VIP_HAS_TREADY = 1,\ - AXIS_VIP_HAS_TSTRB = 0,\ - AXIS_VIP_HAS_TKEEP = 0,\ - AXIS_VIP_HAS_TLAST = 0,\ - AXIS_VIP_HAS_ACLKEN = 0,\ - AXIS_VIP_HAS_ARESETN = 1 - -`define AXIS_VIP_PARAM_ORDER(n) n``_VIP_INTERFACE_MODE,\ - n``_VIP_SIGNAL_SET,\ - n``_VIP_DATA_WIDTH,\ - n``_VIP_ID_WIDTH,\ - n``_VIP_DEST_WIDTH,\ - n``_VIP_USER_WIDTH,\ - n``_VIP_USER_BITS_PER_BYTE,\ - n``_VIP_HAS_TREADY,\ - n``_VIP_HAS_TSTRB,\ - n``_VIP_HAS_TKEEP,\ - n``_VIP_HAS_TLAST,\ - n``_VIP_HAS_ACLKEN,\ - n``_VIP_HAS_ARESETN - -`define AXIS_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_INTERFACE_MODE,\ - th``_``vip``_0_VIP_SIGNAL_SET,\ - th``_``vip``_0_VIP_DATA_WIDTH,\ - th``_``vip``_0_VIP_ID_WIDTH,\ - th``_``vip``_0_VIP_DEST_WIDTH,\ - th``_``vip``_0_VIP_USER_WIDTH,\ - th``_``vip``_0_VIP_USER_BITS_PER_BYTE,\ - th``_``vip``_0_VIP_HAS_TREADY,\ - th``_``vip``_0_VIP_HAS_TSTRB,\ - th``_``vip``_0_VIP_HAS_TKEEP,\ - th``_``vip``_0_VIP_HAS_TLAST,\ - th``_``vip``_0_VIP_HAS_ACLKEN,\ - th``_``vip``_0_VIP_HAS_ARESETN - -`define AXIS_VIP_IF_PARAMS(n) n``_VIP_SIGNAL_SET,\ - n``_VIP_DEST_WIDTH,\ - n``_VIP_DATA_WIDTH,\ - n``_VIP_ID_WIDTH,\ - n``_VIP_USER_WIDTH,\ - n``_VIP_USER_BITS_PER_BYTE,\ - n``_VIP_HAS_ARESETN - -`define AXI 0 -`define AXIS 1 -`define FIFO 2 - // Macros used in Simulation files during simulation `define INFO(m,v) \ PrintInfo($sformatf("%s", \ diff --git a/library/vip/amd/adi_axi_agent.sv b/library/vip/amd/axi/adi_axi_agent.sv similarity index 93% rename from library/vip/amd/adi_axi_agent.sv rename to library/vip/amd/axi/adi_axi_agent.sv index db83d451..bb6c42d2 100644 --- a/library/vip/amd/adi_axi_agent.sv +++ b/library/vip/amd/axi/adi_axi_agent.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axi_definitions.svh" package adi_axi_agent_pkg; @@ -42,14 +43,14 @@ package adi_axi_agent_pkg; import axi_vip_pkg::*; import m_axi_sequencer_pkg::*; import s_axi_sequencer_pkg::*; - import x_monitor_pkg::*; + import adi_axi_monitor_pkg::*; class adi_axi_master_agent #(int `AXI_VIP_PARAM_ORDER(master)) extends adi_agent; axi_mst_agent #(`AXI_VIP_PARAM_ORDER(master)) agent; m_axi_sequencer #(`AXI_VIP_PARAM_ORDER(master)) sequencer; - x_axi_monitor #(`AXI_VIP_PARAM_ORDER(master)) monitor; + adi_axi_monitor #(`AXI_VIP_PARAM_ORDER(master)) monitor; function new( input string name, @@ -70,7 +71,7 @@ package adi_axi_agent_pkg; axi_slv_mem_agent #(`AXI_VIP_PARAM_ORDER(slave)) agent; s_axi_sequencer #(`AXI_VIP_PARAM_ORDER(slave)) sequencer; - x_axi_monitor #(`AXI_VIP_PARAM_ORDER(slave)) monitor; + adi_axi_monitor #(`AXI_VIP_PARAM_ORDER(slave)) monitor; function new( input string name, @@ -90,7 +91,7 @@ package adi_axi_agent_pkg; class adi_axi_passthrough_mem_agent #(int `AXI_VIP_PARAM_ORDER(passthrough)) extends adi_agent; axi_passthrough_mem_agent #(`AXI_VIP_PARAM_ORDER(passthrough)) agent; - x_axi_monitor #(`AXI_VIP_PARAM_ORDER(passthrough)) monitor; + adi_axi_monitor #(`AXI_VIP_PARAM_ORDER(passthrough)) monitor; function new( input string name, diff --git a/library/drivers/common/x_monitor.sv b/library/vip/amd/axi/adi_axi_monitor.sv similarity index 50% rename from library/drivers/common/x_monitor.sv rename to library/vip/amd/axi/adi_axi_monitor.sv index 3eee77a0..3b227d2f 100644 --- a/library/drivers/common/x_monitor.sv +++ b/library/vip/amd/axi/adi_axi_monitor.sv @@ -1,25 +1,35 @@ `include "utils.svh" -package x_monitor_pkg; +package adi_axi_monitor_pkg; - import xil_common_vip_pkg::*; - import axi4stream_vip_pkg::*; import axi_vip_pkg::*; import logger_pkg::*; import adi_common_pkg::*; import pub_sub_pkg::*; - class x_monitor extends adi_monitor; + class adi_axi_monitor #(int `AXI_VIP_PARAM_ORDER(axi)) extends adi_monitor; + + // analysis port from the monitor + protected axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor; + + adi_publisher #(logic [7:0]) publisher_tx; + adi_publisher #(logic [7:0]) publisher_rx; protected bit enabled; // constructor function new( input string name, + input axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor, input adi_agent parent = null); - + super.new(name, parent); + this.monitor = monitor; + + this.publisher_tx = new("Publisher TX", this); + this.publisher_rx = new("Publisher RX", this); + this.enabled = 0; endfunction @@ -37,40 +47,9 @@ package x_monitor_pkg; this.info($sformatf("Monitor enabled"), ADI_VERBOSITY_MEDIUM); endtask: run - // virtual functions - virtual task get_transaction(); - endtask - - endclass - - - class x_axi_monitor #(int `AXI_VIP_PARAM_ORDER(axi)) extends x_monitor; - - // analysis port from the monitor - protected axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor; - protected xil_analysis_port #(axi_monitor_transaction) axi_ap; - - adi_publisher #(logic [7:0]) publisher_tx; - adi_publisher #(logic [7:0]) publisher_rx; - - // constructor - function new( - input string name, - input axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor, - input adi_agent parent = null); - - super.new(name, parent); - - this.monitor = monitor; - this.axi_ap = monitor.item_collected_port; - - this.publisher_tx = new("Publisher TX", this); - this.publisher_rx = new("Publisher RX", this); - endfunction - // collect data from the DDR interface, all WRITE transaction are coming // from the ADC and all READ transactions are going to the DAC - virtual task get_transaction(); + task get_transaction(); axi_monitor_transaction transaction; xil_axi_data_beat data_beat; xil_axi_strb_beat strb_beat; @@ -79,7 +58,7 @@ package x_monitor_pkg; logic [7:0] data_queue [$]; forever begin - this.axi_ap.get(transaction); + this.monitor.item_collected_port.get(transaction); num_bytes = transaction.get_data_width()/8; for (int i=0; i<(transaction.get_len()+1); i++) begin data_beat = transaction.get_data_beat(i); @@ -106,56 +85,4 @@ package x_monitor_pkg; endclass - - class x_axis_monitor #(int `AXIS_VIP_PARAM_ORDER(axis)) extends x_monitor; - - // analysis port from the monitor - protected axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(axis)) monitor; - protected xil_analysis_port #(axi4stream_monitor_transaction) axis_ap; - - adi_publisher #(logic [7:0]) publisher; - - // constructor - function new( - input string name, - input axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(axis)) monitor, - input adi_agent parent = null); - - super.new(name, parent); - - this.monitor = monitor; - this.axis_ap = monitor.item_collected_port; - - this.publisher = new("Publisher", this); - endfunction - - // collect data from the AXI4Strean interface of the stub, this task - // handles both ONESHOT and CYCLIC scenarios - virtual task get_transaction(); - axi4stream_transaction transaction; - xil_axi4stream_data_beat data_beat; - xil_axi4stream_strb_beat keep_beat; - int num_bytes; - logic [7:0] axi_byte; - logic [7:0] data_queue [$]; - - forever begin - this.axis_ap.get(transaction); - // all bytes from a beat are valid - num_bytes = transaction.get_data_width()/8; - data_beat = transaction.get_data_beat(); - keep_beat = transaction.get_keep_beat(); - for (int j=0; j +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + + +`timescale 1ns/1ps + +`ifndef _AXI_DEFINITIONS_SVH_ +`define _AXI_DEFINITIONS_SVH_ + +// Help build VIP Interface parameters name +`define AXI_VIP_IF_PARAMS(n) n``_VIP_PROTOCOL,\ + n``_VIP_ADDR_WIDTH,\ + n``_VIP_WDATA_WIDTH,\ + n``_VIP_RDATA_WIDTH,\ + n``_VIP_WID_WIDTH,\ + n``_VIP_RID_WIDTH,\ + n``_VIP_AWUSER_WIDTH,\ + n``_VIP_WUSER_WIDTH,\ + n``_VIP_BUSER_WIDTH,\ + n``_VIP_ARUSER_WIDTH,\ + n``_VIP_RUSER_WIDTH,\ + n``_VIP_SUPPORTS_NARROW,\ + n``_VIP_HAS_BURST,\ + n``_VIP_HAS_LOCK,\ + n``_VIP_HAS_CACHE,\ + n``_VIP_HAS_REGION,\ + n``_VIP_HAS_PROT,\ + n``_VIP_HAS_QOS,\ + n``_VIP_HAS_WSTRB,\ + n``_VIP_HAS_BRESP,\ + n``_VIP_HAS_RRESP,\ + n``_VIP_HAS_ARESETN + +`define AXI_VIP_PARAM_ORDER(n) n``_VIP_PROTOCOL,\ + n``_VIP_ADDR_WIDTH,\ + n``_VIP_WDATA_WIDTH,\ + n``_VIP_RDATA_WIDTH,\ + n``_VIP_WID_WIDTH,\ + n``_VIP_RID_WIDTH,\ + n``_VIP_AWUSER_WIDTH,\ + n``_VIP_WUSER_WIDTH,\ + n``_VIP_BUSER_WIDTH,\ + n``_VIP_ARUSER_WIDTH,\ + n``_VIP_RUSER_WIDTH,\ + n``_VIP_SUPPORTS_NARROW,\ + n``_VIP_HAS_BURST,\ + n``_VIP_HAS_LOCK,\ + n``_VIP_HAS_CACHE,\ + n``_VIP_HAS_REGION,\ + n``_VIP_HAS_PROT,\ + n``_VIP_HAS_QOS,\ + n``_VIP_HAS_WSTRB,\ + n``_VIP_HAS_BRESP,\ + n``_VIP_HAS_RRESP,\ + n``_VIP_HAS_ARESETN + +`define AXI_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_PROTOCOL,\ + th``_``vip``_0_VIP_ADDR_WIDTH,\ + th``_``vip``_0_VIP_DATA_WIDTH,\ + th``_``vip``_0_VIP_DATA_WIDTH,\ + th``_``vip``_0_VIP_ID_WIDTH,\ + th``_``vip``_0_VIP_ID_WIDTH,\ + th``_``vip``_0_VIP_AWUSER_WIDTH,\ + th``_``vip``_0_VIP_WUSER_WIDTH,\ + th``_``vip``_0_VIP_BUSER_WIDTH,\ + th``_``vip``_0_VIP_ARUSER_WIDTH,\ + th``_``vip``_0_VIP_RUSER_WIDTH,\ + th``_``vip``_0_VIP_SUPPORTS_NARROW,\ + th``_``vip``_0_VIP_HAS_BURST,\ + th``_``vip``_0_VIP_HAS_LOCK,\ + th``_``vip``_0_VIP_HAS_CACHE,\ + th``_``vip``_0_VIP_HAS_REGION,\ + th``_``vip``_0_VIP_HAS_PROT,\ + th``_``vip``_0_VIP_HAS_QOS,\ + th``_``vip``_0_VIP_HAS_WSTRB,\ + th``_``vip``_0_VIP_HAS_BRESP,\ + th``_``vip``_0_VIP_HAS_RRESP,\ + th``_``vip``_0_VIP_HAS_ARESETN + +`endif diff --git a/library/vip/amd/m_axi_sequencer.sv b/library/vip/amd/axi/m_axi_sequencer.sv similarity index 99% rename from library/vip/amd/m_axi_sequencer.sv rename to library/vip/amd/axi/m_axi_sequencer.sv index 7e917b0a..c786d5ee 100644 --- a/library/vip/amd/m_axi_sequencer.sv +++ b/library/vip/amd/axi/m_axi_sequencer.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axi_definitions.svh" package m_axi_sequencer_pkg; diff --git a/library/vip/amd/s_axi_sequencer.sv b/library/vip/amd/axi/s_axi_sequencer.sv similarity index 99% rename from library/vip/amd/s_axi_sequencer.sv rename to library/vip/amd/axi/s_axi_sequencer.sv index b03b2f40..c09f2f5d 100644 --- a/library/vip/amd/s_axi_sequencer.sv +++ b/library/vip/amd/axi/s_axi_sequencer.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axi_definitions.svh" package s_axi_sequencer_pkg; diff --git a/library/vip/amd/adi_axis_agent.sv b/library/vip/amd/axis/adi_axis_agent.sv similarity index 93% rename from library/vip/amd/adi_axis_agent.sv rename to library/vip/amd/axis/adi_axis_agent.sv index 65801c1a..392b79e5 100644 --- a/library/vip/amd/adi_axis_agent.sv +++ b/library/vip/amd/axis/adi_axis_agent.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axis_definitions.svh" package adi_axis_agent_pkg; @@ -42,14 +43,14 @@ package adi_axis_agent_pkg; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; import s_axis_sequencer_pkg::*; - import x_monitor_pkg::*; + import adi_axis_monitor_pkg::*; class adi_axis_master_agent #(int `AXIS_VIP_PARAM_ORDER(master)) extends adi_agent; axi4stream_mst_agent #(`AXIS_VIP_IF_PARAMS(master)) agent; m_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(master)) sequencer; - x_axis_monitor #(`AXIS_VIP_PARAM_ORDER(master)) monitor; + adi_axis_monitor #(`AXIS_VIP_PARAM_ORDER(master)) monitor; function new( input string name, @@ -70,7 +71,7 @@ package adi_axis_agent_pkg; axi4stream_slv_agent #(`AXIS_VIP_IF_PARAMS(slave)) agent; s_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(slave)) sequencer; - x_axis_monitor #(`AXIS_VIP_PARAM_ORDER(slave)) monitor; + adi_axis_monitor #(`AXIS_VIP_PARAM_ORDER(slave)) monitor; function new( input string name, @@ -90,7 +91,7 @@ package adi_axis_agent_pkg; class adi_axis_passthrough_mem_agent #(int `AXIS_VIP_PARAM_ORDER(passthrough)) extends adi_agent; axi4stream_passthrough_agent #(`AXIS_VIP_IF_PARAMS(passthrough)) agent; - x_axis_monitor #(`AXIS_VIP_PARAM_ORDER(passthrough)) monitor; + adi_axis_monitor #(`AXIS_VIP_PARAM_ORDER(passthrough)) monitor; function new( input string name, diff --git a/library/vip/amd/axis/adi_axis_monitor.sv b/library/vip/amd/axis/adi_axis_monitor.sv new file mode 100644 index 00000000..b13849cb --- /dev/null +++ b/library/vip/amd/axis/adi_axis_monitor.sv @@ -0,0 +1,77 @@ +`include "utils.svh" + +package adi_axis_monitor_pkg; + + import axi4stream_vip_pkg::*; + import logger_pkg::*; + import adi_common_pkg::*; + import pub_sub_pkg::*; + + class adi_axis_monitor #(int `AXIS_VIP_PARAM_ORDER(axis)) extends adi_monitor; + + // analysis port from the monitor + protected axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(axis)) monitor; + + adi_publisher #(logic [7:0]) publisher; + + protected bit enabled; + + // constructor + function new( + input string name, + input axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(axis)) monitor, + input adi_agent parent = null); + + super.new(name, parent); + + this.monitor = monitor; + + this.publisher = new("Publisher", this); + + this.enabled = 0; + endfunction + + task run(); + if (this.enabled) begin + this.error($sformatf("Monitor is already running!")); + return; + end + + fork + this.get_transaction(); + join_none + + this.enabled = 1; + this.info($sformatf("Monitor enabled"), ADI_VERBOSITY_MEDIUM); + endtask: run + + // collect data from the AXI4Strean interface of the stub, this task + // handles both ONESHOT and CYCLIC scenarios + task get_transaction(); + axi4stream_transaction transaction; + xil_axi4stream_data_beat data_beat; + xil_axi4stream_strb_beat keep_beat; + int num_bytes; + logic [7:0] axi_byte; + logic [7:0] data_queue [$]; + + forever begin + this.monitor.item_collected_port.get(transaction); + // all bytes from a beat are valid + num_bytes = transaction.get_data_width()/8; + data_beat = transaction.get_data_beat(); + keep_beat = transaction.get_keep_beat(); + for (int j=0; j +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + + +`timescale 1ns/1ps + +`ifndef _AXIS_DEFINITIONS_SVH_ +`define _AXIS_DEFINITIONS_SVH_ + +// Help build VIP Interface parameters name +`define AXIS_VIP_PARAM_DECL AXIS_VIP_INTERFACE_MODE = 2,\ + AXIS_VIP_SIGNAL_SET = 8'b00000011,\ + AXIS_VIP_DATA_WIDTH = 8,\ + AXIS_VIP_ID_WIDTH = 0,\ + AXIS_VIP_DEST_WIDTH = 0,\ + AXIS_VIP_USER_WIDTH = 0,\ + AXIS_VIP_USER_BITS_PER_BYTE = 0,\ + AXIS_VIP_HAS_TREADY = 1,\ + AXIS_VIP_HAS_TSTRB = 0,\ + AXIS_VIP_HAS_TKEEP = 0,\ + AXIS_VIP_HAS_TLAST = 0,\ + AXIS_VIP_HAS_ACLKEN = 0,\ + AXIS_VIP_HAS_ARESETN = 1 + +`define AXIS_VIP_PARAM_ORDER(n) n``_VIP_INTERFACE_MODE,\ + n``_VIP_SIGNAL_SET,\ + n``_VIP_DATA_WIDTH,\ + n``_VIP_ID_WIDTH,\ + n``_VIP_DEST_WIDTH,\ + n``_VIP_USER_WIDTH,\ + n``_VIP_USER_BITS_PER_BYTE,\ + n``_VIP_HAS_TREADY,\ + n``_VIP_HAS_TSTRB,\ + n``_VIP_HAS_TKEEP,\ + n``_VIP_HAS_TLAST,\ + n``_VIP_HAS_ACLKEN,\ + n``_VIP_HAS_ARESETN + +`define AXIS_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_INTERFACE_MODE,\ + th``_``vip``_0_VIP_SIGNAL_SET,\ + th``_``vip``_0_VIP_DATA_WIDTH,\ + th``_``vip``_0_VIP_ID_WIDTH,\ + th``_``vip``_0_VIP_DEST_WIDTH,\ + th``_``vip``_0_VIP_USER_WIDTH,\ + th``_``vip``_0_VIP_USER_BITS_PER_BYTE,\ + th``_``vip``_0_VIP_HAS_TREADY,\ + th``_``vip``_0_VIP_HAS_TSTRB,\ + th``_``vip``_0_VIP_HAS_TKEEP,\ + th``_``vip``_0_VIP_HAS_TLAST,\ + th``_``vip``_0_VIP_HAS_ACLKEN,\ + th``_``vip``_0_VIP_HAS_ARESETN + +`define AXIS_VIP_IF_PARAMS(n) n``_VIP_SIGNAL_SET,\ + n``_VIP_DEST_WIDTH,\ + n``_VIP_DATA_WIDTH,\ + n``_VIP_ID_WIDTH,\ + n``_VIP_USER_WIDTH,\ + n``_VIP_USER_BITS_PER_BYTE,\ + n``_VIP_HAS_ARESETN + +`endif diff --git a/library/vip/amd/m_axis_sequencer.sv b/library/vip/amd/axis/m_axis_sequencer.sv similarity index 99% rename from library/vip/amd/m_axis_sequencer.sv rename to library/vip/amd/axis/m_axis_sequencer.sv index 6a319870..8bf3c429 100644 --- a/library/vip/amd/m_axis_sequencer.sv +++ b/library/vip/amd/axis/m_axis_sequencer.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axis_definitions.svh" package m_axis_sequencer_pkg; diff --git a/library/vip/amd/s_axis_sequencer.sv b/library/vip/amd/axis/s_axis_sequencer.sv similarity index 99% rename from library/vip/amd/s_axis_sequencer.sv rename to library/vip/amd/axis/s_axis_sequencer.sv index dc09e5ba..26e229b7 100644 --- a/library/vip/amd/s_axis_sequencer.sv +++ b/library/vip/amd/axis/s_axis_sequencer.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axis_definitions.svh" package s_axis_sequencer_pkg; diff --git a/testbenches/ip/base/tests/test_program.sv b/testbenches/ip/base/tests/test_program.sv index 6c5c21b5..d002e04a 100644 --- a/testbenches/ip/base/tests/test_program.sv +++ b/testbenches/ip/base/tests/test_program.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axi_definitions.svh" import logger_pkg::*; import test_harness_env_pkg::*; diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv index 48261fdb..a849e39d 100644 --- a/testbenches/ip/scoreboard/environment.sv +++ b/testbenches/ip/scoreboard/environment.sv @@ -1,4 +1,6 @@ `include "utils.svh" +`include "axi_definitions.svh" +`include "axis_definitions.svh" package environment_pkg; diff --git a/testbenches/ip/scoreboard/tests/test_program.sv b/testbenches/ip/scoreboard/tests/test_program.sv index 029698a4..3ae86f18 100644 --- a/testbenches/ip/scoreboard/tests/test_program.sv +++ b/testbenches/ip/scoreboard/tests/test_program.sv @@ -36,9 +36,9 @@ // // `include "utils.svh" +`include "axi_definitions.svh" +`include "axis_definitions.svh" -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; import environment_pkg::*; import test_harness_env_pkg::*; From c99cfd7a00067b25a0f6efa45950b13a398d5c82 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 16 Dec 2024 14:58:15 +0200 Subject: [PATCH 04/37] infrastructure refactorization: Generalized scoreboard Signed-off-by: Istvan-Zsolt Szekely --- library/drivers/common/scoreboard.sv | 26 ++++++++++++++---------- testbenches/ip/scoreboard/environment.sv | 4 ++-- 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/library/drivers/common/scoreboard.sv b/library/drivers/common/scoreboard.sv index f5fe568a..765182f4 100644 --- a/library/drivers/common/scoreboard.sv +++ b/library/drivers/common/scoreboard.sv @@ -9,17 +9,17 @@ package scoreboard_pkg; import adi_common_pkg::*; import pub_sub_pkg::*; - class scoreboard extends adi_component; + class scoreboard #(type data_type = int) extends adi_component; - class subscriber_class extends adi_subscriber #(logic [7:0]); + class subscriber_class extends adi_subscriber #(data_type); - protected scoreboard scoreboard_ref; + protected scoreboard #(data_type) scoreboard_ref; - protected logic [7:0] byte_stream [$]; + protected data_type byte_stream [$]; function new( input string name, - input scoreboard scoreboard_ref, + input scoreboard #(data_type) scoreboard_ref, input adi_component parent = null); super.new(name, parent); @@ -30,19 +30,19 @@ package scoreboard_pkg; virtual function void update(input data_type data [$]); this.info($sformatf("Data received: %d", data.size()), ADI_VERBOSITY_MEDIUM); while (data.size()) begin - this.byte_stream.push_back(data.pop_front); + this.byte_stream.push_back(data.pop_front()); end - if (this.scoreboard_ref.enabled) begin + if (this.scoreboard_ref.get_enabled()) begin this.scoreboard_ref.compare_transaction(); end endfunction: update - function logic [7:0] get_data(); + function data_type get_data(); return this.byte_stream.pop_front(); endfunction: get_data - function void put_data(logic [7:0] data); + function void put_data(data_type data); this.byte_stream.push_back(data); endfunction: put_data @@ -100,6 +100,10 @@ package scoreboard_pkg; this.byte_streams_empty_sig = 1; endtask: stop + function bit get_enabled(); + return this.enabled; + endfunction: get_enabled + // set sink type function void set_sink_type(input bit sink_type); if (!this.enabled) begin @@ -129,8 +133,8 @@ package scoreboard_pkg; // compare the collected data virtual function void compare_transaction(); - logic [7:0] source_byte; - logic [7:0] sink_byte; + data_type source_byte; + data_type sink_byte; if (this.enabled == 0) return; diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv index a849e39d..515d5b1d 100644 --- a/testbenches/ip/scoreboard/environment.sv +++ b/testbenches/ip/scoreboard/environment.sv @@ -26,8 +26,8 @@ package environment_pkg; adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAM_ORDER(adc_dst_pt)) adc_dst_axi_pt_agent; adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAM_ORDER(dac_src_pt)) dac_src_axi_pt_agent; - scoreboard scoreboard_tx; - scoreboard scoreboard_rx; + scoreboard #(logic [7:0]) scoreboard_tx; + scoreboard #(logic [7:0]) scoreboard_rx; //============================================================================ // Constructor From a463503f91d3d84a614a41b3289772d962f41f82 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 16 Dec 2024 15:14:53 +0200 Subject: [PATCH 05/37] infrastructure refactorization: Updated DMA loopback project Signed-off-by: Istvan-Zsolt Szekely --- .../ip/dma_loopback/tests/test_program.sv | 45 +++++++++---------- 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/testbenches/ip/dma_loopback/tests/test_program.sv b/testbenches/ip/dma_loopback/tests/test_program.sv index 0e609f33..62ff95ec 100644 --- a/testbenches/ip/dma_loopback/tests/test_program.sv +++ b/testbenches/ip/dma_loopback/tests/test_program.sv @@ -36,19 +36,22 @@ // // `include "utils.svh" +`include "axi_definitions.svh" import test_harness_env_pkg::*; -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; import dma_trans_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + program test_program; - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + // Register accessors dmac_api m_dmac_api; dmac_api s_dmac_api; @@ -56,7 +59,7 @@ program test_program; initial begin //creating environment - env = new("DMA Loopback Environment", + base_env = new("DMA Loopback Environment", `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, @@ -64,29 +67,25 @@ program test_program; `TH.`MNG_AXI.inst.IF, `TH.`DDR_AXI.inst.IF); - #2ps; - setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); + + base_env.start(); + start_clocks(); + base_env.sys_reset(); - m_dmac_api = new("TX_DMA", env.mng, `TX_DMA_BA); + m_dmac_api = new("TX_DMA", base_env.mng.sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA", env.mng, `RX_DMA_BA); + s_dmac_api = new("RX_DMA", base_env.mng.sequencer, `RX_DMA_BA); s_dmac_api.probe(); - start_clocks(); - sys_reset(); - - #1us; - // ------------------------------------------------------- // Test TX DMA and RX DMA in loopback // ------------------------------------------------------- // Init test data for (int i=0;i<2048*2 ;i=i+2) begin - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(`DDR_BA+i*2,(((i+1)) << 16) | i ,'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(`DDR_BA+i*2,(((i+1)) << 16) | i ,'hF); end do_transfer( @@ -103,6 +102,11 @@ program test_program; .length('h1000) ); + base_env.stop(); + + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); + $finish(); + end task do_transfer(bit [31:0] src_addr, @@ -147,8 +151,8 @@ program test_program; for (int i=0;i Date: Mon, 16 Dec 2024 16:06:58 +0200 Subject: [PATCH 06/37] infrastructure refactorization: Fixed address value in DMA loopback for DDR Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/dma_loopback/tests/test_program.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/testbenches/ip/dma_loopback/tests/test_program.sv b/testbenches/ip/dma_loopback/tests/test_program.sv index 62ff95ec..02320217 100644 --- a/testbenches/ip/dma_loopback/tests/test_program.sv +++ b/testbenches/ip/dma_loopback/tests/test_program.sv @@ -44,6 +44,7 @@ import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; import dma_trans_pkg::*; +import axi_vip_pkg::*; import `PKGIFY(test_harness, mng_axi_vip)::*; import `PKGIFY(test_harness, ddr_axi_vip)::*; @@ -85,7 +86,7 @@ program test_program; // Init test data for (int i=0;i<2048*2 ;i=i+2) begin - base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(`DDR_BA+i*2,(((i+1)) << 16) | i ,'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF); end do_transfer( From 5ee6bb3e646a5f3fa796483578033cdc8be21ca9 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Fri, 17 Jan 2025 16:00:40 +0200 Subject: [PATCH 07/37] infrastructure refactorization: Updated IP level testbenches Signed-off-by: Istvan-Zsolt Szekely --- library/drivers/common/scoreboard.sv | 3 - library/drivers/common/scoreboard_pack.sv | 124 ++++++----- library/vip/adi/spi_vip/adi_spi_vip_ip.tcl | 4 +- library/vip/adi/spi_vip/adi_spi_vip_pkg.sv | 1 + library/vip/adi/spi_vip/s_spi_sequencer.sv | 1 + testbenches/ip/axi_tdd/tests/test_program.sv | 168 +++++++-------- testbenches/ip/axis_sequencers/environment.sv | 110 +++------- .../ip/axis_sequencers/tests/test_program.sv | 96 +++++---- testbenches/ip/dma_flock/environment.sv | 92 +++----- testbenches/ip/dma_flock/scoreboard.sv | 3 +- .../ip/dma_flock/tests/test_program.sv | 82 +++++--- .../tests/test_program_frame_delay.sv | 87 ++++---- .../ip/dma_sg/tests/test_program_1d.sv | 151 ++++++------- .../ip/dma_sg/tests/test_program_2d.sv | 129 ++++++------ .../ip/dma_sg/tests/test_program_tr_queue.sv | 171 +++++++-------- testbenches/ip/i3c_controller/Makefile | 6 +- .../ip/i3c_controller/system_project.tcl | 2 + .../ip/i3c_controller/tests/test_program.sv | 35 +-- .../ip/jesd_loopback/tests/test_program.sv | 144 ++++++------- .../jesd_loopback_64b/tests/test_program.sv | 88 ++++---- .../ip/scoreboard/tests/test_program.sv | 2 +- testbenches/ip/spi_engine/spi_environment.sv | 43 +--- .../ip/spi_engine/tests/test_program.sv | 86 ++++---- .../ip/spi_engine/tests/test_sleep_delay.sv | 86 ++++---- testbenches/ip/util_pack/environment.sv | 199 +++++------------- .../ip/util_pack/tests/test_program.sv | 73 ++++--- 26 files changed, 938 insertions(+), 1048 deletions(-) diff --git a/library/drivers/common/scoreboard.sv b/library/drivers/common/scoreboard.sv index 765182f4..7c1ccc0d 100644 --- a/library/drivers/common/scoreboard.sv +++ b/library/drivers/common/scoreboard.sv @@ -2,9 +2,6 @@ package scoreboard_pkg; - import xil_common_vip_pkg::*; - import axi4stream_vip_pkg::*; - import axi_vip_pkg::*; import logger_pkg::*; import adi_common_pkg::*; import pub_sub_pkg::*; diff --git a/library/drivers/common/scoreboard_pack.sv b/library/drivers/common/scoreboard_pack.sv index 7a7b151d..cd6020b1 100644 --- a/library/drivers/common/scoreboard_pack.sv +++ b/library/drivers/common/scoreboard_pack.sv @@ -2,12 +2,8 @@ package scoreboard_pack_pkg; - import xil_common_vip_pkg::*; - import axi4stream_vip_pkg::*; - import axi_vip_pkg::*; import logger_pkg::*; - import x_monitor_pkg::*; - import mailbox_pkg::*; + import adi_common_pkg::*; import scoreboard_pkg::*; typedef enum { @@ -15,7 +11,7 @@ package scoreboard_pack_pkg; UPACK } pack_type; - class scoreboard_pack extends scoreboard; + class scoreboard_pack #(type data_type = int) extends scoreboard#(.data_type(data_type)); protected int channels; protected int samples; @@ -42,62 +38,90 @@ package scoreboard_pack_pkg; endfunction: new // compare the collected data - virtual task compare_transaction(); + virtual function void compare_transaction(); logic [7:0] source_byte; logic [7:0] sink_byte; - logic [7:0] sink_byte_stream_block [int]; + data_type sink_byte_stream_block [int]; int outer_loop = (this.mode == CPACK) ? this.channels : this.samples; int inner_loop = (this.mode == CPACK) ? this.samples : this.channels; - this.info($sformatf("Scoreboard started"), 100); - - forever begin : tx_path - if (this.enabled == 0) - break; - if ((this.source_byte_stream_size > 0) && - (this.sink_byte_stream_size >= this.channels*this.samples*this.width/8)) begin - byte_streams_empty_sig = 0; - for (int i=0; i 0) && + // (this.sink_byte_stream_size >= this.channels*this.samples*this.width/8)) begin + // byte_streams_empty_sig = 0; + // for (int i=0; i>byte_streams_empty; + // end + // fork begin + // fork + // @source_transaction_event; + // @sink_transaction_event; + // @stop_scoreboard; + // join_any + // byte_streams_empty_sig = 0; + // disable fork; + // end join + // end + // end + + while ((this.subscriber_source.get_size() > 0) && + (this.subscriber_sink.get_size() >= this.channels*this.samples*this.width/8)) begin + byte_streams_empty_sig = 0; + for (int i=0; i>byte_streams_empty; - end - fork begin - fork - @source_transaction_event; - @sink_transaction_event; - @stop_scoreboard; - join_any - byte_streams_empty_sig = 0; - disable fork; - end join end - end + end - endtask /* compare_transaction */ + if ((this.subscriber_source.get_size() == 0) && + (this.subscriber_sink.get_size() == 0)) begin + this.byte_streams_empty_sig = 1; + ->this.byte_streams_empty; + end + endfunction: compare_transaction endclass diff --git a/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl b/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl index 1e745e88..ec3e200a 100644 --- a/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl +++ b/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl @@ -12,8 +12,8 @@ adi_ip_files adi_spi_vip [list \ "adi_spi_vip.sv" \ "spi_vip_if.sv" \ "adi_spi_vip_pkg.ttcl" \ - "$ad_hdl_dir/testbenches/library/utilities/utils.svh" \ - "$ad_hdl_dir/testbenches/library/utilities/logger_pkg.sv" \ + "$ad_tb_dir/library/utilities/utils.svh" \ + "$ad_tb_dir/library/utilities/logger_pkg.sv" \ ] adi_ip_properties_lite adi_spi_vip diff --git a/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv b/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv index b403a0ba..4d66c3c6 100644 --- a/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv +++ b/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv @@ -38,6 +38,7 @@ package adi_spi_vip_pkg; import logger_pkg::*; + import adi_common_pkg::*; `define SPI_VIP_PARAM_ORDER SPI_VIP_MODE ,\ SPI_VIP_CPOL ,\ diff --git a/library/vip/adi/spi_vip/s_spi_sequencer.sv b/library/vip/adi/spi_vip/s_spi_sequencer.sv index 82995926..79112770 100644 --- a/library/vip/adi/spi_vip/s_spi_sequencer.sv +++ b/library/vip/adi/spi_vip/s_spi_sequencer.sv @@ -38,6 +38,7 @@ package s_spi_sequencer_pkg; import logger_pkg::*; + import adi_common_pkg::*; import adi_spi_vip_pkg::*; class s_spi_sequencer #(`SPI_VIP_PARAM_ORDER) extends adi_component; diff --git a/testbenches/ip/axi_tdd/tests/test_program.sv b/testbenches/ip/axi_tdd/tests/test_program.sv index 05324c7b..0819bacd 100644 --- a/testbenches/ip/axi_tdd/tests/test_program.sv +++ b/testbenches/ip/axi_tdd/tests/test_program.sv @@ -37,17 +37,18 @@ // `include "utils.svh" -import test_harness_env_pkg::*; -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; +import test_harness_env_pkg::*; import adi_regmap_pkg::*; import adi_regmap_tdd_gen_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + program test_program; //instantiate the environment - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; //written variables int unsigned ch_on [32]; @@ -88,23 +89,19 @@ program test_program; initial begin //creating environment - env = new("Axi TDD Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); - - #2ps; + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); + base_env.start(); start_clocks(); - sys_reset(); - - #1us; + base_env.sys_reset(); // ------------------------------------------------------- // Test start @@ -112,7 +109,7 @@ program test_program; // Init test data // Read the interface description - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_INTERFACE_DESCRIPTION), val); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_INTERFACE_DESCRIPTION), val); channel_count = `GET_TDDN_CNTRL_INTERFACE_DESCRIPTION_CHANNEL_COUNT_EXTRA(val); reg_count_width = `GET_TDDN_CNTRL_INTERFACE_DESCRIPTION_REGISTER_WIDTH(val); burst_count_width = `GET_TDDN_CNTRL_INTERFACE_DESCRIPTION_BURST_COUNT_WIDTH(val); @@ -122,41 +119,41 @@ program test_program; sync_ext_cdc = `GET_TDDN_CNTRL_INTERFACE_DESCRIPTION_SYNC_EXTERNAL_CDC(val); // Register configuration - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), `SET_TDDN_CNTRL_CHANNEL_ENABLE_CHANNEL_ENABLE(32'hFFFFFFFF)); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'h00000000)); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), `SET_TDDN_CNTRL_BURST_COUNT_BURST_COUNT(channel_count+1)); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), `SET_TDDN_CNTRL_STARTUP_DELAY_STARTUP_DELAY(32'h0000007F)); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), `SET_TDDN_CNTRL_FRAME_LENGTH_FRAME_LENGTH(32'h0000007F)); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), `SET_TDDN_CNTRL_SYNC_COUNTER_LOW_SYNC_COUNTER_LOW(32'h000001FF)); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_HIGH), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_HIGH), `SET_TDDN_CNTRL_SYNC_COUNTER_HIGH_SYNC_COUNTER_HIGH(32'h00000000)); // Reading back the actual register values (the values may change depending on the synthesis configuration) - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), ch_en); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), ch_en); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), burst_count); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), burst_count); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), startup_delay); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), startup_delay); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), frame_length); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), frame_length); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), sync_count_low); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), sync_count_low); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_HIGH), sync_count_high); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_HIGH), sync_count_high); // ------------------------------------------------------- @@ -172,17 +169,17 @@ program test_program; end for (int i=0; i<32; i++) begin - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, `SET_TDDN_CNTRL_CH0_ON_CH0_ON(ch_on[i])); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, `SET_TDDN_CNTRL_CH0_OFF_CH0_OFF(ch_off[i])); end // Read back the values; unimplemented channels should not store these values for (int i=0; i<32; i++) begin - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, val); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, val); if (i <= channel_count) begin expected_val = ch_on[i]; @@ -196,7 +193,7 @@ program test_program; success_count++; end - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, val); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, val); if (i <= channel_count) begin expected_val = ch_off[i]; @@ -212,7 +209,7 @@ program test_program; end // Read the status register to validate the current state - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b00) begin `FATAL(("Idle state: Expected 2'b00 found 2'b%b", current_state)); @@ -222,7 +219,7 @@ program test_program; // Enable the module; use internal sync for transfer triggering - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(1)| @@ -238,7 +235,7 @@ program test_program; // Read the status register to validate the current state repeat (8) @(posedge `TH.dut_tdd.inst.up_clk); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b10) begin `FATAL(("Waiting state: Expected 2'b10 found 2'b%b", current_state)); @@ -264,7 +261,7 @@ program test_program; // Read the status register to validate the current state issuing a parallel thread repeat (8) @(posedge `TH.dut_tdd.inst.up_clk); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b11) begin `FATAL(("Running state: Expected 2'b11 found 2'b%b", current_state)); @@ -281,7 +278,7 @@ program test_program; //*******// // Read the status register to validate the current state repeat (8) @(posedge `TH.dut_tdd.inst.up_clk); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b01) begin `FATAL(("Armed state: Expected 2'b01 found 2'b%b", current_state)); @@ -290,17 +287,17 @@ program test_program; end // Disable the module to change the polarity - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); // Switch to inverted polarity - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'hFFFFFFFF)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); // Re-enable the module - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(1)| @@ -321,14 +318,14 @@ program test_program; // ARMED // //*******// // Disable the module - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); // Switch to direct polarity - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'h00000000)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); // ------------------------------------------------------- @@ -344,16 +341,16 @@ program test_program; end for (int i=0; i<32; i++) begin - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, `SET_TDDN_CNTRL_CH0_ON_CH0_ON(ch_on[i])); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, `SET_TDDN_CNTRL_CH0_OFF_CH0_OFF(ch_off[i])); end // Read back the values; unimplemented channels should not store these values for (int i=0; i<32; i++) begin - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, val); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, val); if (i <= channel_count) begin expected_val = ch_on[i]; @@ -367,7 +364,7 @@ program test_program; success_count++; end - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, val); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, val); if (i <= channel_count) begin expected_val = ch_off[i]; @@ -384,7 +381,7 @@ program test_program; // Enable the module; use external sync for transfer triggering - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(0)| @@ -408,17 +405,17 @@ program test_program; // ARMED // //*******// // Disable the module - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); // Switch to inverted polarity - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'hFFFFFFFF)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); // Keep the module enabled; issue a software sync - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(0)| @@ -439,14 +436,14 @@ program test_program; // ARMED // //*******// // Disable the module - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); // Switch to direct polarity - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'h00000000)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); // ------------------------------------------------------- @@ -454,11 +451,11 @@ program test_program; // ------------------------------------------------------- // Increase the burst count value by 1 - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), `SET_TDDN_CNTRL_BURST_COUNT_BURST_COUNT(channel_count+2)); // Keep the module enabled; issue a software sync; enable external sync and reset on sync - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(0)| @@ -487,7 +484,7 @@ program test_program; end // Disable the module before the end of the burst - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); @(posedge `TH.dut_tdd.inst.tdd_endof_frame); @@ -495,24 +492,24 @@ program test_program; // Check the pulse length using a loop on all available channels check_pulse_length(); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), `SET_TDDN_CNTRL_CHANNEL_ENABLE_CHANNEL_ENABLE(0)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), ch_en); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), ch_en); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), `SET_TDDN_CNTRL_BURST_COUNT_BURST_COUNT(0)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), burst_count); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), burst_count); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), `SET_TDDN_CNTRL_STARTUP_DELAY_STARTUP_DELAY(0)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), startup_delay); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), startup_delay); // Enable the module with external synchronization actived - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(0)| @@ -535,7 +532,7 @@ program test_program; success_count++; end - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), `SET_TDDN_CNTRL_CHANNEL_ENABLE_CHANNEL_ENABLE(ch_en)); ch_en = (ch_en << 1) | 32'b1; @@ -553,7 +550,7 @@ program test_program; success_count++; end - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), `SET_TDDN_CNTRL_CHANNEL_ENABLE_CHANNEL_ENABLE(ch_en)); ch_en = (ch_en >> 1); @@ -561,13 +558,14 @@ program test_program; end // Disable the module - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); + base_env.stop(); stop_clocks(); `INFO(("Testbench finished!"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -582,14 +580,6 @@ program test_program; endtask - task sys_reset(); - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - endtask - - task trigger_ext_event(); #20ns; `TB.sync_in =1'b1; @@ -607,11 +597,15 @@ program test_program; time t1=0, t2=0, expected_pulse_lengh; fork - channel_probe(i, t1, t2); - join_none - @(posedge `TH.dut_tdd.inst.tdd_endof_frame); - repeat (3) @(posedge `TH.dut_tdd.inst.clk); - disable fork; + begin + fork + channel_probe(i, t1, t2); + join_none + @(posedge `TH.dut_tdd.inst.tdd_endof_frame); + repeat (3) @(posedge `TH.dut_tdd.inst.clk); + disable fork; + end + join if (ch_on[i] == ch_off[i]) begin expected_pulse_lengh = 0; diff --git a/testbenches/ip/axis_sequencers/environment.sv b/testbenches/ip/axis_sequencers/environment.sv index ba3fe31c..423e8b63 100644 --- a/testbenches/ip/axis_sequencers/environment.sv +++ b/testbenches/ip/axis_sequencers/environment.sv @@ -1,32 +1,21 @@ `include "utils.svh" +`include "axis_definitions.svh" package environment_pkg; - import m_axi_sequencer_pkg::*; - import s_axi_sequencer_pkg::*; - import m_axis_sequencer_pkg::*; - import s_axis_sequencer_pkg::*; import logger_pkg::*; - import axi_vip_pkg::*; - import axi4stream_vip_pkg::*; - import test_harness_env_pkg::*; - - import `PKGIFY(test_harness, mng_axi_vip)::*; - import `PKGIFY(test_harness, ddr_axi_vip)::*; - - import `PKGIFY(test_harness, src_axis)::*; - import `PKGIFY(test_harness, dst_axis)::*; + import adi_common_pkg::*; - class environment extends test_harness_env; + import axi4stream_vip_pkg::*; + import m_axis_sequencer_pkg::*; + import s_axis_sequencer_pkg::*; + import adi_axis_agent_pkg::*; - // agents and sequencers - `AGENT(test_harness, src_axis, mst_t) src_axis_agent; - `AGENT(test_harness, dst_axis, slv_t) dst_axis_agent; + class axis_sequencer_environment #(int `AXIS_VIP_PARAM_ORDER(src_axis), int `AXIS_VIP_PARAM_ORDER(dst_axis)) extends adi_environment; - m_axis_sequencer #(`AGENT(test_harness, src_axis, mst_t), - `AXIS_VIP_PARAMS(test_harness, src_axis) - ) src_axis_seq; - s_axis_sequencer #(`AGENT(test_harness, dst_axis, slv_t)) dst_axis_seq; + // Agents + adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(src_axis)) src_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAM_ORDER(dst_axis)) dst_axis_agent; //============================================================================ // Constructor @@ -34,34 +23,14 @@ package environment_pkg; function new ( input string name, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, - - virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, - - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, - - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, src_axis)) src_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, dst_axis)) dst_axis_vip_if - ); + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(src_axis)) src_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(dst_axis)) dst_axis_vip_if); // creating the agents - super.new(name, - sys_clk_vip_if, - dma_clk_vip_if, - ddr_clk_vip_if, - sys_rst_vip_if, - mng_vip_if, - ddr_vip_if); - - src_axis_agent = new("Source AXI Stream Agent", src_axis_vip_if); - dst_axis_agent = new("Destination AXI Stream Agent", dst_axis_vip_if); - - src_axis_seq = new("Source AXI Stream Agent", src_axis_agent, this); - dst_axis_seq = new("Destination AXI Stream Agent", dst_axis_agent, this); + super.new(name); + this.src_axis_agent = new("Source AXI Stream Agent", src_axis_vip_if, this); + this.dst_axis_agent = new("Destination AXI Stream Agent", dst_axis_vip_if, this); endfunction //============================================================================ @@ -69,68 +38,41 @@ package environment_pkg; // - Configure the sequencer VIPs with an initial configuration before starting them //============================================================================ task configure(); - xil_axi4stream_ready_gen_policy_t dac_mode; // source stub - src_axis_seq.set_stop_policy(STOP_POLICY_PACKET); + this.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_PACKET); // destination stub dac_mode = XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE; - dst_axis_seq.set_mode(dac_mode); - + this.dst_axis_agent.sequencer.set_mode(dac_mode); endtask //============================================================================ // Start environment //============================================================================ task start(); - - super.start(); - - src_axis_agent.start_master(); - dst_axis_agent.start_slave(); - - endtask - - //============================================================================ - // Start the test - //============================================================================ - task test(); - fork - src_axis_seq.run(); - dst_axis_seq.run(); - join_none - endtask - - - //============================================================================ - // Post test subroutine - //============================================================================ - task post_test(); + this.src_axis_agent.agent.start_master(); + this.dst_axis_agent.agent.start_slave(); endtask //============================================================================ // Run subroutine //============================================================================ task run; - - //pre_test(); - test(); - + fork + this.src_axis_agent.sequencer.run(); + this.dst_axis_agent.sequencer.run(); + join_none endtask //============================================================================ // Stop subroutine //============================================================================ task stop; - - super.stop(); - src_axis_seq.stop(); - src_axis_agent.stop_master(); - dst_axis_agent.stop_slave(); - post_test(); - + this.src_axis_agent.sequencer.stop(); + this.src_axis_agent.agent.stop_master(); + this.dst_axis_agent.agent.stop_slave(); endtask endclass diff --git a/testbenches/ip/axis_sequencers/tests/test_program.sv b/testbenches/ip/axis_sequencers/tests/test_program.sv index ac02bb73..1e513528 100644 --- a/testbenches/ip/axis_sequencers/tests/test_program.sv +++ b/testbenches/ip/axis_sequencers/tests/test_program.sv @@ -37,80 +37,86 @@ // `include "utils.svh" -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; -import m_axis_sequencer_pkg::*; -import s_axis_sequencer_pkg::*; import logger_pkg::*; +import test_harness_env_pkg::*; import environment_pkg::*; import watchdog_pkg::*; +import axi4stream_vip_pkg::*; +import m_axis_sequencer_pkg::*; +import s_axis_sequencer_pkg::*; -//============================================================================= -// Register Maps -//============================================================================= +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +import `PKGIFY(test_harness, src_axis)::*; +import `PKGIFY(test_harness, dst_axis)::*; program test_program; // declare the class instances - environment env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + axis_sequencer_environment #(`AXIS_VIP_PARAMS(test_harness, src_axis), `AXIS_VIP_PARAMS(test_harness, dst_axis)) axis_seq_env; watchdog send_data_wd; initial begin // create environment - env = new("Axis Sequencers Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - `TH.`SRC_AXIS.inst.IF, - `TH.`DST_AXIS.inst.IF - ); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + axis_seq_env = new("Axis Sequencers Environment", + `TH.`SRC_AXIS.inst.IF, + `TH.`DST_AXIS.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.sys_reset(); + base_env.start(); + axis_seq_env.start(); + + base_env.sys_reset(); - env.configure(); + axis_seq_env.configure(); - env.run(); + axis_seq_env.run(); - env.src_axis_seq.set_data_beat_delay(`SRC_BEAT_DELAY); - env.src_axis_seq.set_descriptor_delay(`SRC_DESCRIPTOR_DELAY); + axis_seq_env.src_axis_agent.sequencer.set_data_beat_delay(`SRC_BEAT_DELAY); + axis_seq_env.src_axis_agent.sequencer.set_descriptor_delay(`SRC_DESCRIPTOR_DELAY); - env.dst_axis_seq.set_high_time(`DEST_BEAT_DELAY_HIGH); - env.dst_axis_seq.set_low_time(`DEST_BEAT_DELAY_LOW); + axis_seq_env.dst_axis_agent.sequencer.set_high_time(`DEST_BEAT_DELAY_HIGH); + axis_seq_env.dst_axis_agent.sequencer.set_low_time(`DEST_BEAT_DELAY_LOW); case (`DEST_BACKPRESSURE) - 1: env.dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_SINGLE); - 2: env.dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + 1: axis_seq_env.dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_SINGLE); + 2: axis_seq_env.dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); default: `FATAL(("Destination backpressure mode parameter incorrect!")); endcase case (`SRC_DESCRIPTORS) 1: begin - env.src_axis_seq.set_descriptor_gen_mode(0); - env.src_axis_seq.set_stop_policy(STOP_POLICY_DATA_BEAT); - // env.src_axis_seq.add_xfer_descriptor(32'h600, 1, 0); - env.src_axis_seq.add_xfer_descriptor_packet_size(32'd10, 1, 0); + axis_seq_env.src_axis_agent.sequencer.set_descriptor_gen_mode(0); + axis_seq_env.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_DATA_BEAT); + // axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor(32'h600, 1, 0); + axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor_packet_size(32'd10, 1, 0); send_data_wd = new("Axis Sequencer Watchdog", 1000, "Send data"); end 2: begin - env.src_axis_seq.set_descriptor_gen_mode(0); - env.src_axis_seq.set_stop_policy(STOP_POLICY_DESCRIPTOR_QUEUE); - repeat (10) env.src_axis_seq.add_xfer_descriptor(32'h600, 1, 0); + axis_seq_env.src_axis_agent.sequencer.set_descriptor_gen_mode(0); + axis_seq_env.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_DESCRIPTOR_QUEUE); + repeat (10) axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor(32'h600, 1, 0); send_data_wd = new("Axis Sequencer Watchdog", 30000, "Send data"); end 3: begin - env.src_axis_seq.set_descriptor_gen_mode(1); - env.src_axis_seq.set_stop_policy(STOP_POLICY_PACKET); - env.src_axis_seq.add_xfer_descriptor(32'h600, 1, 0); + axis_seq_env.src_axis_agent.sequencer.set_descriptor_gen_mode(1); + axis_seq_env.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_PACKET); + axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor(32'h600, 1, 0); send_data_wd = new("Axis Sequencer Watchdog", 20000, "Send data"); end @@ -119,27 +125,27 @@ program test_program; send_data_wd.start(); - env.src_axis_seq.start(); + axis_seq_env.src_axis_agent.sequencer.start(); #1step; case (`SRC_DESCRIPTORS) - 1: //env.src_axis_seq.beat_sent(); - env.src_axis_seq.packet_sent(); - 2: env.src_axis_seq.wait_empty_descriptor_queue(); + 1: //axis_seq_env.src_axis_agent.sequencer.beat_sent(); + axis_seq_env.src_axis_agent.sequencer.packet_sent(); + 2: axis_seq_env.src_axis_agent.sequencer.wait_empty_descriptor_queue(); 3: begin #10us; - env.src_axis_seq.stop(); + axis_seq_env.src_axis_agent.sequencer.stop(); - env.src_axis_seq.packet_sent(); + axis_seq_env.src_axis_agent.sequencer.packet_sent(); end default: ; endcase send_data_wd.stop(); - env.stop(); + base_env.stop(); `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/ip/dma_flock/environment.sv b/testbenches/ip/dma_flock/environment.sv index cdf0ff9d..a0f6d155 100644 --- a/testbenches/ip/dma_flock/environment.sv +++ b/testbenches/ip/dma_flock/environment.sv @@ -34,37 +34,24 @@ // *************************************************************************** `include "utils.svh" +`include "axis_definitions.svh" package environment_pkg; - import axi_vip_pkg::*; + import logger_pkg::*; + import adi_common_pkg::*; + import scoreboard_pkg::*; import axi4stream_vip_pkg::*; - import m_axi_sequencer_pkg::*; - import s_axi_sequencer_pkg::*; import m_axis_sequencer_pkg::*; import s_axis_sequencer_pkg::*; - import test_harness_env_pkg::*; - import dma_trans_pkg::*; - import `PKGIFY(test_harness, mng_axi_vip)::*; - import `PKGIFY(test_harness, ddr_axi_vip)::*; - import `PKGIFY(test_harness, src_axis_vip)::*; - import `PKGIFY(test_harness, dst_axis_vip)::*; + import adi_axis_agent_pkg::*; - class environment extends test_harness_env; + class dma_flock_environment #(int `AXIS_VIP_PARAM_ORDER(src_axis), int `AXIS_VIP_PARAM_ORDER(dst_axis)) extends adi_environment; // Agents - `AGENT(test_harness, src_axis_vip, mst_t) src_axis_agent; - `AGENT(test_harness, dst_axis_vip, slv_t) dst_axis_agent; - - // Sequencers - m_axis_sequencer #(`AGENT(test_harness, src_axis_vip, mst_t), - `AXIS_VIP_PARAMS(test_harness, src_axis_vip) - ) src_axis_seq; - s_axis_sequencer #(`AGENT(test_harness, dst_axis_vip, slv_t)) dst_axis_seq; - // Register accessors - - dma_transfer_group trans_q[$]; + adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(src_axis)) src_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAM_ORDER(dst_axis)) dst_axis_agent; scoreboard scrb; @@ -74,34 +61,16 @@ package environment_pkg; function new( input string name, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, - - virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, - - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, src_axis_vip)) src_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, dst_axis_vip)) dst_axis_vip_if - ); - super.new(name, - sys_clk_vip_if, - dma_clk_vip_if, - ddr_clk_vip_if, - sys_rst_vip_if, - mng_vip_if, - ddr_vip_if); + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(src_axis)) src_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(dst_axis)) dst_axis_vip_if); - // Creating the agents - src_axis_agent = new("Src AXI stream agent", src_axis_vip_if); - dst_axis_agent = new("Dest AXI stream agent", dst_axis_vip_if); + super.new(name); - // Creating the sequencers - src_axis_seq = new("Src AXI stream sequencer", src_axis_agent, this); - dst_axis_seq = new("Dest AXI stream sequencer", dst_axis_agent, this); + // Creating the agents + this.src_axis_agent = new("Src AXI stream agent", src_axis_vip_if, this); + this.dst_axis_agent = new("Dest AXI stream agent", dst_axis_vip_if, this); - scrb = new("Scoreboard", this); + this.scrb = new(); endfunction @@ -111,15 +80,12 @@ package environment_pkg; // - Start the agents //============================================================================ task start(); - super.start(); - scrb.connect( - src_axis_agent.monitor.item_collected_port, - dst_axis_agent.monitor.item_collected_port - ); - - src_axis_agent.start_master(); - dst_axis_agent.start_slave(); + this.scrb.connect( + this.src_axis_agent.agent.monitor.item_collected_port, + this.dst_axis_agent.agent.monitor.item_collected_port); + this.src_axis_agent.agent.start_master(); + this.dst_axis_agent.agent.start_slave(); endtask //============================================================================ @@ -128,27 +94,24 @@ package environment_pkg; // - start the sequencers //============================================================================ task test(); - super.test(); - src_axis_seq.run(); + this.src_axis_agent.sequencer.run(); // DEST AXIS does not have to run, scoreboard connects and // gathers packets from the agent - scrb.run(); - test_c_run(); + this.scrb.run(); endtask //============================================================================ // Post test subroutine //============================================================================ task post_test(); - super.post_test(); // wait until done - scrb.shutdown(); + this.scrb.shutdown(); endtask //============================================================================ // Run subroutine //============================================================================ - task run; + task run(); test(); post_test(); endtask @@ -156,10 +119,9 @@ package environment_pkg; //============================================================================ // Stop subroutine //============================================================================ - task stop; - super.stop(); - src_axis_agent.stop_master(); - dst_axis_agent.stop_slave(); + task stop(); + this.src_axis_agent.agent.stop_master(); + this.dst_axis_agent.agent.stop_slave(); endtask endclass diff --git a/testbenches/ip/dma_flock/scoreboard.sv b/testbenches/ip/dma_flock/scoreboard.sv index e728d0d0..37c3c689 100644 --- a/testbenches/ip/dma_flock/scoreboard.sv +++ b/testbenches/ip/dma_flock/scoreboard.sv @@ -120,7 +120,8 @@ package scoreboard_pkg; end end endtask : run_dst - task shutdown; + + task shutdown(); -> shutdown_event; endtask: shutdown diff --git a/testbenches/ip/dma_flock/tests/test_program.sv b/testbenches/ip/dma_flock/tests/test_program.sv index 18347e63..9d34f74e 100644 --- a/testbenches/ip/dma_flock/tests/test_program.sv +++ b/testbenches/ip/dma_flock/tests/test_program.sv @@ -35,18 +35,28 @@ `include "utils.svh" +import logger_pkg::*; import environment_pkg::*; +import test_harness_env_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; -import logger_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; import dma_trans_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +import `PKGIFY(test_harness, src_axis_vip)::*; +import `PKGIFY(test_harness, dst_axis_vip)::*; + program test_program; - environment env; + // declare the class instances + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + dma_flock_environment #(`AXIS_VIP_PARAMS(test_harness, src_axis_vip), `AXIS_VIP_PARAMS(test_harness, dst_axis_vip)) dma_flock_env; + // Register accessors dmac_api m_dmac_api; dmac_api s_dmac_api; @@ -58,32 +68,36 @@ program test_program; initial begin //creating environment - env = new("DMA Flock environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - `TH.`SRC_AXIS.inst.IF, - `TH.`DST_AXIS.inst.IF - ); - - #2ps; + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + dma_flock_env = new("DMA Flock Environment", + `TH.`SRC_AXIS.inst.IF, + `TH.`DST_AXIS.inst.IF); has_sfsync = `M_DMA_CFG_USE_EXT_SYNC; has_dfsync = `S_DMA_CFG_USE_EXT_SYNC; setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); + + base_env.start(); + dma_flock_env.start(); + start_clocks(); - env.sys_reset(); - env.run(); - m_dmac_api = new("TX_DMA_BA", env.mng, `TX_DMA_BA); + base_env.sys_reset(); + + dma_flock_env.run(); + + m_dmac_api = new("TX_DMA_BA", base_env.mng.sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA_BA", env.mng, `RX_DMA_BA); + s_dmac_api = new("RX_DMA_BA", base_env.mng.sequencer, `RX_DMA_BA); s_dmac_api.probe(); sanity_test; @@ -115,8 +129,8 @@ program test_program; .dst_clk( 50000000) ); + base_env.stop(); stop_clocks(); - env.stop(); `INFO(("Testbench done!"), ADI_VERBOSITY_NONE); $finish(); @@ -138,13 +152,13 @@ program test_program; axi_ready_gen wready_gen; // Set no backpressure from AXIS destination - env.dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); - env.dst_axis_seq.user_gen_tready(); + dma_flock_env.dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + dma_flock_env.dst_axis_agent.sequencer.user_gen_tready(); // Set no backpressure from DDR - wready_gen = env.ddr_axi_agent.wr_driver.create_ready("wready"); + wready_gen = base_env.ddr.agent.wr_driver.create_ready("wready"); wready_gen.set_ready_policy(XIL_AXI_READY_GEN_NO_BACKPRESSURE); - env.ddr_axi_agent.wr_driver.send_wready(wready_gen); + base_env.ddr.agent.wr_driver.send_wready(wready_gen); m_seg = new(m_dmac_api.p); rand_succ = m_seg.randomize() with { dst_addr == 0; @@ -160,9 +174,9 @@ program test_program; s_seg = m_seg.toSlaveSeg(); - env.src_axis_seq.set_stop_policy(m_axis_sequencer_pkg::STOP_POLICY_DESCRIPTOR_QUEUE); - env.src_axis_seq.set_data_gen_mode(m_axis_sequencer_pkg::DATA_GEN_MODE_TEST_DATA); - env.src_axis_seq.start(); + dma_flock_env.src_axis_agent.sequencer.set_stop_policy(m_axis_sequencer_pkg::STOP_POLICY_DESCRIPTOR_QUEUE); + dma_flock_env.src_axis_agent.sequencer.set_data_gen_mode(m_axis_sequencer_pkg::DATA_GEN_MODE_TEST_DATA); + dma_flock_env.src_axis_agent.sequencer.start(); m_dmac_api.set_control('b1001); m_dmac_api.set_flags('b111); @@ -191,7 +205,7 @@ program test_program; begin for (int l = 0; l < m_seg.ylength; l++) begin // update the AXIS generator command - env.src_axis_seq.add_xfer_descriptor(.bytes_to_generate(m_seg.length), + dma_flock_env.src_axis_agent.sequencer.add_xfer_descriptor(.bytes_to_generate(m_seg.length), .gen_last(1), .gen_sync(l==0)); end @@ -199,7 +213,7 @@ program test_program; // update the AXIS generator data for (int j = 0; j < m_seg.get_bytes_in_transfer; j++) begin // ADI DMA frames start from offset 0x00 - env.src_axis_seq.push_byte_for_stream(frame_count); + dma_flock_env.src_axis_agent.sequencer.push_byte_for_stream(frame_count); end end join @@ -220,7 +234,7 @@ program test_program; sync_gen_en = 0; // Stop triggers wait stop policy - env.src_axis_seq.stop(); + dma_flock_env.src_axis_agent.sequencer.stop(); // Shutdown DMACs m_dmac_api.disable_dma(); @@ -235,16 +249,16 @@ program test_program; bit [63:0] mtestWData; // Write Data bit [31:0] rdData; - env.mng.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); + base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); mtestWData = 0; repeat (10) begin - env.mng.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); - env.mng.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); + base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); mtestWData += 4; end - env.mng.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); + base_env.mng.sequencer.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); endtask diff --git a/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv b/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv index f91b0498..e0508432 100644 --- a/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv +++ b/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv @@ -35,18 +35,28 @@ `include "utils.svh" -import environment_pkg::*; -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; +import environment_pkg::*; +import test_harness_env_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; import dma_trans_pkg::*; +import axi_vip_pkg::*; +import axi4stream_vip_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +import `PKGIFY(test_harness, src_axis_vip)::*; +import `PKGIFY(test_harness, dst_axis_vip)::*; program test_program_frame_delay; - environment env; + // declare the class instances + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + dma_flock_environment #(`AXIS_VIP_PARAMS(test_harness, src_axis_vip), `AXIS_VIP_PARAMS(test_harness, dst_axis_vip)) dma_flock_env; + // Register accessors dmac_api m_dmac_api; dmac_api s_dmac_api; @@ -59,19 +69,19 @@ program test_program_frame_delay; int sync_gen_en; initial begin + //creating environment - env = new("DMA Flock environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - `TH.`SRC_AXIS.inst.IF, - `TH.`DST_AXIS.inst.IF - ); - - #2ps; + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + dma_flock_env = new("DMA Flock Environment", + `TH.`SRC_AXIS.inst.IF, + `TH.`DST_AXIS.inst.IF); has_sfsync = `M_DMA_CFG_USE_EXT_SYNC; has_dfsync = `S_DMA_CFG_USE_EXT_SYNC; @@ -79,15 +89,20 @@ program test_program_frame_delay; has_s_autorun = `S_DMA_CFG_AUTORUN; setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); + + base_env.start(); + dma_flock_env.start(); + start_clocks(); - env.sys_reset(); - env.run(); - m_dmac_api = new("TX_DMA_BA", env.mng, `TX_DMA_BA); + base_env.sys_reset(); + + dma_flock_env.run(); + + m_dmac_api = new("TX_DMA_BA", base_env.mng.sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA_BA", env.mng, `RX_DMA_BA); + s_dmac_api = new("RX_DMA_BA", base_env.mng.sequencer, `RX_DMA_BA); s_dmac_api.probe(); @@ -145,7 +160,7 @@ program test_program_frame_delay; end stop_clocks(); - env.stop(); + base_env.stop(); `INFO(("Testbench done!"), ADI_VERBOSITY_NONE); $finish(); @@ -169,13 +184,13 @@ program test_program_frame_delay; axi_ready_gen wready_gen; // Set no backpressure from AXIS destination - env.dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); - env.dst_axis_seq.user_gen_tready(); + dma_flock_env.dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + dma_flock_env.dst_axis_agent.sequencer.user_gen_tready(); // Set no backpressure from DDR - wready_gen = env.ddr_axi_agent.wr_driver.create_ready("wready"); + wready_gen = base_env.ddr.agent.wr_driver.create_ready("wready"); wready_gen.set_ready_policy(XIL_AXI_READY_GEN_NO_BACKPRESSURE); - env.ddr_axi_agent.wr_driver.send_wready(wready_gen); + base_env.ddr.agent.wr_driver.send_wready(wready_gen); m_seg = new(m_dmac_api.p); @@ -202,9 +217,9 @@ program test_program_frame_delay; s_seg = m_seg.toSlaveSeg(); - env.src_axis_seq.set_stop_policy(m_axis_sequencer_pkg::STOP_POLICY_DESCRIPTOR_QUEUE); - env.src_axis_seq.set_data_gen_mode(m_axis_sequencer_pkg::DATA_GEN_MODE_TEST_DATA); - env.src_axis_seq.start(); + dma_flock_env.src_axis_agent.sequencer.set_stop_policy(m_axis_sequencer_pkg::STOP_POLICY_DESCRIPTOR_QUEUE); + dma_flock_env.src_axis_agent.sequencer.set_data_gen_mode(m_axis_sequencer_pkg::DATA_GEN_MODE_TEST_DATA); + dma_flock_env.src_axis_agent.sequencer.start(); if (has_autorun == 0) begin m_dmac_api.set_control('b1001); @@ -238,7 +253,7 @@ program test_program_frame_delay; begin for (int l = 0; l < m_seg.ylength; l++) begin // update the AXIS generator command - env.src_axis_seq.add_xfer_descriptor(.bytes_to_generate(m_seg.length), + dma_flock_env.src_axis_agent.sequencer.add_xfer_descriptor(.bytes_to_generate(m_seg.length), .gen_last(1), .gen_sync(l==0)); end @@ -246,7 +261,7 @@ program test_program_frame_delay; // update the AXIS generator data for (int j = 0; j < m_seg.get_bytes_in_transfer; j++) begin // ADI DMA frames start from offset 0x00 - env.src_axis_seq.push_byte_for_stream(frame_count); + dma_flock_env.src_axis_agent.sequencer.push_byte_for_stream(frame_count); end end join @@ -269,7 +284,7 @@ program test_program_frame_delay; sync_gen_en = 0; // Stop triggers wait stop policy - env.src_axis_seq.stop(); + dma_flock_env.src_axis_agent.sequencer.stop(); // Shutdown DMACs if (!has_m_autorun) begin @@ -288,16 +303,16 @@ program test_program_frame_delay; bit [63:0] mtestWData; // Write Data bit [31:0] rdData; - env.mng.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); + base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); mtestWData = 0; repeat (10) begin - env.mng.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); - env.mng.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); + base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); mtestWData += 4; end - env.mng.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); + base_env.mng.sequencer.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); endtask diff --git a/testbenches/ip/dma_sg/tests/test_program_1d.sv b/testbenches/ip/dma_sg/tests/test_program_1d.sv index 12921e48..e8ef4624 100644 --- a/testbenches/ip/dma_sg/tests/test_program_1d.sv +++ b/testbenches/ip/dma_sg/tests/test_program_1d.sv @@ -37,18 +37,21 @@ // `include "utils.svh" -import test_harness_env_pkg::*; -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; +import test_harness_env_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; import dma_trans_pkg::*; +import axi_vip_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program_1d; - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + // Register accessors dmac_api m_dmac_api; dmac_api s_dmac_api; @@ -56,26 +59,24 @@ program test_program_1d; initial begin // Creating environment - env = new("DMA SG Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); - - #2ps; + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); + base_env.start(); `TH.`DEVICE_CLK.inst.IF.start_clock(); - env.sys_reset(); + base_env.sys_reset(); - m_dmac_api = new("TX_DMA", env.mng, `TX_DMA_BA); + m_dmac_api = new("TX_DMA", base_env.mng.sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA", env.mng, `RX_DMA_BA); + s_dmac_api = new("RX_DMA", base_env.mng.sequencer, `RX_DMA_BA); s_dmac_api.probe(); #1us; @@ -86,69 +87,69 @@ program test_program_1d; // Init test data with incrementing 16-bit value from 0 up to address 'h8000 for (int i=0;i<'h4000;i=i+2) begin - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(`DDR_BA+i*2,(((i+1)) << 16) | i ,'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF); end // TX BLOCK // 1st Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_0000), .flags(2'b00), .id ('h0123), .src_addr (`DDR_BA+'h0000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_0060), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_0000)), .flags(2'b00), .id ('h0123), .src_addr (xil_axi_uint'(`DDR_BA+'h0000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_0060)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 2nd Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_0030), .flags(2'b00), .id ('h4567), .src_addr (`DDR_BA+'h1000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_0090), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_0030)), .flags(2'b00), .id ('h4567), .src_addr (xil_axi_uint'(`DDR_BA+'h1000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_0090)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 3rd Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_0060), .flags(2'b00), .id ('h89AB), .src_addr (`DDR_BA+'h2000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_0030), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_0060)), .flags(2'b00), .id ('h89AB), .src_addr (xil_axi_uint'(`DDR_BA+'h2000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_0030)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 4th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_0090), .flags(2'b00), .id ('hCDEF), .src_addr (`DDR_BA+'h3000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_00C0), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_0090)), .flags(2'b00), .id ('hCDEF), .src_addr (xil_axi_uint'(`DDR_BA+'h3000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_00C0)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 5th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_00C0), .flags(2'b00), .id ('hAABB), .src_addr (`DDR_BA+'h4000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_00F0), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_00C0)), .flags(2'b00), .id ('hAABB), .src_addr (xil_axi_uint'(`DDR_BA+'h4000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_00F0)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 6th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_00F0), .flags(2'b00), .id ('hCCDD), .src_addr (`DDR_BA+'h5000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_0120), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_00F0)), .flags(2'b00), .id ('hCCDD), .src_addr (xil_axi_uint'(`DDR_BA+'h5000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_0120)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 7th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_0120), .flags(2'b00), .id ('hEEFF), .src_addr (`DDR_BA+'h6000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_0150), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_0120)), .flags(2'b00), .id ('hEEFF), .src_addr (xil_axi_uint'(`DDR_BA+'h6000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_0150)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 8th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_0150), .flags(2'b11), .id ('h1234), .src_addr (`DDR_BA+'h7000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_FFFF), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_0150)), .flags(2'b11), .id ('h1234), .src_addr (xil_axi_uint'(`DDR_BA+'h7000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_FFFF)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // RX BLOCK // 1st Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_1000), .flags(2'b00), .id ('h3210), .src_addr (0), .dest_addr(`DDR_BA+'h8000), - .next_desc_addr(`DDR_BA+'h1_1060), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_1000)), .flags(2'b00), .id ('h3210), .src_addr (0), .dest_addr(xil_axi_uint'(`DDR_BA+'h8000)), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_1060)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 2nd Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_1030), .flags(2'b00), .id ('h7654), .src_addr (0), .dest_addr(`DDR_BA+'h9000), - .next_desc_addr(`DDR_BA+'h1_1090), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_1030)), .flags(2'b00), .id ('h7654), .src_addr (0), .dest_addr(xil_axi_uint'(`DDR_BA+'h9000)), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_1090)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 3rd Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_1060), .flags(2'b00), .id ('hBA98), .src_addr (0), .dest_addr(`DDR_BA+'hA000), - .next_desc_addr(`DDR_BA+'h1_1030), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_1060)), .flags(2'b00), .id ('hBA98), .src_addr (0), .dest_addr(xil_axi_uint'(`DDR_BA+'hA000)), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_1030)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 4th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_1090), .flags(2'b11), .id ('hFEDC), .src_addr (0), .dest_addr(`DDR_BA+'hB000), - .next_desc_addr(`DDR_BA+'h1_FFFF), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_1090)), .flags(2'b11), .id ('hFEDC), .src_addr (0), .dest_addr(xil_axi_uint'(`DDR_BA+'hB000)), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_FFFF)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 5th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_10C0), .flags(2'b00), .id ('hDCDC), .src_addr (0), .dest_addr(`DDR_BA+'hC000), - .next_desc_addr(`DDR_BA+'h1_10F0), .y_len(0), .x_len('h1FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_10C0)), .flags(2'b00), .id ('hDCDC), .src_addr (0), .dest_addr(xil_axi_uint'(`DDR_BA+'hC000)), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_10F0)), .y_len(0), .x_len('h1FFF), .src_stride(0), .dst_stride(0)); // 6th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_10F0), .flags(2'b11), .id ('hFEFE), .src_addr (0), .dest_addr(`DDR_BA+'hE000), - .next_desc_addr(`DDR_BA+'h1_FFFF), .y_len(0), .x_len('h1FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_10F0)), .flags(2'b11), .id ('hFEFE), .src_addr (0), .dest_addr(xil_axi_uint'(`DDR_BA+'hE000)), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_FFFF)), .y_len(0), .x_len('h1FFF), .src_stride(0), .dst_stride(0)); do_sg_transfer( - .tx_desc_addr(`DDR_BA+'h1_0000), - .rx_desc_addr(`DDR_BA+'h1_1000) + .tx_desc_addr(xil_axi_uint'(`DDR_BA+'h1_0000)), + .rx_desc_addr(xil_axi_uint'(`DDR_BA+'h1_1000)) ); #1us; check_data( - .src_addr(`DDR_BA+'h0000), - .dest_addr(`DDR_BA+'h8000), + .src_addr(xil_axi_uint'(`DDR_BA+'h0000)), + .dest_addr(xil_axi_uint'(`DDR_BA+'h8000)), .length('h8000) ); - env.stop(); + base_env.stop(); `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); @@ -166,18 +167,18 @@ program test_program_1d; bit [31:0] src_stride, bit [31:0] dst_stride); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h00, flags, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h04, id, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h08, dest_addr, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h0C, 0, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h10, src_addr, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h14, 0, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h18, next_desc_addr, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h1C, 0, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h20, y_len, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h24, x_len, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h28, src_stride, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h2C, dst_stride, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h00, flags, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h04, id, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h08, dest_addr, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h0C, 0, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h10, src_addr, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h14, 0, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h18, next_desc_addr, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h1C, 0, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h20, y_len, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h24, x_len, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h28, src_stride, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h2C, dst_stride, 'hF); endtask : write_descriptor @@ -187,25 +188,25 @@ program test_program_1d; dma_segment m_seg, s_seg; int m_tid, s_tid; - env.mng.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr); //TX descriptor first address - env.mng.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr); //TX descriptor first address + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC `SET_DMAC_CONTROL_HWDESC(1) | `SET_DMAC_CONTROL_ENABLE(1)); - env.mng.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags - env.mng.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr); //RX descriptor first address - env.mng.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr); //RX descriptor first address + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC `SET_DMAC_CONTROL_HWDESC(1) | `SET_DMAC_CONTROL_ENABLE(1)); - env.mng.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags - env.mng.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - env.mng.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - env.mng.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr+'hC0); //RX descriptor first address - env.mng.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr+'hC0); //RX descriptor first address + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); m_dmac_api.transfer_id_get(m_tid); @@ -229,8 +230,8 @@ program test_program_1d; for (int i=0;i> 8*i; - env.sdo_src_seq.push_byte_for_stream(data[i]); + spi_env.sdo_src_seq.push_byte_for_stream(data[i]); end - env.sdo_src_seq.add_xfer_descriptor((`DATA_WIDTH/8),0,0); + spi_env.sdo_src_seq.add_xfer_descriptor((`DATA_WIDTH/8),0,0); `endif endtask @@ -277,14 +289,14 @@ bit [`DATA_DLENGTH-1:0] tx_data; task offload_spi_test(); //Configure DMA - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Configure the Offload module axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG); @@ -337,7 +349,7 @@ task offload_spi_test(); end for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin - sdi_read_data[i] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + sdi_read_data[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); if (sdi_read_data[i] != sdi_read_data_store[i]) begin `INFO(("sdi_read_data[%d]: %x; sdi_read_data_store[%d]: %x", i, sdi_read_data[i], i, sdi_read_data_store[i]), ADI_VERBOSITY_LOW); `ERROR(("Offload Read Test FAILED")); diff --git a/testbenches/ip/spi_engine/tests/test_sleep_delay.sv b/testbenches/ip/spi_engine/tests/test_sleep_delay.sv index 1206ffc2..3dee7d3e 100644 --- a/testbenches/ip/spi_engine/tests/test_sleep_delay.sv +++ b/testbenches/ip/spi_engine/tests/test_sleep_delay.sv @@ -34,18 +34,23 @@ // *************************************************************************** `include "utils.svh" +`include "axi_definitions.svh" -import axi_vip_pkg::*; +import logger_pkg::*; +import test_harness_env_pkg::*; +import spi_environment_pkg::*; import axi4stream_vip_pkg::*; import adi_regmap_pkg::*; import adi_regmap_clkgen_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; import adi_regmap_spi_engine_pkg::*; -import logger_pkg::*; -import spi_environment_pkg::*; import spi_engine_instr_pkg::*; import adi_spi_vip_pkg::*; +import axi_vip_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; //--------------------------------------------------------------------------- // SPI Engine configuration parameters @@ -64,7 +69,9 @@ program test_sleep_delay ( timeunit 1ns; timeprecision 100ps; -spi_environment env; +// declare the class instances +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; +spi_environment spi_env; // -------------------------- // Wrapper function for AXI read verify @@ -72,13 +79,13 @@ spi_environment env; task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -87,7 +94,7 @@ endtask task axi_write( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -95,7 +102,7 @@ endtask // -------------------------- task spi_receive( output [`DATA_DLENGTH:0] data); - env.spi_seq.receive_data(data); + spi_env.spi_seq.receive_data(data); endtask // -------------------------- @@ -103,14 +110,14 @@ endtask // -------------------------- task spi_send( input [`DATA_DLENGTH:0] data); - env.spi_seq.send_data(data); + spi_env.spi_seq.send_data(data); endtask // -------------------------- // Wrapper function for waiting for all SPI // -------------------------- task spi_wait_send(); - env.spi_seq.flush_send(); + spi_env.spi_seq.flush_send(); endtask // -------------------------- @@ -119,32 +126,36 @@ endtask initial begin //creating environment - env = new("SPI Engine Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `ifdef DEF_SDO_STREAMING - `TH.`SDO_SRC.inst.IF, - `endif - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - `TH.`SPI_S.inst.IF - ); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + spi_env = new("SPI Engine Environment", + `ifdef DEF_SDO_STREAMING + `TH.`SDO_SRC.inst.IF, + `endif + `TH.`SPI_S.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.configure(); - env.sys_reset(); + base_env.start(); + spi_env.start(); + + base_env.sys_reset(); + + spi_env.configure(); - env.run(); + spi_env.run(); - env.spi_seq.set_default_miso_data('h2AA55); + spi_env.spi_seq.set_default_miso_data('h2AA55); // start sdo source (will wait for data enqueued) `ifdef DEF_SDO_STREAMING - env.sdo_src_seq.start(); + spi_env.sdo_src_seq.start(); `endif sanity_test(); @@ -155,7 +166,8 @@ initial begin cs_delay_test(3,3); - env.stop(); + spi_env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); @@ -373,14 +385,14 @@ task cs_delay_test( `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); //Configure DMA - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Enable SPI Engine axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); @@ -429,7 +441,7 @@ task cs_delay_test( #2000ns for (int i=0; i<=(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS); i=i+1) begin - offload_captured_word_arr[i][`DATA_DLENGTH-1:0] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i][`DATA_DLENGTH-1:0] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); end if (irq_pending == 'h0) begin @@ -455,7 +467,7 @@ task cs_delay_test( `INFO(("CS Delay Test PASSED"), ADI_VERBOSITY_LOW); #2000ns - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(1)); axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(0)); @@ -489,7 +501,7 @@ task cs_delay_test( #2000ns for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin - offload_captured_word_arr[i][`DATA_DLENGTH-1:0] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i][`DATA_DLENGTH-1:0] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); end if (irq_pending == 'h0) begin diff --git a/testbenches/ip/util_pack/environment.sv b/testbenches/ip/util_pack/environment.sv index 5543cd5f..49686ad5 100644 --- a/testbenches/ip/util_pack/environment.sv +++ b/testbenches/ip/util_pack/environment.sv @@ -2,48 +2,25 @@ package environment_pkg; - import m_axi_sequencer_pkg::*; - import s_axi_sequencer_pkg::*; - import m_axis_sequencer_pkg::*; - import s_axis_sequencer_pkg::*; import logger_pkg::*; + import adi_common_pkg::*; - import axi_vip_pkg::*; import axi4stream_vip_pkg::*; - import test_harness_env_pkg::*; + import m_axis_sequencer_pkg::*; + import s_axis_sequencer_pkg::*; + import adi_axis_agent_pkg::*; import scoreboard_pack_pkg::*; - import x_monitor_pkg::*; - - import `PKGIFY(test_harness, mng_axi_vip)::*; - import `PKGIFY(test_harness, ddr_axi_vip)::*; - import `PKGIFY(test_harness, tx_src_axis)::*; - import `PKGIFY(test_harness, tx_dst_axis)::*; - import `PKGIFY(test_harness, rx_src_axis)::*; - import `PKGIFY(test_harness, rx_dst_axis)::*; - - class environment extends test_harness_env; + class util_pack_environment #(int `AXIS_VIP_PARAM_ORDER(tx_src_axis), int `AXIS_VIP_PARAM_ORDER(tx_dst_axis), int `AXIS_VIP_PARAM_ORDER(rx_src_axis), int `AXIS_VIP_PARAM_ORDER(rx_dst_axis)) extends adi_environment; // agents and sequencers - `AGENT(test_harness, tx_src_axis, mst_t) tx_src_axis_agent; - `AGENT(test_harness, tx_dst_axis, slv_t) tx_dst_axis_agent; - `AGENT(test_harness, rx_src_axis, mst_t) rx_src_axis_agent; - `AGENT(test_harness, rx_dst_axis, slv_t) rx_dst_axis_agent; + adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(tx_src_axis)) tx_src_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAM_ORDER(tx_dst_axis)) tx_dst_axis_agent; + adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(rx_src_axis)) rx_src_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAM_ORDER(rx_dst_axis)) rx_dst_axis_agent; - m_axis_sequencer #(`AGENT(test_harness, tx_src_axis, mst_t), - `AXIS_VIP_PARAMS(test_harness, tx_src_axis)) tx_src_axis_seq; - s_axis_sequencer #(`AGENT(test_harness, tx_dst_axis, slv_t)) tx_dst_axis_seq; - m_axis_sequencer #(`AGENT(test_harness, rx_src_axis, mst_t), - `AXIS_VIP_PARAMS(test_harness, rx_src_axis)) rx_src_axis_seq; - s_axis_sequencer #(`AGENT(test_harness, rx_dst_axis, slv_t)) rx_dst_axis_seq; - - x_axis_monitor #(`AGENT(test_harness, tx_src_axis, mst_t)) tx_src_axis_mon; - x_axis_monitor #(`AGENT(test_harness, tx_dst_axis, slv_t)) tx_dst_axis_mon; - x_axis_monitor #(`AGENT(test_harness, rx_src_axis, mst_t)) rx_src_axis_mon; - x_axis_monitor #(`AGENT(test_harness, rx_dst_axis, slv_t)) rx_dst_axis_mon; - - scoreboard_pack scoreboard_tx; - scoreboard_pack scoreboard_rx; + scoreboard_pack #(logic [7:0]) scoreboard_tx; + scoreboard_pack #(logic [7:0]) scoreboard_rx; //============================================================================ // Constructor @@ -51,48 +28,21 @@ package environment_pkg; function new ( input string name, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, - - virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, - - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, - - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, tx_src_axis)) tx_src_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, tx_dst_axis)) tx_dst_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, rx_src_axis)) rx_src_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, rx_dst_axis)) rx_dst_axis_vip_if - ); + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(tx_src_axis)) tx_src_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(tx_dst_axis)) tx_dst_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(rx_src_axis)) rx_src_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(rx_dst_axis)) rx_dst_axis_vip_if); // creating the agents - super.new(name, - sys_clk_vip_if, - dma_clk_vip_if, - ddr_clk_vip_if, - sys_rst_vip_if, - mng_vip_if, - ddr_vip_if); - - tx_src_axis_agent = new("TX Source AXI Stream Agent", tx_src_axis_vip_if); - tx_dst_axis_agent = new("TX Destination AXI Stream Agent", tx_dst_axis_vip_if); - rx_src_axis_agent = new("RX Source AXI Stream Agent", rx_src_axis_vip_if); - rx_dst_axis_agent = new("RX Destination AXI Stream Agent", rx_dst_axis_vip_if); - - tx_src_axis_seq = new("TX Source AXI Stream Agent", tx_src_axis_agent, this); - tx_dst_axis_seq = new("TX Destination AXI Stream Agent", tx_dst_axis_agent, this); - rx_src_axis_seq = new("RX Source AXI Stream Agent", rx_src_axis_agent, this); - rx_dst_axis_seq = new("RX Destination AXI Stream Agent", rx_dst_axis_agent, this); - - tx_src_axis_mon = new("TX Source AXIS Transaction Monitor", tx_src_axis_agent, this); - tx_dst_axis_mon = new("TX Destination AXIS Transaction Monitor", tx_dst_axis_agent, this); - rx_src_axis_mon = new("RX Source AXIS Transaction Monitor", rx_src_axis_agent, this); - rx_dst_axis_mon = new("RX Destination AXIS Transaction Monitor", rx_dst_axis_agent, this); - - scoreboard_tx = new("TX Scoreboard", `CHANNELS, `SAMPLES, `WIDTH, CPACK, this); - scoreboard_rx = new("RX Scoreboard", `CHANNELS, `SAMPLES, `WIDTH, UPACK, this); + super.new(name); + + this.tx_src_axis_agent = new("TX Source AXI Stream Agent", tx_src_axis_vip_if, this); + this.tx_dst_axis_agent = new("TX Destination AXI Stream Agent", tx_dst_axis_vip_if, this); + this.rx_src_axis_agent = new("RX Source AXI Stream Agent", rx_src_axis_vip_if, this); + this.rx_dst_axis_agent = new("RX Destination AXI Stream Agent", rx_dst_axis_vip_if, this); + this.scoreboard_tx = new("TX Scoreboard", `CHANNELS, `SAMPLES, `WIDTH, CPACK, this); + this.scoreboard_rx = new("RX Scoreboard", `CHANNELS, `SAMPLES, `WIDTH, UPACK, this); endfunction //============================================================================ @@ -100,19 +50,17 @@ package environment_pkg; // - Configure the sequencer VIPs with an initial configuration before starting them //============================================================================ task configure(int bytes_to_generate); - // TX stubs - tx_src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - tx_src_axis_seq.add_xfer_descriptor(bytes_to_generate, 0, 0); + this.tx_src_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); + this.tx_src_axis_agent.sequencer.add_xfer_descriptor(bytes_to_generate, 0, 0); - tx_dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + this.tx_dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); // RX stub - rx_src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - rx_src_axis_seq.add_xfer_descriptor(bytes_to_generate, 0, 0); - - rx_dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + this.rx_src_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); + this.rx_src_axis_agent.sequencer.add_xfer_descriptor(bytes_to_generate, 0, 0); + this.rx_dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); endtask //============================================================================ @@ -121,83 +69,44 @@ package environment_pkg; // - Start the agents //============================================================================ task start(); + this.tx_src_axis_agent.agent.start_master(); + this.tx_dst_axis_agent.agent.start_slave(); + this.rx_src_axis_agent.agent.start_master(); + this.rx_dst_axis_agent.agent.start_slave(); - super.start(); - - tx_src_axis_agent.start_master(); - tx_dst_axis_agent.start_slave(); - rx_src_axis_agent.start_master(); - rx_dst_axis_agent.start_slave(); - - scoreboard_tx.set_source_stream(tx_src_axis_mon); - scoreboard_tx.set_sink_stream(tx_dst_axis_mon); - - scoreboard_rx.set_source_stream(rx_src_axis_mon); - scoreboard_rx.set_sink_stream(rx_dst_axis_mon); - - endtask - - //============================================================================ - // Start the test - // - start the RX scoreboard and sequencer - // - start the TX scoreboard and sequencer - // - setup the RX DMA - // - setup the TX DMA - //============================================================================ - task test(); - - fork - tx_src_axis_seq.run(); - tx_dst_axis_seq.run(); - rx_src_axis_seq.run(); - rx_dst_axis_seq.run(); - - tx_src_axis_mon.run(); - tx_dst_axis_mon.run(); - rx_src_axis_mon.run(); - rx_dst_axis_mon.run(); - - scoreboard_tx.run(); - scoreboard_rx.run(); - join_none + this.tx_src_axis_agent.monitor.publisher.subscribe(this.scoreboard_tx.subscriber_source); + this.tx_dst_axis_agent.monitor.publisher.subscribe(this.scoreboard_tx.subscriber_sink); - endtask - - - //============================================================================ - // Post test subroutine - //============================================================================ - task post_test(); - // Evaluate the scoreboard's results + this.rx_src_axis_agent.monitor.publisher.subscribe(this.scoreboard_rx.subscriber_source); + this.rx_dst_axis_agent.monitor.publisher.subscribe(this.scoreboard_rx.subscriber_sink); endtask //============================================================================ // Run subroutine //============================================================================ - task run; - - //pre_test(); - test(); + task run(); + fork + this.tx_src_axis_agent.sequencer.run(); + this.tx_dst_axis_agent.sequencer.run(); + this.rx_src_axis_agent.sequencer.run(); + this.rx_dst_axis_agent.sequencer.run(); + this.scoreboard_tx.run(); + this.scoreboard_rx.run(); + join_none endtask //============================================================================ // Stop subroutine //============================================================================ - task stop; - - super.stop(); - - tx_src_axis_seq.stop(); - rx_src_axis_seq.stop(); - - tx_src_axis_agent.stop_master(); - tx_dst_axis_agent.stop_slave(); - rx_src_axis_agent.stop_master(); - rx_dst_axis_agent.stop_slave(); - - post_test(); - + task stop(); + this.tx_src_axis_agent.sequencer.stop(); + this.rx_src_axis_agent.sequencer.stop(); + + this.tx_src_axis_agent.agent.stop_master(); + this.tx_dst_axis_agent.agent.stop_slave(); + this.rx_src_axis_agent.agent.stop_master(); + this.rx_dst_axis_agent.agent.stop_slave(); endtask endclass diff --git a/testbenches/ip/util_pack/tests/test_program.sv b/testbenches/ip/util_pack/tests/test_program.sv index 8562e7e9..9e2ae2af 100644 --- a/testbenches/ip/util_pack/tests/test_program.sv +++ b/testbenches/ip/util_pack/tests/test_program.sv @@ -36,18 +36,28 @@ // // `include "utils.svh" +`include "axi_definitions.svh" +`include "axis_definitions.svh" -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; +import test_harness_env_pkg::*; import environment_pkg::*; import dmac_api_pkg::*; import watchdog_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +import `PKGIFY(test_harness, tx_src_axis)::*; +import `PKGIFY(test_harness, tx_dst_axis)::*; +import `PKGIFY(test_harness, rx_src_axis)::*; +import `PKGIFY(test_harness, rx_dst_axis)::*; + program test_program; // declare the class instances - environment env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + util_pack_environment #(`AXIS_VIP_PARAMS(test_harness, tx_src_axis), `AXIS_VIP_PARAMS(test_harness, tx_dst_axis), `AXIS_VIP_PARAMS(test_harness, rx_src_axis), `AXIS_VIP_PARAMS(test_harness, rx_dst_axis)) pack_env; watchdog packer_scoreboard_wd; @@ -61,35 +71,37 @@ program test_program; setLoggerVerbosity(ADI_VERBOSITY_NONE); // create environment - env = new("Util Pack Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - - `TH.`TX_SRC_AXIS.inst.IF, - `TH.`TX_DST_AXIS.inst.IF, - `TH.`RX_SRC_AXIS.inst.IF, - `TH.`RX_DST_AXIS.inst.IF - ); - - dmac_tx = new("DMAC TX 0", env.mng, `TX_DMA_BA); - dmac_rx = new("DMAC RX 0", env.mng, `RX_DMA_BA); - - env.start(); - env.sys_reset(); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + pack_env = new("Util Pack Environment", + `TH.`TX_SRC_AXIS.inst.IF, + `TH.`TX_DST_AXIS.inst.IF, + `TH.`RX_SRC_AXIS.inst.IF, + `TH.`RX_DST_AXIS.inst.IF); + + dmac_tx = new("DMAC TX 0", base_env.mng.sequencer, `TX_DMA_BA); + dmac_rx = new("DMAC RX 0", base_env.mng.sequencer, `RX_DMA_BA); + + base_env.start(); + pack_env.start(); + + base_env.sys_reset(); // configure environment sequencers - env.configure(data_length); + pack_env.configure(data_length); `INFO(("Bring up IPs from reset."), ADI_VERBOSITY_LOW); systemBringUp(); // Start the ADC/DAC stubs `INFO(("Call the run() ..."), ADI_VERBOSITY_LOW); - env.run(); + pack_env.run(); // Generate DMA transfers `INFO(("Start DMAs"), ADI_VERBOSITY_LOW); @@ -97,8 +109,8 @@ program test_program; tx_dma_transfer(data_length); // start generating data - env.tx_src_axis_seq.start(); - env.rx_src_axis_seq.start(); + pack_env.tx_src_axis_agent.sequencer.start(); + pack_env.rx_src_axis_agent.sequencer.start(); // prepare watchdog with 20 us of wait time packer_scoreboard_wd = new("Packer watchdog", 20000, "Packers Scoreboard"); @@ -108,13 +120,14 @@ program test_program; // wait for scoreboards to finish fork - env.scoreboard_rx.wait_until_complete(); - env.scoreboard_tx.wait_until_complete(); + pack_env.scoreboard_rx.wait_until_complete(); + pack_env.scoreboard_tx.wait_until_complete(); join packer_scoreboard_wd.stop(); - env.stop(); + pack_env.stop(); + base_env.stop(); `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); @@ -122,12 +135,10 @@ program test_program; end task systemBringUp(); - `INFO(("Bring up RX DMAC 0"), ADI_VERBOSITY_LOW); dmac_rx.enable_dma(); `INFO(("Bring up TX DMAC 0"), ADI_VERBOSITY_LOW); dmac_tx.enable_dma(); - endtask // RX DMA transfer generator From 29b887383293b19669a39d62d20ba55e43eaf180 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 20 Jan 2025 09:36:17 +0200 Subject: [PATCH 08/37] infrastructure refactorization: IP level updates - Fixed SPI engine environment - Updated environment creation and macros Signed-off-by: Istvan-Zsolt Szekely --- library/vip/amd/axi/axi_definitions.svh | 67 +++++++++++++------ library/vip/amd/axi/m_axi_sequencer.sv | 6 +- library/vip/amd/axi/s_axi_sequencer.sv | 6 +- library/vip/amd/axis/adi_axis_agent.sv | 6 +- library/vip/amd/axis/adi_axis_monitor.sv | 6 +- library/vip/amd/axis/axis_definitions.svh | 42 ++++++------ library/vip/amd/axis/m_axis_sequencer.sv | 2 +- library/vip/amd/axis/s_axis_sequencer.sv | 2 +- testbenches/ip/axis_sequencers/environment.sv | 2 +- testbenches/ip/dma_flock/environment.sv | 2 +- testbenches/ip/scoreboard/environment.sv | 2 +- testbenches/ip/spi_engine/spi_environment.sv | 30 ++++----- testbenches/ip/util_pack/environment.sv | 2 +- 13 files changed, 98 insertions(+), 77 deletions(-) diff --git a/library/vip/amd/axi/axi_definitions.svh b/library/vip/amd/axi/axi_definitions.svh index 98576d16..93f026e5 100644 --- a/library/vip/amd/axi/axi_definitions.svh +++ b/library/vip/amd/axi/axi_definitions.svh @@ -40,28 +40,28 @@ `define _AXI_DEFINITIONS_SVH_ // Help build VIP Interface parameters name -`define AXI_VIP_IF_PARAMS(n) n``_VIP_PROTOCOL,\ - n``_VIP_ADDR_WIDTH,\ - n``_VIP_WDATA_WIDTH,\ - n``_VIP_RDATA_WIDTH,\ - n``_VIP_WID_WIDTH,\ - n``_VIP_RID_WIDTH,\ - n``_VIP_AWUSER_WIDTH,\ - n``_VIP_WUSER_WIDTH,\ - n``_VIP_BUSER_WIDTH,\ - n``_VIP_ARUSER_WIDTH,\ - n``_VIP_RUSER_WIDTH,\ - n``_VIP_SUPPORTS_NARROW,\ - n``_VIP_HAS_BURST,\ - n``_VIP_HAS_LOCK,\ - n``_VIP_HAS_CACHE,\ - n``_VIP_HAS_REGION,\ - n``_VIP_HAS_PROT,\ - n``_VIP_HAS_QOS,\ - n``_VIP_HAS_WSTRB,\ - n``_VIP_HAS_BRESP,\ - n``_VIP_HAS_RRESP,\ - n``_VIP_HAS_ARESETN +`define AXI_VIP_PARAM_DECL(n) int n``_VIP_PROTOCOL,\ + n``_VIP_ADDR_WIDTH,\ + n``_VIP_WDATA_WIDTH,\ + n``_VIP_RDATA_WIDTH,\ + n``_VIP_WID_WIDTH,\ + n``_VIP_RID_WIDTH,\ + n``_VIP_AWUSER_WIDTH,\ + n``_VIP_WUSER_WIDTH,\ + n``_VIP_BUSER_WIDTH,\ + n``_VIP_ARUSER_WIDTH,\ + n``_VIP_RUSER_WIDTH,\ + n``_VIP_SUPPORTS_NARROW,\ + n``_VIP_HAS_BURST,\ + n``_VIP_HAS_LOCK,\ + n``_VIP_HAS_CACHE,\ + n``_VIP_HAS_REGION,\ + n``_VIP_HAS_PROT,\ + n``_VIP_HAS_QOS,\ + n``_VIP_HAS_WSTRB,\ + n``_VIP_HAS_BRESP,\ + n``_VIP_HAS_RRESP,\ + n``_VIP_HAS_ARESETN `define AXI_VIP_PARAM_ORDER(n) n``_VIP_PROTOCOL,\ n``_VIP_ADDR_WIDTH,\ @@ -85,6 +85,29 @@ n``_VIP_HAS_BRESP,\ n``_VIP_HAS_RRESP,\ n``_VIP_HAS_ARESETN + +`define AXI_VIP_IF_PARAMS(n) n``_VIP_PROTOCOL,\ + n``_VIP_ADDR_WIDTH,\ + n``_VIP_WDATA_WIDTH,\ + n``_VIP_RDATA_WIDTH,\ + n``_VIP_WID_WIDTH,\ + n``_VIP_RID_WIDTH,\ + n``_VIP_AWUSER_WIDTH,\ + n``_VIP_WUSER_WIDTH,\ + n``_VIP_BUSER_WIDTH,\ + n``_VIP_ARUSER_WIDTH,\ + n``_VIP_RUSER_WIDTH,\ + n``_VIP_SUPPORTS_NARROW,\ + n``_VIP_HAS_BURST,\ + n``_VIP_HAS_LOCK,\ + n``_VIP_HAS_CACHE,\ + n``_VIP_HAS_REGION,\ + n``_VIP_HAS_PROT,\ + n``_VIP_HAS_QOS,\ + n``_VIP_HAS_WSTRB,\ + n``_VIP_HAS_BRESP,\ + n``_VIP_HAS_RRESP,\ + n``_VIP_HAS_ARESETN `define AXI_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_PROTOCOL,\ th``_``vip``_0_VIP_ADDR_WIDTH,\ diff --git a/library/vip/amd/axi/m_axi_sequencer.sv b/library/vip/amd/axi/m_axi_sequencer.sv index c786d5ee..f6db767e 100644 --- a/library/vip/amd/axi/m_axi_sequencer.sv +++ b/library/vip/amd/axi/m_axi_sequencer.sv @@ -43,16 +43,16 @@ package m_axi_sequencer_pkg; import adi_common_pkg::*; import reg_accessor_pkg::*; - class m_axi_sequencer #(int `AXI_VIP_PARAM_ORDER(m)) extends reg_accessor; + class m_axi_sequencer #(`AXI_VIP_PARAM_DECL(AXI)) extends reg_accessor; - axi_mst_agent #(`AXI_VIP_PARAM_ORDER(m)) agent; + axi_mst_agent #(`AXI_VIP_PARAM_ORDER(AXI)) agent; semaphore reader_s; semaphore writer_s; function new( input string name, - input axi_mst_agent #(`AXI_VIP_PARAM_ORDER(m)) agent, + input axi_mst_agent #(`AXI_VIP_PARAM_ORDER(AXI)) agent, input adi_agent parent = null); super.new(name, parent); diff --git a/library/vip/amd/axi/s_axi_sequencer.sv b/library/vip/amd/axi/s_axi_sequencer.sv index c09f2f5d..1e1ab9e3 100644 --- a/library/vip/amd/axi/s_axi_sequencer.sv +++ b/library/vip/amd/axi/s_axi_sequencer.sv @@ -42,13 +42,13 @@ package s_axi_sequencer_pkg; import adi_common_pkg::*; import logger_pkg::*; - class s_axi_sequencer #(int `AXI_VIP_PARAM_ORDER(s)) extends adi_component; + class s_axi_sequencer #(`AXI_VIP_PARAM_DECL(AXI)) extends adi_component; - xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(s)) mem_model; + xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(AXI)) mem_model; function new( input string name, - input xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(s)) mem_model, + input xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(AXI)) mem_model, input adi_agent parent = null); super.new(name, parent); diff --git a/library/vip/amd/axis/adi_axis_agent.sv b/library/vip/amd/axis/adi_axis_agent.sv index 392b79e5..621ff43f 100644 --- a/library/vip/amd/axis/adi_axis_agent.sv +++ b/library/vip/amd/axis/adi_axis_agent.sv @@ -46,7 +46,7 @@ package adi_axis_agent_pkg; import adi_axis_monitor_pkg::*; - class adi_axis_master_agent #(int `AXIS_VIP_PARAM_ORDER(master)) extends adi_agent; + class adi_axis_master_agent #(`AXIS_VIP_PARAM_DECL(master)) extends adi_agent; axi4stream_mst_agent #(`AXIS_VIP_IF_PARAMS(master)) agent; m_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(master)) sequencer; @@ -67,7 +67,7 @@ package adi_axis_agent_pkg; endclass: adi_axis_master_agent - class adi_axis_slave_agent #(int `AXIS_VIP_PARAM_ORDER(slave)) extends adi_agent; + class adi_axis_slave_agent #(`AXIS_VIP_PARAM_DECL(slave)) extends adi_agent; axi4stream_slv_agent #(`AXIS_VIP_IF_PARAMS(slave)) agent; s_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(slave)) sequencer; @@ -88,7 +88,7 @@ package adi_axis_agent_pkg; endclass: adi_axis_slave_agent - class adi_axis_passthrough_mem_agent #(int `AXIS_VIP_PARAM_ORDER(passthrough)) extends adi_agent; + class adi_axis_passthrough_mem_agent #(`AXIS_VIP_PARAM_DECL(passthrough)) extends adi_agent; axi4stream_passthrough_agent #(`AXIS_VIP_IF_PARAMS(passthrough)) agent; adi_axis_monitor #(`AXIS_VIP_PARAM_ORDER(passthrough)) monitor; diff --git a/library/vip/amd/axis/adi_axis_monitor.sv b/library/vip/amd/axis/adi_axis_monitor.sv index b13849cb..e2a4ba55 100644 --- a/library/vip/amd/axis/adi_axis_monitor.sv +++ b/library/vip/amd/axis/adi_axis_monitor.sv @@ -7,10 +7,10 @@ package adi_axis_monitor_pkg; import adi_common_pkg::*; import pub_sub_pkg::*; - class adi_axis_monitor #(int `AXIS_VIP_PARAM_ORDER(axis)) extends adi_monitor; + class adi_axis_monitor #(`AXIS_VIP_PARAM_DECL(AXIS)) extends adi_monitor; // analysis port from the monitor - protected axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(axis)) monitor; + protected axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(AXIS)) monitor; adi_publisher #(logic [7:0]) publisher; @@ -19,7 +19,7 @@ package adi_axis_monitor_pkg; // constructor function new( input string name, - input axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(axis)) monitor, + input axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(AXIS)) monitor, input adi_agent parent = null); super.new(name, parent); diff --git a/library/vip/amd/axis/axis_definitions.svh b/library/vip/amd/axis/axis_definitions.svh index 1db18ff1..ed98435c 100644 --- a/library/vip/amd/axis/axis_definitions.svh +++ b/library/vip/amd/axis/axis_definitions.svh @@ -40,19 +40,19 @@ `define _AXIS_DEFINITIONS_SVH_ // Help build VIP Interface parameters name -`define AXIS_VIP_PARAM_DECL AXIS_VIP_INTERFACE_MODE = 2,\ - AXIS_VIP_SIGNAL_SET = 8'b00000011,\ - AXIS_VIP_DATA_WIDTH = 8,\ - AXIS_VIP_ID_WIDTH = 0,\ - AXIS_VIP_DEST_WIDTH = 0,\ - AXIS_VIP_USER_WIDTH = 0,\ - AXIS_VIP_USER_BITS_PER_BYTE = 0,\ - AXIS_VIP_HAS_TREADY = 1,\ - AXIS_VIP_HAS_TSTRB = 0,\ - AXIS_VIP_HAS_TKEEP = 0,\ - AXIS_VIP_HAS_TLAST = 0,\ - AXIS_VIP_HAS_ACLKEN = 0,\ - AXIS_VIP_HAS_ARESETN = 1 +`define AXIS_VIP_PARAM_DECL(n) int n``_VIP_INTERFACE_MODE, \ + n``_VIP_SIGNAL_SET, \ + n``_VIP_DATA_WIDTH, \ + n``_VIP_ID_WIDTH, \ + n``_VIP_DEST_WIDTH, \ + n``_VIP_USER_WIDTH, \ + n``_VIP_USER_BITS_PER_BYTE, \ + n``_VIP_HAS_TREADY, \ + n``_VIP_HAS_TSTRB, \ + n``_VIP_HAS_TKEEP, \ + n``_VIP_HAS_TLAST, \ + n``_VIP_HAS_ACLKEN, \ + n``_VIP_HAS_ARESETN `define AXIS_VIP_PARAM_ORDER(n) n``_VIP_INTERFACE_MODE,\ n``_VIP_SIGNAL_SET,\ @@ -68,6 +68,14 @@ n``_VIP_HAS_ACLKEN,\ n``_VIP_HAS_ARESETN +`define AXIS_VIP_IF_PARAMS(n) n``_VIP_SIGNAL_SET,\ + n``_VIP_DEST_WIDTH,\ + n``_VIP_DATA_WIDTH,\ + n``_VIP_ID_WIDTH,\ + n``_VIP_USER_WIDTH,\ + n``_VIP_USER_BITS_PER_BYTE,\ + n``_VIP_HAS_ARESETN + `define AXIS_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_INTERFACE_MODE,\ th``_``vip``_0_VIP_SIGNAL_SET,\ th``_``vip``_0_VIP_DATA_WIDTH,\ @@ -82,12 +90,4 @@ th``_``vip``_0_VIP_HAS_ACLKEN,\ th``_``vip``_0_VIP_HAS_ARESETN -`define AXIS_VIP_IF_PARAMS(n) n``_VIP_SIGNAL_SET,\ - n``_VIP_DEST_WIDTH,\ - n``_VIP_DATA_WIDTH,\ - n``_VIP_ID_WIDTH,\ - n``_VIP_USER_WIDTH,\ - n``_VIP_USER_BITS_PER_BYTE,\ - n``_VIP_HAS_ARESETN - `endif diff --git a/library/vip/amd/axis/m_axis_sequencer.sv b/library/vip/amd/axis/m_axis_sequencer.sv index 8bf3c429..8a3155ef 100644 --- a/library/vip/amd/axis/m_axis_sequencer.sv +++ b/library/vip/amd/axis/m_axis_sequencer.sv @@ -312,7 +312,7 @@ package m_axis_sequencer_pkg; endclass: m_axis_sequencer_base - class m_axis_sequencer #(int `AXIS_VIP_PARAM_ORDER(AXIS)) extends m_axis_sequencer_base; + class m_axis_sequencer #(`AXIS_VIP_PARAM_DECL(AXIS)) extends m_axis_sequencer_base; protected axi4stream_mst_driver #(`AXIS_VIP_IF_PARAMS(AXIS)) driver; diff --git a/library/vip/amd/axis/s_axis_sequencer.sv b/library/vip/amd/axis/s_axis_sequencer.sv index 26e229b7..6f566641 100644 --- a/library/vip/amd/axis/s_axis_sequencer.sv +++ b/library/vip/amd/axis/s_axis_sequencer.sv @@ -158,7 +158,7 @@ package s_axis_sequencer_pkg; endclass: s_axis_sequencer_base - class s_axis_sequencer #(int `AXIS_VIP_PARAM_ORDER(AXIS)) extends s_axis_sequencer_base; + class s_axis_sequencer #(`AXIS_VIP_PARAM_DECL(AXIS)) extends s_axis_sequencer_base; protected axi4stream_slv_driver #(`AXIS_VIP_IF_PARAMS(AXIS)) driver; diff --git a/testbenches/ip/axis_sequencers/environment.sv b/testbenches/ip/axis_sequencers/environment.sv index 423e8b63..4007dcc4 100644 --- a/testbenches/ip/axis_sequencers/environment.sv +++ b/testbenches/ip/axis_sequencers/environment.sv @@ -11,7 +11,7 @@ package environment_pkg; import s_axis_sequencer_pkg::*; import adi_axis_agent_pkg::*; - class axis_sequencer_environment #(int `AXIS_VIP_PARAM_ORDER(src_axis), int `AXIS_VIP_PARAM_ORDER(dst_axis)) extends adi_environment; + class axis_sequencer_environment #(`AXIS_VIP_PARAM_DECL(src_axis), `AXIS_VIP_PARAM_DECL(dst_axis)) extends adi_environment; // Agents adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(src_axis)) src_axis_agent; diff --git a/testbenches/ip/dma_flock/environment.sv b/testbenches/ip/dma_flock/environment.sv index a0f6d155..cac44346 100644 --- a/testbenches/ip/dma_flock/environment.sv +++ b/testbenches/ip/dma_flock/environment.sv @@ -47,7 +47,7 @@ package environment_pkg; import s_axis_sequencer_pkg::*; import adi_axis_agent_pkg::*; - class dma_flock_environment #(int `AXIS_VIP_PARAM_ORDER(src_axis), int `AXIS_VIP_PARAM_ORDER(dst_axis)) extends adi_environment; + class dma_flock_environment #(`AXIS_VIP_PARAM_DECL(src_axis), `AXIS_VIP_PARAM_DECL(dst_axis)) extends adi_environment; // Agents adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(src_axis)) src_axis_agent; diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv index 515d5b1d..8efbe384 100644 --- a/testbenches/ip/scoreboard/environment.sv +++ b/testbenches/ip/scoreboard/environment.sv @@ -18,7 +18,7 @@ package environment_pkg; import scoreboard_pkg::*; - class scoreboard_environment #(int `AXIS_VIP_PARAM_ORDER(adc_src), int `AXIS_VIP_PARAM_ORDER(dac_dst), int `AXI_VIP_PARAM_ORDER(adc_dst_pt), int `AXI_VIP_PARAM_ORDER(dac_src_pt)) extends adi_environment; + class scoreboard_environment #(`AXIS_VIP_PARAM_DECL(adc_src), `AXIS_VIP_PARAM_DECL(dac_dst), `AXIS_VIP_PARAM_DECL(adc_dst_pt), `AXIS_VIP_PARAM_DECL(dac_src_pt)) extends adi_environment; // Agents adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(adc_src)) adc_src_axis_agent; diff --git a/testbenches/ip/spi_engine/spi_environment.sv b/testbenches/ip/spi_engine/spi_environment.sv index e93a3c99..76f17bd3 100644 --- a/testbenches/ip/spi_engine/spi_environment.sv +++ b/testbenches/ip/spi_engine/spi_environment.sv @@ -62,9 +62,7 @@ package spi_environment_pkg; // Sequencers s_spi_sequencer #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_seq; `ifdef DEF_SDO_STREAMING - m_axis_sequencer #(`AGENT(test_harness, sdo_src, mst_t), - `AXIS_VIP_PARAMS(test_harness, sdo_src) - ) sdo_src_seq; + m_axis_sequencer #(`AXIS_VIP_PARAMS(test_harness, sdo_src)) sdo_src_seq; `endif //============================================================================ @@ -74,22 +72,22 @@ package spi_environment_pkg; input string name, `ifdef DEF_SDO_STREAMING - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, sdo_src)) sdo_src_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness_sdo_src_0)) sdo_src_axis_vip_if, `endif virtual interface spi_vip_if #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_s_vip_if); super.new(name); // Creating the agents - spi_agent = new("SPI VIP Agent", spi_s_vip_if, this); + this.spi_agent = new("SPI VIP Agent", spi_s_vip_if, this); `ifdef DEF_SDO_STREAMING - sdo_src_agent = new("SDO Source AXI Stream Agent", sdo_src_axis_vip_if); + this.sdo_src_agent = new("SDO Source AXI Stream Agent", sdo_src_axis_vip_if); `endif // Creating the sequencers - spi_seq = new("SPI VIP Agent", spi_agent, this); + this.spi_seq = new("SPI VIP Agent", this.spi_agent, this); `ifdef DEF_SDO_STREAMING - sdo_src_seq = new("SPI VIP Agent", sdo_src_agent, this); + this.sdo_src_seq = new("SDO Source AXI Stream Sequencer", this.sdo_src_agent.driver); `endif // downgrade reset check: we are currently using a clock generator for the SPI clock, @@ -106,8 +104,8 @@ package spi_environment_pkg; //============================================================================ task configure(); `ifdef DEF_SDO_STREAMING - sdo_src_seq.set_stop_policy(STOP_POLICY_PACKET); - sdo_src_seq.set_data_gen_mode(DATA_GEN_MODE_TEST_DATA); + this.sdo_src_seq.set_stop_policy(STOP_POLICY_PACKET); + this.sdo_src_seq.set_data_gen_mode(DATA_GEN_MODE_TEST_DATA); `endif endtask @@ -117,9 +115,9 @@ package spi_environment_pkg; // - Start the agents //============================================================================ task start(); - spi_agent.start(); + this.spi_agent.start(); `ifdef DEF_SDO_STREAMING - sdo_src_agent.start_master(); + this.sdo_src_agent.start_master(); `endif endtask @@ -131,7 +129,7 @@ package spi_environment_pkg; task test(); fork `ifdef DEF_SDO_STREAMING - sdo_src_seq.run(); + this.sdo_src_seq.run(); `endif join_none endtask @@ -153,10 +151,10 @@ package spi_environment_pkg; // Stop subroutine //============================================================================ task stop(); - spi_agent.stop(); + this.spi_agent.stop(); `ifdef DEF_SDO_STREAMING - sdo_src_seq.stop(); - sdo_src_agent.stop_master(); + this.sdo_src_seq.stop(); + this.sdo_src_agent.stop_master(); `endif endtask diff --git a/testbenches/ip/util_pack/environment.sv b/testbenches/ip/util_pack/environment.sv index 49686ad5..41cdd55e 100644 --- a/testbenches/ip/util_pack/environment.sv +++ b/testbenches/ip/util_pack/environment.sv @@ -11,7 +11,7 @@ package environment_pkg; import adi_axis_agent_pkg::*; import scoreboard_pack_pkg::*; - class util_pack_environment #(int `AXIS_VIP_PARAM_ORDER(tx_src_axis), int `AXIS_VIP_PARAM_ORDER(tx_dst_axis), int `AXIS_VIP_PARAM_ORDER(rx_src_axis), int `AXIS_VIP_PARAM_ORDER(rx_dst_axis)) extends adi_environment; + class util_pack_environment #(`AXIS_VIP_PARAM_DECL(tx_src_axis), `AXIS_VIP_PARAM_DECL(tx_dst_axis), `AXIS_VIP_PARAM_DECL(rx_src_axis), `AXIS_VIP_PARAM_DECL(rx_dst_axis)) extends adi_environment; // agents and sequencers adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(tx_src_axis)) tx_src_axis_agent; From 53c1327f968722a6f4cb49920f7e581c6d6c2868 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 20 Jan 2025 10:54:41 +0200 Subject: [PATCH 09/37] infrastructure refactorization: Updated Project level testbenches Signed-off-by: Istvan-Zsolt Szekely --- .../project/ad463x/tests/test_program.sv | 49 +++-- .../project/ad57xx/ad57xx_environment.sv | 66 +------ .../project/ad57xx/tests/test_program.sv | 66 ++++--- .../project/ad738x/tests/test_program.sv | 49 +++-- .../project/ad7606x/tests/test_program_4ch.sv | 37 ++-- .../project/ad7606x/tests/test_program_6ch.sv | 35 ++-- .../project/ad7606x/tests/test_program_8ch.sv | 35 ++-- .../project/ad7606x/tests/test_program_si.sv | 45 ++--- .../project/ad7616/tests/test_program_pi.sv | 49 +++-- .../project/ad7616/tests/test_program_si.sv | 49 +++-- .../project/ad9083/tests/test_program.sv | 178 +++++++++--------- .../ad_quadmxfe1_ebz/tests/test_dma.sv | 110 +++++------ .../ad_quadmxfe1_ebz/tests/test_program.sv | 138 +++++++------- .../tests/test_program_64b66b.sv | 166 ++++++++-------- .../project/adrv9001/tests/test_program.sv | 101 +++++----- .../project/adrv9009/tests/test_program.sv | 138 +++++++------- .../project/fmcomms2/tests/test_program.sv | 42 ++--- .../project/mxfe/tests/test_program.sv | 172 ++++++++--------- .../project/pluto/tests/test_program.sv | 42 +++-- .../pulsar_adc_pmdz/tests/test_program.sv | 49 +++-- 20 files changed, 798 insertions(+), 818 deletions(-) diff --git a/testbenches/project/ad463x/tests/test_program.sv b/testbenches/project/ad463x/tests/test_program.sv index ab354508..5582ae6a 100644 --- a/testbenches/project/ad463x/tests/test_program.sv +++ b/testbenches/project/ad463x/tests/test_program.sv @@ -47,6 +47,9 @@ import adi_regmap_spi_engine_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + //--------------------------------------------------------------------------- // SPI Engine configuration parameters //--------------------------------------------------------------------------- @@ -98,7 +101,7 @@ program test_program ( input ad463x_spi_clk, input [(`NUM_OF_SDI - 1):0] ad463x_spi_sdi); -test_harness_env env; +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verify @@ -107,14 +110,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -124,7 +127,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -133,7 +136,7 @@ endtask initial begin //creating environment - env = new("AD463X Environment", + base_env = new("AD463X Environment", `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, @@ -142,13 +145,9 @@ initial begin `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - #100 + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -160,10 +159,10 @@ initial begin offload_spi_test(); - env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -254,7 +253,7 @@ bit [31:0] sdi_preg[$]; bit [31:0] sdi_nreg[$]; initial begin - while(1) begin + forever begin @(posedge ad463x_spi_clk); m_spi_csn_int_d <= m_spi_csn_int_s; end @@ -272,7 +271,7 @@ assign end_of_word = (CPOL ^ CPHA) ? (spi_sclk_neg_counter == DATA_DLENGTH); initial begin - while(1) begin + forever begin @(posedge spi_sclk_bfm or posedge m_spi_csn_negedge_s); if (m_spi_csn_negedge_s) begin spi_sclk_pos_counter <= 8'b0; @@ -283,7 +282,7 @@ initial begin end initial begin - while(1) begin + forever begin @(negedge spi_sclk_bfm or posedge m_spi_csn_negedge_s); if (m_spi_csn_negedge_s) begin spi_sclk_neg_counter <= 8'b0; @@ -295,7 +294,7 @@ end // SDI shift register initial begin - while(1) begin + forever begin // synchronization if (CPHA ^ CPOL) @(posedge spi_sclk_bfm or posedge m_spi_csn_negedge_s); @@ -347,7 +346,7 @@ bit [31:0] sdi_shiftreg_old; assign sdi_shiftreg2 = {1'b0, sdi_shiftreg[31:1]}; initial begin - while(1) begin + forever begin @(posedge ad463x_echo_sclk); sdi_data_store <= {sdi_shiftreg[27:0], 4'b0}; if (sdi_data_store == 'h0 && shiftreg_sampled == 'h1 && sdi_shiftreg != 'h0) begin @@ -430,7 +429,7 @@ end bit [31:0] offload_transfer_cnt; initial begin - while(1) begin + forever begin @(posedge shiftreg_sampled && offload_status); offload_transfer_cnt <= offload_transfer_cnt + 'h1; end @@ -446,14 +445,14 @@ bit [31:0] offload_captured_word_arr [(2 * NUM_OF_TRANSFERS) -1 :0]; task offload_spi_test(); //Configure DMA - env.mng.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*2)-1)); // X_LENGHTH = 1024-1 - env.mng.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - env.mng.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*2)-1)); // X_LENGHTH = 1024-1 + base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module @@ -486,7 +485,7 @@ task offload_spi_test(); for (int i=0; i<=((2 * NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - offload_captured_word_arr[i] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i] = base_env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); end if (irq_pending == 'h0) begin diff --git a/testbenches/project/ad57xx/ad57xx_environment.sv b/testbenches/project/ad57xx/ad57xx_environment.sv index b30a885e..51e4c0cb 100644 --- a/testbenches/project/ad57xx/ad57xx_environment.sv +++ b/testbenches/project/ad57xx/ad57xx_environment.sv @@ -37,18 +37,15 @@ package ad57xx_environment_pkg; - import axi_vip_pkg::*; - import axi4stream_vip_pkg::*; - import m_axi_sequencer_pkg::*; - import s_axi_sequencer_pkg::*; + import logger_pkg::*; + import adi_common_pkg::*; + import s_spi_sequencer_pkg::*; import adi_spi_vip_pkg::*; - import test_harness_env_pkg::*; - import `PKGIFY(test_harness, mng_axi_vip)::*; - import `PKGIFY(test_harness, ddr_axi_vip)::*; + import `PKGIFY(test_harness, spi_s_vip)::*; - class ad57xx_environment extends test_harness_env; + class ad57xx_environment extends adi_environment; // Agents adi_spi_agent #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_agent; @@ -62,30 +59,14 @@ package ad57xx_environment_pkg; function new( input string name, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, - - virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, - - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, virtual interface spi_vip_if #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_s_vip_if ); - super.new(name, - sys_clk_vip_if, - dma_clk_vip_if, - ddr_clk_vip_if, - sys_rst_vip_if, - mng_vip_if, - ddr_vip_if); - // Creating the agents - spi_agent = new("SPI VIP Agent", spi_s_vip_if, this); + this.spi_agent = new("SPI VIP Agent", spi_s_vip_if, this); // Creating the sequencers - spi_seq = new("SPI VIP Sequencer", spi_agent, this); + this.spi_seq = new("SPI VIP Sequencer", this.spi_agent, this); endfunction @@ -95,43 +76,14 @@ package ad57xx_environment_pkg; // - Start the agents //============================================================================ task start(); - super.start(); - spi_agent.start(); - endtask - - //============================================================================ - // Start the test - // - start the scoreboard - // - start the sequencers - //============================================================================ - task test(); - super.test(); - fork - - join_none - endtask - - //============================================================================ - // Post test subroutine - //============================================================================ - task post_test(); - super.post_test(); - endtask - - //============================================================================ - // Run subroutine - //============================================================================ - task run; - test(); - post_test(); + this.spi_agent.start(); endtask //============================================================================ // Stop subroutine //============================================================================ task stop; - spi_agent.stop(); - super.stop(); + this.spi_agent.stop(); endtask endclass diff --git a/testbenches/project/ad57xx/tests/test_program.sv b/testbenches/project/ad57xx/tests/test_program.sv index e1bdb3e1..b9128388 100644 --- a/testbenches/project/ad57xx/tests/test_program.sv +++ b/testbenches/project/ad57xx/tests/test_program.sv @@ -35,6 +35,9 @@ `include "utils.svh" +import logger_pkg::*; +import test_harness_env_pkg::*; +import ad57xx_environment_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; import adi_regmap_pkg::*; @@ -42,11 +45,12 @@ import adi_regmap_clkgen_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; import adi_regmap_spi_engine_pkg::*; -import logger_pkg::*; -import ad57xx_environment_pkg::*; import spi_engine_instr_pkg::*; import adi_spi_vip_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + //--------------------------------------------------------------------------- // SPI Engine configuration parameters //--------------------------------------------------------------------------- @@ -60,7 +64,8 @@ timeprecision 100ps; typedef enum {DATA_MODE_RANDOM, DATA_MODE_RAMP, DATA_MODE_PATTERN} offload_test_t; -ad57xx_environment env; +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; +ad57xx_environment spi_env; // -------------------------- // Wrapper function for AXI read verify @@ -68,13 +73,13 @@ ad57xx_environment env; task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -83,7 +88,7 @@ endtask task axi_write( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -91,7 +96,7 @@ endtask // -------------------------- task spi_receive( output [`DATA_DLENGTH:0] data); - env.spi_seq.receive_data(data); + spi_env.spi_seq.receive_data(data); endtask // -------------------------- @@ -99,14 +104,14 @@ endtask // -------------------------- task spi_send( input [`DATA_DLENGTH:0] data); - env.spi_seq.send_data(data); + spi_env.spi_seq.send_data(data); endtask // -------------------------- // Wrapper function for waiting for all SPI // -------------------------- task spi_wait_send(); - env.spi_seq.flush_send(); + spi_env.spi_seq.flush_send(); endtask @@ -117,21 +122,25 @@ endtask initial begin //creating environment - env = new("Axis Sequencers Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - `TH.`SPI_S.inst.IF); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + spi_env = new("SPI Environment", + `TH.`SPI_S.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.spi_seq.set_default_miso_data('h0); + base_env.start(); + spi_env.start(); + + spi_env.spi_seq.set_default_miso_data('h0); - env.sys_reset(); + base_env.sys_reset(); sanity_test(); @@ -143,10 +152,11 @@ initial begin offload_spi_test(`TEST_DATA_MODE); - env.stop(); + spi_env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -268,21 +278,21 @@ task offload_spi_test( temp_data = {4'b0001,dac_word,2'b00}; sdo_write_data_store [i] = temp_data; - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(.addr(`DDR_BA + 4*i), + base_env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(.addr(`DDR_BA + 4*i), .payload(temp_data), .strb('1)); spi_send('0); end //Configure TX DMA - env.mng.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - env.mng.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); - env.mng.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA)); - env.mng.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Configure the Offload module axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG); diff --git a/testbenches/project/ad738x/tests/test_program.sv b/testbenches/project/ad738x/tests/test_program.sv index 49ce5017..5c1c80cc 100644 --- a/testbenches/project/ad738x/tests/test_program.sv +++ b/testbenches/project/ad738x/tests/test_program.sv @@ -47,6 +47,9 @@ import adi_regmap_spi_engine_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + //--------------------------------------------------------------------------- // SPI Engine configuration parameters //--------------------------------------------------------------------------- @@ -98,7 +101,7 @@ program test_program ( input ad738x_spi_cs); -test_harness_env env; +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verif @@ -107,14 +110,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -124,7 +127,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -133,22 +136,18 @@ endtask initial begin //creating environment - env = new("AD738X Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - #100 + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -160,10 +159,10 @@ initial begin offload_spi_test(); - env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -420,14 +419,14 @@ task offload_spi_test(); `INFO(("Axi_pwm_gen started"), ADI_VERBOSITY_LOW); //Configure DMA - env.mng.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*2)-1)); // X_LENGHTH = 1024-1 - env.mng.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - env.mng.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*2)-1)); // X_LENGHTH = 1024-1 + base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module axi_write (`SPI_AD738x_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), INST_CFG); @@ -455,7 +454,7 @@ task offload_spi_test(); for (int i=0; i<=((2* NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - offload_captured_word_arr[i] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); end if (offload_captured_word_arr [(2 * NUM_OF_TRANSFERS) - 1:2] != offload_sdi_data_store_arr [(2 * NUM_OF_TRANSFERS) - 1:2]) begin diff --git a/testbenches/project/ad7606x/tests/test_program_4ch.sv b/testbenches/project/ad7606x/tests/test_program_4ch.sv index 0bcedcfb..e33a02d2 100755 --- a/testbenches/project/ad7606x/tests/test_program_4ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_4ch.sv @@ -47,7 +47,10 @@ import adi_regmap_common_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; -localparam SIMPLE_STATUS_CRC = 0; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +parameter SIMPLE_STATUS_CRC = 0; localparam CH0 = 8'h00 * 4; localparam CH1 = 8'h10 * 4; @@ -69,7 +72,7 @@ program test_program_4ch ( output rx_busy, output logic [2:0] adc_config_mode); - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verif @@ -78,14 +81,14 @@ program test_program_4ch ( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -95,7 +98,7 @@ program test_program_4ch ( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -103,19 +106,19 @@ program test_program_4ch ( // -------------------------- initial begin - //creating environment - env = new("AD7606X Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.sys_reset(); + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -133,10 +136,10 @@ program test_program_4ch ( #100 db_transmission_test(); - env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end diff --git a/testbenches/project/ad7606x/tests/test_program_6ch.sv b/testbenches/project/ad7606x/tests/test_program_6ch.sv index 2613b3bc..f9fe57e9 100755 --- a/testbenches/project/ad7606x/tests/test_program_6ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_6ch.sv @@ -47,7 +47,10 @@ import adi_regmap_common_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; -localparam SIMPLE_STATUS_CRC = 0; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +parameter SIMPLE_STATUS_CRC = 0; localparam CH0 = 8'h00 * 4; localparam CH1 = 8'h10 * 4; @@ -71,7 +74,7 @@ program test_program_6ch ( output rx_busy, output logic [2:0] adc_config_mode); - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verif @@ -80,14 +83,14 @@ program test_program_6ch ( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -97,7 +100,7 @@ program test_program_6ch ( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -105,19 +108,19 @@ program test_program_6ch ( // -------------------------- initial begin - //creating environment - env = new("AD7606X Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.sys_reset(); + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -136,7 +139,7 @@ program test_program_6ch ( #100 db_transmission_test(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end diff --git a/testbenches/project/ad7606x/tests/test_program_8ch.sv b/testbenches/project/ad7606x/tests/test_program_8ch.sv index df553d99..38cd7d80 100755 --- a/testbenches/project/ad7606x/tests/test_program_8ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_8ch.sv @@ -47,7 +47,10 @@ import adi_regmap_common_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; -localparam SIMPLE_STATUS_CRC = 0; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +parameter SIMPLE_STATUS_CRC = 0; localparam CH0 = 8'h00 * 4; localparam CH1 = 8'h10 * 4; @@ -73,7 +76,7 @@ program test_program_8ch ( output rx_busy, output logic [2:0] adc_config_mode); - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verif @@ -82,14 +85,14 @@ program test_program_8ch ( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -99,7 +102,7 @@ program test_program_8ch ( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -107,19 +110,19 @@ program test_program_8ch ( // -------------------------- initial begin - //creating environment - env = new("AD7606X Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.sys_reset(); + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -138,7 +141,7 @@ program test_program_8ch ( #100 db_transmission_test(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end diff --git a/testbenches/project/ad7606x/tests/test_program_si.sv b/testbenches/project/ad7606x/tests/test_program_si.sv index fed5120c..4f55c963 100755 --- a/testbenches/project/ad7606x/tests/test_program_si.sv +++ b/testbenches/project/ad7606x/tests/test_program_si.sv @@ -47,6 +47,9 @@ import adi_regmap_spi_engine_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + //--------------------------------------------------------------------------- // SPI Engine configuration parameters //--------------------------------------------------------------------------- @@ -100,7 +103,7 @@ program test_program_si ( input rx_busy, output rx_cnvst_n); - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verify @@ -109,14 +112,14 @@ program test_program_si ( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -126,7 +129,7 @@ program test_program_si ( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -134,19 +137,19 @@ program test_program_si ( // -------------------------- initial begin - //creating environment - env = new("AD7606X Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.sys_reset(); + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -159,7 +162,7 @@ program test_program_si ( offload_spi_test(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -430,14 +433,14 @@ program test_program_si ( task offload_spi_test(); //Configure DMA - env.mng.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*`NUM_OF_SDI)-1)); // X_LENGHTH - env.mng.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - env.mng.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*`NUM_OF_SDI)-1)); // X_LENGHTH + base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), INST_CFG); @@ -466,7 +469,7 @@ program test_program_si ( for (int i=0; i<=((`NUM_OF_SDI * NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - offload_captured_word_arr[i] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); end if (offload_captured_word_arr != offload_sdi_data_store_arr) begin `ERROR(("Offload Test FAILED")); diff --git a/testbenches/project/ad7616/tests/test_program_pi.sv b/testbenches/project/ad7616/tests/test_program_pi.sv index 3fa69e9c..14a1bef6 100755 --- a/testbenches/project/ad7616/tests/test_program_pi.sv +++ b/testbenches/project/ad7616/tests/test_program_pi.sv @@ -47,6 +47,9 @@ import adi_regmap_pwm_gen_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + localparam AD7616_CTRL_RESETN = 1; localparam AD7616_CTRL_CNVST_EN = 2; localparam NUM_OF_TRANSFERS = 10; @@ -61,7 +64,7 @@ program test_program_pi ( input sys_clk, input rx_busy); -test_harness_env env; +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verif @@ -70,14 +73,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -87,7 +90,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -96,22 +99,18 @@ endtask initial begin //creating environment - env = new("AD7616 Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - #100 + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -119,10 +118,10 @@ initial begin data_acquisition_test(); - env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -210,13 +209,13 @@ task data_acquisition_test(); `INFO(("Axi_pwm_gen started"), ADI_VERBOSITY_LOW); // Configure DMA - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS // Configure AXI_AD7616 axi_write (`AXI_AD7616_BA + GetAddrs(AXI_AD7616_REG_UP_CNTRL), @@ -233,7 +232,7 @@ task data_acquisition_test(); transfer_status = 1; - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA wait(transfer_cnt == 2 * NUM_OF_TRANSFERS ); @@ -254,7 +253,7 @@ task data_acquisition_test(); for (int i=0; i<=((NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - captured_word_arr[i] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); end if (captured_word_arr != dma_data_store_arr) begin diff --git a/testbenches/project/ad7616/tests/test_program_si.sv b/testbenches/project/ad7616/tests/test_program_si.sv index 4f8cf554..bf8f4497 100755 --- a/testbenches/project/ad7616/tests/test_program_si.sv +++ b/testbenches/project/ad7616/tests/test_program_si.sv @@ -47,6 +47,9 @@ import adi_regmap_spi_engine_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + //--------------------------------------------------------------------------- // SPI Engine configuration parameters //--------------------------------------------------------------------------- @@ -101,7 +104,7 @@ program test_program_si ( output rx_busy); -test_harness_env env; +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verif @@ -110,14 +113,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.RegRead32(raddr,data); endtask // -------------------------- @@ -127,7 +130,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -136,22 +139,18 @@ endtask initial begin //creating environment - env = new("AD7616 Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - #100 + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -163,10 +162,10 @@ initial begin offload_spi_test(); - env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -420,14 +419,14 @@ task offload_spi_test(); `INFO(("Axi_pwm_gen started"), ADI_VERBOSITY_LOW); //Configure DMA - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 + base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module axi_write (`SPI_AD7616_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), INST_CFG); @@ -456,7 +455,7 @@ task offload_spi_test(); for (int i=0; i<=((NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - offload_captured_word_arr[i] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); end if (offload_captured_word_arr [(NUM_OF_TRANSFERS) - 1:2] != offload_sdi_data_store_arr [(NUM_OF_TRANSFERS) - 1:2]) begin diff --git a/testbenches/project/ad9083/tests/test_program.sv b/testbenches/project/ad9083/tests/test_program.sv index 4b089441..71b71461 100644 --- a/testbenches/project/ad9083/tests/test_program.sv +++ b/testbenches/project/ad9083/tests/test_program.sv @@ -52,11 +52,16 @@ import adi_regmap_xcvr_pkg::*; import adi_jesd204_pkg::*; import adi_xcvr_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + parameter RX_OUT_BYTES = 8; parameter TX_OUT_BYTES = 8; + program test_program; - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + bit [31:0] val; int link_clk_freq; int device_clk_freq; @@ -70,22 +75,17 @@ program test_program; initial begin //creating environment - env = new("AD9083 Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); - - #2ps; + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - - `TH.`SYS_CLK.inst.IF.start_clock; - `TH.`DMA_CLK.inst.IF.start_clock; - `TH.`DDR_CLK.inst.IF.start_clock; + + base_env.start(); link_clk_freq = lane_rate/40; data_path_width = 4; @@ -102,13 +102,7 @@ program test_program; `TH.`DEVICE_CLK.inst.IF.start_clock; `TH.`SYSREF_CLK.inst.IF.start_clock; - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - - #1us; + base_env.sys_reset(); // ------------------------------------------------------- // Test DDS path @@ -118,29 +112,29 @@ program test_program; // // Enable Rx channel - env.mng.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); // Select DDS as source - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(32'h00000fff)); - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INIT_1(16'h0000)| `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); // Pull out TPL cores from reset - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - env.mng.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_ADC_COMMON_REG_RSTN_RSTN(1)); // Sync DDS cores - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); // @@ -148,25 +142,25 @@ program test_program; // //LINK DISABLE - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); //SYSREFCONF - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_CONF), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_CONF), `SET_JESD_TX_SYSREF_CONF_SYSREF_DISABLE(0)); // Enable SYSREF handling //CONF0 - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF0), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF0), `SET_JESD_TX_LINK_CONF0_OCTETS_PER_FRAME(`TX_JESD_F-1)| `SET_JESD_TX_LINK_CONF0_OCTETS_PER_MULTIFRAME(`TX_JESD_F*`TX_JESD_K-1)); - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF4), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF4), `SET_JESD_TX_LINK_CONF4_TPL_BEATS_PER_MULTIFRAME((`TX_JESD_F*`TX_JESD_K)/TX_OUT_BYTES-1)); //CONF1 - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF1), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF1), `SET_JESD_TX_LINK_CONF1_SCRAMBLER_DISABLE(0)); // Scrambler enable //LINK ENABLE - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); // @@ -174,39 +168,39 @@ program test_program; // //LINK DISABLE - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); //SYSREFCONF - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_CONF), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_CONF), `SET_JESD_RX_SYSREF_CONF_SYSREF_DISABLE(0)); // Enable SYSREF handling //CONF0 - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF0), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF0), `SET_JESD_RX_LINK_CONF0_OCTETS_PER_FRAME(`RX_JESD_F-1)| `SET_JESD_RX_LINK_CONF0_OCTETS_PER_MULTIFRAME(`RX_JESD_F*`RX_JESD_K-1)); - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF4), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF4), `SET_JESD_RX_LINK_CONF4_TPL_BEATS_PER_MULTIFRAME((`RX_JESD_F*`RX_JESD_K)/RX_OUT_BYTES-1)); // Beats per multiframe //CONF1 - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF1), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF1), `SET_JESD_RX_LINK_CONF1_DESCRAMBLER_DISABLE(0)); // Scrambler enable //LINK ENABLE - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); //XCVR INIT //REG CTRL - env.mng.RegWrite32(`RX_XCVR_BA + GetAddrs(XCVR_CONTROL), + base_env.mng.sequencer.RegWrite32(`RX_XCVR_BA + GetAddrs(XCVR_CONTROL), `SET_XCVR_CONTROL_LPM_DFE_N(1)| `SET_XCVR_CONTROL_OUTCLK_SEL(4)); // RXOUTCLK uses DIV2 - env.mng.RegWrite32(`TX_XCVR_BA + GetAddrs(XCVR_CONTROL), + base_env.mng.sequencer.RegWrite32(`TX_XCVR_BA + GetAddrs(XCVR_CONTROL), `SET_XCVR_CONTROL_LPM_DFE_N(1)| `SET_XCVR_CONTROL_OUTCLK_SEL(4)); // TXOUTCLK uses DIV2 - env.mng.RegWrite32(`RX_XCVR_BA + GetAddrs(XCVR_RESETN), + base_env.mng.sequencer.RegWrite32(`RX_XCVR_BA + GetAddrs(XCVR_RESETN), `SET_XCVR_RESETN_RESETN(1)); - env.mng.RegWrite32(`TX_XCVR_BA + GetAddrs(XCVR_RESETN), + base_env.mng.sequencer.RegWrite32(`TX_XCVR_BA + GetAddrs(XCVR_RESETN), `SET_XCVR_RESETN_RESETN(1)); // Give time the PLLs to lock @@ -214,22 +208,22 @@ program test_program; //Read status back // Check SYSREF_STATUS - env.mng.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); - env.mng.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); // Check if in DATA state and SYNC is 1 - env.mng.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_STATUS), `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); - env.mng.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_STATUS), `SET_JESD_TX_LINK_STATUS_STATUS_SYNC(1)| `SET_JESD_TX_LINK_STATUS_STATUS_STATE(3)); //LINK DISABLE - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); // ------------------------------------------------------- @@ -240,85 +234,85 @@ program test_program; // .step (1), // .max_sample(2048) for (int i=0;i<2048*2 ;i=i+2) begin - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(`DDR_BA+i*2,(((i+1)) << 16) | i ,15); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(`DDR_BA+i*2,(((i+1)) << 16) | i ,15); end #5us; // Reset TPL cores - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_DAC_COMMON_REG_RSTN_RSTN(0)); - env.mng.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_ADC_COMMON_REG_RSTN_RSTN(0)); // Pull out TPL cores from reset - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - env.mng.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_ADC_COMMON_REG_RSTN_RSTN(1)); // Configure Transport Layer for DMA - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); #1us; // Configure TX DMA - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(0)| `SET_DMAC_FLAGS_TLAST(1)); // use TLAST, disable CYCLIC - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); // X_LENGTH = 992-1 - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA)); // SRC_ADDRESS - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer // Configure RX DMA - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(0)| `SET_DMAC_FLAGS_TLAST(1)); // use TLAST, disable CYCLIC - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); // X_LENGTH = 992-1 - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00001000)); // DEST_ADDRESS - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer //LINK ENABLE - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); #25us; //Read status back // Check SYSREF_STATUS - env.mng.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); - env.mng.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); #1us; // Check if in DATA state and SYNC is 1 - env.mng.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_STATUS), `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); - env.mng.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_STATUS), `SET_JESD_TX_LINK_STATUS_STATUS_SYNC(1)| `SET_JESD_TX_LINK_STATUS_STATUS_STATE(3)); #5us; - env.mng.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(0)); #5us; @@ -331,45 +325,45 @@ program test_program; //LINK DISABLE - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); - env.mng.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); #5us; // Configure TX DMA - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(0)| `SET_DMAC_FLAGS_TLAST(1)); // use TLAST, disable CYCLIC - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); // X_LENGTH = 992-1 - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA)); // SRC_ADDRESS - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer // Configure RX DMA - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(0)| `SET_DMAC_FLAGS_TLAST(1)); // use TLAST, disable CYCLIC - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); // X_LENGTH = 992-1 - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00002000)); // DEST_ADDRESS - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA //LINK ENABLE - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); #10us; @@ -381,10 +375,10 @@ program test_program; .max_sample(496) ); - env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -403,7 +397,7 @@ program test_program; for (int i=0;i Date: Mon, 20 Jan 2025 15:22:50 +0200 Subject: [PATCH 10/37] infrastructure refactorization: Updates and fixes Signed-off-by: Istvan-Zsolt Szekely --- .../ip/dma_loopback/tests/test_program.sv | 14 ++--- testbenches/ip/hbm/tests/test_program.sv | 57 ++++++++++--------- .../project/ad463x/tests/test_program.sv | 2 +- .../project/ad57xx/tests/test_program.sv | 2 +- .../project/ad738x/tests/test_program.sv | 2 +- .../project/ad7606x/tests/test_program_si.sv | 2 +- .../project/ad9083/tests/test_program.sv | 2 +- .../ad_quadmxfe1_ebz/tests/test_program.sv | 2 +- .../project/adrv9001/tests/test_program.sv | 12 ++-- .../project/adrv9009/tests/test_program.sv | 2 +- .../project/fmcomms2/tests/test_program.sv | 2 +- .../project/mxfe/tests/test_program.sv | 8 +-- .../project/pluto/tests/test_program.sv | 4 +- .../pulsar_adc_pmdz/tests/test_program.sv | 2 +- 14 files changed, 57 insertions(+), 56 deletions(-) diff --git a/testbenches/ip/dma_loopback/tests/test_program.sv b/testbenches/ip/dma_loopback/tests/test_program.sv index 02320217..0c1c93b3 100644 --- a/testbenches/ip/dma_loopback/tests/test_program.sv +++ b/testbenches/ip/dma_loopback/tests/test_program.sv @@ -60,13 +60,13 @@ program test_program; initial begin //creating environment - base_env = new("DMA Loopback Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); diff --git a/testbenches/ip/hbm/tests/test_program.sv b/testbenches/ip/hbm/tests/test_program.sv index a8480581..69abbfe0 100644 --- a/testbenches/ip/hbm/tests/test_program.sv +++ b/testbenches/ip/hbm/tests/test_program.sv @@ -44,37 +44,38 @@ import axi4stream_vip_pkg::*; import logger_pkg::*; import adi_regmap_dmac_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + `define RX_DMA 32'h7c42_0000 `define TX_DMA 32'h7c43_0000 `define DDR_BASE 32'h8000_0000 program test_program; - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + bit [31:0] val; bit [31:0] src_addr; initial begin //creating environment - env = new("HBM Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); - - #2ps; + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - `TH.`HBM_CLK.inst.IF.start_clock; + base_env.start(); - env.sys_reset(); + `TH.`HBM_CLK.inst.IF.start_clock; - #1us; + base_env.sys_reset(); // // ------------------------------------------------------- // // Test TX DMA and RX DMA in loopback @@ -82,7 +83,7 @@ program test_program; // // // Init test data // for (int i=0;i<2048*2 ;i=i+2) begin -// env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(`DDR_BASE+src_addr+i*2,(((i+1)) << 16) | i ,'hF); +// base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(`DDR_BASE+src_addr+i*2,(((i+1)) << 16) | i ,'hF); // end // // do_transfer( @@ -99,7 +100,7 @@ program test_program; // .length('h1000) // ); // -// env.stop(); +// base_env.stop(); // // `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); // $finish(); @@ -111,27 +112,27 @@ program test_program; // bit [31:0] length); // // // Configure TX DMA -// env.mng.RegWrite32(`TX_DMA+GetAddrs(dmac_CONTROL), +// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_CONTROL), // `SET_dmac_CONTROL_ENABLE(1)); -// env.mng.RegWrite32(`TX_DMA+GetAddrs(dmac_FLAGS), +// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_FLAGS), // `SET_dmac_FLAGS_TLAST(32'h00000006)); -// env.mng.RegWrite32(`TX_DMA+GetAddrs(dmac_X_LENGTH), +// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_X_LENGTH), // `SET_dmac_X_LENGTH_X_LENGTH(length-1)); -// env.mng.RegWrite32(`TX_DMA+GetAddrs(dmac_SRC_ADDRESS), +// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_SRC_ADDRESS), // `SET_dmac_SRC_ADDRESS_SRC_ADDRESS(src_addr)); -// env.mng.RegWrite32(`TX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), +// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), // `SET_dmac_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // // // Configure RX DMA -// env.mng.RegWrite32(`RX_DMA+GetAddrs(dmac_CONTROL), +// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_CONTROL), // `SET_dmac_CONTROL_ENABLE(1)); -// env.mng.RegWrite32(`RX_DMA+GetAddrs(dmac_FLAGS), +// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_FLAGS), // `SET_dmac_FLAGS_TLAST(32'h00000006)); -// env.mng.RegWrite32(`RX_DMA+GetAddrs(dmac_X_LENGTH), +// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_X_LENGTH), // `SET_dmac_X_LENGTH_X_LENGTH(length-1)); -// env.mng.RegWrite32(`RX_DMA+GetAddrs(dmac_DEST_ADDRESS), +// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_DEST_ADDRESS), // `SET_dmac_DEST_ADDRESS_DEST_ADDRESS(dest_addr)); -// env.mng.RegWrite32(`RX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), +// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), // `SET_dmac_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // endtask // @@ -149,8 +150,8 @@ program test_program; // for (int i=0;i Date: Mon, 20 Jan 2025 16:26:59 +0200 Subject: [PATCH 11/37] ad7616: Fixes - Fixed the serial test - Parallel data acquisition test still failing Signed-off-by: Istvan-Zsolt Szekely --- library/regmaps/adi_regmap_axi_ad7616_pkg.sv | 16 ++++++------- testbenches/project/ad7616/cfgs/cfg_pi.tcl | 2 +- testbenches/project/ad7616/cfgs/cfg_si.tcl | 2 +- testbenches/project/ad7616/system_bd.tcl | 10 ++------ testbenches/project/ad7616/system_project.tcl | 6 ++--- testbenches/project/ad7616/system_tb.sv | 2 +- .../project/ad7616/tests/test_program_pi.sv | 12 ++++------ .../project/ad7616/tests/test_program_si.sv | 24 +++++++------------ 8 files changed, 29 insertions(+), 45 deletions(-) diff --git a/library/regmaps/adi_regmap_axi_ad7616_pkg.sv b/library/regmaps/adi_regmap_axi_ad7616_pkg.sv index 8630ec2f..45b3c0a4 100644 --- a/library/regmaps/adi_regmap_axi_ad7616_pkg.sv +++ b/library/regmaps/adi_regmap_axi_ad7616_pkg.sv @@ -41,22 +41,22 @@ package adi_regmap_axi_ad7616_pkg; /* AXI AD7616 (axi_ad7616) */ - const reg_t AXI_AD7616_REG_VERSION = '{ 'h0400, "REG_VERSION" , '{ + const reg_t AXI_AD7616_REG_VERSION = '{ 'h0000, "REG_VERSION" , '{ "VERSION": '{ 31, 0, RO, 'h00001002 }}}; `define SET_AXI_AD7616_REG_VERSION_VERSION(x) SetField(AXI_AD7616_REG_VERSION,"VERSION",x) `define GET_AXI_AD7616_REG_VERSION_VERSION(x) GetField(AXI_AD7616_REG_VERSION,"VERSION",x) - const reg_t AXI_AD7616_REG_ID = '{ 'h0404, "REG_ID" , '{ + const reg_t AXI_AD7616_REG_ID = '{ 'h0004, "REG_ID" , '{ "ID": '{ 31, 0, RO, 'h00000000 }}}; `define SET_AXI_AD7616_REG_ID_ID(x) SetField(AXI_AD7616_REG_ID,"ID",x) `define GET_AXI_AD7616_REG_ID_ID(x) GetField(AXI_AD7616_REG_ID,"ID",x) - const reg_t AXI_AD7616_REG_SCRATCH = '{ 'h0408, "REG_SCRATCH" , '{ + const reg_t AXI_AD7616_REG_SCRATCH = '{ 'h0008, "REG_SCRATCH" , '{ "SCRATCH": '{ 31, 0, RW, 'h00000000 }}}; `define SET_AXI_AD7616_REG_SCRATCH_SCRATCH(x) SetField(AXI_AD7616_REG_SCRATCH,"SCRATCH",x) `define GET_AXI_AD7616_REG_SCRATCH_SCRATCH(x) GetField(AXI_AD7616_REG_SCRATCH,"SCRATCH",x) - const reg_t AXI_AD7616_REG_UP_CNTRL = '{ 'h0440, "REG_UP_CNTRL" , '{ + const reg_t AXI_AD7616_REG_UP_CNTRL = '{ 'h0040, "REG_UP_CNTRL" , '{ "CNVST_EN": '{ 1, 1, RW, 'h0 }, "RESETN": '{ 0, 0, RW, 'h0 }}}; `define SET_AXI_AD7616_REG_UP_CNTRL_CNVST_EN(x) SetField(AXI_AD7616_REG_UP_CNTRL,"CNVST_EN",x) @@ -64,22 +64,22 @@ package adi_regmap_axi_ad7616_pkg; `define SET_AXI_AD7616_REG_UP_CNTRL_RESETN(x) SetField(AXI_AD7616_REG_UP_CNTRL,"RESETN",x) `define GET_AXI_AD7616_REG_UP_CNTRL_RESETN(x) GetField(AXI_AD7616_REG_UP_CNTRL,"RESETN",x) - const reg_t AXI_AD7616_REG_UP_CONV_RATE = '{ 'h0444, "REG_UP_CONV_RATE" , '{ + const reg_t AXI_AD7616_REG_UP_CONV_RATE = '{ 'h0044, "REG_UP_CONV_RATE" , '{ "UP_CONV_RATE": '{ 31, 0, RW, 'h00000000 }}}; `define SET_AXI_AD7616_REG_UP_CONV_RATE_UP_CONV_RATE(x) SetField(AXI_AD7616_REG_UP_CONV_RATE,"UP_CONV_RATE",x) `define GET_AXI_AD7616_REG_UP_CONV_RATE_UP_CONV_RATE(x) GetField(AXI_AD7616_REG_UP_CONV_RATE,"UP_CONV_RATE",x) - const reg_t AXI_AD7616_REG_UP_BURST_LENGTH = '{ 'h0448, "REG_UP_BURST_LENGTH" , '{ + const reg_t AXI_AD7616_REG_UP_BURST_LENGTH = '{ 'h0048, "REG_UP_BURST_LENGTH" , '{ "UP_BURST_LENGTH": '{ 4, 0, RW, 'h000 }}}; `define SET_AXI_AD7616_REG_UP_BURST_LENGTH_UP_BURST_LENGTH(x) SetField(AXI_AD7616_REG_UP_BURST_LENGTH,"UP_BURST_LENGTH",x) `define GET_AXI_AD7616_REG_UP_BURST_LENGTH_UP_BURST_LENGTH(x) GetField(AXI_AD7616_REG_UP_BURST_LENGTH,"UP_BURST_LENGTH",x) - const reg_t AXI_AD7616_REG_UP_READ_DATA = '{ 'h044c, "REG_UP_READ_DATA" , '{ + const reg_t AXI_AD7616_REG_UP_READ_DATA = '{ 'h004c, "REG_UP_READ_DATA" , '{ "UP_READ_DATA": '{ 31, 0, RO, 'h00000000 }}}; `define SET_AXI_AD7616_REG_UP_READ_DATA_UP_READ_DATA(x) SetField(AXI_AD7616_REG_UP_READ_DATA,"UP_READ_DATA",x) `define GET_AXI_AD7616_REG_UP_READ_DATA_UP_READ_DATA(x) GetField(AXI_AD7616_REG_UP_READ_DATA,"UP_READ_DATA",x) - const reg_t AXI_AD7616_REG_UP_WRITE_DATA = '{ 'h0450, "REG_UP_WRITE_DATA" , '{ + const reg_t AXI_AD7616_REG_UP_WRITE_DATA = '{ 'h0050, "REG_UP_WRITE_DATA" , '{ "UP_WRITE_DATA": '{ 31, 0, WO, 'h00000000 }}}; `define SET_AXI_AD7616_REG_UP_WRITE_DATA_UP_WRITE_DATA(x) SetField(AXI_AD7616_REG_UP_WRITE_DATA,"UP_WRITE_DATA",x) `define GET_AXI_AD7616_REG_UP_WRITE_DATA_UP_WRITE_DATA(x) GetField(AXI_AD7616_REG_UP_WRITE_DATA,"UP_WRITE_DATA",x) diff --git a/testbenches/project/ad7616/cfgs/cfg_pi.tcl b/testbenches/project/ad7616/cfgs/cfg_pi.tcl index 49b70d8e..e447cce9 100755 --- a/testbenches/project/ad7616/cfgs/cfg_pi.tcl +++ b/testbenches/project/ad7616/cfgs/cfg_pi.tcl @@ -1,3 +1,3 @@ global ad_project_params -set ad_project_params(SER_PAR_N) 0 +set ad_project_params(INTF) 0 diff --git a/testbenches/project/ad7616/cfgs/cfg_si.tcl b/testbenches/project/ad7616/cfgs/cfg_si.tcl index ce97f85c..b1f2479c 100755 --- a/testbenches/project/ad7616/cfgs/cfg_si.tcl +++ b/testbenches/project/ad7616/cfgs/cfg_si.tcl @@ -1,3 +1,3 @@ global ad_project_params -set ad_project_params(SER_PAR_N) 1 +set ad_project_params(INTF) 1 diff --git a/testbenches/project/ad7616/system_bd.tcl b/testbenches/project/ad7616/system_bd.tcl index 5d5c5336..7fd76333 100755 --- a/testbenches/project/ad7616/system_bd.tcl +++ b/testbenches/project/ad7616/system_bd.tcl @@ -36,7 +36,7 @@ global ad_project_params # system level parameters -set SER_PAR_N $ad_project_params(SER_PAR_N) +set INTF $ad_project_params(INTF) adi_project_files [list \ "$ad_hdl_dir/library/common/ad_edge_detect.v" \ @@ -48,7 +48,7 @@ adi_project_files [list \ source $ad_hdl_dir/projects/ad7616_sdz/common/ad7616_bd.tcl -if {$SER_PAR_N == 1} { +if {$INTF == 1} { create_bd_port -dir O spi_clk create_bd_port -dir O ad7616_irq @@ -63,8 +63,6 @@ if {$SER_PAR_N == 1} { } else { create_bd_port -dir O sys_clk - ad_disconnect spi_clk ad7616_pwm_gen/ext_clk - ad_connect sys_cpu_clk ad7616_pwm_gen/ext_clk ad_connect sys_clk sys_cpu_clk set BA_AD7616 0x44A80000 @@ -80,7 +78,3 @@ adi_sim_add_define "AD7616_DMA_BA=[format "%d" ${BA_DMA}]" set BA_PWM 0x44B00000 set_property offset $BA_PWM [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_ad7616_pwm_gen}] adi_sim_add_define "AD7616_PWM_GEN_BA=[format "%d" ${BA_PWM}]" - -set BA_CLKGEN 0x44A70000 -set_property offset $BA_CLKGEN [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_spi_clkgen}] -adi_sim_add_define "AD7616_AXI_CLKGEN_BA=[format "%d" ${BA_CLKGEN}]" diff --git a/testbenches/project/ad7616/system_project.tcl b/testbenches/project/ad7616/system_project.tcl index 931ccbf7..378c3ba9 100755 --- a/testbenches/project/ad7616/system_project.tcl +++ b/testbenches/project/ad7616/system_project.tcl @@ -16,12 +16,12 @@ set project_name [file rootname $cfg_file] # Set project params global ad_project_params -set SER_PAR_N $ad_project_params(SER_PAR_N) +set INTF $ad_project_params(INTF) #set a default test program -if {$SER_PAR_N == 1} { +if {$INTF == 1} { adi_sim_add_define "TEST_PROGRAM=test_program_si" -} elseif {$SER_PAR_N == 0} { +} elseif {$INTF == 0} { adi_sim_add_define "TEST_PROGRAM=test_program_pi" } else { adi_sim_add_define "TEST_PROGRAM=test_program_si" diff --git a/testbenches/project/ad7616/system_tb.sv b/testbenches/project/ad7616/system_tb.sv index 8d4d43c6..73480c91 100755 --- a/testbenches/project/ad7616/system_tb.sv +++ b/testbenches/project/ad7616/system_tb.sv @@ -39,7 +39,7 @@ module system_tb(); generate - if (`SER_PAR_N == 1) begin //serial interface + if (`INTF == 1) begin //serial interface wire ad7616_spi_sclk; wire ad7616_spi_sdo; wire [1:0] ad7616_spi_sdi; diff --git a/testbenches/project/ad7616/tests/test_program_pi.sv b/testbenches/project/ad7616/tests/test_program_pi.sv index 14a1bef6..6f302f47 100755 --- a/testbenches/project/ad7616/tests/test_program_pi.sv +++ b/testbenches/project/ad7616/tests/test_program_pi.sv @@ -196,12 +196,6 @@ bit [31:0] captured_word_arr [(NUM_OF_TRANSFERS) -1 :0]; task data_acquisition_test(); - // Start spi clk generator - axi_write (`AD7616_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), - `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | - `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) - ); - // Configure pwm gen axi_write (`AD7616_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); // PWM_GEN reset in regmap (ACTIVE HIGH) axi_write (`AD7616_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_PULSE_X_PERIOD), `SET_AXI_PWM_GEN_REG_PULSE_X_PERIOD_PULSE_X_PERIOD('h64)); // set PWM period @@ -253,10 +247,12 @@ task data_acquisition_test(); for (int i=0; i<=((NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); end - if (captured_word_arr != dma_data_store_arr) begin + `INFO(("captured_word_arr: %x; dma_data_store_arr %x", captured_word_arr, dma_data_store_arr), ADI_VERBOSITY_LOW); + + if (captured_word_arr != dma_data_store_arr) begin `ERROR(("Data Acquisition Test FAILED")); end else begin `INFO(("Data Acquisition Test PASSED"), ADI_VERBOSITY_LOW); diff --git a/testbenches/project/ad7616/tests/test_program_si.sv b/testbenches/project/ad7616/tests/test_program_si.sv index bf8f4497..54407e77 100755 --- a/testbenches/project/ad7616/tests/test_program_si.sv +++ b/testbenches/project/ad7616/tests/test_program_si.sv @@ -113,14 +113,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - base_env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -130,7 +130,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - base_env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -419,14 +419,14 @@ task offload_spi_test(); `INFO(("Axi_pwm_gen started"), ADI_VERBOSITY_LOW); //Configure DMA - base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 - base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module axi_write (`SPI_AD7616_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), INST_CFG); @@ -455,7 +455,7 @@ task offload_spi_test(); for (int i=0; i<=((NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - offload_captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); end if (offload_captured_word_arr [(NUM_OF_TRANSFERS) - 1:2] != offload_sdi_data_store_arr [(NUM_OF_TRANSFERS) - 1:2]) begin @@ -472,12 +472,6 @@ endtask bit [31:0] sdi_fifo_data = 0; task fifo_spi_test(); - // Start spi clk generator - axi_write (`AD7616_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), - `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | - `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) - ); - // Enable SPI Engine axi_write (`SPI_AD7616_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); From 269401b68fe4a6ee475c8354374e713778c1746c Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 20 Jan 2025 17:17:41 +0200 Subject: [PATCH 12/37] dma_flock: Fixed testbench after rebase Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/dma_flock/environment.sv | 2 +- testbenches/ip/dma_flock/scoreboard.sv | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/testbenches/ip/dma_flock/environment.sv b/testbenches/ip/dma_flock/environment.sv index cac44346..6305c7c4 100644 --- a/testbenches/ip/dma_flock/environment.sv +++ b/testbenches/ip/dma_flock/environment.sv @@ -70,7 +70,7 @@ package environment_pkg; this.src_axis_agent = new("Src AXI stream agent", src_axis_vip_if, this); this.dst_axis_agent = new("Dest AXI stream agent", dst_axis_vip_if, this); - this.scrb = new(); + this.scrb = new("Scoreboard", this); endfunction diff --git a/testbenches/ip/dma_flock/scoreboard.sv b/testbenches/ip/dma_flock/scoreboard.sv index 37c3c689..7d532bd2 100644 --- a/testbenches/ip/dma_flock/scoreboard.sv +++ b/testbenches/ip/dma_flock/scoreboard.sv @@ -37,6 +37,7 @@ package scoreboard_pkg; + import adi_common_pkg::*; import xil_common_vip_pkg::*; import axi4stream_vip_pkg::*; import axi_vip_pkg::*; From 41dfa6fa98f19305e724c375438ee2a2e1a850e5 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Tue, 21 Jan 2025 09:04:57 +0200 Subject: [PATCH 13/37] adi_datatypes: Added FIFO and LIFO class implementation Signed-off-by: Istvan-Zsolt Szekely --- library/utilities/adi_datatypes.sv | 160 +++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 library/utilities/adi_datatypes.sv diff --git a/library/utilities/adi_datatypes.sv b/library/utilities/adi_datatypes.sv new file mode 100644 index 00000000..45219c0a --- /dev/null +++ b/library/utilities/adi_datatypes.sv @@ -0,0 +1,160 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +package adi_datatypes_pkg; + + import logger_pkg::*; + import adi_common_pkg::*; + + class adi_fifo #(type data_type = int) extends adi_component; + + local data_type adi_fifo [$]; + local int depth; + + function new( + input string name, + input int depth, + input adi_component parent = null); + + super.new(name, parent); + + this.depth = depth; + endfunction: new + + function bit push(input data_type data); + if (this.adi_fifo.size() == this.depth && this.depth != 0) begin + return 1'b0; + end else begin + this.adi_fifo.push_back(data); + return 1'b1; + end + endfunction: push + + function data_type pop(); + if (this.adi_fifo.size() == 0) begin + return null; + end else begin + return this.adi_fifo.pop_front(); + end + endfunction: pop + + function int room(); + return depth-this.adi_fifo.size(); + endfunction: room + + function int size(); + return this.adi_fifo.size(); + endfunction: room + + function void clear(); + this.adi_fifo.delete(); + endfunction: clear + + function bit insert( + input int index, + input data_type data); + + if (this.adi_fifo.size() == this.depth && this.depth != 0) begin + return 1'b0; + end else begin + this.adi_fifo.insert(index, data); + return 1'b1; + end + endfunction: clear + + endclass: adi_fifo + + + class adi_lifo #(type data_type = int) extends adi_component; + + local data_type adi_fifo [$]; + local int depth; + + function new( + input string name, + input int depth, + input adi_component parent = null); + + super.new(name, parent); + + this.depth = depth; + endfunction: new + + function bit push(input data_type data); + if (this.adi_fifo.size() == this.depth && this.depth != 0) begin + return 1'b0; + end else begin + this.adi_fifo.push_front(data); + return 1'b1; + end + endfunction: push + + function data_type pop(); + if (this.adi_fifo.size() == 0) begin + return null; + end else begin + return this.adi_fifo.pop_front(); + end + endfunction: pop + + function int room(); + return depth-this.adi_fifo.size(); + endfunction: room + + function int size(); + return this.adi_fifo.size(); + endfunction: room + + function void clear(); + this.adi_fifo.delete(); + endfunction: clear + + function bit insert( + input int index, + input data_type data); + + if (this.adi_fifo.size() == this.depth && this.depth != 0) begin + return 1'b0; + end else begin + this.adi_fifo.insert(index, data); + return 1'b1; + end + endfunction: clear + + endclass: adi_lifo + +endpackage: adi_datatypes_pkg From 2991e44bd30c819b79aa27c0a32120e8a1379450 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Thu, 30 Jan 2025 09:04:46 +0200 Subject: [PATCH 14/37] infrastructure refactorization: Minor fixes Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/scoreboard/environment.sv | 2 +- testbenches/project/ad57xx/ad57xx_environment.sv | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv index 8efbe384..36a298c1 100644 --- a/testbenches/ip/scoreboard/environment.sv +++ b/testbenches/ip/scoreboard/environment.sv @@ -18,7 +18,7 @@ package environment_pkg; import scoreboard_pkg::*; - class scoreboard_environment #(`AXIS_VIP_PARAM_DECL(adc_src), `AXIS_VIP_PARAM_DECL(dac_dst), `AXIS_VIP_PARAM_DECL(adc_dst_pt), `AXIS_VIP_PARAM_DECL(dac_src_pt)) extends adi_environment; + class scoreboard_environment #(`AXIS_VIP_PARAM_DECL(adc_src), `AXIS_VIP_PARAM_DECL(dac_dst), `AXI_VIP_PARAM_DECL(adc_dst_pt), `AXI_VIP_PARAM_DECL(dac_src_pt)) extends adi_environment; // Agents adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(adc_src)) adc_src_axis_agent; diff --git a/testbenches/project/ad57xx/ad57xx_environment.sv b/testbenches/project/ad57xx/ad57xx_environment.sv index 51e4c0cb..7ed92c78 100644 --- a/testbenches/project/ad57xx/ad57xx_environment.sv +++ b/testbenches/project/ad57xx/ad57xx_environment.sv @@ -59,8 +59,9 @@ package ad57xx_environment_pkg; function new( input string name, - virtual interface spi_vip_if #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_s_vip_if - ); + virtual interface spi_vip_if #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_s_vip_if); + + super.new(name); // Creating the agents this.spi_agent = new("SPI VIP Agent", spi_s_vip_if, this); @@ -82,7 +83,7 @@ package ad57xx_environment_pkg; //============================================================================ // Stop subroutine //============================================================================ - task stop; + task stop(); this.spi_agent.stop(); endtask From 1fe651d27f4646cc312f245bd784b338be106acb Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Fri, 18 Oct 2024 14:46:39 +0100 Subject: [PATCH 15/37] util_axis_fifo_asym: Initial testbench commit Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/util_axis_fifo_asym/Makefile | 59 +++ testbenches/ip/util_axis_fifo_asym/README.md | 27 ++ .../ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl | 28 ++ .../ip/util_axis_fifo_asym/environment.sv | 188 +++++++++ .../ip/util_axis_fifo_asym/system_bd.tcl | 99 +++++ .../ip/util_axis_fifo_asym/system_project.tcl | 49 +++ .../ip/util_axis_fifo_asym/system_tb.sv | 56 +++ .../util_axis_fifo_asym/tests/test_program.sv | 116 ++++++ .../util_axis_fifo_asym/waves/cfg_rand.wcfg | 369 ++++++++++++++++++ 9 files changed, 991 insertions(+) create mode 100644 testbenches/ip/util_axis_fifo_asym/Makefile create mode 100644 testbenches/ip/util_axis_fifo_asym/README.md create mode 100644 testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl create mode 100644 testbenches/ip/util_axis_fifo_asym/environment.sv create mode 100644 testbenches/ip/util_axis_fifo_asym/system_bd.tcl create mode 100644 testbenches/ip/util_axis_fifo_asym/system_project.tcl create mode 100644 testbenches/ip/util_axis_fifo_asym/system_tb.sv create mode 100644 testbenches/ip/util_axis_fifo_asym/tests/test_program.sv create mode 100644 testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg diff --git a/testbenches/ip/util_axis_fifo_asym/Makefile b/testbenches/ip/util_axis_fifo_asym/Makefile new file mode 100644 index 00000000..ec82fca6 --- /dev/null +++ b/testbenches/ip/util_axis_fifo_asym/Makefile @@ -0,0 +1,59 @@ +#################################################################################### +#################################################################################### +## Copyright 2022(c) Analog Devices, Inc. +#################################################################################### +#################################################################################### + +# All test-bench dependencies except test programs +SV_DEPS += ../../../library/utilities/utils.svh +SV_DEPS += ../../../library/utilities/logger_pkg.sv +SV_DEPS += ../../../library/regmaps/reg_accessor.sv +SV_DEPS += ../../../library/vip/amd/m_axis_sequencer.sv +SV_DEPS += ../../../library/vip/amd/s_axis_sequencer.sv +SV_DEPS += ../../../library/vip/amd/m_axi_sequencer.sv +SV_DEPS += ../../../library/vip/amd/s_axi_sequencer.sv +SV_DEPS += ../../../library/utilities/test_harness_env.sv +SV_DEPS += ../../../library/regmaps/adi_peripheral_pkg.sv +SV_DEPS += ../../../library/regmaps/adi_regmap_pkg.sv +SV_DEPS += ../../../library/drivers/common/mailbox.sv +SV_DEPS += ../../../library/drivers/common/x_monitor.sv +SV_DEPS += ../../../library/drivers/common/scoreboard.sv +SV_DEPS += ../../../library/drivers/common/filter.sv +SV_DEPS += ../../../library/drivers/common/interfaces.svh +SV_DEPS += ../../../library/drivers/common/watchdog.sv +SV_DEPS += environment.sv +SV_DEPS += system_tb.sv + +ENV_DEPS += system_project.tcl +ENV_DEPS += system_bd.tcl +ENV_DEPS += ../../../scripts/adi_sim.tcl +ENV_DEPS += ../../../scripts/run_sim.tcl + +LIB_DEPS := util_cdc +LIB_DEPS += util_axis_fifo +LIB_DEPS += util_axis_fifo_asym + +# default test program +TP := test_program + +# config files should have the following format +# cfg__.tcl +CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) +#$(warning $(CFG_FILES)) + +# List of tests and configuration combinations that has to be run +# Format is: : +TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP)) + +include ../../../scripts/project-sim.mk + +# usage : +# +# run specific test on a specific configuration in gui mode +# make CFG=cfg2_fsync TST=test_frame_delay MODE=gui +# +# run all test from a configuration +# make cfg1_mm2mm_default + +#################################################################################### +#################################################################################### diff --git a/testbenches/ip/util_axis_fifo_asym/README.md b/testbenches/ip/util_axis_fifo_asym/README.md new file mode 100644 index 00000000..f1495cb4 --- /dev/null +++ b/testbenches/ip/util_axis_fifo_asym/README.md @@ -0,0 +1,27 @@ +Usage : + +Run all tests in batch mode: + + make + + +Run all tests in GUI mode: + + make MODE=gui + + +Run specific test on a specific configuration in gui mode: + + make CFG= TST= MODE=gui + + +Run all test from a configuration: + + make + + +Where: + + * is a file from the cfgs directory without the tcl extension of format cfg\* + * is a file from the tests directory without the tcl extension + diff --git a/testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl b/testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl new file mode 100644 index 00000000..632414e6 --- /dev/null +++ b/testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl @@ -0,0 +1,28 @@ +global ad_project_params + +set random_width [expr int(8*pow(2, int(7.0*rand()+1)))] +set INPUT_WIDTH $random_width +set ad_project_params(INPUT_WIDTH) $INPUT_WIDTH + +set random_width [expr int(8*pow(2, int(7.0*rand()+1)))] +set OUTPUT_WIDTH $random_width +set ad_project_params(OUTPUT_WIDTH) $OUTPUT_WIDTH + +set FIFO_LIMITED [expr int(rand()*2)] +set ad_project_params(FIFO_LIMITED) $FIFO_LIMITED + +if {$FIFO_LIMITED} { + if {$INPUT_WIDTH > $OUTPUT_WIDTH} { + set RATIO $INPUT_WIDTH/$OUTPUT_WIDTH + } else { + set RATIO $OUTPUT_WIDTH/$INPUT_WIDTH + } +} else { + set RATIO 1 +} + +set random_width [expr int(int(log($RATIO)/log(2))+4.0*rand()+1)] +set ad_project_params(ADDRESS_WIDTH) $random_width + +set ad_project_params(INPUT_CLK) [expr int(rand()*9000)+1000] +set ad_project_params(OUTPUT_CLK) [expr int(rand()*9000)+1000] diff --git a/testbenches/ip/util_axis_fifo_asym/environment.sv b/testbenches/ip/util_axis_fifo_asym/environment.sv new file mode 100644 index 00000000..d31cfd8c --- /dev/null +++ b/testbenches/ip/util_axis_fifo_asym/environment.sv @@ -0,0 +1,188 @@ +`include "utils.svh" + +package environment_pkg; + + import m_axi_sequencer_pkg::*; + import s_axi_sequencer_pkg::*; + import m_axis_sequencer_pkg::*; + import s_axis_sequencer_pkg::*; + import logger_pkg::*; + + import axi_vip_pkg::*; + import axi4stream_vip_pkg::*; + import test_harness_env_pkg::*; + import scoreboard_pkg::*; + import x_monitor_pkg::*; + + import `PKGIFY(test_harness, mng_axi_vip)::*; + import `PKGIFY(test_harness, ddr_axi_vip)::*; + + import `PKGIFY(test_harness, input_axis)::*; + import `PKGIFY(test_harness, output_axis)::*; + + class environment extends test_harness_env; + + virtual interface clk_if input_clk_if; + virtual interface clk_if output_clk_if; + + // agents and sequencers + `AGENT(test_harness, input_axis, mst_t) input_axis_agent; + `AGENT(test_harness, output_axis, slv_t) output_axis_agent; + + m_axis_sequencer #(`AGENT(test_harness, input_axis, mst_t), + `AXIS_VIP_PARAMS(test_harness, input_axis) + ) input_axis_seq; + s_axis_sequencer #(`AGENT(test_harness, output_axis, slv_t)) output_axis_seq; + + x_axis_monitor #(`AGENT(test_harness, input_axis, mst_t)) input_axis_mon; + x_axis_monitor #(`AGENT(test_harness, output_axis, slv_t)) output_axis_mon; + + scoreboard scoreboard_inst; + + //============================================================================ + // Constructor + //============================================================================ + function new ( + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, + + virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, + + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, + + virtual interface clk_if input_clk_if, + virtual interface clk_if output_clk_if, + + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, input_axis)) input_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, output_axis)) output_axis_vip_if + ); + + // creating the agents + super.new(sys_clk_vip_if, + dma_clk_vip_if, + ddr_clk_vip_if, + sys_rst_vip_if, + mng_vip_if, + ddr_vip_if); + + this.input_clk_if = input_clk_if; + this.output_clk_if = output_clk_if; + + input_axis_agent = new("Input AXI Stream Agent", input_axis_vip_if); + output_axis_agent = new("Output AXI Stream Agent", output_axis_vip_if); + + input_axis_seq = new(input_axis_agent); + output_axis_seq = new(output_axis_agent); + + input_axis_mon = new("Input AXIS Transaction Monitor", input_axis_agent); + output_axis_mon = new("Output AXIS Transaction Monitor", output_axis_agent); + + scoreboard_inst = new("Verification Environment Scoreboard"); + + endfunction + + //============================================================================ + // Configure environment + //============================================================================ + task configure(); + + // configuration for input + this.input_axis_seq.set_stop_policy(STOP_POLICY_PACKET); + this.input_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); + this.input_axis_seq.set_descriptor_gen_mode(1); + this.input_axis_seq.set_data_beat_delay(0); + this.input_axis_seq.set_descriptor_delay(0); + this.input_axis_seq.set_inactive_drive_output_0(); + + // configuration for output + this.output_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + + // this.output_axis_seq.set_use_variable_ranges(); + // this.output_axis_seq.set_high_time_range(1,1); + // this.output_axis_seq.set_low_time_range(0,0); + + // this.output_axis_seq.clr_use_variable_ranges(); + // this.output_axis_seq.set_high_time(1); + // this.output_axis_seq.set_low_time(1); + + endtask + + //============================================================================ + // Start environment + // - Connect all the agents to the scoreboard + // - Start the agents + //============================================================================ + task start(); + + super.start(); + + input_clk_if.start_clock(`INPUT_CLK); + output_clk_if.start_clock(`OUTPUT_CLK); + + input_axis_agent.start_master(); + output_axis_agent.start_slave(); + + scoreboard_inst.set_source_stream(input_axis_mon); + scoreboard_inst.set_sink_stream(output_axis_mon); + + endtask + + //============================================================================ + // Start the test + // - start the RX scoreboard and sequencer + // - start the TX scoreboard and sequencer + // - setup the RX DMA + // - setup the TX DMA + //============================================================================ + task test(); + + fork + input_axis_seq.run(); + output_axis_seq.run(); + + input_axis_mon.run(); + output_axis_mon.run(); + + scoreboard_inst.run(); + join_none + + endtask + + + //============================================================================ + // Post test subroutine + //============================================================================ + task post_test(); + // Evaluate the scoreboard's results + endtask + + //============================================================================ + // Run subroutine + //============================================================================ + task run; + + //pre_test(); + test(); + + endtask + + //============================================================================ + // Stop subroutine + //============================================================================ + task stop; + + super.stop(); + + input_axis_seq.stop(); + input_axis_agent.stop_master(); + output_axis_agent.stop_slave(); + + post_test(); + + endtask + + endclass + +endpackage diff --git a/testbenches/ip/util_axis_fifo_asym/system_bd.tcl b/testbenches/ip/util_axis_fifo_asym/system_bd.tcl new file mode 100644 index 00000000..2e33dd51 --- /dev/null +++ b/testbenches/ip/util_axis_fifo_asym/system_bd.tcl @@ -0,0 +1,99 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# +# In this HDL repository, there are many different and unique modules, consisting +# of various HDL (Verilog or VHDL) components. The individual modules are +# developed independently, and may be accompanied by separate and unique license +# terms. +# +# The user should read each of these license terms, and understand the +# freedoms and responsibilities that he or she has by using this source/core. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. +# +# Redistribution and use of source or resulting binaries, with or without modification +# of this file, are permitted under one of the following two license terms: +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory +# of this repository (LICENSE_GPL2), and also online at: +# +# +# OR +# +# 2. An ADI specific BSD license, which can be found in the top level directory +# of this repository (LICENSE_ADIBSD), and also on-line at: +# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# This will allow to generate bit files and not release the source code, +# as long as it attaches to an ADI device. +# +# *************************************************************************** +# *************************************************************************** + +global ad_hdl_dir + +source ../../../../scripts/adi_env.tcl + +# system level parameters +global ad_project_params + +set INPUT_WIDTH $ad_project_params(INPUT_WIDTH) +set OUTPUT_WIDTH $ad_project_params(OUTPUT_WIDTH) +set FIFO_LIMITED $ad_project_params(FIFO_LIMITED) +set ADDRESS_WIDTH $ad_project_params(ADDRESS_WIDTH) + +# input clock and reset +create_bd_port -dir I input_clk + +# output clock and reset +create_bd_port -dir I output_clk + + +ad_ip_instance util_axis_fifo_asym util_axis_fifo_asym_DUT [list \ + ASYNC_CLK 1 \ + S_DATA_WIDTH $INPUT_WIDTH \ + ADDRESS_WIDTH $ADDRESS_WIDTH \ + M_DATA_WIDTH $OUTPUT_WIDTH \ + M_AXIS_REGISTERED 1 \ + ALMOST_EMPTY_THRESHOLD 16 \ + ALMOST_FULL_THRESHOLD 16 \ + TLAST_EN 1 \ + TKEEP_EN 1 \ + FIFO_LIMITED $FIFO_LIMITED \ + ADDRESS_WIDTH_PERSPECTIVE 0 \ +] + +ad_connect input_clk util_axis_fifo_asym_DUT/s_axis_aclk +ad_connect sys_cpu_resetn util_axis_fifo_asym_DUT/s_axis_aresetn + +ad_connect output_clk util_axis_fifo_asym_DUT/m_axis_aclk +ad_connect sys_cpu_resetn util_axis_fifo_asym_DUT/m_axis_aresetn + +ad_ip_instance axi4stream_vip input_axis [list \ + INTERFACE_MODE {MASTER} \ + HAS_TREADY {1} \ + HAS_TLAST {1} \ + HAS_TKEEP {1} \ + TDATA_NUM_BYTES [expr {$INPUT_WIDTH/8}] \ +] +adi_sim_add_define "INPUT_AXIS=input_axis" + +ad_connect input_clk input_axis/aclk +ad_connect sys_cpu_resetn input_axis/aresetn + +ad_connect util_axis_fifo_asym_DUT/s_axis input_axis/m_axis + +ad_ip_instance axi4stream_vip output_axis [list \ + INTERFACE_MODE {SLAVE} \ + TDATA_NUM_BYTES [expr {$OUTPUT_WIDTH/8}] \ + HAS_TLAST {1} \ +] +adi_sim_add_define "OUTPUT_AXIS=output_axis" + +ad_connect output_clk output_axis/aclk +ad_connect sys_cpu_resetn output_axis/aresetn + +ad_connect util_axis_fifo_asym_DUT/m_axis output_axis/s_axis diff --git a/testbenches/ip/util_axis_fifo_asym/system_project.tcl b/testbenches/ip/util_axis_fifo_asym/system_project.tcl new file mode 100644 index 00000000..4245b0ec --- /dev/null +++ b/testbenches/ip/util_axis_fifo_asym/system_project.tcl @@ -0,0 +1,49 @@ +source ../../../scripts/adi_sim.tcl +source ../../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +if {$argc < 1} { + puts "Expecting at least one argument that specifies the test configuration" + exit 1 +} else { + set cfg_file [lindex $argv 0] +} + +# Read config file +source "cfgs/${cfg_file}" + +global ad_project_params + +# Set the project name +set project_name [file rootname $cfg_file] + +# Create the project +adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" + +# Add test files to the project +adi_sim_project_files [list \ + "../../../library/utilities/utils.svh" \ + "../../../library/utilities/logger_pkg.sv" \ + "../../../library/regmaps/reg_accessor.sv" \ + "../../../library/vip/amd/m_axis_sequencer.sv" \ + "../../../library/vip/amd/s_axis_sequencer.sv" \ + "../../../library/vip/amd/m_axi_sequencer.sv" \ + "../../../library/vip/amd/s_axi_sequencer.sv" \ + "../../../library/regmaps/adi_peripheral_pkg.sv" \ + "../../../library/regmaps/adi_regmap_pkg.sv" \ + "../../../library/utilities/test_harness_env.sv" \ + "../../../library/drivers/common/mailbox.sv" \ + "../../../library/drivers/common/x_monitor.sv" \ + "../../../library/drivers/common/scoreboard.sv" \ + "../../../library/drivers/common/filter.sv" \ + "../../../library/drivers/common/interfaces.svh" \ + "../../../library/drivers/common/watchdog.sv" \ + "environment.sv" \ + "tests/test_program.sv" \ + "system_tb.sv" \ + ] + +#set a default test program +adi_sim_add_define "TEST_PROGRAM=test_program" + +adi_sim_generate $project_name diff --git a/testbenches/ip/util_axis_fifo_asym/system_tb.sv b/testbenches/ip/util_axis_fifo_asym/system_tb.sv new file mode 100644 index 00000000..ea79f943 --- /dev/null +++ b/testbenches/ip/util_axis_fifo_asym/system_tb.sv @@ -0,0 +1,56 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +`include "utils.svh" +`include "interfaces.svh" + +module system_tb(); + + clk_if input_clk_if(); + clk_if output_clk_if(); + + `TEST_PROGRAM test( + .input_clk_if(input_clk_if), + .output_clk_if(output_clk_if) + ); + + test_harness `TH ( + .input_clk (input_clk_if.clk), + .output_clk (output_clk_if.clk) + ); + +endmodule diff --git a/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv new file mode 100644 index 00000000..10814784 --- /dev/null +++ b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv @@ -0,0 +1,116 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// +// +// +`include "utils.svh" + +import axi_vip_pkg::*; +import axi4stream_vip_pkg::*; +import logger_pkg::*; +import environment_pkg::*; +import m_axis_sequencer_pkg::*; +import s_axis_sequencer_pkg::*; +import watchdog_pkg::*; + +program test_program ( + clk_if input_clk_if, + clk_if output_clk_if); + + // declare the class instances + environment env; + + watchdog send_data_wd; + + initial begin + + // create environment + env = new(`TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF, + + input_clk_if, + output_clk_if, + + `TH.`INPUT_AXIS.inst.IF, + `TH.`OUTPUT_AXIS.inst.IF + ); + + setLoggerVerbosity(5); + + env.start(); + env.sys_reset(); + + env.configure(); + + env.run(); + + send_data_wd = new(500000, "Send data"); + + send_data_wd.start(); + + env.input_axis_seq.start(); + + // stimulus + repeat($urandom_range(5,13)) begin + send_data_wd.reset(); + + repeat($urandom_range(1,5)) + env.input_axis_seq.add_xfer_descriptor($urandom_range(1,1000), 1, 0); + + #($urandom_range(1,10)*1us); + + env.input_axis_seq.clear_descriptor_queue(); + + #1us; + + env.scoreboard_inst.wait_until_complete(); + + `INFOV(("Packet finished."), 5); + end + + send_data_wd.stop(); + + env.stop(); + + `INFO(("Test bench done!")); + $finish(); + + end + +endprogram diff --git a/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg b/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg new file mode 100644 index 00000000..235e962d --- /dev/null +++ b/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg @@ -0,0 +1,369 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + m_axis_aclk + m_axis_aclk + + + m_axis_aresetn + m_axis_aresetn + + + M_AXIS + M_AXIS + true + STYLE_ENUM_TRANSACTION + fff,fff=blank + true + #00E600 + /system_tb/test_harness/input_axis/M_AXIS.streamWaveData + 2 + /system_tb/test_harness/input_axis/M_AXIS.linkStarve + #99E600 + /system_tb/test_harness/input_axis/M_AXIS.linkStall + #E64C00 + /system_tb/test_harness/input_axis/M_AXIS.streamTooltipData + + + s_axis_aclk + s_axis_aclk + + + s_axis_aresetn + s_axis_aresetn + + + S_AXIS + S_AXIS + true + STYLE_ENUM_TRANSACTION + fff,fff=blank + true + #00E600 + /system_tb/test_harness/output_axis/S_AXIS.streamWaveData + 2 + /system_tb/test_harness/output_axis/S_AXIS.linkStarve + #99E600 + /system_tb/test_harness/output_axis/S_AXIS.linkStall + #E64C00 + /system_tb/test_harness/output_axis/S_AXIS.streamTooltipData + + + SLAVE + label + + + Slave + label + + Blk0 + label + + + s_axis_aclk + s_axis_aclk + + + s_axis_aresetn + s_axis_aresetn + + + s_axis_ready + s_axis_ready + + + s_axis_valid + s_axis_valid + + + s_axis_data[63:0] + s_axis_data[63:0] + + + s_axis_tkeep[7:0] + s_axis_tkeep[7:0] + + + s_axis_tlast + s_axis_tlast + + + s_axis_room[4:0] + s_axis_room[4:0] + + + s_axis_full + s_axis_full + + + s_axis_almost_full + s_axis_almost_full + + + Blk1 + label + + + s_axis_aclk + s_axis_aclk + + + s_axis_aresetn + s_axis_aresetn + + + s_axis_ready + s_axis_ready + + + s_axis_valid + s_axis_valid + + + s_axis_data[63:0] + s_axis_data[63:0] + + + s_axis_tkeep[7:0] + s_axis_tkeep[7:0] + + + s_axis_tlast + s_axis_tlast + + + s_axis_room[4:0] + s_axis_room[4:0] + + + s_axis_full + s_axis_full + + + s_axis_almost_full + s_axis_almost_full + + + Higher + label + + + s_axis_counter[0:0] + s_axis_counter[0:0] + + + s_axis_ready_int_s[1:0] + s_axis_ready_int_s[1:0] + + + s_axis_valid_int_s[1:0] + s_axis_valid_int_s[1:0] + + + s_axis_data_int_s[127:0] + s_axis_data_int_s[127:0] + + + s_axis_tkeep_int_s[15:0] + s_axis_tkeep_int_s[15:0] + + + s_axis_tlast_int_s[1:0] + s_axis_tlast_int_s[1:0] + + + s_axis_full_int_s[1:0] + s_axis_full_int_s[1:0] + + + s_axis_almost_full_int_s[1:0] + s_axis_almost_full_int_s[1:0] + + + s_axis_room_int_s[9:0] + s_axis_room_int_s[9:0] + + + \small_slave.s_axis_valid_int_d [1:0] + \small_slave.s_axis_valid_int_d [1:0] + + + + MASTER + label + + + Master + label + + Blk0 + label + + + m_axis_aclk + m_axis_aclk + + + m_axis_aresetn + m_axis_aresetn + + + m_axis_ready + m_axis_ready + + + m_axis_valid + m_axis_valid + + + m_axis_data[63:0] + m_axis_data[63:0] + + + m_axis_tkeep[7:0] + m_axis_tkeep[7:0] + + + m_axis_tlast + m_axis_tlast + + + m_axis_level[4:0] + m_axis_level[4:0] + + + m_axis_empty + m_axis_empty + + + m_axis_almost_empty + m_axis_almost_empty + + + Blk1 + label + + + m_axis_aclk + m_axis_aclk + + + m_axis_aresetn + m_axis_aresetn + + + m_axis_ready + m_axis_ready + + + m_axis_valid + m_axis_valid + + + m_axis_data[63:0] + m_axis_data[63:0] + + + m_axis_tkeep[7:0] + m_axis_tkeep[7:0] + + + m_axis_tlast + m_axis_tlast + + + m_axis_level[4:0] + m_axis_level[4:0] + + + m_axis_empty + m_axis_empty + + + m_axis_almost_empty + m_axis_almost_empty + + + Higher + label + + + m_axis_counter[0:0] + m_axis_counter[0:0] + + + m_axis_ready_int_s[1:0] + m_axis_ready_int_s[1:0] + + + m_axis_valid_int_s[1:0] + m_axis_valid_int_s[1:0] + + + m_axis_data_int_s[127:0] + m_axis_data_int_s[127:0] + + + m_axis_tkeep_int_s[15:0] + m_axis_tkeep_int_s[15:0] + + + m_axis_tlast_int_s[1:0] + m_axis_tlast_int_s[1:0] + + + m_axis_empty_int_s[1:0] + m_axis_empty_int_s[1:0] + + + m_axis_almost_empty_int_s[1:0] + m_axis_almost_empty_int_s[1:0] + + + m_axis_level_int_s[9:0] + m_axis_level_int_s[9:0] + + + From fc60809a5c4615dba3d87534f35ef5f520fbb775 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Wed, 22 Jan 2025 08:28:26 +0200 Subject: [PATCH 16/37] util_axis_fifo_asym: Updated after rebase Signed-off-by: Istvan-Zsolt Szekely --- library/drivers/common/watchdog.sv | 2 +- library/utilities/test_harness_env.sv | 16 +- .../ip/scoreboard/tests/test_program.sv | 2 +- testbenches/ip/util_axis_fifo_asym/Makefile | 30 +-- .../ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl | 26 ++- .../ip/util_axis_fifo_asym/environment.sv | 178 +++++------------- .../ip/util_axis_fifo_asym/system_bd.tcl | 69 ++++--- .../ip/util_axis_fifo_asym/system_project.tcl | 30 +-- .../ip/util_axis_fifo_asym/system_tb.sv | 14 +- .../util_axis_fifo_asym/tests/test_program.sv | 92 +++++---- 10 files changed, 200 insertions(+), 259 deletions(-) diff --git a/library/drivers/common/watchdog.sv b/library/drivers/common/watchdog.sv index ed09fda6..5d377358 100644 --- a/library/drivers/common/watchdog.sv +++ b/library/drivers/common/watchdog.sv @@ -82,7 +82,7 @@ package watchdog_pkg; fork begin #(this.timer*1ns); - this.error($sformatf("Watchdog timer timed out! %s", this.message)); + this.fatal($sformatf("Watchdog timer timed out! %s", this.message)); end @this.stop_event; join_any diff --git a/library/utilities/test_harness_env.sv b/library/utilities/test_harness_env.sv index 3f05d8b2..50c2566f 100644 --- a/library/utilities/test_harness_env.sv +++ b/library/utilities/test_harness_env.sv @@ -91,9 +91,9 @@ package test_harness_env_pkg; this.mng.agent.start_master(); this.ddr.agent.start_slave(); - this.sys_clk_vip_if.start_clock; - this.dma_clk_vip_if.start_clock; - this.ddr_clk_vip_if.start_clock; + this.sys_clk_vip_if.start_clock(); + this.dma_clk_vip_if.start_clock(); + this.ddr_clk_vip_if.start_clock(); endtask //============================================================================ @@ -103,9 +103,9 @@ package test_harness_env_pkg; this.mng.agent.stop_master(); this.ddr.agent.stop_slave(); - this.sys_clk_vip_if.stop_clock; - this.dma_clk_vip_if.stop_clock; - this.ddr_clk_vip_if.stop_clock; + this.sys_clk_vip_if.stop_clock(); + this.dma_clk_vip_if.stop_clock(); + this.ddr_clk_vip_if.stop_clock(); endtask //============================================================================ @@ -113,9 +113,9 @@ package test_harness_env_pkg; //============================================================================ task sys_reset(); //asserts all the resets for 100 ns - this.sys_rst_vip_if.assert_reset; + this.sys_rst_vip_if.assert_reset(); #200; - this.sys_rst_vip_if.deassert_reset; + this.sys_rst_vip_if.deassert_reset(); #800; endtask diff --git a/testbenches/ip/scoreboard/tests/test_program.sv b/testbenches/ip/scoreboard/tests/test_program.sv index 962c573f..dc821f98 100644 --- a/testbenches/ip/scoreboard/tests/test_program.sv +++ b/testbenches/ip/scoreboard/tests/test_program.sv @@ -60,7 +60,7 @@ import `PKGIFY(test_harness, dac_src_axi_pt_1)::*; `define ADC_TRANSFER_LENGTH 32'h600 -program test_program; +program test_program(); // declare the class instances test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; diff --git a/testbenches/ip/util_axis_fifo_asym/Makefile b/testbenches/ip/util_axis_fifo_asym/Makefile index ec82fca6..72f90010 100644 --- a/testbenches/ip/util_axis_fifo_asym/Makefile +++ b/testbenches/ip/util_axis_fifo_asym/Makefile @@ -4,30 +4,14 @@ #################################################################################### #################################################################################### -# All test-bench dependencies except test programs -SV_DEPS += ../../../library/utilities/utils.svh -SV_DEPS += ../../../library/utilities/logger_pkg.sv -SV_DEPS += ../../../library/regmaps/reg_accessor.sv -SV_DEPS += ../../../library/vip/amd/m_axis_sequencer.sv -SV_DEPS += ../../../library/vip/amd/s_axis_sequencer.sv -SV_DEPS += ../../../library/vip/amd/m_axi_sequencer.sv -SV_DEPS += ../../../library/vip/amd/s_axi_sequencer.sv -SV_DEPS += ../../../library/utilities/test_harness_env.sv -SV_DEPS += ../../../library/regmaps/adi_peripheral_pkg.sv -SV_DEPS += ../../../library/regmaps/adi_regmap_pkg.sv -SV_DEPS += ../../../library/drivers/common/mailbox.sv -SV_DEPS += ../../../library/drivers/common/x_monitor.sv -SV_DEPS += ../../../library/drivers/common/scoreboard.sv -SV_DEPS += ../../../library/drivers/common/filter.sv -SV_DEPS += ../../../library/drivers/common/interfaces.svh -SV_DEPS += ../../../library/drivers/common/watchdog.sv -SV_DEPS += environment.sv -SV_DEPS += system_tb.sv +# Makeincludes +include ../../../scripts/make_tb_path.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_common.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_axis.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_scoreboard.mk -ENV_DEPS += system_project.tcl -ENV_DEPS += system_bd.tcl -ENV_DEPS += ../../../scripts/adi_sim.tcl -ENV_DEPS += ../../../scripts/run_sim.tcl +# Remaining test-bench dependencies except test programs +SV_DEPS += environment.sv LIB_DEPS := util_cdc LIB_DEPS += util_axis_fifo diff --git a/testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl b/testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl index 632414e6..9cfd760c 100644 --- a/testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl +++ b/testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl @@ -1,5 +1,14 @@ global ad_project_params +set async_clk [expr int(rand()*2)] +set ad_project_params(ASYNC_CLK) $async_clk + +set tkeep_en [expr int(rand()*2)] +set ad_project_params(TKEEP_EN) $tkeep_en + +set tlast_en [expr int(rand()*2)] +set ad_project_params(TLAST_EN) $tlast_en + set random_width [expr int(8*pow(2, int(7.0*rand()+1)))] set INPUT_WIDTH $random_width set ad_project_params(INPUT_WIDTH) $INPUT_WIDTH @@ -8,10 +17,10 @@ set random_width [expr int(8*pow(2, int(7.0*rand()+1)))] set OUTPUT_WIDTH $random_width set ad_project_params(OUTPUT_WIDTH) $OUTPUT_WIDTH -set FIFO_LIMITED [expr int(rand()*2)] -set ad_project_params(FIFO_LIMITED) $FIFO_LIMITED +set fifo_limited [expr int(rand()*2)] +set ad_project_params(FIFO_LIMITED) $fifo_limited -if {$FIFO_LIMITED} { +if {$fifo_limited} { if {$INPUT_WIDTH > $OUTPUT_WIDTH} { set RATIO $INPUT_WIDTH/$OUTPUT_WIDTH } else { @@ -24,5 +33,12 @@ if {$FIFO_LIMITED} { set random_width [expr int(int(log($RATIO)/log(2))+4.0*rand()+1)] set ad_project_params(ADDRESS_WIDTH) $random_width -set ad_project_params(INPUT_CLK) [expr int(rand()*9000)+1000] -set ad_project_params(OUTPUT_CLK) [expr int(rand()*9000)+1000] +set input_clk [expr int(rand()*9)+1] +set ad_project_params(INPUT_CLK) $input_clk + +if {$async_clk} { + set output_clk [expr int(rand()*9)+1] + set ad_project_params(OUTPUT_CLK) $output_clk +} else { + set ad_project_params(OUTPUT_CLK) $input_clk +} diff --git a/testbenches/ip/util_axis_fifo_asym/environment.sv b/testbenches/ip/util_axis_fifo_asym/environment.sv index d31cfd8c..cff284f7 100644 --- a/testbenches/ip/util_axis_fifo_asym/environment.sv +++ b/testbenches/ip/util_axis_fifo_asym/environment.sv @@ -1,112 +1,72 @@ `include "utils.svh" +`include "axis_definitions.svh" package environment_pkg; - import m_axi_sequencer_pkg::*; - import s_axi_sequencer_pkg::*; - import m_axis_sequencer_pkg::*; - import s_axis_sequencer_pkg::*; import logger_pkg::*; - - import axi_vip_pkg::*; + import adi_common_pkg::*; import axi4stream_vip_pkg::*; - import test_harness_env_pkg::*; + import m_axis_sequencer_pkg::*; + import s_axis_sequencer_pkg::*; + import adi_axis_agent_pkg::*; import scoreboard_pkg::*; - import x_monitor_pkg::*; - import `PKGIFY(test_harness, mng_axi_vip)::*; - import `PKGIFY(test_harness, ddr_axi_vip)::*; + class util_axis_fifo_environment #(`AXIS_VIP_PARAM_DECL(input_axis), `AXIS_VIP_PARAM_DECL(output_axis), int INPUT_CLK, int OUTPUT_CLK) extends adi_environment; - import `PKGIFY(test_harness, input_axis)::*; - import `PKGIFY(test_harness, output_axis)::*; + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(INPUT_CLK)) input_clk_vip_if; + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(OUTPUT_CLK)) output_clk_vip_if; - class environment extends test_harness_env; + adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(input_axis)) input_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAM_ORDER(output_axis)) output_axis_agent; - virtual interface clk_if input_clk_if; - virtual interface clk_if output_clk_if; - - // agents and sequencers - `AGENT(test_harness, input_axis, mst_t) input_axis_agent; - `AGENT(test_harness, output_axis, slv_t) output_axis_agent; - - m_axis_sequencer #(`AGENT(test_harness, input_axis, mst_t), - `AXIS_VIP_PARAMS(test_harness, input_axis) - ) input_axis_seq; - s_axis_sequencer #(`AGENT(test_harness, output_axis, slv_t)) output_axis_seq; - - x_axis_monitor #(`AGENT(test_harness, input_axis, mst_t)) input_axis_mon; - x_axis_monitor #(`AGENT(test_harness, output_axis, slv_t)) output_axis_mon; - - scoreboard scoreboard_inst; + scoreboard #(logic [7:0]) scoreboard_inst; //============================================================================ // Constructor //============================================================================ function new ( - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, - - virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, + input string name, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(INPUT_CLK)) input_clk_vip_if, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(OUTPUT_CLK)) output_clk_vip_if, - virtual interface clk_if input_clk_if, - virtual interface clk_if output_clk_if, - - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, input_axis)) input_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, output_axis)) output_axis_vip_if - ); + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(input_axis)) input_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(output_axis)) output_axis_vip_if); // creating the agents - super.new(sys_clk_vip_if, - dma_clk_vip_if, - ddr_clk_vip_if, - sys_rst_vip_if, - mng_vip_if, - ddr_vip_if); - - this.input_clk_if = input_clk_if; - this.output_clk_if = output_clk_if; - - input_axis_agent = new("Input AXI Stream Agent", input_axis_vip_if); - output_axis_agent = new("Output AXI Stream Agent", output_axis_vip_if); + super.new(name); - input_axis_seq = new(input_axis_agent); - output_axis_seq = new(output_axis_agent); + this.input_clk_vip_if = input_clk_vip_if; + this.output_clk_vip_if = output_clk_vip_if; - input_axis_mon = new("Input AXIS Transaction Monitor", input_axis_agent); - output_axis_mon = new("Output AXIS Transaction Monitor", output_axis_agent); - - scoreboard_inst = new("Verification Environment Scoreboard"); + this.input_axis_agent = new("Input AXI Stream Agent", input_axis_vip_if, this); + this.output_axis_agent = new("Output AXI Stream Agent", output_axis_vip_if, this); + this.scoreboard_inst = new("Util AXIS FIFO Scoreboard", this); endfunction //============================================================================ // Configure environment //============================================================================ task configure(); - // configuration for input - this.input_axis_seq.set_stop_policy(STOP_POLICY_PACKET); - this.input_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - this.input_axis_seq.set_descriptor_gen_mode(1); - this.input_axis_seq.set_data_beat_delay(0); - this.input_axis_seq.set_descriptor_delay(0); - this.input_axis_seq.set_inactive_drive_output_0(); + this.input_axis_agent.sequencer.set_stop_policy(STOP_POLICY_PACKET); + this.input_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); + this.input_axis_agent.sequencer.set_descriptor_gen_mode(1); + this.input_axis_agent.sequencer.set_data_beat_delay(0); + this.input_axis_agent.sequencer.set_descriptor_delay(0); + this.input_axis_agent.sequencer.set_inactive_drive_output_0(); // configuration for output - this.output_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + this.output_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); - // this.output_axis_seq.set_use_variable_ranges(); - // this.output_axis_seq.set_high_time_range(1,1); - // this.output_axis_seq.set_low_time_range(0,0); - - // this.output_axis_seq.clr_use_variable_ranges(); - // this.output_axis_seq.set_high_time(1); - // this.output_axis_seq.set_low_time(1); + // this.output_axis_agent.sequencer.set_use_variable_ranges(); + // this.output_axis_agent.sequencer.set_high_time_range(1,1); + // this.output_axis_agent.sequencer.set_low_time_range(0,0); + // this.output_axis_agent.sequencer.clr_use_variable_ranges(); + // this.output_axis_agent.sequencer.set_high_time(1); + // this.output_axis_agent.sequencer.set_low_time(1); endtask //============================================================================ @@ -115,72 +75,38 @@ package environment_pkg; // - Start the agents //============================================================================ task start(); + this.input_clk_vip_if.start_clock(); + this.output_clk_vip_if.start_clock(); - super.start(); - - input_clk_if.start_clock(`INPUT_CLK); - output_clk_if.start_clock(`OUTPUT_CLK); - - input_axis_agent.start_master(); - output_axis_agent.start_slave(); - - scoreboard_inst.set_source_stream(input_axis_mon); - scoreboard_inst.set_sink_stream(output_axis_mon); + this.input_axis_agent.agent.start_master(); + this.output_axis_agent.agent.start_slave(); + this.input_axis_agent.monitor.publisher.subscribe(this.scoreboard_inst.subscriber_source); + this.output_axis_agent.monitor.publisher.subscribe(this.scoreboard_inst.subscriber_sink); endtask //============================================================================ - // Start the test - // - start the RX scoreboard and sequencer - // - start the TX scoreboard and sequencer - // - setup the RX DMA - // - setup the TX DMA + // Run subroutine //============================================================================ - task test(); - + task run(); fork - input_axis_seq.run(); - output_axis_seq.run(); + this.input_axis_agent.sequencer.run(); + this.output_axis_agent.sequencer.run(); - input_axis_mon.run(); - output_axis_mon.run(); + this.input_axis_agent.monitor.run(); + this.output_axis_agent.monitor.run(); - scoreboard_inst.run(); + this.scoreboard_inst.run(); join_none - - endtask - - - //============================================================================ - // Post test subroutine - //============================================================================ - task post_test(); - // Evaluate the scoreboard's results - endtask - - //============================================================================ - // Run subroutine - //============================================================================ - task run; - - //pre_test(); - test(); - endtask //============================================================================ // Stop subroutine //============================================================================ - task stop; - - super.stop(); - - input_axis_seq.stop(); - input_axis_agent.stop_master(); - output_axis_agent.stop_slave(); - - post_test(); - + task stop(); + this.input_axis_agent.sequencer.stop(); + this.input_axis_agent.agent.stop_master(); + this.output_axis_agent.agent.stop_slave(); endtask endclass diff --git a/testbenches/ip/util_axis_fifo_asym/system_bd.tcl b/testbenches/ip/util_axis_fifo_asym/system_bd.tcl index 2e33dd51..66fd1740 100644 --- a/testbenches/ip/util_axis_fifo_asym/system_bd.tcl +++ b/testbenches/ip/util_axis_fifo_asym/system_bd.tcl @@ -33,67 +33,94 @@ # *************************************************************************** # *************************************************************************** -global ad_hdl_dir - -source ../../../../scripts/adi_env.tcl - -# system level parameters global ad_project_params +set ASYNC_CLK $ad_project_params(ASYNC_CLK) +set TKEEP_EN $ad_project_params(TKEEP_EN) +set TLAST_EN $ad_project_params(TLAST_EN) set INPUT_WIDTH $ad_project_params(INPUT_WIDTH) set OUTPUT_WIDTH $ad_project_params(OUTPUT_WIDTH) set FIFO_LIMITED $ad_project_params(FIFO_LIMITED) set ADDRESS_WIDTH $ad_project_params(ADDRESS_WIDTH) +set INPUT_CLK $ad_project_params(INPUT_CLK) +set OUTPUT_CLK $ad_project_params(OUTPUT_CLK) + +# Input clock +ad_ip_instance clk_vip input_clk_vip [ list \ + INTERFACE_MODE {MASTER} \ + FREQ_HZ [expr pow(10, 9)/$INPUT_CLK] \ +] +adi_sim_add_define "INPUT_CLK_VIP=input_clk_vip" + +ad_ip_instance clk_vip output_clk_vip [ list \ + INTERFACE_MODE {MASTER} \ + FREQ_HZ [expr pow(10, 9)/$OUTPUT_CLK] \ +] +adi_sim_add_define "OUTPUT_CLK_VIP=output_clk_vip" + +ad_connect input_clk input_clk_vip/clk_out +ad_connect output_clk output_clk_vip/clk_out + +ad_ip_instance proc_sys_reset input_rstgen +ad_ip_parameter input_rstgen CONFIG.C_EXT_RST_WIDTH 1 + +ad_ip_instance proc_sys_reset output_rstgen +ad_ip_parameter output_rstgen CONFIG.C_EXT_RST_WIDTH 1 -# input clock and reset -create_bd_port -dir I input_clk +ad_connect sys_rst_vip/rst_out input_rstgen/ext_reset_in +ad_connect sys_rst_vip/rst_out output_rstgen/ext_reset_in -# output clock and reset -create_bd_port -dir I output_clk +ad_connect input_clk input_rstgen/slowest_sync_clk +ad_connect output_clk output_rstgen/slowest_sync_clk +ad_connect input_resetn input_rstgen/peripheral_aresetn +ad_connect output_resetn output_rstgen/peripheral_aresetn ad_ip_instance util_axis_fifo_asym util_axis_fifo_asym_DUT [list \ - ASYNC_CLK 1 \ + ASYNC_CLK $ASYNC_CLK \ S_DATA_WIDTH $INPUT_WIDTH \ ADDRESS_WIDTH $ADDRESS_WIDTH \ M_DATA_WIDTH $OUTPUT_WIDTH \ M_AXIS_REGISTERED 1 \ - ALMOST_EMPTY_THRESHOLD 16 \ - ALMOST_FULL_THRESHOLD 16 \ - TLAST_EN 1 \ - TKEEP_EN 1 \ + ALMOST_EMPTY_THRESHOLD 0 \ + ALMOST_FULL_THRESHOLD 0 \ + TLAST_EN $TLAST_EN \ + TKEEP_EN $TKEEP_EN \ FIFO_LIMITED $FIFO_LIMITED \ ADDRESS_WIDTH_PERSPECTIVE 0 \ ] ad_connect input_clk util_axis_fifo_asym_DUT/s_axis_aclk -ad_connect sys_cpu_resetn util_axis_fifo_asym_DUT/s_axis_aresetn +ad_connect input_resetn util_axis_fifo_asym_DUT/s_axis_aresetn ad_connect output_clk util_axis_fifo_asym_DUT/m_axis_aclk -ad_connect sys_cpu_resetn util_axis_fifo_asym_DUT/m_axis_aresetn +ad_connect output_resetn util_axis_fifo_asym_DUT/m_axis_aresetn ad_ip_instance axi4stream_vip input_axis [list \ INTERFACE_MODE {MASTER} \ HAS_TREADY {1} \ - HAS_TLAST {1} \ - HAS_TKEEP {1} \ + TDEST_WIDTH {0} \ + TID_WIDTH {0} \ + HAS_TLAST $TLAST_EN \ + HAS_TKEEP $TKEEP_EN \ TDATA_NUM_BYTES [expr {$INPUT_WIDTH/8}] \ ] adi_sim_add_define "INPUT_AXIS=input_axis" ad_connect input_clk input_axis/aclk -ad_connect sys_cpu_resetn input_axis/aresetn +ad_connect input_resetn input_axis/aresetn ad_connect util_axis_fifo_asym_DUT/s_axis input_axis/m_axis ad_ip_instance axi4stream_vip output_axis [list \ INTERFACE_MODE {SLAVE} \ + HAS_TLAST $TLAST_EN \ + HAS_TKEEP $TKEEP_EN \ TDATA_NUM_BYTES [expr {$OUTPUT_WIDTH/8}] \ - HAS_TLAST {1} \ ] adi_sim_add_define "OUTPUT_AXIS=output_axis" ad_connect output_clk output_axis/aclk -ad_connect sys_cpu_resetn output_axis/aresetn +ad_connect output_resetn output_axis/aresetn ad_connect util_axis_fifo_asym_DUT/m_axis output_axis/s_axis diff --git a/testbenches/ip/util_axis_fifo_asym/system_project.tcl b/testbenches/ip/util_axis_fifo_asym/system_project.tcl index 4245b0ec..86b8f596 100644 --- a/testbenches/ip/util_axis_fifo_asym/system_project.tcl +++ b/testbenches/ip/util_axis_fifo_asym/system_project.tcl @@ -1,6 +1,4 @@ source ../../../scripts/adi_sim.tcl -source ../../../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl if {$argc < 1} { puts "Expecting at least one argument that specifies the test configuration" @@ -12,36 +10,20 @@ if {$argc < 1} { # Read config file source "cfgs/${cfg_file}" -global ad_project_params - # Set the project name set project_name [file rootname $cfg_file] # Create the project adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" +source $ad_tb_dir/library/includes/sp_include_axis.tcl +source $ad_tb_dir/library/includes/sp_include_scoreboard.tcl + # Add test files to the project adi_sim_project_files [list \ - "../../../library/utilities/utils.svh" \ - "../../../library/utilities/logger_pkg.sv" \ - "../../../library/regmaps/reg_accessor.sv" \ - "../../../library/vip/amd/m_axis_sequencer.sv" \ - "../../../library/vip/amd/s_axis_sequencer.sv" \ - "../../../library/vip/amd/m_axi_sequencer.sv" \ - "../../../library/vip/amd/s_axi_sequencer.sv" \ - "../../../library/regmaps/adi_peripheral_pkg.sv" \ - "../../../library/regmaps/adi_regmap_pkg.sv" \ - "../../../library/utilities/test_harness_env.sv" \ - "../../../library/drivers/common/mailbox.sv" \ - "../../../library/drivers/common/x_monitor.sv" \ - "../../../library/drivers/common/scoreboard.sv" \ - "../../../library/drivers/common/filter.sv" \ - "../../../library/drivers/common/interfaces.svh" \ - "../../../library/drivers/common/watchdog.sv" \ - "environment.sv" \ - "tests/test_program.sv" \ - "system_tb.sv" \ - ] + "environment.sv" \ + "tests/test_program.sv" \ +] #set a default test program adi_sim_add_define "TEST_PROGRAM=test_program" diff --git a/testbenches/ip/util_axis_fifo_asym/system_tb.sv b/testbenches/ip/util_axis_fifo_asym/system_tb.sv index ea79f943..e92f32ea 100644 --- a/testbenches/ip/util_axis_fifo_asym/system_tb.sv +++ b/testbenches/ip/util_axis_fifo_asym/system_tb.sv @@ -36,21 +36,11 @@ `timescale 1ns/1ps `include "utils.svh" -`include "interfaces.svh" module system_tb(); - clk_if input_clk_if(); - clk_if output_clk_if(); + `TEST_PROGRAM test(); - `TEST_PROGRAM test( - .input_clk_if(input_clk_if), - .output_clk_if(output_clk_if) - ); - - test_harness `TH ( - .input_clk (input_clk_if.clk), - .output_clk (output_clk_if.clk) - ); + test_harness `TH (); endmodule diff --git a/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv index 10814784..8608bb06 100644 --- a/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv +++ b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv @@ -36,79 +36,95 @@ // // `include "utils.svh" +`include "axis_definitions.svh" -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; +import test_harness_env_pkg::*; import environment_pkg::*; -import m_axis_sequencer_pkg::*; -import s_axis_sequencer_pkg::*; import watchdog_pkg::*; -program test_program ( - clk_if input_clk_if, - clk_if output_clk_if); +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +import `PKGIFY(test_harness, input_axis)::*; +import `PKGIFY(test_harness, output_axis)::*; + +program test_program (); // declare the class instances - environment env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + util_axis_fifo_environment #(`AXIS_VIP_PARAMS(test_harness, input_axis), `AXIS_VIP_PARAMS(test_harness, output_axis), `INPUT_CLK, `OUTPUT_CLK) uaf_env; watchdog send_data_wd; initial begin // create environment - env = new(`TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - - input_clk_if, - output_clk_if, - - `TH.`INPUT_AXIS.inst.IF, - `TH.`OUTPUT_AXIS.inst.IF - ); - - setLoggerVerbosity(5); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + uaf_env = new("Util AXIS FIFO Environment", + `TH.`INPUT_CLK_VIP.inst.IF, + `TH.`OUTPUT_CLK_VIP.inst.IF, + `TH.`INPUT_AXIS.inst.IF, + `TH.`OUTPUT_AXIS.inst.IF); + + setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.sys_reset(); + base_env.start(); + uaf_env.start(); + + base_env.sys_reset(); - env.configure(); + uaf_env.configure(); + uaf_env.input_axis_agent.sequencer.set_keep_some(); - env.run(); + uaf_env.run(); - send_data_wd = new(500000, "Send data"); + send_data_wd = new("Util AXIS FIFO Watchdog", 500000, "Send data"); send_data_wd.start(); - env.input_axis_seq.start(); + uaf_env.input_axis_agent.sequencer.start(); // stimulus - repeat($urandom_range(5,13)) begin + repeat($urandom_range(5,10)) begin send_data_wd.reset(); - repeat($urandom_range(1,5)) - env.input_axis_seq.add_xfer_descriptor($urandom_range(1,1000), 1, 0); + if ((!`TKEEP_EN || !`TLAST_EN) && `INPUT_WIDTH < `OUTPUT_WIDTH) begin + repeat($urandom_range(1,5)) begin + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_packet_size($urandom_range(1,128)*`OUTPUT_WIDTH/`INPUT_WIDTH, `TLAST_EN, 0); + end + end else begin + repeat($urandom_range(1,5)) begin + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor($urandom_range(1,1024), `TLAST_EN, 0); + end + end #($urandom_range(1,10)*1us); - env.input_axis_seq.clear_descriptor_queue(); + uaf_env.input_axis_agent.sequencer.clear_descriptor_queue(); #1us; - env.scoreboard_inst.wait_until_complete(); + uaf_env.scoreboard_inst.wait_until_complete(); - `INFOV(("Packet finished."), 5); + `INFO(("Packet finished."), ADI_VERBOSITY_LOW); end send_data_wd.stop(); - - env.stop(); + + #100ns; + + uaf_env.stop(); + base_env.stop(); - `INFO(("Test bench done!")); + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); end From 2693a758811ab7d55b71cfc7347451fe5dc8cda1 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Wed, 22 Jan 2025 13:11:47 +0200 Subject: [PATCH 17/37] util_axis_fifo_asym: Updates and fixes - Extended the ADI agent with additional functions - Fixes issues with the AXIS VIP sequencer - Updated the testbench Signed-off-by: Istvan-Zsolt Szekely --- library/vip/amd/axis/adi_axis_agent.sv | 48 ++++ library/vip/amd/axis/adi_axis_monitor.sv | 22 +- library/vip/amd/axis/m_axis_sequencer.sv | 72 +++--- .../ip/util_axis_fifo_asym/environment.sv | 16 +- .../util_axis_fifo_asym/tests/test_program.sv | 3 +- .../util_axis_fifo_asym/waves/cfg_rand.wcfg | 210 ++++++------------ 6 files changed, 193 insertions(+), 178 deletions(-) diff --git a/library/vip/amd/axis/adi_axis_agent.sv b/library/vip/amd/axis/adi_axis_agent.sv index 621ff43f..3fd767db 100644 --- a/library/vip/amd/axis/adi_axis_agent.sv +++ b/library/vip/amd/axis/adi_axis_agent.sv @@ -64,6 +64,21 @@ package adi_axis_agent_pkg; this.monitor = new("Monitor", this.agent.monitor, this); endfunction: new + task start(); + this.agent.start_master(); + endtask: start + + task run(); + this.sequencer.run(); + this.monitor.run(); + endtask: run + + task stop(); + this.monitor.stop(); + this.sequencer.stop(); + this.agent.stop_master(); + endtask: stop + endclass: adi_axis_master_agent @@ -85,12 +100,28 @@ package adi_axis_agent_pkg; this.monitor = new("Monitor", this.agent.monitor, this); endfunction: new + task start(); + this.agent.start_slave(); + endtask: start + + task run(); + this.sequencer.run(); + this.monitor.run(); + endtask: run + + task stop(); + this.monitor.stop(); + this.agent.stop_slave(); + endtask: stop + endclass: adi_axis_slave_agent class adi_axis_passthrough_mem_agent #(`AXIS_VIP_PARAM_DECL(passthrough)) extends adi_agent; axi4stream_passthrough_agent #(`AXIS_VIP_IF_PARAMS(passthrough)) agent; + m_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(passthrough)) master_sequencer; + s_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(passthrough)) slave_sequencer; adi_axis_monitor #(`AXIS_VIP_PARAM_ORDER(passthrough)) monitor; function new( @@ -104,6 +135,23 @@ package adi_axis_agent_pkg; this.monitor = new("Monitor", this.agent.monitor, this); endfunction: new + task start(); + this.warning($sformatf("Start must called manually in the test program or environment")); + endtask: start + + task run(); + this.master_sequencer.run(); + this.slave_sequencer.run(); + this.monitor.run(); + endtask: run + + task stop(); + this.monitor.stop(); + this.master_sequencer.stop(); + this.agent.stop_slave(); + this.agent.stop_master(); + endtask: stop + endclass: adi_axis_passthrough_mem_agent endpackage diff --git a/library/vip/amd/axis/adi_axis_monitor.sv b/library/vip/amd/axis/adi_axis_monitor.sv index e2a4ba55..77b5d3a5 100644 --- a/library/vip/amd/axis/adi_axis_monitor.sv +++ b/library/vip/amd/axis/adi_axis_monitor.sv @@ -15,6 +15,7 @@ package adi_axis_monitor_pkg; adi_publisher #(logic [7:0]) publisher; protected bit enabled; + protected event enable_ev; // constructor function new( @@ -37,14 +38,27 @@ package adi_axis_monitor_pkg; return; end - fork - this.get_transaction(); - join_none - this.enabled = 1; this.info($sformatf("Monitor enabled"), ADI_VERBOSITY_MEDIUM); + + fork + begin + this.get_transaction(); + end + begin + if (this.enabled == 1) begin + @enable_ev; + end + disable fork; + end + join_none endtask: run + function void stop(); + this.enabled = 0; + -> enable_ev; + endfunction: stop + // collect data from the AXI4Strean interface of the stub, this task // handles both ONESHOT and CYCLIC scenarios task get_transaction(); diff --git a/library/vip/amd/axis/m_axis_sequencer.sv b/library/vip/amd/axis/m_axis_sequencer.sv index 8a3155ef..3cc86628 100644 --- a/library/vip/amd/axis/m_axis_sequencer.sv +++ b/library/vip/amd/axis/m_axis_sequencer.sv @@ -49,7 +49,6 @@ package m_axis_sequencer_pkg; } data_gen_mode_t; typedef enum bit [1:0] { - STOP_POLICY_IMMEDIATE = 2'h0, // disable as soon as possible STOP_POLICY_DATA_BEAT = 2'h1, // disable after the data beat has been transferred STOP_POLICY_PACKET = 2'h2, // disable after the packet has been transferred STOP_POLICY_DESCRIPTOR_QUEUE = 2'h3 // disable after the packet queue has been transferred @@ -117,21 +116,26 @@ package m_axis_sequencer_pkg; // set vif proxy to drive outputs with 0 when inactive virtual task set_inactive_drive_output_0(); + this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); endtask: set_inactive_drive_output_0 // check if ready is asserted virtual function bit check_ready_asserted(); + this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); endfunction: check_ready_asserted // wait for set amount of clock cycles virtual task wait_clk_count(input int wait_clocks); + this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); endtask: wait_clk_count // pack the byte stream into transfers(beats) then in packets by setting the tlast virtual protected task packetize(); + this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); endtask: packetize virtual protected task sender(); + this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); endtask: sender // create transfer based on data beats per packet @@ -139,8 +143,20 @@ package m_axis_sequencer_pkg; input int data_beats_per_packet, input int gen_tlast = 1, input int gen_sync = 1); + + this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); endfunction: add_xfer_descriptor_packet_size + // wait until data beat is sent + virtual task beat_sent(); + this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + endtask: beat_sent + + // wait until packet is sent + virtual task packet_sent(); + this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + endtask: packet_sent + // set disable policy function void set_stop_policy(input stop_policy_t stop_policy); @@ -216,16 +232,6 @@ package m_axis_sequencer_pkg; wait_clk_count(descriptor_delay); endtask: descriptor_delay_subroutine - // wait until data beat is sent - task beat_sent(); - @beat_done; - endtask: beat_sent - - // wait until packet is sent - task packet_sent(); - @packet_done; - endtask: packet_sent - // wait until queue is empty task wait_empty_descriptor_queue(); if (this.queue_empty_sig) @@ -249,13 +255,11 @@ package m_axis_sequencer_pkg; fork begin @disable_ev; - if (this.queue_empty_sig == 0) - case (stop_policy) - STOP_POLICY_DESCRIPTOR_QUEUE: @queue_empty; - STOP_POLICY_PACKET: @packet_done; - STOP_POLICY_DATA_BEAT: @beat_done; - STOP_POLICY_IMMEDIATE: ; - endcase + case (stop_policy) + STOP_POLICY_DESCRIPTOR_QUEUE: wait_empty_descriptor_queue(); + STOP_POLICY_PACKET: packet_sent(); + STOP_POLICY_DATA_BEAT: beat_sent(); + endcase end forever begin if (descriptor_q.size() > 0) begin @@ -330,6 +334,22 @@ package m_axis_sequencer_pkg; endfunction: new + // wait until data beat is sent + virtual task beat_sent(); + if (this.driver.is_driver_idle()) begin + return; + end + @beat_done; + endtask: beat_sent + + // wait until packet is sent + virtual task packet_sent(); + if (this.driver.is_driver_idle() && this.trans.get_last()) begin + return; + end + @packet_done; + endtask: packet_sent + // create transfer based on data beats per packet virtual function void add_xfer_descriptor_packet_size( input int data_beats_per_packet, @@ -443,7 +463,6 @@ package m_axis_sequencer_pkg; this.info($sformatf("waiting transfer to complete"), ADI_VERBOSITY_HIGH); @beat_done; end - ->> packet_done; endtask: packetize // packet sender function @@ -457,19 +476,20 @@ package m_axis_sequencer_pkg; fork begin @disable_ev; - if (this.queue_empty_sig == 0) - case (stop_policy) - STOP_POLICY_DESCRIPTOR_QUEUE: @queue_empty; - STOP_POLICY_PACKET: @packet_done; - STOP_POLICY_DATA_BEAT: @beat_done; - STOP_POLICY_IMMEDIATE: ; - endcase + case (stop_policy) + STOP_POLICY_DESCRIPTOR_QUEUE: wait_empty_descriptor_queue(); + STOP_POLICY_PACKET: packet_sent(); + STOP_POLICY_DATA_BEAT: beat_sent(); + endcase end forever begin @data_av_ev; this.info($sformatf("sending axis transaction"), ADI_VERBOSITY_HIGH); this.driver.send(trans); ->> beat_done; + if (this.trans.get_last()) begin + ->> packet_done; + end end join_any disable fork; diff --git a/testbenches/ip/util_axis_fifo_asym/environment.sv b/testbenches/ip/util_axis_fifo_asym/environment.sv index cff284f7..3c5d6372 100644 --- a/testbenches/ip/util_axis_fifo_asym/environment.sv +++ b/testbenches/ip/util_axis_fifo_asym/environment.sv @@ -78,8 +78,8 @@ package environment_pkg; this.input_clk_vip_if.start_clock(); this.output_clk_vip_if.start_clock(); - this.input_axis_agent.agent.start_master(); - this.output_axis_agent.agent.start_slave(); + this.input_axis_agent.start(); + this.output_axis_agent.start(); this.input_axis_agent.monitor.publisher.subscribe(this.scoreboard_inst.subscriber_source); this.output_axis_agent.monitor.publisher.subscribe(this.scoreboard_inst.subscriber_sink); @@ -90,11 +90,8 @@ package environment_pkg; //============================================================================ task run(); fork - this.input_axis_agent.sequencer.run(); - this.output_axis_agent.sequencer.run(); - - this.input_axis_agent.monitor.run(); - this.output_axis_agent.monitor.run(); + this.input_axis_agent.run(); + this.output_axis_agent.run(); this.scoreboard_inst.run(); join_none @@ -104,9 +101,8 @@ package environment_pkg; // Stop subroutine //============================================================================ task stop(); - this.input_axis_agent.sequencer.stop(); - this.input_axis_agent.agent.stop_master(); - this.output_axis_agent.agent.stop_slave(); + this.input_axis_agent.stop(); + this.output_axis_agent.stop(); endtask endclass diff --git a/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv index 8608bb06..a2fc7226 100644 --- a/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv +++ b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv @@ -109,8 +109,7 @@ program test_program (); #($urandom_range(1,10)*1us); uaf_env.input_axis_agent.sequencer.clear_descriptor_queue(); - - #1us; + uaf_env.input_axis_agent.sequencer.wait_empty_descriptor_queue(); uaf_env.scoreboard_inst.wait_until_complete(); diff --git a/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg b/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg index 235e962d..d6014f4b 100644 --- a/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg +++ b/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg @@ -6,6 +6,11 @@ + + + + + @@ -14,34 +19,30 @@ - + - - - - - + - - - + + + - - + + - + m_axis_aclk m_axis_aclk @@ -118,20 +119,20 @@ s_axis_valid - s_axis_data[63:0] - s_axis_data[63:0] + s_axis_data[127:0] + s_axis_data[127:0] - s_axis_tkeep[7:0] - s_axis_tkeep[7:0] + s_axis_tkeep[15:0] + s_axis_tkeep[15:0] s_axis_tlast s_axis_tlast - s_axis_room[4:0] - s_axis_room[4:0] + s_axis_room[2:0] + s_axis_room[2:0] s_axis_full @@ -145,61 +146,21 @@ Blk1 label - - s_axis_aclk - s_axis_aclk - - - s_axis_aresetn - s_axis_aresetn - - - s_axis_ready - s_axis_ready - - - s_axis_valid - s_axis_valid - - - s_axis_data[63:0] - s_axis_data[63:0] - - - s_axis_tkeep[7:0] - s_axis_tkeep[7:0] - - - s_axis_tlast - s_axis_tlast - - - s_axis_room[4:0] - s_axis_room[4:0] - - - s_axis_full - s_axis_full - - - s_axis_almost_full - s_axis_almost_full - Higher label - s_axis_counter[0:0] - s_axis_counter[0:0] + s_axis_counter[-1:0] + s_axis_counter[-1:0] - s_axis_ready_int_s[1:0] - s_axis_ready_int_s[1:0] + s_axis_ready_int_s[0:0] + s_axis_ready_int_s[0:0] - s_axis_valid_int_s[1:0] - s_axis_valid_int_s[1:0] + s_axis_valid_int_s[0:0] + s_axis_valid_int_s[0:0] s_axis_data_int_s[127:0] @@ -210,24 +171,20 @@ s_axis_tkeep_int_s[15:0] - s_axis_tlast_int_s[1:0] - s_axis_tlast_int_s[1:0] + s_axis_tlast_int_s[0:0] + s_axis_tlast_int_s[0:0] - s_axis_full_int_s[1:0] - s_axis_full_int_s[1:0] + s_axis_full_int_s[0:0] + s_axis_full_int_s[0:0] - s_axis_almost_full_int_s[1:0] - s_axis_almost_full_int_s[1:0] + s_axis_almost_full_int_s[0:0] + s_axis_almost_full_int_s[0:0] - s_axis_room_int_s[9:0] - s_axis_room_int_s[9:0] - - - \small_slave.s_axis_valid_int_d [1:0] - \small_slave.s_axis_valid_int_d [1:0] + s_axis_room_int_s[2:0] + s_axis_room_int_s[2:0] @@ -258,20 +215,20 @@ m_axis_valid - m_axis_data[63:0] - m_axis_data[63:0] + m_axis_data[127:0] + m_axis_data[127:0] - m_axis_tkeep[7:0] - m_axis_tkeep[7:0] + m_axis_tkeep[15:0] + m_axis_tkeep[15:0] m_axis_tlast m_axis_tlast - m_axis_level[4:0] - m_axis_level[4:0] + m_axis_level[2:0] + m_axis_level[2:0] m_axis_empty @@ -285,61 +242,21 @@ Blk1 label - - m_axis_aclk - m_axis_aclk - - - m_axis_aresetn - m_axis_aresetn - - - m_axis_ready - m_axis_ready - - - m_axis_valid - m_axis_valid - - - m_axis_data[63:0] - m_axis_data[63:0] - - - m_axis_tkeep[7:0] - m_axis_tkeep[7:0] - - - m_axis_tlast - m_axis_tlast - - - m_axis_level[4:0] - m_axis_level[4:0] - - - m_axis_empty - m_axis_empty - - - m_axis_almost_empty - m_axis_almost_empty - Higher label - m_axis_counter[0:0] - m_axis_counter[0:0] + m_axis_counter[-1:0] + m_axis_counter[-1:0] - m_axis_ready_int_s[1:0] - m_axis_ready_int_s[1:0] + m_axis_ready_int_s[0:0] + m_axis_ready_int_s[0:0] - m_axis_valid_int_s[1:0] - m_axis_valid_int_s[1:0] + m_axis_valid_int_s[0:0] + m_axis_valid_int_s[0:0] m_axis_data_int_s[127:0] @@ -350,20 +267,41 @@ m_axis_tkeep_int_s[15:0] - m_axis_tlast_int_s[1:0] - m_axis_tlast_int_s[1:0] + m_axis_tlast_int_s[0:0] + m_axis_tlast_int_s[0:0] - m_axis_empty_int_s[1:0] - m_axis_empty_int_s[1:0] + m_axis_empty_int_s[0:0] + m_axis_empty_int_s[0:0] - m_axis_almost_empty_int_s[1:0] - m_axis_almost_empty_int_s[1:0] + m_axis_almost_empty_int_s[0:0] + m_axis_almost_empty_int_s[0:0] - m_axis_level_int_s[9:0] - m_axis_level_int_s[9:0] + m_axis_level_int_s[2:0] + m_axis_level_int_s[2:0] + + true + STYLE_ENUM_TRANSACTION + fff,fff=blank + true + #00E600 + /system_tb/test_harness/util_axis_fifo_asym_DUT/s_axis.streamWaveData + 2 + /system_tb/test_harness/util_axis_fifo_asym_DUT/s_axis.linkStarve + #99E600 + /system_tb/test_harness/util_axis_fifo_asym_DUT/s_axis.linkStall + #E64C00 + /system_tb/test_harness/util_axis_fifo_asym_DUT/s_axis.streamTooltipData + s_axis + s_axis + + + + m_axis + m_axis + From 98691b5d72aa78fd5dcd8627d43c16321227f104 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Wed, 22 Jan 2025 13:36:54 +0200 Subject: [PATCH 18/37] util_axis_fifo_asym: Updated waveform configuration Signed-off-by: Istvan-Zsolt Szekely --- .../util_axis_fifo_asym/waves/cfg_rand.wcfg | 253 +----------------- 1 file changed, 6 insertions(+), 247 deletions(-) diff --git a/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg b/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg index d6014f4b..d556dd92 100644 --- a/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg +++ b/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg @@ -34,255 +34,15 @@ - - - + + + - - + + - - - m_axis_aclk - m_axis_aclk - - - m_axis_aresetn - m_axis_aresetn - - - M_AXIS - M_AXIS - true - STYLE_ENUM_TRANSACTION - fff,fff=blank - true - #00E600 - /system_tb/test_harness/input_axis/M_AXIS.streamWaveData - 2 - /system_tb/test_harness/input_axis/M_AXIS.linkStarve - #99E600 - /system_tb/test_harness/input_axis/M_AXIS.linkStall - #E64C00 - /system_tb/test_harness/input_axis/M_AXIS.streamTooltipData - - - s_axis_aclk - s_axis_aclk - - - s_axis_aresetn - s_axis_aresetn - - - S_AXIS - S_AXIS - true - STYLE_ENUM_TRANSACTION - fff,fff=blank - true - #00E600 - /system_tb/test_harness/output_axis/S_AXIS.streamWaveData - 2 - /system_tb/test_harness/output_axis/S_AXIS.linkStarve - #99E600 - /system_tb/test_harness/output_axis/S_AXIS.linkStall - #E64C00 - /system_tb/test_harness/output_axis/S_AXIS.streamTooltipData - - - SLAVE - label - - - Slave - label - - Blk0 - label - - - s_axis_aclk - s_axis_aclk - - - s_axis_aresetn - s_axis_aresetn - - - s_axis_ready - s_axis_ready - - - s_axis_valid - s_axis_valid - - - s_axis_data[127:0] - s_axis_data[127:0] - - - s_axis_tkeep[15:0] - s_axis_tkeep[15:0] - - - s_axis_tlast - s_axis_tlast - - - s_axis_room[2:0] - s_axis_room[2:0] - - - s_axis_full - s_axis_full - - - s_axis_almost_full - s_axis_almost_full - - - Blk1 - label - - - Higher - label - - - s_axis_counter[-1:0] - s_axis_counter[-1:0] - - - s_axis_ready_int_s[0:0] - s_axis_ready_int_s[0:0] - - - s_axis_valid_int_s[0:0] - s_axis_valid_int_s[0:0] - - - s_axis_data_int_s[127:0] - s_axis_data_int_s[127:0] - - - s_axis_tkeep_int_s[15:0] - s_axis_tkeep_int_s[15:0] - - - s_axis_tlast_int_s[0:0] - s_axis_tlast_int_s[0:0] - - - s_axis_full_int_s[0:0] - s_axis_full_int_s[0:0] - - - s_axis_almost_full_int_s[0:0] - s_axis_almost_full_int_s[0:0] - - - s_axis_room_int_s[2:0] - s_axis_room_int_s[2:0] - - - - MASTER - label - - - Master - label - - Blk0 - label - - - m_axis_aclk - m_axis_aclk - - - m_axis_aresetn - m_axis_aresetn - - - m_axis_ready - m_axis_ready - - - m_axis_valid - m_axis_valid - - - m_axis_data[127:0] - m_axis_data[127:0] - - - m_axis_tkeep[15:0] - m_axis_tkeep[15:0] - - - m_axis_tlast - m_axis_tlast - - - m_axis_level[2:0] - m_axis_level[2:0] - - - m_axis_empty - m_axis_empty - - - m_axis_almost_empty - m_axis_almost_empty - - - Blk1 - label - - - Higher - label - - - m_axis_counter[-1:0] - m_axis_counter[-1:0] - - - m_axis_ready_int_s[0:0] - m_axis_ready_int_s[0:0] - - - m_axis_valid_int_s[0:0] - m_axis_valid_int_s[0:0] - - - m_axis_data_int_s[127:0] - m_axis_data_int_s[127:0] - - - m_axis_tkeep_int_s[15:0] - m_axis_tkeep_int_s[15:0] - - - m_axis_tlast_int_s[0:0] - m_axis_tlast_int_s[0:0] - - - m_axis_empty_int_s[0:0] - m_axis_empty_int_s[0:0] - - - m_axis_almost_empty_int_s[0:0] - m_axis_almost_empty_int_s[0:0] - - - m_axis_level_int_s[2:0] - m_axis_level_int_s[2:0] - - + true STYLE_ENUM_TRANSACTION @@ -298,7 +58,6 @@ /system_tb/test_harness/util_axis_fifo_asym_DUT/s_axis.streamTooltipData s_axis s_axis - m_axis From 2f11dc99c3809956f1312e96e704aaae754b37af Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Wed, 22 Jan 2025 13:40:09 +0200 Subject: [PATCH 19/37] util_axis_fifo: Initial testbench commit Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/util_axis_fifo/Makefile | 42 ++++++ testbenches/ip/util_axis_fifo/README.md | 27 ++++ .../ip/util_axis_fifo/cfgs/cfg_rand.tcl | 27 ++++ testbenches/ip/util_axis_fifo/environment.sv | 110 ++++++++++++++ testbenches/ip/util_axis_fifo/system_bd.tcl | 122 ++++++++++++++++ .../ip/util_axis_fifo/system_project.tcl | 31 ++++ testbenches/ip/util_axis_fifo/system_tb.sv | 46 ++++++ .../ip/util_axis_fifo/tests/test_program.sv | 136 ++++++++++++++++++ .../ip/util_axis_fifo/waves/cfg_rand.wcfg | 66 +++++++++ 9 files changed, 607 insertions(+) create mode 100644 testbenches/ip/util_axis_fifo/Makefile create mode 100644 testbenches/ip/util_axis_fifo/README.md create mode 100644 testbenches/ip/util_axis_fifo/cfgs/cfg_rand.tcl create mode 100644 testbenches/ip/util_axis_fifo/environment.sv create mode 100644 testbenches/ip/util_axis_fifo/system_bd.tcl create mode 100644 testbenches/ip/util_axis_fifo/system_project.tcl create mode 100644 testbenches/ip/util_axis_fifo/system_tb.sv create mode 100644 testbenches/ip/util_axis_fifo/tests/test_program.sv create mode 100644 testbenches/ip/util_axis_fifo/waves/cfg_rand.wcfg diff --git a/testbenches/ip/util_axis_fifo/Makefile b/testbenches/ip/util_axis_fifo/Makefile new file mode 100644 index 00000000..a1d6b38a --- /dev/null +++ b/testbenches/ip/util_axis_fifo/Makefile @@ -0,0 +1,42 @@ +#################################################################################### +#################################################################################### +## Copyright 2022(c) Analog Devices, Inc. +#################################################################################### +#################################################################################### + +# Makeincludes +include ../../../scripts/make_tb_path.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_common.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_axis.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_scoreboard.mk + +# Remaining test-bench dependencies except test programs +SV_DEPS += environment.sv + +LIB_DEPS := util_cdc +LIB_DEPS += util_axis_fifo + +# default test program +TP := test_program + +# config files should have the following format +# cfg__.tcl +CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) +#$(warning $(CFG_FILES)) + +# List of tests and configuration combinations that has to be run +# Format is: : +TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP)) + +include ../../../scripts/project-sim.mk + +# usage : +# +# run specific test on a specific configuration in gui mode +# make CFG=cfg2_fsync TST=test_frame_delay MODE=gui +# +# run all test from a configuration +# make cfg1_mm2mm_default + +#################################################################################### +#################################################################################### diff --git a/testbenches/ip/util_axis_fifo/README.md b/testbenches/ip/util_axis_fifo/README.md new file mode 100644 index 00000000..f1495cb4 --- /dev/null +++ b/testbenches/ip/util_axis_fifo/README.md @@ -0,0 +1,27 @@ +Usage : + +Run all tests in batch mode: + + make + + +Run all tests in GUI mode: + + make MODE=gui + + +Run specific test on a specific configuration in gui mode: + + make CFG= TST= MODE=gui + + +Run all test from a configuration: + + make + + +Where: + + * is a file from the cfgs directory without the tcl extension of format cfg\* + * is a file from the tests directory without the tcl extension + diff --git a/testbenches/ip/util_axis_fifo/cfgs/cfg_rand.tcl b/testbenches/ip/util_axis_fifo/cfgs/cfg_rand.tcl new file mode 100644 index 00000000..157dc77e --- /dev/null +++ b/testbenches/ip/util_axis_fifo/cfgs/cfg_rand.tcl @@ -0,0 +1,27 @@ +global ad_project_params + +set async_clk [expr int(rand()*2)] +set ad_project_params(ASYNC_CLK) $async_clk + +set tkeep_en [expr int(rand()*2)] +set ad_project_params(TKEEP_EN) $tkeep_en + +set tlast_en [expr int(rand()*2)] +set ad_project_params(TLAST_EN) $tlast_en + +set random_width [expr int(8*pow(2, int(7.0*rand()+1)))] +set DATA_WIDTH $random_width +set ad_project_params(DATA_WIDTH) $DATA_WIDTH + +set random_width [expr int(5.0*rand())] +set ad_project_params(ADDRESS_WIDTH) $random_width + +set input_clk [expr int(rand()*9)+1] +set ad_project_params(INPUT_CLK) $input_clk + +if {$async_clk} { + set output_clk [expr int(rand()*9)+1] + set ad_project_params(OUTPUT_CLK) $output_clk +} else { + set ad_project_params(OUTPUT_CLK) $input_clk +} diff --git a/testbenches/ip/util_axis_fifo/environment.sv b/testbenches/ip/util_axis_fifo/environment.sv new file mode 100644 index 00000000..3c5d6372 --- /dev/null +++ b/testbenches/ip/util_axis_fifo/environment.sv @@ -0,0 +1,110 @@ +`include "utils.svh" +`include "axis_definitions.svh" + +package environment_pkg; + + import logger_pkg::*; + import adi_common_pkg::*; + import axi4stream_vip_pkg::*; + import m_axis_sequencer_pkg::*; + import s_axis_sequencer_pkg::*; + import adi_axis_agent_pkg::*; + import scoreboard_pkg::*; + + class util_axis_fifo_environment #(`AXIS_VIP_PARAM_DECL(input_axis), `AXIS_VIP_PARAM_DECL(output_axis), int INPUT_CLK, int OUTPUT_CLK) extends adi_environment; + + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(INPUT_CLK)) input_clk_vip_if; + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(OUTPUT_CLK)) output_clk_vip_if; + + adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(input_axis)) input_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAM_ORDER(output_axis)) output_axis_agent; + + scoreboard #(logic [7:0]) scoreboard_inst; + + //============================================================================ + // Constructor + //============================================================================ + function new ( + input string name, + + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(INPUT_CLK)) input_clk_vip_if, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(OUTPUT_CLK)) output_clk_vip_if, + + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(input_axis)) input_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(output_axis)) output_axis_vip_if); + + // creating the agents + super.new(name); + + this.input_clk_vip_if = input_clk_vip_if; + this.output_clk_vip_if = output_clk_vip_if; + + this.input_axis_agent = new("Input AXI Stream Agent", input_axis_vip_if, this); + this.output_axis_agent = new("Output AXI Stream Agent", output_axis_vip_if, this); + + this.scoreboard_inst = new("Util AXIS FIFO Scoreboard", this); + endfunction + + //============================================================================ + // Configure environment + //============================================================================ + task configure(); + // configuration for input + this.input_axis_agent.sequencer.set_stop_policy(STOP_POLICY_PACKET); + this.input_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); + this.input_axis_agent.sequencer.set_descriptor_gen_mode(1); + this.input_axis_agent.sequencer.set_data_beat_delay(0); + this.input_axis_agent.sequencer.set_descriptor_delay(0); + this.input_axis_agent.sequencer.set_inactive_drive_output_0(); + + // configuration for output + this.output_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + + // this.output_axis_agent.sequencer.set_use_variable_ranges(); + // this.output_axis_agent.sequencer.set_high_time_range(1,1); + // this.output_axis_agent.sequencer.set_low_time_range(0,0); + + // this.output_axis_agent.sequencer.clr_use_variable_ranges(); + // this.output_axis_agent.sequencer.set_high_time(1); + // this.output_axis_agent.sequencer.set_low_time(1); + endtask + + //============================================================================ + // Start environment + // - Connect all the agents to the scoreboard + // - Start the agents + //============================================================================ + task start(); + this.input_clk_vip_if.start_clock(); + this.output_clk_vip_if.start_clock(); + + this.input_axis_agent.start(); + this.output_axis_agent.start(); + + this.input_axis_agent.monitor.publisher.subscribe(this.scoreboard_inst.subscriber_source); + this.output_axis_agent.monitor.publisher.subscribe(this.scoreboard_inst.subscriber_sink); + endtask + + //============================================================================ + // Run subroutine + //============================================================================ + task run(); + fork + this.input_axis_agent.run(); + this.output_axis_agent.run(); + + this.scoreboard_inst.run(); + join_none + endtask + + //============================================================================ + // Stop subroutine + //============================================================================ + task stop(); + this.input_axis_agent.stop(); + this.output_axis_agent.stop(); + endtask + + endclass + +endpackage diff --git a/testbenches/ip/util_axis_fifo/system_bd.tcl b/testbenches/ip/util_axis_fifo/system_bd.tcl new file mode 100644 index 00000000..79aeedc3 --- /dev/null +++ b/testbenches/ip/util_axis_fifo/system_bd.tcl @@ -0,0 +1,122 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# +# In this HDL repository, there are many different and unique modules, consisting +# of various HDL (Verilog or VHDL) components. The individual modules are +# developed independently, and may be accompanied by separate and unique license +# terms. +# +# The user should read each of these license terms, and understand the +# freedoms and responsibilities that he or she has by using this source/core. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. +# +# Redistribution and use of source or resulting binaries, with or without modification +# of this file, are permitted under one of the following two license terms: +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory +# of this repository (LICENSE_GPL2), and also online at: +# +# +# OR +# +# 2. An ADI specific BSD license, which can be found in the top level directory +# of this repository (LICENSE_ADIBSD), and also on-line at: +# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# This will allow to generate bit files and not release the source code, +# as long as it attaches to an ADI device. +# +# *************************************************************************** +# *************************************************************************** + +global ad_project_params + +set ASYNC_CLK $ad_project_params(ASYNC_CLK) +set TKEEP_EN $ad_project_params(TKEEP_EN) +set TLAST_EN $ad_project_params(TLAST_EN) +set DATA_WIDTH $ad_project_params(DATA_WIDTH) +set ADDRESS_WIDTH $ad_project_params(ADDRESS_WIDTH) +set INPUT_CLK $ad_project_params(INPUT_CLK) +set OUTPUT_CLK $ad_project_params(OUTPUT_CLK) + +# Input clock +ad_ip_instance clk_vip input_clk_vip [ list \ + INTERFACE_MODE {MASTER} \ + FREQ_HZ [expr pow(10, 9)/$INPUT_CLK] \ +] +adi_sim_add_define "INPUT_CLK_VIP=input_clk_vip" + +ad_ip_instance clk_vip output_clk_vip [ list \ + INTERFACE_MODE {MASTER} \ + FREQ_HZ [expr pow(10, 9)/$OUTPUT_CLK] \ +] +adi_sim_add_define "OUTPUT_CLK_VIP=output_clk_vip" + +ad_connect input_clk input_clk_vip/clk_out +ad_connect output_clk output_clk_vip/clk_out + +ad_ip_instance proc_sys_reset input_rstgen +ad_ip_parameter input_rstgen CONFIG.C_EXT_RST_WIDTH 1 + +ad_ip_instance proc_sys_reset output_rstgen +ad_ip_parameter output_rstgen CONFIG.C_EXT_RST_WIDTH 1 + +ad_connect sys_rst_vip/rst_out input_rstgen/ext_reset_in +ad_connect sys_rst_vip/rst_out output_rstgen/ext_reset_in + +ad_connect input_clk input_rstgen/slowest_sync_clk +ad_connect output_clk output_rstgen/slowest_sync_clk + +ad_connect input_resetn input_rstgen/peripheral_aresetn +ad_connect output_resetn output_rstgen/peripheral_aresetn + +ad_ip_instance util_axis_fifo util_axis_fifo_DUT [list \ + ASYNC_CLK $ASYNC_CLK \ + DATA_WIDTH $DATA_WIDTH \ + ADDRESS_WIDTH $ADDRESS_WIDTH \ + M_AXIS_REGISTERED 1 \ + ALMOST_EMPTY_THRESHOLD 0 \ + ALMOST_FULL_THRESHOLD 0 \ + TLAST_EN $TLAST_EN \ + TKEEP_EN $TKEEP_EN \ + REMOVE_NULL_BEAT_EN 0 \ +] + +ad_connect input_clk util_axis_fifo_DUT/s_axis_aclk +ad_connect input_resetn util_axis_fifo_DUT/s_axis_aresetn + +ad_connect output_clk util_axis_fifo_DUT/m_axis_aclk +ad_connect output_resetn util_axis_fifo_DUT/m_axis_aresetn + +ad_ip_instance axi4stream_vip input_axis [list \ + INTERFACE_MODE {MASTER} \ + HAS_TREADY {1} \ + TDEST_WIDTH {0} \ + TID_WIDTH {0} \ + HAS_TLAST $TLAST_EN \ + HAS_TKEEP $TKEEP_EN \ + TDATA_NUM_BYTES [expr {$DATA_WIDTH/8}] \ +] +adi_sim_add_define "INPUT_AXIS=input_axis" + +ad_connect input_clk input_axis/aclk +ad_connect input_resetn input_axis/aresetn + +ad_connect util_axis_fifo_DUT/s_axis input_axis/m_axis + +ad_ip_instance axi4stream_vip output_axis [list \ + INTERFACE_MODE {SLAVE} \ + HAS_TLAST $TLAST_EN \ + HAS_TKEEP $TKEEP_EN \ + TDATA_NUM_BYTES [expr {$DATA_WIDTH/8}] \ +] +adi_sim_add_define "OUTPUT_AXIS=output_axis" + +ad_connect output_clk output_axis/aclk +ad_connect output_resetn output_axis/aresetn + +ad_connect util_axis_fifo_DUT/m_axis output_axis/s_axis diff --git a/testbenches/ip/util_axis_fifo/system_project.tcl b/testbenches/ip/util_axis_fifo/system_project.tcl new file mode 100644 index 00000000..86b8f596 --- /dev/null +++ b/testbenches/ip/util_axis_fifo/system_project.tcl @@ -0,0 +1,31 @@ +source ../../../scripts/adi_sim.tcl + +if {$argc < 1} { + puts "Expecting at least one argument that specifies the test configuration" + exit 1 +} else { + set cfg_file [lindex $argv 0] +} + +# Read config file +source "cfgs/${cfg_file}" + +# Set the project name +set project_name [file rootname $cfg_file] + +# Create the project +adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" + +source $ad_tb_dir/library/includes/sp_include_axis.tcl +source $ad_tb_dir/library/includes/sp_include_scoreboard.tcl + +# Add test files to the project +adi_sim_project_files [list \ + "environment.sv" \ + "tests/test_program.sv" \ +] + +#set a default test program +adi_sim_add_define "TEST_PROGRAM=test_program" + +adi_sim_generate $project_name diff --git a/testbenches/ip/util_axis_fifo/system_tb.sv b/testbenches/ip/util_axis_fifo/system_tb.sv new file mode 100644 index 00000000..e92f32ea --- /dev/null +++ b/testbenches/ip/util_axis_fifo/system_tb.sv @@ -0,0 +1,46 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +`include "utils.svh" + +module system_tb(); + + `TEST_PROGRAM test(); + + test_harness `TH (); + +endmodule diff --git a/testbenches/ip/util_axis_fifo/tests/test_program.sv b/testbenches/ip/util_axis_fifo/tests/test_program.sv new file mode 100644 index 00000000..98696ca4 --- /dev/null +++ b/testbenches/ip/util_axis_fifo/tests/test_program.sv @@ -0,0 +1,136 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// +// +// +`include "utils.svh" +`include "axis_definitions.svh" + +import logger_pkg::*; +import test_harness_env_pkg::*; +import environment_pkg::*; +import watchdog_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +import `PKGIFY(test_harness, input_axis)::*; +import `PKGIFY(test_harness, output_axis)::*; + +program test_program (); + + // declare the class instances + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + util_axis_fifo_environment #(`AXIS_VIP_PARAMS(test_harness, input_axis), `AXIS_VIP_PARAMS(test_harness, output_axis), `INPUT_CLK, `OUTPUT_CLK) uaf_env; + + watchdog send_data_wd; + + initial begin + + // create environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + uaf_env = new("Util AXIS FIFO Environment", + `TH.`INPUT_CLK_VIP.inst.IF, + `TH.`OUTPUT_CLK_VIP.inst.IF, + `TH.`INPUT_AXIS.inst.IF, + `TH.`OUTPUT_AXIS.inst.IF); + + setLoggerVerbosity(ADI_VERBOSITY_NONE); + + base_env.start(); + uaf_env.start(); + + base_env.sys_reset(); + + uaf_env.configure(); + + if (!`TKEEP_EN) begin + uaf_env.input_axis_agent.sequencer.set_keep_some(); + end else begin + uaf_env.input_axis_agent.sequencer.set_keep_all(); + end + + uaf_env.run(); + + send_data_wd = new("Util AXIS FIFO Watchdog", 500000, "Send data"); + + send_data_wd.start(); + + uaf_env.input_axis_agent.sequencer.start(); + + // stimulus + repeat($urandom_range(5,10)) begin + send_data_wd.reset(); + + if (!`TKEEP_EN) begin + repeat($urandom_range(1,5)) begin + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_packet_size($urandom_range(1,128), `TLAST_EN, 0); + end + end else begin + repeat($urandom_range(1,5)) begin + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor($urandom_range(1,1024), `TLAST_EN, 0); + end + end + + #($urandom_range(1,10)*1us); + + uaf_env.input_axis_agent.sequencer.clear_descriptor_queue(); + uaf_env.input_axis_agent.sequencer.wait_empty_descriptor_queue(); + + uaf_env.scoreboard_inst.wait_until_complete(); + + `INFO(("Packet finished."), ADI_VERBOSITY_LOW); + end + + send_data_wd.stop(); + + #100ns; + + uaf_env.stop(); + base_env.stop(); + + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); + $finish(); + + end + +endprogram diff --git a/testbenches/ip/util_axis_fifo/waves/cfg_rand.wcfg b/testbenches/ip/util_axis_fifo/waves/cfg_rand.wcfg new file mode 100644 index 00000000..2346364e --- /dev/null +++ b/testbenches/ip/util_axis_fifo/waves/cfg_rand.wcfg @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + STYLE_ENUM_TRANSACTION + fff,fff=blank + true + #00E600 + /system_tb/test_harness/util_axis_fifo_DUT/s_axis.streamWaveData + 2 + /system_tb/test_harness/util_axis_fifo_DUT/s_axis.linkStarve + #99E600 + /system_tb/test_harness/util_axis_fifo_DUT/s_axis.linkStall + #E64C00 + /system_tb/test_harness/util_axis_fifo_DUT/s_axis.streamTooltipData + s_axis + s_axis + + + m_axis + m_axis + + From 76665e5cd975af7e31deb5bc86c6fd2b3bf73cbf Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Wed, 22 Jan 2025 15:39:28 +0200 Subject: [PATCH 20/37] util_axis_fifo: Updated ADI AXI and AXIS agents Signed-off-by: Istvan-Zsolt Szekely --- library/vip/amd/axi/adi_axi_agent.sv | 47 +++++++++++++++++++++++++- library/vip/amd/axi/adi_axi_monitor.sv | 22 +++++++++--- library/vip/amd/axi/m_axi_sequencer.sv | 29 +++++++++------- library/vip/amd/axis/adi_axis_agent.sv | 2 ++ 4 files changed, 82 insertions(+), 18 deletions(-) diff --git a/library/vip/amd/axi/adi_axi_agent.sv b/library/vip/amd/axi/adi_axi_agent.sv index bb6c42d2..cbb78a42 100644 --- a/library/vip/amd/axi/adi_axi_agent.sv +++ b/library/vip/amd/axi/adi_axi_agent.sv @@ -60,10 +60,23 @@ package adi_axi_agent_pkg; super.new(name, parent); this.agent = new("Agent", master_vip_if); - this.sequencer = new("Sequencer", this.agent, this); + this.sequencer = new("Sequencer", this.agent.wr_driver, this.agent.rd_driver, this); this.monitor = new("Monitor TX", this.agent.monitor, this); endfunction: new + task start(); + this.agent.start_master(); + endtask: start + + task run(); + this.monitor.run(); + endtask: run + + task stop(); + this.monitor.stop(); + this.agent.stop_master(); + endtask: stop + endclass: adi_axi_master_agent @@ -85,12 +98,27 @@ package adi_axi_agent_pkg; this.monitor = new("Monitor TX", this.agent.monitor, this); endfunction: new + task start(); + this.agent.start_slave(); + endtask: start + + task run(); + this.monitor.run(); + endtask: run + + task stop(); + this.monitor.stop(); + this.agent.stop_slave(); + endtask: stop + endclass: adi_axi_slave_mem_agent class adi_axi_passthrough_mem_agent #(int `AXI_VIP_PARAM_ORDER(passthrough)) extends adi_agent; axi_passthrough_mem_agent #(`AXI_VIP_PARAM_ORDER(passthrough)) agent; + m_axi_sequencer #(`AXI_VIP_PARAM_ORDER(passthrough)) master_sequencer; + s_axi_sequencer #(`AXI_VIP_PARAM_ORDER(passthrough)) slave_sequencer; adi_axi_monitor #(`AXI_VIP_PARAM_ORDER(passthrough)) monitor; function new( @@ -101,9 +129,26 @@ package adi_axi_agent_pkg; super.new(name, parent); this.agent = new("Agent", passthrough_vip_if); + this.master_sequencer = new("Slave Sequencer", this.agent.mst_wr_driver, this.agent.mst_rd_driver, this); + this.slave_sequencer = new("Slave Sequencer", this.agent.mem_model, this); this.monitor = new("Monitor TX", this.agent.monitor, this); endfunction: new + task start(); + this.warning($sformatf("Start must called manually in the test program or environment")); + endtask: start + + task run(); + this.slave_sequencer.run(); + this.monitor.run(); + endtask: run + + task stop(); + this.monitor.stop(); + this.agent.stop_slave(); + this.agent.stop_master(); + endtask: stop + endclass: adi_axi_passthrough_mem_agent endpackage diff --git a/library/vip/amd/axi/adi_axi_monitor.sv b/library/vip/amd/axi/adi_axi_monitor.sv index 3b227d2f..3603af7f 100644 --- a/library/vip/amd/axi/adi_axi_monitor.sv +++ b/library/vip/amd/axi/adi_axi_monitor.sv @@ -16,6 +16,7 @@ package adi_axi_monitor_pkg; adi_publisher #(logic [7:0]) publisher_rx; protected bit enabled; + protected event enable_ev; // constructor function new( @@ -39,14 +40,27 @@ package adi_axi_monitor_pkg; return; end - fork - this.get_transaction(); - join_none - this.enabled = 1; this.info($sformatf("Monitor enabled"), ADI_VERBOSITY_MEDIUM); + + fork + begin + this.get_transaction(); + end + begin + if (this.enabled == 1) begin + @enable_ev; + end + disable fork; + end + join_none endtask: run + function void stop(); + this.enabled = 0; + -> enable_ev; + endfunction: stop + // collect data from the DDR interface, all WRITE transaction are coming // from the ADC and all READ transactions are going to the DAC task get_transaction(); diff --git a/library/vip/amd/axi/m_axi_sequencer.sv b/library/vip/amd/axi/m_axi_sequencer.sv index f6db767e..b339e2af 100644 --- a/library/vip/amd/axi/m_axi_sequencer.sv +++ b/library/vip/amd/axi/m_axi_sequencer.sv @@ -45,19 +45,22 @@ package m_axi_sequencer_pkg; class m_axi_sequencer #(`AXI_VIP_PARAM_DECL(AXI)) extends reg_accessor; - axi_mst_agent #(`AXI_VIP_PARAM_ORDER(AXI)) agent; + axi_mst_wr_driver #(`AXI_VIP_PARAM_ORDER(AXI)) wr_driver; + axi_mst_rd_driver #(`AXI_VIP_PARAM_ORDER(AXI)) rd_driver; semaphore reader_s; semaphore writer_s; function new( input string name, - input axi_mst_agent #(`AXI_VIP_PARAM_ORDER(AXI)) agent, + input axi_mst_wr_driver #(`AXI_VIP_PARAM_ORDER(AXI)) wr_driver, + input axi_mst_rd_driver #(`AXI_VIP_PARAM_ORDER(AXI)) rd_driver, input adi_agent parent = null); super.new(name, parent); - this.agent = agent; + this.wr_driver = wr_driver; + this.rd_driver = rd_driver; reader_s = new(1); writer_s = new(1); @@ -137,7 +140,7 @@ package m_axi_sequencer_pkg; input bit [63:0] data =0); axi_transaction wr_trans; - wr_trans = agent.wr_driver.create_transaction(name); + wr_trans = wr_driver.create_transaction(name); wr_trans.set_write_cmd(addr, burst, id, len, size); wr_trans.set_prot(prot); wr_trans.set_lock(lock); @@ -145,7 +148,7 @@ package m_axi_sequencer_pkg; wr_trans.set_region(region); wr_trans.set_qos(qos); wr_trans.set_data_block(data); - agent.wr_driver.send(wr_trans); + wr_driver.send(wr_trans); endtask : single_write_transaction_api @@ -164,7 +167,7 @@ package m_axi_sequencer_pkg; input bit [63:0] data =0); axi_transaction wr_trans; - wr_trans = agent.wr_driver.create_transaction(name); + wr_trans = wr_driver.create_transaction(name); wr_trans.set_write_cmd(addr, burst, id, len, size); wr_trans.set_prot(prot); wr_trans.set_lock(lock); @@ -173,8 +176,8 @@ package m_axi_sequencer_pkg; wr_trans.set_qos(qos); wr_trans.set_data_block(data); wr_trans.set_driver_return_item_policy(XIL_AXI_PAYLOAD_RETURN); - agent.wr_driver.send(wr_trans); - agent.wr_driver.wait_rsp(wr_trans); + wr_driver.send(wr_trans); + wr_driver.wait_rsp(wr_trans); endtask : single_write_transaction_readback_api @@ -193,14 +196,14 @@ package m_axi_sequencer_pkg; input xil_axi_data_beat aruser =0); axi_transaction rd_trans; - rd_trans = agent.rd_driver.create_transaction(name); + rd_trans = rd_driver.create_transaction(name); rd_trans.set_read_cmd(addr, burst, id, len, size); rd_trans.set_prot(prot); rd_trans.set_lock(lock); rd_trans.set_cache(cache); rd_trans.set_region(region); rd_trans.set_qos(qos); - agent.rd_driver.send(rd_trans); + rd_driver.send(rd_trans); endtask : single_read_transaction_api task automatic single_read_transaction_readback_api ( @@ -219,7 +222,7 @@ package m_axi_sequencer_pkg; output xil_axi_data_beat Rdatabeat[]); axi_transaction rd_trans; - rd_trans = agent.rd_driver.create_transaction(name); + rd_trans = rd_driver.create_transaction(name); rd_trans.set_driver_return_item_policy(XIL_AXI_PAYLOAD_RETURN); rd_trans.set_read_cmd(addr, burst, id, len, size); rd_trans.set_prot(prot); @@ -227,8 +230,8 @@ package m_axi_sequencer_pkg; rd_trans.set_cache(cache); rd_trans.set_region(region); rd_trans.set_qos(qos); - agent.rd_driver.send(rd_trans); - agent.rd_driver.wait_rsp(rd_trans); + rd_driver.send(rd_trans); + rd_driver.wait_rsp(rd_trans); Rdatabeat = new[rd_trans.get_len()+1]; for( xil_axi_uint beat=0; beat Date: Wed, 22 Jan 2025 18:20:13 +0200 Subject: [PATCH 21/37] util_axis_fifo: Fixed ADI AXI agent run call Signed-off-by: Istvan-Zsolt Szekely --- library/vip/amd/axi/adi_axi_agent.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/library/vip/amd/axi/adi_axi_agent.sv b/library/vip/amd/axi/adi_axi_agent.sv index cbb78a42..ea969ff8 100644 --- a/library/vip/amd/axi/adi_axi_agent.sv +++ b/library/vip/amd/axi/adi_axi_agent.sv @@ -139,7 +139,6 @@ package adi_axi_agent_pkg; endtask: start task run(); - this.slave_sequencer.run(); this.monitor.run(); endtask: run From 8ee0dee20c4bb7a80ac8d534015aa7262d6368ce Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 27 Jan 2025 17:15:22 +0200 Subject: [PATCH 22/37] General updates: - Added/Updated licensce headers - Updated testbench depndencies - Updated class hierarchy Signed-off-by: Istvan-Zsolt Szekely --- library/drivers/common/scoreboard.sv | 35 ++++++ library/drivers/common/scoreboard_pack.sv | 79 ++++++-------- library/drivers/common/watchdog.sv | 5 +- .../drivers/data_offload/data_offload_api.sv | 15 +-- library/drivers/dmac/dma_trans.sv | 4 +- library/drivers/dmac/dmac_api.sv | 15 +-- library/drivers/jesd/adi_jesd204_pkg.sv | 18 +-- library/drivers/xcvr/adi_xcvr_pkg.sv | 15 +-- library/includes/Makeinclude_axi.mk | 3 +- library/includes/Makeinclude_axis.mk | 2 +- library/includes/Makeinclude_common.mk | 4 +- library/includes/Makeinclude_data_offload.mk | 2 +- library/includes/Makeinclude_dmac.mk | 2 +- library/includes/Makeinclude_jesd.mk | 2 +- library/includes/Makeinclude_regmap.mk | 6 +- library/includes/Makeinclude_scoreboard.mk | 2 +- library/includes/Makeinclude_spi_engine.mk | 2 +- library/includes/Makeinclude_tdd.mk | 2 +- library/includes/Makeinclude_xcvr.mk | 2 +- library/includes/sp_include_axi.tcl | 5 +- library/includes/sp_include_axis.tcl | 4 +- library/includes/sp_include_common.tcl | 6 +- library/includes/sp_include_data_offload.tcl | 4 +- library/includes/sp_include_dmac.tcl | 4 +- library/includes/sp_include_jesd.tcl | 4 +- library/includes/sp_include_regmap.tcl | 8 +- library/includes/sp_include_scoreboard.tcl | 4 +- library/includes/sp_include_spi_engine.tcl | 4 +- library/includes/sp_include_tdd.tcl | 4 +- library/includes/sp_include_xcvr.tcl | 4 +- library/regmaps/adi_regmap_adc_pkg.sv | 2 +- library/regmaps/adi_regmap_axi_ad7616_pkg.sv | 2 +- library/regmaps/adi_regmap_clkgen_pkg.sv | 2 +- .../regmaps/adi_regmap_clock_monitor_pkg.sv | 2 +- library/regmaps/adi_regmap_common_pkg.sv | 2 +- library/regmaps/adi_regmap_dac_pkg.sv | 2 +- .../regmaps/adi_regmap_data_offload_pkg.sv | 4 +- library/regmaps/adi_regmap_dmac_pkg.sv | 2 +- library/regmaps/adi_regmap_fan_control_pkg.sv | 2 +- library/regmaps/adi_regmap_gpreg_pkg.sv | 2 +- library/regmaps/adi_regmap_hdmi_pkg.sv | 2 +- .../regmaps/adi_regmap_i3c_controller_pkg.sv | 2 +- library/regmaps/adi_regmap_iodelay_pkg.sv | 2 +- library/regmaps/adi_regmap_jesd_rx_pkg.sv | 2 +- library/regmaps/adi_regmap_jesd_tpl_pkg.sv | 2 +- library/regmaps/adi_regmap_jesd_tx_pkg.sv | 2 +- library/regmaps/adi_regmap_pkg.sv | 4 +- library/regmaps/adi_regmap_pwm_gen_pkg.sv | 2 +- library/regmaps/adi_regmap_spi_engine_pkg.sv | 2 +- library/regmaps/adi_regmap_system_id_pkg.sv | 2 +- library/regmaps/adi_regmap_tdd_gen_pkg.sv | 2 +- library/regmaps/adi_regmap_tdd_trans_pkg.sv | 2 +- library/regmaps/adi_regmap_xcvr_pkg.sv | 2 +- .../adi_api_pkg.sv} | 59 +++++----- library/utilities/adi_common_pkg.sv | 76 +------------ library/utilities/adi_datatypes.sv | 4 +- .../adi_environment_pkg.sv} | 34 +++--- .../adi_vip_pkg.sv} | 57 ++++++---- library/utilities/logger_pkg.sv | 4 +- library/utilities/pub_sub_pkg.sv | 4 +- library/utilities/test_harness_env.sv | 6 +- library/utilities/utils.svh | 4 +- library/vip/adi/io_vip/Makefile | 2 +- library/vip/adi/io_vip/io_vip.sv | 2 +- library/vip/adi/io_vip/io_vip_if.sv | 2 +- library/vip/adi/spi_vip/Makefile | 2 +- library/vip/adi/spi_vip/s_spi_sequencer.sv | 4 +- library/vip/amd/axi/adi_axi_agent.sv | 9 +- library/vip/amd/axi/adi_axi_monitor.sv | 41 ++++++- library/vip/amd/axi/axi_definitions.svh | 5 +- library/vip/amd/axi/m_axi_sequencer.sv | 103 ++++++++++++------ library/vip/amd/axi/s_axi_sequencer.sv | 72 +++++++++--- library/vip/amd/axis/adi_axis_agent.sv | 9 +- library/vip/amd/axis/adi_axis_monitor.sv | 43 +++++++- library/vip/amd/axis/axis_definitions.svh | 5 +- library/vip/amd/axis/m_axis_sequencer.sv | 42 +++---- library/vip/amd/axis/s_axis_sequencer.sv | 40 +++---- scripts/make_tb_path.mk | 2 +- scripts/project-sim.mk | 2 +- testbenches/ip/axi_tdd/Makefile | 2 +- testbenches/ip/axi_tdd/system_bd.tcl | 4 +- testbenches/ip/axi_tdd/system_tb.sv | 4 +- testbenches/ip/axi_tdd/tests/test_program.sv | 8 +- testbenches/ip/axi_tdd/waves/cfg1.wcfg | 1 - testbenches/ip/axis_sequencers/Makefile | 2 +- testbenches/ip/axis_sequencers/environment.sv | 37 ++++++- testbenches/ip/axis_sequencers/system_bd.tcl | 4 +- testbenches/ip/axis_sequencers/system_tb.sv | 4 +- .../ip/axis_sequencers/tests/test_program.sv | 16 ++- .../ip/axis_sequencers/waves/cfg1.wcfg | 1 - testbenches/ip/base/Makefile | 2 +- testbenches/ip/base/system_bd.tcl | 4 +- testbenches/ip/base/system_tb.sv | 4 +- testbenches/ip/base/tests/test_program.sv | 4 +- testbenches/ip/base/waves/cfg1.wcfg | 1 - testbenches/ip/data_offload/Makefile | 2 +- .../ip/data_offload/tests/test_program.sv | 37 ++++++- testbenches/ip/data_offload_2/Makefile | 2 +- .../ip/data_offload_2/data_offload_pkg.sv | 10 +- .../ip/data_offload_2/do_scoreboard.sv | 4 +- testbenches/ip/data_offload_2/environment.sv | 4 +- testbenches/ip/data_offload_2/system_tb.sv | 4 +- .../ip/data_offload_2/tests/test_program.sv | 8 +- .../data_offload_2/tests/test_program_sync.sv | 8 +- testbenches/ip/data_offload_2/waves/cfg1.wcfg | 1 - testbenches/ip/data_offload_2/waves/cfg2.wcfg | 1 - testbenches/ip/data_offload_2/waves/cfg3.wcfg | 2 +- testbenches/ip/data_offload_2/waves/cfg4.wcfg | 2 +- testbenches/ip/dma_flock/environment.sv | 4 +- testbenches/ip/dma_flock/scoreboard.sv | 2 +- testbenches/ip/dma_flock/system_tb.sv | 2 +- .../ip/dma_flock/tests/test_program.sv | 4 +- .../tests/test_program_frame_delay.sv | 4 +- testbenches/ip/dma_flock/waves/cfg1.wcfg | 4 +- .../ip/dma_flock/waves/cfg2_fsync.wcfg | 4 +- .../dma_flock/waves/cfg3_fsync_autorun.wcfg | 4 +- testbenches/ip/dma_loopback/Makefile | 2 +- testbenches/ip/dma_loopback/system_bd.tcl | 4 +- testbenches/ip/dma_loopback/system_tb.sv | 4 +- .../ip/dma_loopback/tests/test_program.sv | 8 +- testbenches/ip/dma_sg/system_bd.tcl | 2 +- testbenches/ip/dma_sg/system_tb.sv | 2 +- .../ip/dma_sg/tests/test_program_1d.sv | 6 +- .../ip/dma_sg/tests/test_program_2d.sv | 6 +- .../ip/dma_sg/tests/test_program_tr_queue.sv | 6 +- testbenches/ip/dma_sg/waves/cfg1.wcfg | 4 +- testbenches/ip/dma_sg/waves/cfg2.wcfg | 4 +- testbenches/ip/hbm/Makefile | 2 +- testbenches/ip/hbm/system_bd.tcl | 4 +- testbenches/ip/hbm/system_tb.sv | 4 +- testbenches/ip/hbm/tests/test_program.sv | 8 +- .../ip/i3c_controller/tests/test_program.sv | 4 +- testbenches/ip/i3c_controller/waves/cfg1.wcfg | 2 +- testbenches/ip/jesd_loopback/Makefile | 2 +- testbenches/ip/jesd_loopback/system_bd.tcl | 4 +- testbenches/ip/jesd_loopback/system_tb.sv | 4 +- .../ip/jesd_loopback/tests/test_program.sv | 8 +- testbenches/ip/jesd_loopback/waves/cfg1.wcfg | 4 +- testbenches/ip/jesd_loopback_64b/Makefile | 2 +- .../ip/jesd_loopback_64b/system_bd.tcl | 4 +- testbenches/ip/jesd_loopback_64b/system_tb.sv | 4 +- .../jesd_loopback_64b/tests/test_program.sv | 8 +- testbenches/ip/scoreboard/Makefile | 2 +- testbenches/ip/scoreboard/environment.sv | 39 ++++++- testbenches/ip/scoreboard/system_bd.tcl | 4 +- testbenches/ip/scoreboard/system_tb.sv | 4 +- .../ip/scoreboard/tests/test_program.sv | 8 +- testbenches/ip/scoreboard/waves/cfg1.wcfg | 4 +- testbenches/ip/spi_engine/Makefile | 4 +- testbenches/ip/spi_engine/spi_environment.sv | 2 +- testbenches/ip/spi_engine/system_tb.sv | 4 +- .../ip/spi_engine/tests/test_program.sv | 4 +- testbenches/ip/spi_engine/waves/cfg01.wcfg | 2 +- .../ip/spi_engine/waves/cfg_inv_cs.wcfg | 2 +- .../spi_engine/waves/cfg_sdo_streaming.wcfg | 2 +- testbenches/ip/util_axis_fifo/Makefile | 2 +- testbenches/ip/util_axis_fifo/environment.sv | 37 ++++++- testbenches/ip/util_axis_fifo/system_bd.tcl | 4 +- testbenches/ip/util_axis_fifo/system_tb.sv | 4 +- .../ip/util_axis_fifo/tests/test_program.sv | 12 +- .../ip/util_axis_fifo/waves/cfg_rand.wcfg | 2 +- testbenches/ip/util_axis_fifo_asym/Makefile | 2 +- .../ip/util_axis_fifo_asym/environment.sv | 37 ++++++- .../ip/util_axis_fifo_asym/system_bd.tcl | 4 +- .../ip/util_axis_fifo_asym/system_tb.sv | 4 +- .../util_axis_fifo_asym/tests/test_program.sv | 12 +- .../util_axis_fifo_asym/waves/cfg_rand.wcfg | 2 +- testbenches/ip/util_pack/Makefile | 2 +- testbenches/ip/util_pack/environment.sv | 41 ++++++- testbenches/ip/util_pack/system_bd.tcl | 4 +- testbenches/ip/util_pack/system_tb.sv | 4 +- .../ip/util_pack/tests/test_program.sv | 8 +- testbenches/ip/util_pack/waves/cfg1.wcfg | 4 +- testbenches/ip/util_pack/waves/cfg_rand.wcfg | 4 +- testbenches/project/ad463x/Makefile | 5 +- testbenches/project/ad463x/system_bd.tcl | 4 +- testbenches/project/ad463x/system_tb.sv | 4 +- .../project/ad463x/tests/test_program.sv | 4 +- testbenches/project/ad57xx/Makefile | 4 +- .../project/ad57xx/ad57xx_environment.sv | 4 +- testbenches/project/ad57xx/system_bd.tcl | 2 +- testbenches/project/ad57xx/waves/cfg1.wcfg | 2 +- testbenches/project/ad738x/Makefile | 4 +- testbenches/project/ad738x/system_bd.tcl | 4 +- testbenches/project/ad738x/system_tb.sv | 4 +- .../project/ad738x/tests/test_program.sv | 4 +- testbenches/project/ad7606x/Makefile | 4 +- testbenches/project/ad7606x/system_bd.tcl | 4 +- testbenches/project/ad7606x/system_tb.sv | 4 +- .../project/ad7606x/tests/test_program_4ch.sv | 4 +- .../project/ad7606x/tests/test_program_6ch.sv | 4 +- .../project/ad7606x/tests/test_program_8ch.sv | 4 +- .../project/ad7606x/tests/test_program_si.sv | 4 +- .../ad7606x/waves/system_tb_behav.wcfg | 2 +- testbenches/project/ad7616/Makefile | 4 +- testbenches/project/ad7616/system_bd.tcl | 4 +- testbenches/project/ad7616/system_tb.sv | 4 +- .../project/ad7616/tests/test_program_pi.sv | 4 +- .../project/ad7616/tests/test_program_si.sv | 4 +- testbenches/project/ad7616/waves/cfg_pi.wcfg | 2 +- testbenches/project/ad7616/waves/cfg_si.wcfg | 2 +- testbenches/project/ad9083/Makefile | 4 +- testbenches/project/ad9083/system_bd.tcl | 4 +- testbenches/project/ad9083/system_tb.sv | 4 +- .../project/ad9083/tests/test_program.sv | 8 +- testbenches/project/ad_quadmxfe1_ebz/Makefile | 4 +- .../project/ad_quadmxfe1_ebz/system_bd.tcl | 4 +- .../project/ad_quadmxfe1_ebz/system_tb.sv | 4 +- .../ad_quadmxfe1_ebz/tests/test_dma.sv | 8 +- .../ad_quadmxfe1_ebz/tests/test_program.sv | 8 +- .../tests/test_program_64b66b.sv | 8 +- testbenches/project/adrv9001/Makefile | 4 +- testbenches/project/adrv9001/system_bd.tcl | 4 +- testbenches/project/adrv9001/system_tb.sv | 4 +- .../project/adrv9001/tests/test_program.sv | 8 +- testbenches/project/adrv9009/Makefile | 4 +- testbenches/project/adrv9009/system_bd.tcl | 2 +- testbenches/project/adrv9009/system_tb.sv | 2 +- .../project/adrv9009/tests/test_program.sv | 6 +- testbenches/project/adrv9009/waves/cfg1.wcfg | 4 +- testbenches/project/fmcomms2/Makefile | 4 +- testbenches/project/fmcomms2/system_bd.tcl | 4 +- testbenches/project/fmcomms2/system_tb.sv | 4 +- .../project/fmcomms2/tests/test_program.sv | 8 +- testbenches/project/mxfe/Makefile | 4 +- testbenches/project/mxfe/system_bd.tcl | 4 +- testbenches/project/mxfe/system_tb.sv | 4 +- .../project/mxfe/tests/test_program.sv | 8 +- testbenches/project/mxfe/waves/cfg1.wcfg | 4 +- testbenches/project/pluto/system_bd.tcl | 2 +- testbenches/project/pluto/system_tb.sv | 2 +- .../project/pluto/tests/test_program.sv | 6 +- testbenches/project/pluto/waves/cfg1.wcfg | 2 +- testbenches/project/pulsar_adc_pmdz/Makefile | 4 +- .../project/pulsar_adc_pmdz/spi_engine.svh | 4 +- .../project/pulsar_adc_pmdz/system_bd.tcl | 4 +- .../project/pulsar_adc_pmdz/system_tb.sv | 4 +- .../pulsar_adc_pmdz/tests/test_program.sv | 4 +- .../project/pulsar_adc_pmdz/waves/cfg1.wcfg | 2 +- 239 files changed, 1033 insertions(+), 780 deletions(-) rename library/{regmaps/adi_peripheral_pkg.sv => utilities/adi_api_pkg.sv} (76%) rename library/{drivers/common/interfaces.svh => utilities/adi_environment_pkg.sv} (76%) rename library/{regmaps/reg_accessor.sv => utilities/adi_vip_pkg.sv} (63%) diff --git a/library/drivers/common/scoreboard.sv b/library/drivers/common/scoreboard.sv index 7c1ccc0d..b2d54f43 100644 --- a/library/drivers/common/scoreboard.sv +++ b/library/drivers/common/scoreboard.sv @@ -1,3 +1,38 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" package scoreboard_pkg; diff --git a/library/drivers/common/scoreboard_pack.sv b/library/drivers/common/scoreboard_pack.sv index cd6020b1..25b3c15c 100644 --- a/library/drivers/common/scoreboard_pack.sv +++ b/library/drivers/common/scoreboard_pack.sv @@ -1,3 +1,38 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" package scoreboard_pack_pkg; @@ -49,50 +84,6 @@ package scoreboard_pack_pkg; if (this.enabled == 0) return; - - // forever begin : tx_path - // if (this.enabled == 0) - // break; - // if ((this.source_byte_stream_size > 0) && - // (this.sink_byte_stream_size >= this.channels*this.samples*this.width/8)) begin - // byte_streams_empty_sig = 0; - // for (int i=0; i>byte_streams_empty; - // end - // fork begin - // fork - // @source_transaction_event; - // @sink_transaction_event; - // @stop_scoreboard; - // join_any - // byte_streams_empty_sig = 0; - // disable fork; - // end join - // end - // end while ((this.subscriber_source.get_size() > 0) && (this.subscriber_sink.get_size() >= this.channels*this.samples*this.width/8)) begin diff --git a/library/drivers/common/watchdog.sv b/library/drivers/common/watchdog.sv index 5d377358..94f270cb 100644 --- a/library/drivers/common/watchdog.sv +++ b/library/drivers/common/watchdog.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,12 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** + `include "utils.svh" package watchdog_pkg; diff --git a/library/drivers/data_offload/data_offload_api.sv b/library/drivers/data_offload/data_offload_api.sv index c36ef999..4a036f7f 100644 --- a/library/drivers/data_offload/data_offload_api.sv +++ b/library/drivers/data_offload/data_offload_api.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -38,19 +38,20 @@ package data_offload_api_pkg; import logger_pkg::*; - import adi_peripheral_pkg::*; - import adi_regmap_data_offload_pkg::*; + import adi_common_pkg::*; + import adi_api_pkg::*; import adi_regmap_pkg::*; - import reg_accessor_pkg::*; + import adi_regmap_data_offload_pkg::*; + import m_axi_sequencer_pkg::*; - class data_offload_api extends adi_peripheral; + class data_offload_api extends adi_api; // ----------------- // // ----------------- function new( input string name, - input reg_accessor bus, + input m_axi_sequencer_base bus, input bit [31:0] base_address, input adi_component parent = null); diff --git a/library/drivers/dmac/dma_trans.sv b/library/drivers/dmac/dma_trans.sv index 23cebbe2..e66b26b6 100644 --- a/library/drivers/dmac/dma_trans.sv +++ b/library/drivers/dmac/dma_trans.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018, 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018, 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/drivers/dmac/dmac_api.sv b/library/drivers/dmac/dmac_api.sv index 1f676e9a..fe28abd6 100644 --- a/library/drivers/dmac/dmac_api.sv +++ b/library/drivers/dmac/dmac_api.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018, 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018, 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -38,13 +38,14 @@ package dmac_api_pkg; import logger_pkg::*; - import adi_peripheral_pkg::*; - import adi_regmap_dmac_pkg::*; + import adi_common_pkg::*; + import adi_api_pkg::*; import adi_regmap_pkg::*; - import reg_accessor_pkg::*; + import adi_regmap_dmac_pkg::*; + import m_axi_sequencer_pkg::*; import dma_trans_pkg::*; - class dmac_api extends adi_peripheral; + class dmac_api extends adi_api; // DMAC parameters axi_dmac_params_t p; @@ -54,7 +55,7 @@ package dmac_api_pkg; // ----------------- function new( input string name, - input reg_accessor bus, + input m_axi_sequencer_base bus, input bit [31:0] base_address, input adi_component parent = null); diff --git a/library/drivers/jesd/adi_jesd204_pkg.sv b/library/drivers/jesd/adi_jesd204_pkg.sv index bea6f505..457aab58 100644 --- a/library/drivers/jesd/adi_jesd204_pkg.sv +++ b/library/drivers/jesd/adi_jesd204_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,19 +26,21 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** + `include "utils.svh" package adi_jesd204_pkg; import logger_pkg::*; - import adi_peripheral_pkg::*; - import reg_accessor_pkg::*; + import adi_common_pkg::*; + import adi_api_pkg::*; + import m_axi_sequencer_pkg::*; import adi_regmap_pkg::*; import adi_regmap_jesd_tx_pkg::*; import adi_regmap_jesd_rx_pkg::*; @@ -181,7 +183,7 @@ package adi_jesd204_pkg; //============================================================================ // Base Link layer class //============================================================================ - class link_layer extends adi_peripheral; + class link_layer extends adi_api; jesd_link link; int dp_width = 4; // Data width towards Phy @@ -196,7 +198,7 @@ package adi_jesd204_pkg; // ----------------- // // ----------------- - function new (string name, reg_accessor bus, bit [31:0] base_address, jesd_link link); + function new (string name, m_axi_sequencer_base bus, bit [31:0] base_address, jesd_link link); super.new(name, bus, base_address); this.link = link; @@ -273,7 +275,7 @@ package adi_jesd204_pkg; // ----------------- // // ----------------- - function new (string name, reg_accessor bus, bit [31:0] base_address, jesd_link link); + function new (string name, m_axi_sequencer_base bus, bit [31:0] base_address, jesd_link link); super.new(name, bus, base_address, link); endfunction @@ -433,7 +435,7 @@ package adi_jesd204_pkg; // ----------------- // // ----------------- - function new (string name, reg_accessor bus, bit [31:0] base_address, jesd_link link); + function new (string name, m_axi_sequencer_base bus, bit [31:0] base_address, jesd_link link); super.new(name, bus, base_address, link); endfunction diff --git a/library/drivers/xcvr/adi_xcvr_pkg.sv b/library/drivers/xcvr/adi_xcvr_pkg.sv index e31576c0..6dfed2fe 100644 --- a/library/drivers/xcvr/adi_xcvr_pkg.sv +++ b/library/drivers/xcvr/adi_xcvr_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,22 +26,23 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on_line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** + `include "utils.svh" package adi_xcvr_pkg; import logger_pkg::*; - import adi_peripheral_pkg::*; - import reg_accessor_pkg::*; + import adi_common_pkg::*; + import adi_api_pkg::*; + import m_axi_sequencer_pkg::*; import adi_regmap_pkg::*; import adi_regmap_xcvr_pkg::*; - import adi_jesd204_pkg::*; typedef enum bit [2:0] { OUTCLKPCS = 1, @@ -285,7 +286,7 @@ package adi_xcvr_pkg; //============================================================================ // Xilinx XCVR class //============================================================================ - class xcvr extends adi_peripheral; + class xcvr extends adi_api; // Capabilities bit qpll_enable; @@ -299,7 +300,7 @@ package adi_xcvr_pkg; // ----------------- // // ----------------- - function new (string name, reg_accessor bus, bit [31:0] base_address); + function new (string name, m_axi_sequencer_base bus, bit [31:0] base_address); super.new(name, bus, base_address); endfunction diff --git a/library/includes/Makeinclude_axi.mk b/library/includes/Makeinclude_axi.mk index 8a1b27c8..5db1b2d8 100644 --- a/library/includes/Makeinclude_axi.mk +++ b/library/includes/Makeinclude_axi.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 - 2025 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -9,4 +9,3 @@ SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/s_axi_sequencer.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/adi_axi_monitor.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/axi_definitions.svh SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv -SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/reg_accessor.sv diff --git a/library/includes/Makeinclude_axis.mk b/library/includes/Makeinclude_axis.mk index 5810ebd7..2ecbf0d1 100644 --- a/library/includes/Makeinclude_axis.mk +++ b/library/includes/Makeinclude_axis.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_common.mk b/library/includes/Makeinclude_common.mk index 8a0ea7eb..10ae4c67 100644 --- a/library/includes/Makeinclude_common.mk +++ b/library/includes/Makeinclude_common.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 - 2025 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -9,6 +9,8 @@ include $(TB_LIBRARY_PATH)/includes/Makeinclude_axi.mk SV_DEPS += $(TB_LIBRARY_PATH)/utilities/utils.svh SV_DEPS += $(TB_LIBRARY_PATH)/utilities/logger_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/utilities/adi_common_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/adi_vip_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/adi_environment_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/utilities/test_harness_env.sv SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/watchdog.sv diff --git a/library/includes/Makeinclude_data_offload.mk b/library/includes/Makeinclude_data_offload.mk index bec4f316..fb2c6111 100644 --- a/library/includes/Makeinclude_data_offload.mk +++ b/library/includes/Makeinclude_data_offload.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_dmac.mk b/library/includes/Makeinclude_dmac.mk index 5c43ce10..291e67d5 100644 --- a/library/includes/Makeinclude_dmac.mk +++ b/library/includes/Makeinclude_dmac.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_jesd.mk b/library/includes/Makeinclude_jesd.mk index 3f8889e2..e1af70d9 100644 --- a/library/includes/Makeinclude_jesd.mk +++ b/library/includes/Makeinclude_jesd.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_regmap.mk b/library/includes/Makeinclude_regmap.mk index 30977cc9..8ad04899 100644 --- a/library/includes/Makeinclude_regmap.mk +++ b/library/includes/Makeinclude_regmap.mk @@ -1,8 +1,8 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 - 2025 Analog Devices, Inc. #################################################################################### #################################################################################### # All test-bench dependencies except test programs -SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/reg_accessor.sv -SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_peripheral_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/adi_common_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/adi_api_pkg.sv diff --git a/library/includes/Makeinclude_scoreboard.mk b/library/includes/Makeinclude_scoreboard.mk index 3fd4e67a..76c8c8b0 100644 --- a/library/includes/Makeinclude_scoreboard.mk +++ b/library/includes/Makeinclude_scoreboard.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_spi_engine.mk b/library/includes/Makeinclude_spi_engine.mk index 1c0af3b0..543c325f 100644 --- a/library/includes/Makeinclude_spi_engine.mk +++ b/library/includes/Makeinclude_spi_engine.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_tdd.mk b/library/includes/Makeinclude_tdd.mk index 0d078b04..60f6a7d3 100644 --- a/library/includes/Makeinclude_tdd.mk +++ b/library/includes/Makeinclude_tdd.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_xcvr.mk b/library/includes/Makeinclude_xcvr.mk index 23dc8402..b041e70c 100644 --- a/library/includes/Makeinclude_xcvr.mk +++ b/library/includes/Makeinclude_xcvr.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/sp_include_axi.tcl b/library/includes/sp_include_axi.tcl index 89aaa064..50885ff7 100644 --- a/library/includes/sp_include_axi.tcl +++ b/library/includes/sp_include_axi.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # @@ -41,5 +41,4 @@ adi_sim_project_files [list \ "$ad_tb_dir/library/vip/amd/axi/adi_axi_monitor.sv" \ "$ad_tb_dir/library/vip/amd/axi/axi_definitions.svh" \ "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ - "$ad_tb_dir/library/regmaps/reg_accessor.sv" \ ] diff --git a/library/includes/sp_include_axis.tcl b/library/includes/sp_include_axis.tcl index 50532616..28a261dd 100644 --- a/library/includes/sp_include_axis.tcl +++ b/library/includes/sp_include_axis.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_common.tcl b/library/includes/sp_include_common.tcl index ec70bb7f..d0548016 100644 --- a/library/includes/sp_include_common.tcl +++ b/library/includes/sp_include_common.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # @@ -40,6 +40,8 @@ adi_sim_project_files [list \ "$ad_tb_dir/library/utilities/utils.svh" \ "$ad_tb_dir/library/utilities/logger_pkg.sv" \ "$ad_tb_dir/library/utilities/adi_common_pkg.sv" \ + "$ad_tb_dir/library/utilities/adi_vip_pkg.sv" \ + "$ad_tb_dir/library/utilities/adi_environment_pkg.sv" \ "$ad_tb_dir/library/utilities/test_harness_env.sv" \ "$ad_tb_dir/library/drivers/common/watchdog.sv" \ "system_tb.sv" \ diff --git a/library/includes/sp_include_data_offload.tcl b/library/includes/sp_include_data_offload.tcl index e1a8c2c2..206af6b6 100644 --- a/library/includes/sp_include_data_offload.tcl +++ b/library/includes/sp_include_data_offload.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_dmac.tcl b/library/includes/sp_include_dmac.tcl index 511727c1..9d6a9038 100644 --- a/library/includes/sp_include_dmac.tcl +++ b/library/includes/sp_include_dmac.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_jesd.tcl b/library/includes/sp_include_jesd.tcl index e768ea17..f12665f6 100644 --- a/library/includes/sp_include_jesd.tcl +++ b/library/includes/sp_include_jesd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_regmap.tcl b/library/includes/sp_include_regmap.tcl index 583fbde0..7a4f27dc 100644 --- a/library/includes/sp_include_regmap.tcl +++ b/library/includes/sp_include_regmap.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # @@ -35,7 +35,7 @@ # Add test files to the project adi_sim_project_files [list \ - "$ad_tb_dir/library/regmaps/reg_accessor.sv" \ - "$ad_tb_dir/library/regmaps/adi_peripheral_pkg.sv" \ + "$ad_tb_dir/library/utilities/adi_common_pkg.sv" \ "$ad_tb_dir/library/regmaps/adi_regmap_pkg.sv" \ + "$ad_tb_dir/library/utilities/adi_api_pkg.sv" \ ] diff --git a/library/includes/sp_include_scoreboard.tcl b/library/includes/sp_include_scoreboard.tcl index 03ac1a8b..22fd1cc9 100644 --- a/library/includes/sp_include_scoreboard.tcl +++ b/library/includes/sp_include_scoreboard.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_spi_engine.tcl b/library/includes/sp_include_spi_engine.tcl index 114a5561..f090ec45 100644 --- a/library/includes/sp_include_spi_engine.tcl +++ b/library/includes/sp_include_spi_engine.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_tdd.tcl b/library/includes/sp_include_tdd.tcl index 38a8b855..08ffa379 100644 --- a/library/includes/sp_include_tdd.tcl +++ b/library/includes/sp_include_tdd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_xcvr.tcl b/library/includes/sp_include_xcvr.tcl index 6e27586a..8ca8ac85 100644 --- a/library/includes/sp_include_xcvr.tcl +++ b/library/includes/sp_include_xcvr.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/regmaps/adi_regmap_adc_pkg.sv b/library/regmaps/adi_regmap_adc_pkg.sv index 3a110dcc..51eb3e15 100644 --- a/library/regmaps/adi_regmap_adc_pkg.sv +++ b/library/regmaps/adi_regmap_adc_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_axi_ad7616_pkg.sv b/library/regmaps/adi_regmap_axi_ad7616_pkg.sv index 45b3c0a4..4ceaf753 100644 --- a/library/regmaps/adi_regmap_axi_ad7616_pkg.sv +++ b/library/regmaps/adi_regmap_axi_ad7616_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_clkgen_pkg.sv b/library/regmaps/adi_regmap_clkgen_pkg.sv index ad66325b..784753a7 100644 --- a/library/regmaps/adi_regmap_clkgen_pkg.sv +++ b/library/regmaps/adi_regmap_clkgen_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_clock_monitor_pkg.sv b/library/regmaps/adi_regmap_clock_monitor_pkg.sv index e5cc8fb5..74d472d2 100644 --- a/library/regmaps/adi_regmap_clock_monitor_pkg.sv +++ b/library/regmaps/adi_regmap_clock_monitor_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_common_pkg.sv b/library/regmaps/adi_regmap_common_pkg.sv index 002feb30..fe201938 100644 --- a/library/regmaps/adi_regmap_common_pkg.sv +++ b/library/regmaps/adi_regmap_common_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_dac_pkg.sv b/library/regmaps/adi_regmap_dac_pkg.sv index 912d3aa7..4fa4bad6 100644 --- a/library/regmaps/adi_regmap_dac_pkg.sv +++ b/library/regmaps/adi_regmap_dac_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_data_offload_pkg.sv b/library/regmaps/adi_regmap_data_offload_pkg.sv index 3142b6d6..e351cb61 100644 --- a/library/regmaps/adi_regmap_data_offload_pkg.sv +++ b/library/regmaps/adi_regmap_data_offload_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2021 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/regmaps/adi_regmap_dmac_pkg.sv b/library/regmaps/adi_regmap_dmac_pkg.sv index a893c0c2..973ecdde 100644 --- a/library/regmaps/adi_regmap_dmac_pkg.sv +++ b/library/regmaps/adi_regmap_dmac_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_fan_control_pkg.sv b/library/regmaps/adi_regmap_fan_control_pkg.sv index a70ef05c..e0f39185 100644 --- a/library/regmaps/adi_regmap_fan_control_pkg.sv +++ b/library/regmaps/adi_regmap_fan_control_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_gpreg_pkg.sv b/library/regmaps/adi_regmap_gpreg_pkg.sv index 95b5efdb..6ecb347a 100644 --- a/library/regmaps/adi_regmap_gpreg_pkg.sv +++ b/library/regmaps/adi_regmap_gpreg_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_hdmi_pkg.sv b/library/regmaps/adi_regmap_hdmi_pkg.sv index 38f24daa..028114b3 100644 --- a/library/regmaps/adi_regmap_hdmi_pkg.sv +++ b/library/regmaps/adi_regmap_hdmi_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_i3c_controller_pkg.sv b/library/regmaps/adi_regmap_i3c_controller_pkg.sv index f4587188..37fa8736 100644 --- a/library/regmaps/adi_regmap_i3c_controller_pkg.sv +++ b/library/regmaps/adi_regmap_i3c_controller_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_iodelay_pkg.sv b/library/regmaps/adi_regmap_iodelay_pkg.sv index 89ced2f4..26722c93 100644 --- a/library/regmaps/adi_regmap_iodelay_pkg.sv +++ b/library/regmaps/adi_regmap_iodelay_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_jesd_rx_pkg.sv b/library/regmaps/adi_regmap_jesd_rx_pkg.sv index 1c8371a3..cf1943ec 100644 --- a/library/regmaps/adi_regmap_jesd_rx_pkg.sv +++ b/library/regmaps/adi_regmap_jesd_rx_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_jesd_tpl_pkg.sv b/library/regmaps/adi_regmap_jesd_tpl_pkg.sv index fb6ccb77..07f12cd6 100644 --- a/library/regmaps/adi_regmap_jesd_tpl_pkg.sv +++ b/library/regmaps/adi_regmap_jesd_tpl_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_jesd_tx_pkg.sv b/library/regmaps/adi_regmap_jesd_tx_pkg.sv index 4e99b5ce..577b10b0 100644 --- a/library/regmaps/adi_regmap_jesd_tx_pkg.sv +++ b/library/regmaps/adi_regmap_jesd_tx_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_pkg.sv b/library/regmaps/adi_regmap_pkg.sv index c67e1cf3..048c1c1e 100644 --- a/library/regmaps/adi_regmap_pkg.sv +++ b/library/regmaps/adi_regmap_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2021 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/regmaps/adi_regmap_pwm_gen_pkg.sv b/library/regmaps/adi_regmap_pwm_gen_pkg.sv index 3ebddf50..5914ec5a 100644 --- a/library/regmaps/adi_regmap_pwm_gen_pkg.sv +++ b/library/regmaps/adi_regmap_pwm_gen_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_spi_engine_pkg.sv b/library/regmaps/adi_regmap_spi_engine_pkg.sv index daac4b55..66974a78 100644 --- a/library/regmaps/adi_regmap_spi_engine_pkg.sv +++ b/library/regmaps/adi_regmap_spi_engine_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_system_id_pkg.sv b/library/regmaps/adi_regmap_system_id_pkg.sv index 81d4abad..dd6f5580 100644 --- a/library/regmaps/adi_regmap_system_id_pkg.sv +++ b/library/regmaps/adi_regmap_system_id_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_tdd_gen_pkg.sv b/library/regmaps/adi_regmap_tdd_gen_pkg.sv index 018fa140..587eb02d 100644 --- a/library/regmaps/adi_regmap_tdd_gen_pkg.sv +++ b/library/regmaps/adi_regmap_tdd_gen_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_tdd_trans_pkg.sv b/library/regmaps/adi_regmap_tdd_trans_pkg.sv index 0f42437b..38f0bd33 100644 --- a/library/regmaps/adi_regmap_tdd_trans_pkg.sv +++ b/library/regmaps/adi_regmap_tdd_trans_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_xcvr_pkg.sv b/library/regmaps/adi_regmap_xcvr_pkg.sv index 8832b038..5a48c027 100644 --- a/library/regmaps/adi_regmap_xcvr_pkg.sv +++ b/library/regmaps/adi_regmap_xcvr_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_peripheral_pkg.sv b/library/utilities/adi_api_pkg.sv similarity index 76% rename from library/regmaps/adi_peripheral_pkg.sv rename to library/utilities/adi_api_pkg.sv index 26ed9a24..f3c5bde9 100644 --- a/library/regmaps/adi_peripheral_pkg.sv +++ b/library/utilities/adi_api_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,62 +26,51 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** + `include "utils.svh" -package adi_peripheral_pkg; +package adi_api_pkg; import logger_pkg::*; import adi_common_pkg::*; - import reg_accessor_pkg::*; + import m_axi_sequencer_pkg::*; - //============================================================================ - // Base peripheral class - //============================================================================ - class adi_peripheral extends adi_component; - reg_accessor bus; - bit [31:0] base_address; + class adi_api extends adi_component; + + protected m_axi_sequencer_base bus; + protected bit [31:0] base_address; // Semantic versioning bit [7:0] ver_major; bit [7:0] ver_minor; bit [7:0] ver_patch; - string name; - - // ----------------- - // - // ----------------- function new( input string name, - input reg_accessor bus, + input m_axi_sequencer_base bus, input bit [31:0] base_address, input adi_component parent = null); super.new(name, parent); - + this.bus = bus; this.base_address = base_address; - endfunction + endfunction: new + - // ----------------- - // - // ----------------- virtual task probe(); bit [31:0] val; this.bus.RegRead32(this.base_address + 'h0, val); {ver_major, ver_minor, ver_patch} = val; this.info($sformatf("Found peripheral version: %0d.%0d.%s", ver_major, ver_minor, ver_patch), ADI_VERBOSITY_HIGH); endtask - - // ----------------- - // - // ----------------- + task axi_read( input [31:0] addr, output [31:0] data); @@ -89,9 +78,6 @@ package adi_peripheral_pkg; this.bus.RegRead32(this.base_address + addr, data); endtask: axi_read - // ----------------- - // - // ----------------- task axi_write( input [31:0] addr, input [31:0] data); @@ -99,9 +85,6 @@ package adi_peripheral_pkg; this.bus.RegWrite32(this.base_address + addr, data); endtask: axi_write - // ----------------- - // - // ----------------- task axi_verify( input [31:0] addr, input [31:0] data); @@ -109,6 +92,16 @@ package adi_peripheral_pkg; this.bus.RegReadVerify32(this.base_address + addr, data); endtask: axi_verify - endclass + endclass: adi_api + + + class adi_regmap extends adi_component; + function new( + input string name, + input adi_api parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_regmap -endpackage +endpackage: adi_api_pkg diff --git a/library/utilities/adi_common_pkg.sv b/library/utilities/adi_common_pkg.sv index 5b3d2464..6edf6bc7 100644 --- a/library/utilities/adi_common_pkg.sv +++ b/library/utilities/adi_common_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -88,74 +88,4 @@ package adi_common_pkg; endfunction: new endclass: adi_component - - class adi_environment extends adi_component; - function new( - input string name, - input adi_environment parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_environment - - - class adi_api extends adi_component; - function new( - input string name, - input adi_component parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_api - - - class adi_regmap extends adi_component; - function new( - input string name, - input adi_api parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_regmap - - - class adi_agent extends adi_component; - function new( - input string name, - input adi_environment parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_agent - - - class adi_driver extends adi_component; - function new( - input string name, - input adi_agent parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_driver - - - class adi_sequencer extends adi_component; - function new( - input string name, - input adi_agent parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_sequencer - - - class adi_monitor extends adi_component; - function new( - input string name, - input adi_agent parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_monitor - -endpackage +endpackage: adi_common_pkg diff --git a/library/utilities/adi_datatypes.sv b/library/utilities/adi_datatypes.sv index 45219c0a..73c63dc9 100644 --- a/library/utilities/adi_datatypes.sv +++ b/library/utilities/adi_datatypes.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/drivers/common/interfaces.svh b/library/utilities/adi_environment_pkg.sv similarity index 76% rename from library/drivers/common/interfaces.svh rename to library/utilities/adi_environment_pkg.sv index a7a2d397..c57ab8e9 100644 --- a/library/drivers/common/interfaces.svh +++ b/library/utilities/adi_environment_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,28 +26,28 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -`ifndef _INTERFACES_SVH_ -`define _INTERFACES_SVH_ +`include "utils.svh" -interface clk_if (); - logic clk; +package adi_environment_pkg; - task start_clock(int clk_period); - clk = 1'b1; - fork - forever begin - #((clk_period / 2)*1ps); - clk = ~clk; - end - join_none - endtask: start_clock -endinterface: clk_if + import logger_pkg::*; + import adi_common_pkg::*; + import adi_environment_pkg::*; -`endif + class adi_environment extends adi_component; + function new( + input string name, + input adi_environment parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_environment + +endpackage: adi_environment_pkg diff --git a/library/regmaps/reg_accessor.sv b/library/utilities/adi_vip_pkg.sv similarity index 63% rename from library/regmaps/reg_accessor.sv rename to library/utilities/adi_vip_pkg.sv index ab6ad68f..b33cca46 100644 --- a/library/regmaps/reg_accessor.sv +++ b/library/utilities/adi_vip_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,39 +26,58 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -package reg_accessor_pkg; +`include "utils.svh" - import axi_vip_pkg::*; +package adi_vip_pkg; + + import logger_pkg::*; import adi_common_pkg::*; + import adi_environment_pkg::*; + + class adi_agent extends adi_component; + function new( + input string name, + input adi_environment parent = null); - class reg_accessor extends adi_component; + super.new(name, parent); + endfunction: new + endclass: adi_agent + + class adi_driver extends adi_component; function new( input string name, - input adi_component parent = null); - + input adi_agent parent = null); + super.new(name, parent); - endfunction + endfunction: new + endclass: adi_driver + + + class adi_sequencer extends adi_component; + function new( + input string name, + input adi_agent parent = null); - virtual task automatic RegWrite32(input xil_axi_ulong addr =0, - input bit [31:0] data); - endtask: RegWrite32 + super.new(name, parent); + endfunction: new + endclass: adi_sequencer - virtual task automatic RegRead32(input xil_axi_ulong addr =0, - output bit [31:0] data); - endtask: RegRead32 - virtual task automatic RegReadVerify32(input xil_axi_ulong addr =0, - input bit [31:0] data); - endtask: RegReadVerify32 + class adi_monitor extends adi_component; + function new( + input string name, + input adi_agent parent = null); - endclass + super.new(name, parent); + endfunction: new + endclass: adi_monitor -endpackage +endpackage: adi_vip_pkg diff --git a/library/utilities/logger_pkg.sv b/library/utilities/logger_pkg.sv index 6db5d3cb..0f610791 100644 --- a/library/utilities/logger_pkg.sv +++ b/library/utilities/logger_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/utilities/pub_sub_pkg.sv b/library/utilities/pub_sub_pkg.sv index 570395a6..96044b7f 100644 --- a/library/utilities/pub_sub_pkg.sv +++ b/library/utilities/pub_sub_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/utilities/test_harness_env.sv b/library/utilities/test_harness_env.sv index 50c2566f..17545cbe 100644 --- a/library/utilities/test_harness_env.sv +++ b/library/utilities/test_harness_env.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -39,7 +39,7 @@ package test_harness_env_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import adi_axi_agent_pkg::*; diff --git a/library/utilities/utils.svh b/library/utilities/utils.svh index 03a240df..804a60d8 100644 --- a/library/utilities/utils.svh +++ b/library/utilities/utils.svh @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/vip/adi/io_vip/Makefile b/library/vip/adi/io_vip/Makefile index 8e61c693..99cf89e5 100644 --- a/library/vip/adi/io_vip/Makefile +++ b/library/vip/adi/io_vip/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2024 Analog Devices, Inc. +## Copyright (C) 2018 - 2024 Analog Devices, Inc. ## Auto-generated, do not modify! #################################################################################### diff --git a/library/vip/adi/io_vip/io_vip.sv b/library/vip/adi/io_vip/io_vip.sv index 62eb8f65..70c491c2 100644 --- a/library/vip/adi/io_vip/io_vip.sv +++ b/library/vip/adi/io_vip/io_vip.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/vip/adi/io_vip/io_vip_if.sv b/library/vip/adi/io_vip/io_vip_if.sv index c9fb7dac..7ec2fa9e 100644 --- a/library/vip/adi/io_vip/io_vip_if.sv +++ b/library/vip/adi/io_vip/io_vip_if.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/vip/adi/spi_vip/Makefile b/library/vip/adi/spi_vip/Makefile index 890ed530..4be1d86f 100644 --- a/library/vip/adi/spi_vip/Makefile +++ b/library/vip/adi/spi_vip/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2024 Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/library/vip/adi/spi_vip/s_spi_sequencer.sv b/library/vip/adi/spi_vip/s_spi_sequencer.sv index 79112770..bb0a2d73 100644 --- a/library/vip/adi/spi_vip/s_spi_sequencer.sv +++ b/library/vip/adi/spi_vip/s_spi_sequencer.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/vip/amd/axi/adi_axi_agent.sv b/library/vip/amd/axi/adi_axi_agent.sv index ea969ff8..90b77e56 100644 --- a/library/vip/amd/axi/adi_axi_agent.sv +++ b/library/vip/amd/axi/adi_axi_agent.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -39,7 +39,8 @@ package adi_axi_agent_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; + import adi_environment_pkg::*; import axi_vip_pkg::*; import m_axi_sequencer_pkg::*; import s_axi_sequencer_pkg::*; @@ -150,4 +151,4 @@ package adi_axi_agent_pkg; endclass: adi_axi_passthrough_mem_agent -endpackage +endpackage: adi_axi_agent_pkg diff --git a/library/vip/amd/axi/adi_axi_monitor.sv b/library/vip/amd/axi/adi_axi_monitor.sv index 3603af7f..8c440d22 100644 --- a/library/vip/amd/axi/adi_axi_monitor.sv +++ b/library/vip/amd/axi/adi_axi_monitor.sv @@ -1,10 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" package adi_axi_monitor_pkg; import axi_vip_pkg::*; import logger_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; import pub_sub_pkg::*; class adi_axi_monitor #(int `AXI_VIP_PARAM_ORDER(axi)) extends adi_monitor; @@ -97,6 +132,6 @@ package adi_axi_monitor_pkg; end endtask: get_transaction - endclass + endclass: adi_axi_monitor -endpackage +endpackage: adi_axi_monitor_pkg diff --git a/library/vip/amd/axi/axi_definitions.svh b/library/vip/amd/axi/axi_definitions.svh index 93f026e5..bc8a2372 100644 --- a/library/vip/amd/axi/axi_definitions.svh +++ b/library/vip/amd/axi/axi_definitions.svh @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,14 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** - `timescale 1ns/1ps `ifndef _AXI_DEFINITIONS_SVH_ diff --git a/library/vip/amd/axi/m_axi_sequencer.sv b/library/vip/amd/axi/m_axi_sequencer.sv index b339e2af..c271d9ea 100644 --- a/library/vip/amd/axi/m_axi_sequencer.sv +++ b/library/vip/amd/axi/m_axi_sequencer.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -40,10 +40,43 @@ package m_axi_sequencer_pkg; import axi_vip_pkg::*; import logger_pkg::*; - import adi_common_pkg::*; - import reg_accessor_pkg::*; + import adi_vip_pkg::*; - class m_axi_sequencer #(`AXI_VIP_PARAM_DECL(AXI)) extends reg_accessor; + + class m_axi_sequencer_base extends adi_sequencer; + + function new( + input string name, + input adi_agent parent = null); + + super.new(name, parent); + endfunction: new + + virtual task automatic RegWrite32( + input xil_axi_ulong addr =0, + input bit [31:0] data); + + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: RegWrite32 + + virtual task automatic RegRead32( + input xil_axi_ulong addr =0, + output bit [31:0] data); + + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: RegRead32 + + virtual task automatic RegReadVerify32( + input xil_axi_ulong addr =0, + input bit [31:0] data); + + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: RegReadVerify32 + + endclass: m_axi_sequencer_base + + + class m_axi_sequencer #(`AXI_VIP_PARAM_DECL(AXI)) extends m_axi_sequencer_base; axi_mst_wr_driver #(`AXI_VIP_PARAM_ORDER(AXI)) wr_driver; axi_mst_rd_driver #(`AXI_VIP_PARAM_ORDER(AXI)) rd_driver; @@ -64,13 +97,14 @@ package m_axi_sequencer_pkg; reader_s = new(1); writer_s = new(1); - endfunction + endfunction: new // --------------------------------------------------------------------------- // Generic tasks // --------------------------------------------------------------------------- - virtual task automatic RegWrite32(input xil_axi_ulong addr =0, - input bit [31:0] data); + virtual task automatic RegWrite32( + input xil_axi_ulong addr =0, + input bit [31:0] data); static xil_axi_uint id =0; @@ -85,11 +119,11 @@ package m_axi_sequencer_pkg; .data(data)); id++; writer_s.put(1); - endtask : RegWrite32 - virtual task automatic RegRead32(input xil_axi_ulong addr =0, - output bit [31:0] data); + virtual task automatic RegRead32( + input xil_axi_ulong addr =0, + output bit [31:0] data); xil_axi_data_beat DataBeat_for_read[]; static xil_axi_uint id =0; @@ -107,37 +141,37 @@ package m_axi_sequencer_pkg; this.info($sformatf(" Reading data : %h @ 0x%h", data, addr), ADI_VERBOSITY_HIGH); reader_s.put(1); - endtask : RegRead32 - virtual task automatic RegReadVerify32(input xil_axi_ulong addr =0, - input bit [31:0] data); + virtual task automatic RegReadVerify32( + input xil_axi_ulong addr =0, + input bit [31:0] data); + bit [31:0] data_out; RegRead32(.addr(addr), .data(data_out)); if (data !== data_out) begin this.error($sformatf(" Address : %h; Data mismatch. Read data is : %h; expected is %h", addr, data_out, data)); end - endtask : RegReadVerify32 // --------------------------------------------------------------------------- // BFM specific tasks // --------------------------------------------------------------------------- - task automatic single_write_transaction_api ( - input string name ="single_write", - input xil_axi_uint id =0, - input xil_axi_ulong addr =0, - input xil_axi_len_t len =0, - input xil_axi_size_t size =xil_axi_size_t'(xil_clog2((32)/8)), - input xil_axi_burst_t burst =XIL_AXI_BURST_TYPE_INCR, - input xil_axi_lock_t lock = XIL_AXI_ALOCK_NOLOCK, - input xil_axi_cache_t cache =3, - input xil_axi_prot_t prot =0, - input xil_axi_region_t region =0, - input xil_axi_qos_t qos =0, - input bit [63:0] data =0); + protected task automatic single_write_transaction_api ( + input string name ="single_write", + input xil_axi_uint id =0, + input xil_axi_ulong addr =0, + input xil_axi_len_t len =0, + input xil_axi_size_t size =xil_axi_size_t'(xil_clog2((32)/8)), + input xil_axi_burst_t burst =XIL_AXI_BURST_TYPE_INCR, + input xil_axi_lock_t lock = XIL_AXI_ALOCK_NOLOCK, + input xil_axi_cache_t cache =3, + input xil_axi_prot_t prot =0, + input xil_axi_region_t region =0, + input xil_axi_qos_t qos =0, + input bit [63:0] data =0); axi_transaction wr_trans; wr_trans = wr_driver.create_transaction(name); @@ -149,10 +183,9 @@ package m_axi_sequencer_pkg; wr_trans.set_qos(qos); wr_trans.set_data_block(data); wr_driver.send(wr_trans); - endtask : single_write_transaction_api - task automatic single_write_transaction_readback_api ( + protected task automatic single_write_transaction_readback_api ( input string name ="single_write", input xil_axi_uint id =0, input xil_axi_ulong addr =0, @@ -178,10 +211,9 @@ package m_axi_sequencer_pkg; wr_trans.set_driver_return_item_policy(XIL_AXI_PAYLOAD_RETURN); wr_driver.send(wr_trans); wr_driver.wait_rsp(wr_trans); - endtask : single_write_transaction_readback_api - task automatic single_read_transaction_api ( + protected task automatic single_read_transaction_api ( input string name ="single_read", input xil_axi_uint id =0, input xil_axi_ulong addr =0, @@ -206,7 +238,7 @@ package m_axi_sequencer_pkg; rd_driver.send(rd_trans); endtask : single_read_transaction_api - task automatic single_read_transaction_readback_api ( + protected task automatic single_read_transaction_readback_api ( input string name ="single_read", input xil_axi_uint id =0, input xil_axi_ulong addr =0, @@ -237,9 +269,8 @@ package m_axi_sequencer_pkg; Rdatabeat[beat] = rd_trans.get_data_beat(beat); //$display("Read data from Driver: beat index %d, Data beat %h ", beat, Rdatabeat[beat]); end - endtask : single_read_transaction_readback_api - endclass + endclass: m_axi_sequencer -endpackage +endpackage: m_axi_sequencer_pkg diff --git a/library/vip/amd/axi/s_axi_sequencer.sv b/library/vip/amd/axi/s_axi_sequencer.sv index 1e1ab9e3..90786f96 100644 --- a/library/vip/amd/axi/s_axi_sequencer.sv +++ b/library/vip/amd/axi/s_axi_sequencer.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -39,10 +39,44 @@ package s_axi_sequencer_pkg; import axi_vip_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; import logger_pkg::*; - class s_axi_sequencer #(`AXI_VIP_PARAM_DECL(AXI)) extends adi_component; + + class s_axi_sequencer_base extends adi_sequencer; + + function new( + input string name, + input adi_agent parent = null); + + super.new(name, parent); + endfunction: new + + virtual task get_byte_from_mem( + input xil_axi_ulong addr, + output bit [7:0] data); + + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: get_byte_from_mem + + virtual task set_byte_in_mem( + input xil_axi_ulong addr, + input bit [7:0] data); + + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: set_byte_in_mem + + virtual task verify_byte( + input xil_axi_ulong addr, + input bit [7:0] refdata); + + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: verify_byte + + endclass: s_axi_sequencer_base + + + class s_axi_sequencer #(`AXI_VIP_PARAM_DECL(AXI)) extends s_axi_sequencer_base; xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(AXI)) mem_model; @@ -54,10 +88,12 @@ package s_axi_sequencer_pkg; super.new(name, parent); this.mem_model = mem_model; - endfunction + endfunction: new + + task get_byte_from_mem( + input xil_axi_ulong addr, + output bit [7:0] data); - task get_byte_from_mem(input xil_axi_ulong addr, - output bit [7:0] data); bit [31:0] four_bytes; four_bytes = this.mem_model.backdoor_memory_read_4byte(addr); case (addr[1:0]) @@ -66,10 +102,12 @@ package s_axi_sequencer_pkg; 2'b10: data = four_bytes[16+:8]; 2'b11: data = four_bytes[24+:8]; endcase - endtask + endtask: get_byte_from_mem + + task set_byte_in_mem( + input xil_axi_ulong addr, + input bit [7:0] data); - task set_byte_in_mem(input xil_axi_ulong addr, - input bit [7:0] data); bit [3:0] strb; case (addr[1:0]) 2'b00: strb = 'b0001; @@ -80,18 +118,20 @@ package s_axi_sequencer_pkg; this.mem_model.backdoor_memory_write_4byte(.addr(addr), .payload({4{data}}), .strb(strb)); - endtask + endtask: set_byte_in_mem - task verify_byte(input xil_axi_ulong addr, - input bit [7:0] refdata); + task verify_byte( + input xil_axi_ulong addr, + input bit [7:0] refdata); + bit [7:0] data; get_byte_from_mem (addr, data); if (data !== refdata) begin this.error($sformatf("Unexpected value at address %0h . Expected: %0h Found: %0h", addr, refdata, data)); end - endtask + endtask: verify_byte - endclass + endclass: s_axi_sequencer -endpackage +endpackage: s_axi_sequencer_pkg diff --git a/library/vip/amd/axis/adi_axis_agent.sv b/library/vip/amd/axis/adi_axis_agent.sv index b40e4611..96ce1b25 100644 --- a/library/vip/amd/axis/adi_axis_agent.sv +++ b/library/vip/amd/axis/adi_axis_agent.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -39,7 +39,8 @@ package adi_axis_agent_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; + import adi_environment_pkg::*; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; import s_axis_sequencer_pkg::*; @@ -156,4 +157,4 @@ package adi_axis_agent_pkg; endclass: adi_axis_passthrough_mem_agent -endpackage +endpackage: adi_axis_agent_pkg diff --git a/library/vip/amd/axis/adi_axis_monitor.sv b/library/vip/amd/axis/adi_axis_monitor.sv index 77b5d3a5..c038ce62 100644 --- a/library/vip/amd/axis/adi_axis_monitor.sv +++ b/library/vip/amd/axis/adi_axis_monitor.sv @@ -1,10 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" package adi_axis_monitor_pkg; import axi4stream_vip_pkg::*; import logger_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; import pub_sub_pkg::*; class adi_axis_monitor #(`AXIS_VIP_PARAM_DECL(AXIS)) extends adi_monitor; @@ -30,7 +65,7 @@ package adi_axis_monitor_pkg; this.publisher = new("Publisher", this); this.enabled = 0; - endfunction + endfunction: new task run(); if (this.enabled) begin @@ -86,6 +121,6 @@ package adi_axis_monitor_pkg; end endtask: get_transaction - endclass + endclass: adi_axis_monitor -endpackage +endpackage: adi_axis_monitor_pkg diff --git a/library/vip/amd/axis/axis_definitions.svh b/library/vip/amd/axis/axis_definitions.svh index ed98435c..1588109c 100644 --- a/library/vip/amd/axis/axis_definitions.svh +++ b/library/vip/amd/axis/axis_definitions.svh @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,14 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** - `timescale 1ns/1ps `ifndef _AXIS_DEFINITIONS_SVH_ diff --git a/library/vip/amd/axis/m_axis_sequencer.sv b/library/vip/amd/axis/m_axis_sequencer.sv index 3cc86628..fa3e39b5 100644 --- a/library/vip/amd/axis/m_axis_sequencer.sv +++ b/library/vip/amd/axis/m_axis_sequencer.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -39,7 +39,7 @@ package m_axis_sequencer_pkg; import axi4stream_vip_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; import logger_pkg::*; typedef enum { @@ -55,7 +55,7 @@ package m_axis_sequencer_pkg; } stop_policy_t; - class m_axis_sequencer_base extends adi_component; + class m_axis_sequencer_base extends adi_sequencer; protected bit enabled; protected bit queue_empty_sig; @@ -116,45 +116,45 @@ package m_axis_sequencer_pkg; // set vif proxy to drive outputs with 0 when inactive virtual task set_inactive_drive_output_0(); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endtask: set_inactive_drive_output_0 // check if ready is asserted virtual function bit check_ready_asserted(); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endfunction: check_ready_asserted // wait for set amount of clock cycles virtual task wait_clk_count(input int wait_clocks); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endtask: wait_clk_count // pack the byte stream into transfers(beats) then in packets by setting the tlast virtual protected task packetize(); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endtask: packetize virtual protected task sender(); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endtask: sender // create transfer based on data beats per packet - virtual function void add_xfer_descriptor_packet_size( + virtual function void add_xfer_descriptor_sample_count( input int data_beats_per_packet, input int gen_tlast = 1, input int gen_sync = 1); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); - endfunction: add_xfer_descriptor_packet_size + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endfunction: add_xfer_descriptor_sample_count // wait until data beat is sent virtual task beat_sent(); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endtask: beat_sent // wait until packet is sent virtual task packet_sent(); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endtask: packet_sent @@ -209,7 +209,7 @@ package m_axis_sequencer_pkg; endfunction: set_keep_some // create transfer descriptor - function void add_xfer_descriptor( + function void add_xfer_descriptor_byte_count( input int bytes_to_generate, input int gen_last = 1, input int gen_sync = 1); @@ -224,7 +224,7 @@ package m_axis_sequencer_pkg; descriptor_q.push_back(descriptor); this.queue_empty_sig = 0; ->>queue_ev; - endfunction: add_xfer_descriptor + endfunction: add_xfer_descriptor_byte_count // descriptor delay subroutine // - can be overridden in inherited classes for more specific delay generation @@ -351,13 +351,13 @@ package m_axis_sequencer_pkg; endtask: packet_sent // create transfer based on data beats per packet - virtual function void add_xfer_descriptor_packet_size( + virtual function void add_xfer_descriptor_sample_count( input int data_beats_per_packet, input int gen_tlast = 1, input int gen_sync = 1); - add_xfer_descriptor(data_beats_per_packet*AXIS_VIP_DATA_WIDTH/8, gen_tlast, gen_sync); - endfunction: add_xfer_descriptor_packet_size + add_xfer_descriptor_byte_count(data_beats_per_packet*AXIS_VIP_DATA_WIDTH/8, gen_tlast, gen_sync); + endfunction: add_xfer_descriptor_sample_count // set vif proxy to drive outputs with 0 when inactive virtual task set_inactive_drive_output_0(); @@ -497,6 +497,6 @@ package m_axis_sequencer_pkg; end endtask: sender - endclass + endclass: m_axis_sequencer -endpackage +endpackage: m_axis_sequencer_pkg diff --git a/library/vip/amd/axis/s_axis_sequencer.sv b/library/vip/amd/axis/s_axis_sequencer.sv index 6f566641..6745caa2 100644 --- a/library/vip/amd/axis/s_axis_sequencer.sv +++ b/library/vip/amd/axis/s_axis_sequencer.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -39,10 +39,10 @@ package s_axis_sequencer_pkg; import axi4stream_vip_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; import logger_pkg::*; - class s_axis_sequencer_base extends adi_component; + class s_axis_sequencer_base extends adi_sequencer; protected xil_axi4stream_data_byte byte_stream [$]; protected xil_axi4stream_ready_gen_policy_t mode; @@ -89,20 +89,20 @@ package s_axis_sequencer_pkg; // ready generation policy functions function void set_mode(input xil_axi4stream_ready_gen_policy_t mode); this.mode = mode; - endfunction + endfunction: set_mode function xil_axi4stream_ready_gen_policy_t get_mode(); return this.mode; - endfunction + endfunction: get_mode // high time functions function void set_high_time(input xil_axi4stream_uint high_time); this.high_time = high_time; - endfunction + endfunction: set_high_time function xil_axi4stream_uint get_high_time(); return this.high_time; - endfunction + endfunction: get_high_time function void set_high_time_range( input xil_axi4stream_uint high_time_min, @@ -110,12 +110,12 @@ package s_axis_sequencer_pkg; this.high_time_min = high_time_min; this.high_time_max = high_time_max; - endfunction + endfunction: set_high_time_range // low time functions function void set_low_time(input xil_axi4stream_uint low_time); this.low_time = low_time; - endfunction + endfunction: set_low_time function xil_axi4stream_uint get_low_time(); return this.low_time; @@ -127,7 +127,7 @@ package s_axis_sequencer_pkg; this.low_time_min = low_time_min; this.low_time_max = low_time_max; - endfunction + endfunction: set_low_time_range // function for verifying bytes task verify_byte(input bit [7:0] refdata); @@ -140,20 +140,22 @@ package s_axis_sequencer_pkg; this.error($sformatf("Unexpected data received. Expected: %0h Found: %0h Left : %0d", refdata, data, byte_stream.size())); end end - endtask + endtask: verify_byte // call ready generation function task run(); user_gen_tready(); - endtask + endtask: run // virtual tasks to be implemented virtual task user_gen_tready(); - endtask + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: user_gen_tready virtual task get_transfer(); - endtask + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: get_transfer endclass: s_axis_sequencer_base @@ -171,7 +173,7 @@ package s_axis_sequencer_pkg; super.new(name, parent); this.driver = driver; - endfunction + endfunction: new virtual task user_gen_tready(); @@ -194,8 +196,8 @@ package s_axis_sequencer_pkg; tready_gen.set_high_time_range(this.high_time_min, this.high_time_max); end this.driver.send_tready(tready_gen); - endtask + endtask: user_gen_tready - endclass + endclass: s_axis_sequencer -endpackage +endpackage: s_axis_sequencer_pkg diff --git a/scripts/make_tb_path.mk b/scripts/make_tb_path.mk index c1d3707b..f0c6d921 100644 --- a/scripts/make_tb_path.mk +++ b/scripts/make_tb_path.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/scripts/project-sim.mk b/scripts/project-sim.mk index 228a3710..dc6b13e6 100644 --- a/scripts/project-sim.mk +++ b/scripts/project-sim.mk @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018-2024 (c) Analog Devices, Inc. +## Copyright (C) 2018-2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/axi_tdd/Makefile b/testbenches/ip/axi_tdd/Makefile index 074e4aa1..95b799c2 100644 --- a/testbenches/ip/axi_tdd/Makefile +++ b/testbenches/ip/axi_tdd/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022(c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/axi_tdd/system_bd.tcl b/testbenches/ip/axi_tdd/system_bd.tcl index 88e6ba6b..9511a29b 100644 --- a/testbenches/ip/axi_tdd/system_bd.tcl +++ b/testbenches/ip/axi_tdd/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/axi_tdd/system_tb.sv b/testbenches/ip/axi_tdd/system_tb.sv index abf189ed..5d95605a 100644 --- a/testbenches/ip/axi_tdd/system_tb.sv +++ b/testbenches/ip/axi_tdd/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/axi_tdd/tests/test_program.sv b/testbenches/ip/axi_tdd/tests/test_program.sv index 0819bacd..a27562f4 100644 --- a/testbenches/ip/axi_tdd/tests/test_program.sv +++ b/testbenches/ip/axi_tdd/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; diff --git a/testbenches/ip/axi_tdd/waves/cfg1.wcfg b/testbenches/ip/axi_tdd/waves/cfg1.wcfg index 54504f63..ae7e3945 100644 --- a/testbenches/ip/axi_tdd/waves/cfg1.wcfg +++ b/testbenches/ip/axi_tdd/waves/cfg1.wcfg @@ -14,7 +14,6 @@ - diff --git a/testbenches/ip/axis_sequencers/Makefile b/testbenches/ip/axis_sequencers/Makefile index 0319e0db..095446af 100644 --- a/testbenches/ip/axis_sequencers/Makefile +++ b/testbenches/ip/axis_sequencers/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022(c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/axis_sequencers/environment.sv b/testbenches/ip/axis_sequencers/environment.sv index 4007dcc4..20198af9 100644 --- a/testbenches/ip/axis_sequencers/environment.sv +++ b/testbenches/ip/axis_sequencers/environment.sv @@ -1,10 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" `include "axis_definitions.svh" package environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; diff --git a/testbenches/ip/axis_sequencers/system_bd.tcl b/testbenches/ip/axis_sequencers/system_bd.tcl index b05934de..783cc71c 100644 --- a/testbenches/ip/axis_sequencers/system_bd.tcl +++ b/testbenches/ip/axis_sequencers/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/axis_sequencers/system_tb.sv b/testbenches/ip/axis_sequencers/system_tb.sv index 36eff4db..2723b531 100644 --- a/testbenches/ip/axis_sequencers/system_tb.sv +++ b/testbenches/ip/axis_sequencers/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/axis_sequencers/tests/test_program.sv b/testbenches/ip/axis_sequencers/tests/test_program.sv index 1e513528..08600126 100644 --- a/testbenches/ip/axis_sequencers/tests/test_program.sv +++ b/testbenches/ip/axis_sequencers/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; @@ -101,22 +99,22 @@ program test_program; 1: begin axis_seq_env.src_axis_agent.sequencer.set_descriptor_gen_mode(0); axis_seq_env.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_DATA_BEAT); - // axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor(32'h600, 1, 0); - axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor_packet_size(32'd10, 1, 0); + // axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor_byte_count(32'h600, 1, 0); + axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor_sample_count(32'd10, 1, 0); send_data_wd = new("Axis Sequencer Watchdog", 1000, "Send data"); end 2: begin axis_seq_env.src_axis_agent.sequencer.set_descriptor_gen_mode(0); axis_seq_env.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_DESCRIPTOR_QUEUE); - repeat (10) axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor(32'h600, 1, 0); + repeat (10) axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor_byte_count(32'h600, 1, 0); send_data_wd = new("Axis Sequencer Watchdog", 30000, "Send data"); end 3: begin axis_seq_env.src_axis_agent.sequencer.set_descriptor_gen_mode(1); axis_seq_env.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_PACKET); - axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor(32'h600, 1, 0); + axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor_byte_count(32'h600, 1, 0); send_data_wd = new("Axis Sequencer Watchdog", 20000, "Send data"); end diff --git a/testbenches/ip/axis_sequencers/waves/cfg1.wcfg b/testbenches/ip/axis_sequencers/waves/cfg1.wcfg index 4a417396..a320c7a1 100644 --- a/testbenches/ip/axis_sequencers/waves/cfg1.wcfg +++ b/testbenches/ip/axis_sequencers/waves/cfg1.wcfg @@ -14,7 +14,6 @@ - diff --git a/testbenches/ip/base/Makefile b/testbenches/ip/base/Makefile index 845120e2..74545915 100644 --- a/testbenches/ip/base/Makefile +++ b/testbenches/ip/base/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/base/system_bd.tcl b/testbenches/ip/base/system_bd.tcl index 7e456b0a..c0eabdcb 100644 --- a/testbenches/ip/base/system_bd.tcl +++ b/testbenches/ip/base/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/base/system_tb.sv b/testbenches/ip/base/system_tb.sv index b2e0c285..0ad34c87 100644 --- a/testbenches/ip/base/system_tb.sv +++ b/testbenches/ip/base/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/base/tests/test_program.sv b/testbenches/ip/base/tests/test_program.sv index d002e04a..cfd43413 100644 --- a/testbenches/ip/base/tests/test_program.sv +++ b/testbenches/ip/base/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/base/waves/cfg1.wcfg b/testbenches/ip/base/waves/cfg1.wcfg index 2fe219f8..4469603f 100644 --- a/testbenches/ip/base/waves/cfg1.wcfg +++ b/testbenches/ip/base/waves/cfg1.wcfg @@ -13,7 +13,6 @@ - diff --git a/testbenches/ip/data_offload/Makefile b/testbenches/ip/data_offload/Makefile index 7770fc41..136eaf46 100644 --- a/testbenches/ip/data_offload/Makefile +++ b/testbenches/ip/data_offload/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/data_offload/tests/test_program.sv b/testbenches/ip/data_offload/tests/test_program.sv index 3268193e..152fb9f1 100644 --- a/testbenches/ip/data_offload/tests/test_program.sv +++ b/testbenches/ip/data_offload/tests/test_program.sv @@ -1,3 +1,38 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" import axi_vip_pkg::*; @@ -82,7 +117,7 @@ module test_program(); // ADC stub env.adc_src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - env.adc_src_axis_seq.add_xfer_descriptor(`ADC_TRANSFER_LENGTH, 0, 0); + env.adc_src_axis_seq.add_xfer_descriptor_byte_count(`ADC_TRANSFER_LENGTH, 0, 0); // DAC stub dac_mode = XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE; diff --git a/testbenches/ip/data_offload_2/Makefile b/testbenches/ip/data_offload_2/Makefile index 08279063..6e4dc321 100644 --- a/testbenches/ip/data_offload_2/Makefile +++ b/testbenches/ip/data_offload_2/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2021(c) Analog Devices, Inc. +## Copyright (C) 2021 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/data_offload_2/data_offload_pkg.sv b/testbenches/ip/data_offload_2/data_offload_pkg.sv index 9b79fdb9..ee5b2d77 100644 --- a/testbenches/ip/data_offload_2/data_offload_pkg.sv +++ b/testbenches/ip/data_offload_2/data_offload_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -59,16 +59,16 @@ package data_offload_pkg; import axi_vip_pkg::*; - import reg_accessor_pkg::*; + import m_axi_sequencer_pkg::*; import logger_pkg::*; class data_offload; - reg_accessor bus; + m_axi_sequencer_base bus; xil_axi_ulong base_address; bit [1:0] reg_control; - function new (reg_accessor bus, xil_axi_ulong base_address); + function new (m_axi_sequencer_base bus, xil_axi_ulong base_address); this.bus = bus; this.base_address = base_address; endfunction diff --git a/testbenches/ip/data_offload_2/do_scoreboard.sv b/testbenches/ip/data_offload_2/do_scoreboard.sv index 8a4f56a3..0f1b1a00 100644 --- a/testbenches/ip/data_offload_2/do_scoreboard.sv +++ b/testbenches/ip/data_offload_2/do_scoreboard.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/data_offload_2/environment.sv b/testbenches/ip/data_offload_2/environment.sv index f204d1fb..5da43a2c 100644 --- a/testbenches/ip/data_offload_2/environment.sv +++ b/testbenches/ip/data_offload_2/environment.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/data_offload_2/system_tb.sv b/testbenches/ip/data_offload_2/system_tb.sv index f468237e..536ac1a3 100644 --- a/testbenches/ip/data_offload_2/system_tb.sv +++ b/testbenches/ip/data_offload_2/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/data_offload_2/tests/test_program.sv b/testbenches/ip/data_offload_2/tests/test_program.sv index a58d67f2..29ea8db1 100644 --- a/testbenches/ip/data_offload_2/tests/test_program.sv +++ b/testbenches/ip/data_offload_2/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -82,7 +82,7 @@ module test_program( env.src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); for (int i = 0; i < `SRC_TRANSFERS_INITIAL_COUNT; i++) - env.src_axis_seq.add_xfer_descriptor(`SRC_TRANSFERS_LENGTH, `PATH_TYPE, 0); // Only gen TLAST in TX path + env.src_axis_seq.add_xfer_descriptor_byte_count(`SRC_TRANSFERS_LENGTH, `PATH_TYPE, 0); // Only gen TLAST in TX path env.dst_axis_seq.set_mode(`DST_READY_MODE); env.dst_axis_seq.set_high_time(`DST_READY_HIGH); @@ -132,7 +132,7 @@ module test_program( #100 for (int i = 0; i < `SRC_TRANSFERS_DELAYED_COUNT; i++) - env.src_axis_seq.add_xfer_descriptor(`SRC_TRANSFERS_LENGTH, `PATH_TYPE, 0); + env.src_axis_seq.add_xfer_descriptor_byte_count(`SRC_TRANSFERS_LENGTH, `PATH_TYPE, 0); if (!`OFFLOAD_ONESHOT) begin env.src_axis_seq.wait_empty_descriptor_queue(); diff --git a/testbenches/ip/data_offload_2/tests/test_program_sync.sv b/testbenches/ip/data_offload_2/tests/test_program_sync.sv index 4955b720..4ce9c4f9 100644 --- a/testbenches/ip/data_offload_2/tests/test_program_sync.sv +++ b/testbenches/ip/data_offload_2/tests/test_program_sync.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -73,7 +73,7 @@ module test_program_sync ( //========================================================================= env.src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - env.src_axis_seq.add_xfer_descriptor(`SRC_TRANSFERS_LENGTH, 1, 0); + env.src_axis_seq.add_xfer_descriptor_byte_count(`SRC_TRANSFERS_LENGTH, 1, 0); env.dst_axis_seq.set_mode(`DST_READY_MODE); env.dst_axis_seq.set_high_time(`DST_READY_HIGH); @@ -140,7 +140,7 @@ module test_program_sync ( //init_req <= 1'b1; #100 - // env.src_axis_seq.add_xfer_descriptor(`SRC_TRANSFERS_LENGTH, 1, 0); + // env.src_axis_seq.add_xfer_descriptor_byte_count(`SRC_TRANSFERS_LENGTH, 1, 0); // @env.src_axis_seq.queue_empty; // init_req <= 1'b0; diff --git a/testbenches/ip/data_offload_2/waves/cfg1.wcfg b/testbenches/ip/data_offload_2/waves/cfg1.wcfg index 8c32df33..fe3763c0 100644 --- a/testbenches/ip/data_offload_2/waves/cfg1.wcfg +++ b/testbenches/ip/data_offload_2/waves/cfg1.wcfg @@ -14,7 +14,6 @@ - diff --git a/testbenches/ip/data_offload_2/waves/cfg2.wcfg b/testbenches/ip/data_offload_2/waves/cfg2.wcfg index 9fa04440..10d70433 100644 --- a/testbenches/ip/data_offload_2/waves/cfg2.wcfg +++ b/testbenches/ip/data_offload_2/waves/cfg2.wcfg @@ -14,7 +14,6 @@ - diff --git a/testbenches/ip/data_offload_2/waves/cfg3.wcfg b/testbenches/ip/data_offload_2/waves/cfg3.wcfg index fd2b5b57..c4434594 100644 --- a/testbenches/ip/data_offload_2/waves/cfg3.wcfg +++ b/testbenches/ip/data_offload_2/waves/cfg3.wcfg @@ -14,7 +14,7 @@ - + diff --git a/testbenches/ip/data_offload_2/waves/cfg4.wcfg b/testbenches/ip/data_offload_2/waves/cfg4.wcfg index 96af8b88..6ce229cf 100644 --- a/testbenches/ip/data_offload_2/waves/cfg4.wcfg +++ b/testbenches/ip/data_offload_2/waves/cfg4.wcfg @@ -14,7 +14,7 @@ - + diff --git a/testbenches/ip/dma_flock/environment.sv b/testbenches/ip/dma_flock/environment.sv index 6305c7c4..864938b5 100644 --- a/testbenches/ip/dma_flock/environment.sv +++ b/testbenches/ip/dma_flock/environment.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -39,7 +39,7 @@ package environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import scoreboard_pkg::*; import axi4stream_vip_pkg::*; diff --git a/testbenches/ip/dma_flock/scoreboard.sv b/testbenches/ip/dma_flock/scoreboard.sv index 7d532bd2..2e5f1828 100644 --- a/testbenches/ip/dma_flock/scoreboard.sv +++ b/testbenches/ip/dma_flock/scoreboard.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/testbenches/ip/dma_flock/system_tb.sv b/testbenches/ip/dma_flock/system_tb.sv index 8fb9ed2f..f76d6dd6 100644 --- a/testbenches/ip/dma_flock/system_tb.sv +++ b/testbenches/ip/dma_flock/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/testbenches/ip/dma_flock/tests/test_program.sv b/testbenches/ip/dma_flock/tests/test_program.sv index 9d34f74e..a0a7b268 100644 --- a/testbenches/ip/dma_flock/tests/test_program.sv +++ b/testbenches/ip/dma_flock/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -205,7 +205,7 @@ program test_program; begin for (int l = 0; l < m_seg.ylength; l++) begin // update the AXIS generator command - dma_flock_env.src_axis_agent.sequencer.add_xfer_descriptor(.bytes_to_generate(m_seg.length), + dma_flock_env.src_axis_agent.sequencer.add_xfer_descriptor_byte_count(.bytes_to_generate(m_seg.length), .gen_last(1), .gen_sync(l==0)); end diff --git a/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv b/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv index e0508432..d25cf0cd 100644 --- a/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv +++ b/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -253,7 +253,7 @@ program test_program_frame_delay; begin for (int l = 0; l < m_seg.ylength; l++) begin // update the AXIS generator command - dma_flock_env.src_axis_agent.sequencer.add_xfer_descriptor(.bytes_to_generate(m_seg.length), + dma_flock_env.src_axis_agent.sequencer.add_xfer_descriptor_byte_count(.bytes_to_generate(m_seg.length), .gen_last(1), .gen_sync(l==0)); end diff --git a/testbenches/ip/dma_flock/waves/cfg1.wcfg b/testbenches/ip/dma_flock/waves/cfg1.wcfg index f099716c..2e3129b7 100644 --- a/testbenches/ip/dma_flock/waves/cfg1.wcfg +++ b/testbenches/ip/dma_flock/waves/cfg1.wcfg @@ -6,7 +6,7 @@ - + @@ -19,7 +19,7 @@ - + diff --git a/testbenches/ip/dma_flock/waves/cfg2_fsync.wcfg b/testbenches/ip/dma_flock/waves/cfg2_fsync.wcfg index f099716c..2e3129b7 100644 --- a/testbenches/ip/dma_flock/waves/cfg2_fsync.wcfg +++ b/testbenches/ip/dma_flock/waves/cfg2_fsync.wcfg @@ -6,7 +6,7 @@ - + @@ -19,7 +19,7 @@ - + diff --git a/testbenches/ip/dma_flock/waves/cfg3_fsync_autorun.wcfg b/testbenches/ip/dma_flock/waves/cfg3_fsync_autorun.wcfg index f099716c..2e3129b7 100644 --- a/testbenches/ip/dma_flock/waves/cfg3_fsync_autorun.wcfg +++ b/testbenches/ip/dma_flock/waves/cfg3_fsync_autorun.wcfg @@ -6,7 +6,7 @@ - + @@ -19,7 +19,7 @@ - + diff --git a/testbenches/ip/dma_loopback/Makefile b/testbenches/ip/dma_loopback/Makefile index 3b461f72..aabd7597 100644 --- a/testbenches/ip/dma_loopback/Makefile +++ b/testbenches/ip/dma_loopback/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/dma_loopback/system_bd.tcl b/testbenches/ip/dma_loopback/system_bd.tcl index a2fa7b7c..f190aee1 100644 --- a/testbenches/ip/dma_loopback/system_bd.tcl +++ b/testbenches/ip/dma_loopback/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/dma_loopback/system_tb.sv b/testbenches/ip/dma_loopback/system_tb.sv index 3aa095c4..5c718309 100644 --- a/testbenches/ip/dma_loopback/system_tb.sv +++ b/testbenches/ip/dma_loopback/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/dma_loopback/tests/test_program.sv b/testbenches/ip/dma_loopback/tests/test_program.sv index 0c1c93b3..3201e808 100644 --- a/testbenches/ip/dma_loopback/tests/test_program.sv +++ b/testbenches/ip/dma_loopback/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" `include "axi_definitions.svh" diff --git a/testbenches/ip/dma_sg/system_bd.tcl b/testbenches/ip/dma_sg/system_bd.tcl index a7259071..41b9c641 100644 --- a/testbenches/ip/dma_sg/system_bd.tcl +++ b/testbenches/ip/dma_sg/system_bd.tcl @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/dma_sg/system_tb.sv b/testbenches/ip/dma_sg/system_tb.sv index 7ecc8a20..9c4dea57 100644 --- a/testbenches/ip/dma_sg/system_tb.sv +++ b/testbenches/ip/dma_sg/system_tb.sv @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/dma_sg/tests/test_program_1d.sv b/testbenches/ip/dma_sg/tests/test_program_1d.sv index e8ef4624..b3d7bbf7 100644 --- a/testbenches/ip/dma_sg/tests/test_program_1d.sv +++ b/testbenches/ip/dma_sg/tests/test_program_1d.sv @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; diff --git a/testbenches/ip/dma_sg/tests/test_program_2d.sv b/testbenches/ip/dma_sg/tests/test_program_2d.sv index 957db4d3..f225caf6 100644 --- a/testbenches/ip/dma_sg/tests/test_program_2d.sv +++ b/testbenches/ip/dma_sg/tests/test_program_2d.sv @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; diff --git a/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv b/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv index ed74898c..ba5c8c34 100644 --- a/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv +++ b/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; diff --git a/testbenches/ip/dma_sg/waves/cfg1.wcfg b/testbenches/ip/dma_sg/waves/cfg1.wcfg index b928ce3d..e93a4032 100644 --- a/testbenches/ip/dma_sg/waves/cfg1.wcfg +++ b/testbenches/ip/dma_sg/waves/cfg1.wcfg @@ -5,7 +5,7 @@ - + @@ -17,7 +17,7 @@ - + diff --git a/testbenches/ip/dma_sg/waves/cfg2.wcfg b/testbenches/ip/dma_sg/waves/cfg2.wcfg index a4a4c9df..a187b39f 100644 --- a/testbenches/ip/dma_sg/waves/cfg2.wcfg +++ b/testbenches/ip/dma_sg/waves/cfg2.wcfg @@ -5,7 +5,7 @@ - + @@ -17,7 +17,7 @@ - + diff --git a/testbenches/ip/hbm/Makefile b/testbenches/ip/hbm/Makefile index 956fb144..f6e420b5 100644 --- a/testbenches/ip/hbm/Makefile +++ b/testbenches/ip/hbm/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/hbm/system_bd.tcl b/testbenches/ip/hbm/system_bd.tcl index 71be57d5..33153841 100644 --- a/testbenches/ip/hbm/system_bd.tcl +++ b/testbenches/ip/hbm/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/hbm/system_tb.sv b/testbenches/ip/hbm/system_tb.sv index 3aa095c4..5c718309 100644 --- a/testbenches/ip/hbm/system_tb.sv +++ b/testbenches/ip/hbm/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/hbm/tests/test_program.sv b/testbenches/ip/hbm/tests/test_program.sv index 69abbfe0..1314ab12 100644 --- a/testbenches/ip/hbm/tests/test_program.sv +++ b/testbenches/ip/hbm/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/ip/i3c_controller/tests/test_program.sv b/testbenches/ip/i3c_controller/tests/test_program.sv index fa196f8e..21d7a395 100755 --- a/testbenches/ip/i3c_controller/tests/test_program.sv +++ b/testbenches/ip/i3c_controller/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/i3c_controller/waves/cfg1.wcfg b/testbenches/ip/i3c_controller/waves/cfg1.wcfg index 7649a5c6..090e3cba 100755 --- a/testbenches/ip/i3c_controller/waves/cfg1.wcfg +++ b/testbenches/ip/i3c_controller/waves/cfg1.wcfg @@ -13,7 +13,7 @@ - + diff --git a/testbenches/ip/jesd_loopback/Makefile b/testbenches/ip/jesd_loopback/Makefile index 197b3f07..9b805f0a 100644 --- a/testbenches/ip/jesd_loopback/Makefile +++ b/testbenches/ip/jesd_loopback/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/jesd_loopback/system_bd.tcl b/testbenches/ip/jesd_loopback/system_bd.tcl index 7b71ed7a..31d59778 100644 --- a/testbenches/ip/jesd_loopback/system_bd.tcl +++ b/testbenches/ip/jesd_loopback/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/jesd_loopback/system_tb.sv b/testbenches/ip/jesd_loopback/system_tb.sv index 2abe0526..6394fb3f 100644 --- a/testbenches/ip/jesd_loopback/system_tb.sv +++ b/testbenches/ip/jesd_loopback/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/jesd_loopback/tests/test_program.sv b/testbenches/ip/jesd_loopback/tests/test_program.sv index e37fe6f1..fcec78de 100644 --- a/testbenches/ip/jesd_loopback/tests/test_program.sv +++ b/testbenches/ip/jesd_loopback/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; diff --git a/testbenches/ip/jesd_loopback/waves/cfg1.wcfg b/testbenches/ip/jesd_loopback/waves/cfg1.wcfg index 571dd15b..56454f25 100644 --- a/testbenches/ip/jesd_loopback/waves/cfg1.wcfg +++ b/testbenches/ip/jesd_loopback/waves/cfg1.wcfg @@ -6,7 +6,7 @@ - + @@ -20,7 +20,7 @@ - + diff --git a/testbenches/ip/jesd_loopback_64b/Makefile b/testbenches/ip/jesd_loopback_64b/Makefile index 197b3f07..9b805f0a 100644 --- a/testbenches/ip/jesd_loopback_64b/Makefile +++ b/testbenches/ip/jesd_loopback_64b/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/jesd_loopback_64b/system_bd.tcl b/testbenches/ip/jesd_loopback_64b/system_bd.tcl index 33387a9a..e032ad70 100644 --- a/testbenches/ip/jesd_loopback_64b/system_bd.tcl +++ b/testbenches/ip/jesd_loopback_64b/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/jesd_loopback_64b/system_tb.sv b/testbenches/ip/jesd_loopback_64b/system_tb.sv index 656b5063..8e1f73d4 100644 --- a/testbenches/ip/jesd_loopback_64b/system_tb.sv +++ b/testbenches/ip/jesd_loopback_64b/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/jesd_loopback_64b/tests/test_program.sv b/testbenches/ip/jesd_loopback_64b/tests/test_program.sv index 365fa399..c93f33ce 100644 --- a/testbenches/ip/jesd_loopback_64b/tests/test_program.sv +++ b/testbenches/ip/jesd_loopback_64b/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; diff --git a/testbenches/ip/scoreboard/Makefile b/testbenches/ip/scoreboard/Makefile index b8505a2d..b39c6e04 100644 --- a/testbenches/ip/scoreboard/Makefile +++ b/testbenches/ip/scoreboard/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022(c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv index 36a298c1..cd4405ad 100644 --- a/testbenches/ip/scoreboard/environment.sv +++ b/testbenches/ip/scoreboard/environment.sv @@ -1,3 +1,38 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" `include "axi_definitions.svh" `include "axis_definitions.svh" @@ -5,7 +40,7 @@ package environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; @@ -59,7 +94,7 @@ package environment_pkg; task configure(int bytes_to_generate); // ADC stub this.adc_src_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - this.adc_src_axis_agent.sequencer.add_xfer_descriptor(bytes_to_generate, 0, 0); + this.adc_src_axis_agent.sequencer.add_xfer_descriptor_byte_count(bytes_to_generate, 0, 0); // DAC stub this.dac_dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); diff --git a/testbenches/ip/scoreboard/system_bd.tcl b/testbenches/ip/scoreboard/system_bd.tcl index ccf48bfd..a0d7856a 100644 --- a/testbenches/ip/scoreboard/system_bd.tcl +++ b/testbenches/ip/scoreboard/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/scoreboard/system_tb.sv b/testbenches/ip/scoreboard/system_tb.sv index 36eff4db..2723b531 100644 --- a/testbenches/ip/scoreboard/system_tb.sv +++ b/testbenches/ip/scoreboard/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/scoreboard/tests/test_program.sv b/testbenches/ip/scoreboard/tests/test_program.sv index dc821f98..48f580e6 100644 --- a/testbenches/ip/scoreboard/tests/test_program.sv +++ b/testbenches/ip/scoreboard/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" `include "axi_definitions.svh" `include "axis_definitions.svh" diff --git a/testbenches/ip/scoreboard/waves/cfg1.wcfg b/testbenches/ip/scoreboard/waves/cfg1.wcfg index d74bb02b..4e1d4cb4 100644 --- a/testbenches/ip/scoreboard/waves/cfg1.wcfg +++ b/testbenches/ip/scoreboard/waves/cfg1.wcfg @@ -6,7 +6,7 @@ - + @@ -22,7 +22,7 @@ - + diff --git a/testbenches/ip/spi_engine/Makefile b/testbenches/ip/spi_engine/Makefile index 629aab2d..c256e5a8 100644 --- a/testbenches/ip/spi_engine/Makefile +++ b/testbenches/ip/spi_engine/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -22,12 +22,10 @@ ENV_DEPS += $(HDL_LIBRARY_PATH)/common/ad_edge_detect.v LIB_DEPS += axi_clkgen LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid LIB_DEPS += spi_engine/axi_spi_engine LIB_DEPS += spi_engine/spi_engine_execution LIB_DEPS += spi_engine/spi_engine_interconnect LIB_DEPS += spi_engine/spi_engine_offload -LIB_DEPS += sysid_rom # default test programs # Format is: diff --git a/testbenches/ip/spi_engine/spi_environment.sv b/testbenches/ip/spi_engine/spi_environment.sv index 76f17bd3..27bea6bf 100644 --- a/testbenches/ip/spi_engine/spi_environment.sv +++ b/testbenches/ip/spi_engine/spi_environment.sv @@ -38,7 +38,7 @@ package spi_environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; diff --git a/testbenches/ip/spi_engine/system_tb.sv b/testbenches/ip/spi_engine/system_tb.sv index 71a5a321..d002884d 100644 --- a/testbenches/ip/spi_engine/system_tb.sv +++ b/testbenches/ip/spi_engine/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 - 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/spi_engine/tests/test_program.sv b/testbenches/ip/spi_engine/tests/test_program.sv index 91cb8631..06dfdf4b 100644 --- a/testbenches/ip/spi_engine/tests/test_program.sv +++ b/testbenches/ip/spi_engine/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -224,7 +224,7 @@ task sdo_stream_gen( data[i] = (tx_data & (8'hFF << 8*i)) >> 8*i; spi_env.sdo_src_seq.push_byte_for_stream(data[i]); end - spi_env.sdo_src_seq.add_xfer_descriptor((`DATA_WIDTH/8),0,0); + spi_env.sdo_src_seq.add_xfer_descriptor_byte_count((`DATA_WIDTH/8),0,0); `endif endtask diff --git a/testbenches/ip/spi_engine/waves/cfg01.wcfg b/testbenches/ip/spi_engine/waves/cfg01.wcfg index 274ebdb8..c8dac025 100644 --- a/testbenches/ip/spi_engine/waves/cfg01.wcfg +++ b/testbenches/ip/spi_engine/waves/cfg01.wcfg @@ -12,7 +12,7 @@ - + diff --git a/testbenches/ip/spi_engine/waves/cfg_inv_cs.wcfg b/testbenches/ip/spi_engine/waves/cfg_inv_cs.wcfg index 9ae838f3..3bb16eb9 100644 --- a/testbenches/ip/spi_engine/waves/cfg_inv_cs.wcfg +++ b/testbenches/ip/spi_engine/waves/cfg_inv_cs.wcfg @@ -12,7 +12,7 @@ - + diff --git a/testbenches/ip/spi_engine/waves/cfg_sdo_streaming.wcfg b/testbenches/ip/spi_engine/waves/cfg_sdo_streaming.wcfg index 6d15b161..e7262c34 100644 --- a/testbenches/ip/spi_engine/waves/cfg_sdo_streaming.wcfg +++ b/testbenches/ip/spi_engine/waves/cfg_sdo_streaming.wcfg @@ -20,7 +20,7 @@ - + diff --git a/testbenches/ip/util_axis_fifo/Makefile b/testbenches/ip/util_axis_fifo/Makefile index a1d6b38a..55ee4501 100644 --- a/testbenches/ip/util_axis_fifo/Makefile +++ b/testbenches/ip/util_axis_fifo/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022(c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/util_axis_fifo/environment.sv b/testbenches/ip/util_axis_fifo/environment.sv index 3c5d6372..be53ef02 100644 --- a/testbenches/ip/util_axis_fifo/environment.sv +++ b/testbenches/ip/util_axis_fifo/environment.sv @@ -1,10 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" `include "axis_definitions.svh" package environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; import s_axis_sequencer_pkg::*; diff --git a/testbenches/ip/util_axis_fifo/system_bd.tcl b/testbenches/ip/util_axis_fifo/system_bd.tcl index 79aeedc3..32bbcb7a 100644 --- a/testbenches/ip/util_axis_fifo/system_bd.tcl +++ b/testbenches/ip/util_axis_fifo/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/util_axis_fifo/system_tb.sv b/testbenches/ip/util_axis_fifo/system_tb.sv index e92f32ea..57d8c109 100644 --- a/testbenches/ip/util_axis_fifo/system_tb.sv +++ b/testbenches/ip/util_axis_fifo/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/util_axis_fifo/tests/test_program.sv b/testbenches/ip/util_axis_fifo/tests/test_program.sv index 98696ca4..3f124c2d 100644 --- a/testbenches/ip/util_axis_fifo/tests/test_program.sv +++ b/testbenches/ip/util_axis_fifo/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" `include "axis_definitions.svh" @@ -103,11 +101,11 @@ program test_program (); if (!`TKEEP_EN) begin repeat($urandom_range(1,5)) begin - uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_packet_size($urandom_range(1,128), `TLAST_EN, 0); + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_sample_count($urandom_range(1,128), `TLAST_EN, 0); end end else begin repeat($urandom_range(1,5)) begin - uaf_env.input_axis_agent.sequencer.add_xfer_descriptor($urandom_range(1,1024), `TLAST_EN, 0); + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_byte_count($urandom_range(1,1024), `TLAST_EN, 0); end end diff --git a/testbenches/ip/util_axis_fifo/waves/cfg_rand.wcfg b/testbenches/ip/util_axis_fifo/waves/cfg_rand.wcfg index 2346364e..9b1d7fa9 100644 --- a/testbenches/ip/util_axis_fifo/waves/cfg_rand.wcfg +++ b/testbenches/ip/util_axis_fifo/waves/cfg_rand.wcfg @@ -20,7 +20,7 @@ - + diff --git a/testbenches/ip/util_axis_fifo_asym/Makefile b/testbenches/ip/util_axis_fifo_asym/Makefile index 72f90010..b5bf4cd6 100644 --- a/testbenches/ip/util_axis_fifo_asym/Makefile +++ b/testbenches/ip/util_axis_fifo_asym/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022(c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/util_axis_fifo_asym/environment.sv b/testbenches/ip/util_axis_fifo_asym/environment.sv index 3c5d6372..9da1f018 100644 --- a/testbenches/ip/util_axis_fifo_asym/environment.sv +++ b/testbenches/ip/util_axis_fifo_asym/environment.sv @@ -1,10 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" `include "axis_definitions.svh" package environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; import s_axis_sequencer_pkg::*; diff --git a/testbenches/ip/util_axis_fifo_asym/system_bd.tcl b/testbenches/ip/util_axis_fifo_asym/system_bd.tcl index 66fd1740..5352fb0d 100644 --- a/testbenches/ip/util_axis_fifo_asym/system_bd.tcl +++ b/testbenches/ip/util_axis_fifo_asym/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/util_axis_fifo_asym/system_tb.sv b/testbenches/ip/util_axis_fifo_asym/system_tb.sv index e92f32ea..57d8c109 100644 --- a/testbenches/ip/util_axis_fifo_asym/system_tb.sv +++ b/testbenches/ip/util_axis_fifo_asym/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv index a2fc7226..9caafd9b 100644 --- a/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv +++ b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" `include "axis_definitions.svh" @@ -98,11 +96,11 @@ program test_program (); if ((!`TKEEP_EN || !`TLAST_EN) && `INPUT_WIDTH < `OUTPUT_WIDTH) begin repeat($urandom_range(1,5)) begin - uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_packet_size($urandom_range(1,128)*`OUTPUT_WIDTH/`INPUT_WIDTH, `TLAST_EN, 0); + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_sample_count($urandom_range(1,128)*`OUTPUT_WIDTH/`INPUT_WIDTH, `TLAST_EN, 0); end end else begin repeat($urandom_range(1,5)) begin - uaf_env.input_axis_agent.sequencer.add_xfer_descriptor($urandom_range(1,1024), `TLAST_EN, 0); + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_byte_count($urandom_range(1,1024), `TLAST_EN, 0); end end diff --git a/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg b/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg index d556dd92..f762d66c 100644 --- a/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg +++ b/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg @@ -20,7 +20,7 @@ - + diff --git a/testbenches/ip/util_pack/Makefile b/testbenches/ip/util_pack/Makefile index 34d6d9ed..4a5d1227 100644 --- a/testbenches/ip/util_pack/Makefile +++ b/testbenches/ip/util_pack/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/util_pack/environment.sv b/testbenches/ip/util_pack/environment.sv index 41cdd55e..2be4feae 100644 --- a/testbenches/ip/util_pack/environment.sv +++ b/testbenches/ip/util_pack/environment.sv @@ -1,9 +1,44 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" package environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; @@ -52,13 +87,13 @@ package environment_pkg; task configure(int bytes_to_generate); // TX stubs this.tx_src_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - this.tx_src_axis_agent.sequencer.add_xfer_descriptor(bytes_to_generate, 0, 0); + this.tx_src_axis_agent.sequencer.add_xfer_descriptor_byte_count(bytes_to_generate, 0, 0); this.tx_dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); // RX stub this.rx_src_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - this.rx_src_axis_agent.sequencer.add_xfer_descriptor(bytes_to_generate, 0, 0); + this.rx_src_axis_agent.sequencer.add_xfer_descriptor_byte_count(bytes_to_generate, 0, 0); this.rx_dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); endtask diff --git a/testbenches/ip/util_pack/system_bd.tcl b/testbenches/ip/util_pack/system_bd.tcl index e1bd41d9..f0f0e29d 100644 --- a/testbenches/ip/util_pack/system_bd.tcl +++ b/testbenches/ip/util_pack/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/util_pack/system_tb.sv b/testbenches/ip/util_pack/system_tb.sv index b2e0c285..0ad34c87 100644 --- a/testbenches/ip/util_pack/system_tb.sv +++ b/testbenches/ip/util_pack/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/util_pack/tests/test_program.sv b/testbenches/ip/util_pack/tests/test_program.sv index 9e2ae2af..83e520d6 100644 --- a/testbenches/ip/util_pack/tests/test_program.sv +++ b/testbenches/ip/util_pack/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" `include "axi_definitions.svh" `include "axis_definitions.svh" diff --git a/testbenches/ip/util_pack/waves/cfg1.wcfg b/testbenches/ip/util_pack/waves/cfg1.wcfg index 6319d37f..2ef4b934 100644 --- a/testbenches/ip/util_pack/waves/cfg1.wcfg +++ b/testbenches/ip/util_pack/waves/cfg1.wcfg @@ -6,7 +6,7 @@ - + @@ -20,7 +20,7 @@ - + diff --git a/testbenches/ip/util_pack/waves/cfg_rand.wcfg b/testbenches/ip/util_pack/waves/cfg_rand.wcfg index 6319d37f..2ef4b934 100644 --- a/testbenches/ip/util_pack/waves/cfg_rand.wcfg +++ b/testbenches/ip/util_pack/waves/cfg_rand.wcfg @@ -6,7 +6,7 @@ - + @@ -20,7 +20,7 @@ - + diff --git a/testbenches/project/ad463x/Makefile b/testbenches/project/ad463x/Makefile index ba422b1e..a76023b9 100644 --- a/testbenches/project/ad463x/Makefile +++ b/testbenches/project/ad463x/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -21,12 +21,9 @@ LIB_DEPS += ad463x_data_capture LIB_DEPS += axi_dmac LIB_DEPS += util_pack/util_upack2 LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom LIB_DEPS += axi_clkgen LIB_DEPS += axi_i2s_adi LIB_DEPS += axi_pwm_gen -LIB_DEPS += axi_sysid LIB_DEPS += spi_engine/axi_spi_engine LIB_DEPS += spi_engine/spi_axis_reorder LIB_DEPS += spi_engine/spi_engine_execution diff --git a/testbenches/project/ad463x/system_bd.tcl b/testbenches/project/ad463x/system_bd.tcl index 68071e82..9d43872f 100644 --- a/testbenches/project/ad463x/system_bd.tcl +++ b/testbenches/project/ad463x/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/ad463x/system_tb.sv b/testbenches/project/ad463x/system_tb.sv index 81a65aaf..b36523b1 100644 --- a/testbenches/project/ad463x/system_tb.sv +++ b/testbenches/project/ad463x/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad463x/tests/test_program.sv b/testbenches/project/ad463x/tests/test_program.sv index bb8c049a..0b19dd4d 100644 --- a/testbenches/project/ad463x/tests/test_program.sv +++ b/testbenches/project/ad463x/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad57xx/Makefile b/testbenches/project/ad57xx/Makefile index 45db572c..15fd8b7e 100644 --- a/testbenches/project/ad57xx/Makefile +++ b/testbenches/project/ad57xx/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -19,13 +19,11 @@ SV_DEPS += ad57xx_environment.sv LIB_DEPS += axi_clkgen LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid LIB_DEPS += util_axis_fifo LIB_DEPS += spi_engine/axi_spi_engine LIB_DEPS += spi_engine/spi_engine_execution LIB_DEPS += spi_engine/spi_engine_interconnect LIB_DEPS += spi_engine/spi_engine_offload -LIB_DEPS += sysid_rom SIM_LIB_DEPS += spi_vip diff --git a/testbenches/project/ad57xx/ad57xx_environment.sv b/testbenches/project/ad57xx/ad57xx_environment.sv index 7ed92c78..3978ce52 100644 --- a/testbenches/project/ad57xx/ad57xx_environment.sv +++ b/testbenches/project/ad57xx/ad57xx_environment.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -38,7 +38,7 @@ package ad57xx_environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import s_spi_sequencer_pkg::*; import adi_spi_vip_pkg::*; diff --git a/testbenches/project/ad57xx/system_bd.tcl b/testbenches/project/ad57xx/system_bd.tcl index 0fc21b31..20ec4742 100644 --- a/testbenches/project/ad57xx/system_bd.tcl +++ b/testbenches/project/ad57xx/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/testbenches/project/ad57xx/waves/cfg1.wcfg b/testbenches/project/ad57xx/waves/cfg1.wcfg index ac78db12..7b6f8893 100644 --- a/testbenches/project/ad57xx/waves/cfg1.wcfg +++ b/testbenches/project/ad57xx/waves/cfg1.wcfg @@ -20,7 +20,7 @@ - + diff --git a/testbenches/project/ad738x/Makefile b/testbenches/project/ad738x/Makefile index a15dd306..8946fadb 100644 --- a/testbenches/project/ad738x/Makefile +++ b/testbenches/project/ad738x/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2021(c) Analog Devices, Inc. +## Copyright (C) 2021 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -18,12 +18,10 @@ LIB_DEPS += axi_clkgen LIB_DEPS += axi_dmac LIB_DEPS += axi_i2s_adi LIB_DEPS += axi_pwm_gen -LIB_DEPS += axi_sysid LIB_DEPS += spi_engine/axi_spi_engine LIB_DEPS += spi_engine/spi_engine_execution LIB_DEPS += spi_engine/spi_engine_interconnect LIB_DEPS += spi_engine/spi_engine_offload -LIB_DEPS += sysid_rom LIB_DEPS += util_axis_upscale LIB_DEPS += util_pulse_gen diff --git a/testbenches/project/ad738x/system_bd.tcl b/testbenches/project/ad738x/system_bd.tcl index bdab458f..bb842441 100644 --- a/testbenches/project/ad738x/system_bd.tcl +++ b/testbenches/project/ad738x/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/ad738x/system_tb.sv b/testbenches/project/ad738x/system_tb.sv index b63b2f1b..667e6827 100644 --- a/testbenches/project/ad738x/system_tb.sv +++ b/testbenches/project/ad738x/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad738x/tests/test_program.sv b/testbenches/project/ad738x/tests/test_program.sv index dd77f5f5..4f4ea8e8 100644 --- a/testbenches/project/ad738x/tests/test_program.sv +++ b/testbenches/project/ad738x/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7606x/Makefile b/testbenches/project/ad7606x/Makefile index 879ba8d2..3ee06a16 100755 --- a/testbenches/project/ad7606x/Makefile +++ b/testbenches/project/ad7606x/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022 (c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -26,8 +26,6 @@ LIB_DEPS += axi_hdmi_tx LIB_DEPS += axi_i2s_adi LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_spdif_tx -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom LIB_DEPS += util_i2c_mixer LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += util_cdc diff --git a/testbenches/project/ad7606x/system_bd.tcl b/testbenches/project/ad7606x/system_bd.tcl index 46d20621..c0f8b635 100755 --- a/testbenches/project/ad7606x/system_bd.tcl +++ b/testbenches/project/ad7606x/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/ad7606x/system_tb.sv b/testbenches/project/ad7606x/system_tb.sv index db6083ae..bfbb0f8b 100755 --- a/testbenches/project/ad7606x/system_tb.sv +++ b/testbenches/project/ad7606x/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7606x/tests/test_program_4ch.sv b/testbenches/project/ad7606x/tests/test_program_4ch.sv index e33a02d2..b259a2bc 100755 --- a/testbenches/project/ad7606x/tests/test_program_4ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_4ch.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7606x/tests/test_program_6ch.sv b/testbenches/project/ad7606x/tests/test_program_6ch.sv index f9fe57e9..140783da 100755 --- a/testbenches/project/ad7606x/tests/test_program_6ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_6ch.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7606x/tests/test_program_8ch.sv b/testbenches/project/ad7606x/tests/test_program_8ch.sv index 38cd7d80..a3eec321 100755 --- a/testbenches/project/ad7606x/tests/test_program_8ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_8ch.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7606x/tests/test_program_si.sv b/testbenches/project/ad7606x/tests/test_program_si.sv index 3ab60eed..341c6a0f 100755 --- a/testbenches/project/ad7606x/tests/test_program_si.sv +++ b/testbenches/project/ad7606x/tests/test_program_si.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7606x/waves/system_tb_behav.wcfg b/testbenches/project/ad7606x/waves/system_tb_behav.wcfg index b675d7af..5461ca48 100644 --- a/testbenches/project/ad7606x/waves/system_tb_behav.wcfg +++ b/testbenches/project/ad7606x/waves/system_tb_behav.wcfg @@ -17,7 +17,7 @@ - + diff --git a/testbenches/project/ad7616/Makefile b/testbenches/project/ad7616/Makefile index f9e4de96..2d6e09c4 100755 --- a/testbenches/project/ad7616/Makefile +++ b/testbenches/project/ad7616/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022 (c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -22,12 +22,10 @@ LIB_DEPS += axi_clkgen LIB_DEPS += axi_ad7616 LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid LIB_DEPS += spi_engine/axi_spi_engine LIB_DEPS += spi_engine/spi_engine_execution LIB_DEPS += spi_engine/spi_engine_interconnect LIB_DEPS += spi_engine/spi_engine_offload -LIB_DEPS += sysid_rom # default test program TP := test_program_si diff --git a/testbenches/project/ad7616/system_bd.tcl b/testbenches/project/ad7616/system_bd.tcl index 7fd76333..26c8695d 100755 --- a/testbenches/project/ad7616/system_bd.tcl +++ b/testbenches/project/ad7616/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/ad7616/system_tb.sv b/testbenches/project/ad7616/system_tb.sv index 73480c91..21f79533 100755 --- a/testbenches/project/ad7616/system_tb.sv +++ b/testbenches/project/ad7616/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7616/tests/test_program_pi.sv b/testbenches/project/ad7616/tests/test_program_pi.sv index 6f302f47..1d9c557d 100755 --- a/testbenches/project/ad7616/tests/test_program_pi.sv +++ b/testbenches/project/ad7616/tests/test_program_pi.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7616/tests/test_program_si.sv b/testbenches/project/ad7616/tests/test_program_si.sv index 54407e77..bb2544d9 100755 --- a/testbenches/project/ad7616/tests/test_program_si.sv +++ b/testbenches/project/ad7616/tests/test_program_si.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7616/waves/cfg_pi.wcfg b/testbenches/project/ad7616/waves/cfg_pi.wcfg index 74cfc7aa..9e48c1fc 100644 --- a/testbenches/project/ad7616/waves/cfg_pi.wcfg +++ b/testbenches/project/ad7616/waves/cfg_pi.wcfg @@ -12,7 +12,7 @@ - + diff --git a/testbenches/project/ad7616/waves/cfg_si.wcfg b/testbenches/project/ad7616/waves/cfg_si.wcfg index 31026027..22e7c6b7 100644 --- a/testbenches/project/ad7616/waves/cfg_si.wcfg +++ b/testbenches/project/ad7616/waves/cfg_si.wcfg @@ -12,7 +12,7 @@ - + diff --git a/testbenches/project/ad9083/Makefile b/testbenches/project/ad9083/Makefile index 79078678..8d54f115 100644 --- a/testbenches/project/ad9083/Makefile +++ b/testbenches/project/ad9083/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -29,8 +29,6 @@ LIB_DEPS += util_pack/util_upack2 LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/util_adxcvr -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom # default test program TP := test_program diff --git a/testbenches/project/ad9083/system_bd.tcl b/testbenches/project/ad9083/system_bd.tcl index 7b199bb6..c978ab69 100644 --- a/testbenches/project/ad9083/system_bd.tcl +++ b/testbenches/project/ad9083/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/ad9083/system_tb.sv b/testbenches/project/ad9083/system_tb.sv index 29d4246f..e95c19ab 100644 --- a/testbenches/project/ad9083/system_tb.sv +++ b/testbenches/project/ad9083/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad9083/tests/test_program.sv b/testbenches/project/ad9083/tests/test_program.sv index 6adfa373..530dce4d 100644 --- a/testbenches/project/ad9083/tests/test_program.sv +++ b/testbenches/project/ad9083/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/ad_quadmxfe1_ebz/Makefile b/testbenches/project/ad_quadmxfe1_ebz/Makefile index 9e9d4915..04c19b42 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/Makefile +++ b/testbenches/project/ad_quadmxfe1_ebz/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -32,8 +32,6 @@ LIB_DEPS += util_pack/util_upack2 LIB_DEPS += util_pad LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/util_adxcvr -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom # default test program diff --git a/testbenches/project/ad_quadmxfe1_ebz/system_bd.tcl b/testbenches/project/ad_quadmxfe1_ebz/system_bd.tcl index ea5538cb..b7886d0c 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/system_bd.tcl +++ b/testbenches/project/ad_quadmxfe1_ebz/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/ad_quadmxfe1_ebz/system_tb.sv b/testbenches/project/ad_quadmxfe1_ebz/system_tb.sv index 9638c3dd..92b8445f 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/system_tb.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv b/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv index 26d80231..d7a66cc2 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv index ac31f492..ba9ffd3c 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv index 85233c61..661b9c70 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/adrv9001/Makefile b/testbenches/project/adrv9001/Makefile index c17fe47d..efb482a5 100644 --- a/testbenches/project/adrv9001/Makefile +++ b/testbenches/project/adrv9001/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -19,8 +19,6 @@ LIB_DEPS += axi_dmac LIB_DEPS += axi_adrv9001 LIB_DEPS += util_pack/util_upack2 LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom # default test program TP := test_program diff --git a/testbenches/project/adrv9001/system_bd.tcl b/testbenches/project/adrv9001/system_bd.tcl index d177cbb2..accace89 100644 --- a/testbenches/project/adrv9001/system_bd.tcl +++ b/testbenches/project/adrv9001/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/adrv9001/system_tb.sv b/testbenches/project/adrv9001/system_tb.sv index df6e59ca..5ae474dd 100644 --- a/testbenches/project/adrv9001/system_tb.sv +++ b/testbenches/project/adrv9001/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/adrv9001/tests/test_program.sv b/testbenches/project/adrv9001/tests/test_program.sv index f4608377..296d9629 100644 --- a/testbenches/project/adrv9001/tests/test_program.sv +++ b/testbenches/project/adrv9001/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import axi_vip_pkg::*; diff --git a/testbenches/project/adrv9009/Makefile b/testbenches/project/adrv9009/Makefile index f11e8b86..44b5c1b4 100755 --- a/testbenches/project/adrv9009/Makefile +++ b/testbenches/project/adrv9009/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -18,14 +18,12 @@ SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_adc_pkg.sv LIB_DEPS += axi_clkgen LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac LIB_DEPS += jesd204/axi_jesd204_tx LIB_DEPS += jesd204/jesd204_tx LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc LIB_DEPS += jesd204/axi_jesd204_rx LIB_DEPS += jesd204/jesd204_rx -LIB_DEPS += sysid_rom LIB_DEPS += util_dacfifo LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += util_pack/util_upack2 diff --git a/testbenches/project/adrv9009/system_bd.tcl b/testbenches/project/adrv9009/system_bd.tcl index 58dc58ac..9ee413bb 100755 --- a/testbenches/project/adrv9009/system_bd.tcl +++ b/testbenches/project/adrv9009/system_bd.tcl @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/adrv9009/system_tb.sv b/testbenches/project/adrv9009/system_tb.sv index 869e982d..1cbfa1a1 100755 --- a/testbenches/project/adrv9009/system_tb.sv +++ b/testbenches/project/adrv9009/system_tb.sv @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/adrv9009/tests/test_program.sv b/testbenches/project/adrv9009/tests/test_program.sv index 7ffd9494..6804367b 100755 --- a/testbenches/project/adrv9009/tests/test_program.sv +++ b/testbenches/project/adrv9009/tests/test_program.sv @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/adrv9009/waves/cfg1.wcfg b/testbenches/project/adrv9009/waves/cfg1.wcfg index f12b0f16..d974f8f9 100755 --- a/testbenches/project/adrv9009/waves/cfg1.wcfg +++ b/testbenches/project/adrv9009/waves/cfg1.wcfg @@ -6,7 +6,7 @@ - + @@ -19,7 +19,7 @@ - + diff --git a/testbenches/project/fmcomms2/Makefile b/testbenches/project/fmcomms2/Makefile index 7e64b79b..e3dd8868 100644 --- a/testbenches/project/fmcomms2/Makefile +++ b/testbenches/project/fmcomms2/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -16,8 +16,6 @@ SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_common_pkg.sv LIB_DEPS += axi_ad9361 LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += util_pack/util_upack2 LIB_DEPS += util_rfifo diff --git a/testbenches/project/fmcomms2/system_bd.tcl b/testbenches/project/fmcomms2/system_bd.tcl index 1fdd39b0..07429f7d 100644 --- a/testbenches/project/fmcomms2/system_bd.tcl +++ b/testbenches/project/fmcomms2/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/fmcomms2/system_tb.sv b/testbenches/project/fmcomms2/system_tb.sv index 1d23bbed..af75692e 100644 --- a/testbenches/project/fmcomms2/system_tb.sv +++ b/testbenches/project/fmcomms2/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/fmcomms2/tests/test_program.sv b/testbenches/project/fmcomms2/tests/test_program.sv index f87f626b..ead8416b 100644 --- a/testbenches/project/fmcomms2/tests/test_program.sv +++ b/testbenches/project/fmcomms2/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/mxfe/Makefile b/testbenches/project/mxfe/Makefile index 1af65b08..e1cb4ac0 100644 --- a/testbenches/project/mxfe/Makefile +++ b/testbenches/project/mxfe/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -35,8 +35,6 @@ LIB_DEPS += util_pack/util_upack2 LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/util_adxcvr -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom # default test program TP := test_program diff --git a/testbenches/project/mxfe/system_bd.tcl b/testbenches/project/mxfe/system_bd.tcl index 31c05a74..8ace956d 100644 --- a/testbenches/project/mxfe/system_bd.tcl +++ b/testbenches/project/mxfe/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/mxfe/system_tb.sv b/testbenches/project/mxfe/system_tb.sv index 4d06b4a0..80bb03c2 100644 --- a/testbenches/project/mxfe/system_tb.sv +++ b/testbenches/project/mxfe/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/mxfe/tests/test_program.sv b/testbenches/project/mxfe/tests/test_program.sv index ec65fea1..cbfa6728 100644 --- a/testbenches/project/mxfe/tests/test_program.sv +++ b/testbenches/project/mxfe/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/mxfe/waves/cfg1.wcfg b/testbenches/project/mxfe/waves/cfg1.wcfg index e2aea726..bda64c90 100644 --- a/testbenches/project/mxfe/waves/cfg1.wcfg +++ b/testbenches/project/mxfe/waves/cfg1.wcfg @@ -6,7 +6,7 @@ - + @@ -21,7 +21,7 @@ - + diff --git a/testbenches/project/pluto/system_bd.tcl b/testbenches/project/pluto/system_bd.tcl index 89a966c9..f2b1add1 100644 --- a/testbenches/project/pluto/system_bd.tcl +++ b/testbenches/project/pluto/system_bd.tcl @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/pluto/system_tb.sv b/testbenches/project/pluto/system_tb.sv index 9d80b90f..653a1155 100644 --- a/testbenches/project/pluto/system_tb.sv +++ b/testbenches/project/pluto/system_tb.sv @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/pluto/tests/test_program.sv b/testbenches/project/pluto/tests/test_program.sv index fe35cb2e..8dd72e0a 100644 --- a/testbenches/project/pluto/tests/test_program.sv +++ b/testbenches/project/pluto/tests/test_program.sv @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/pluto/waves/cfg1.wcfg b/testbenches/project/pluto/waves/cfg1.wcfg index 0ac0b6eb..a10fec27 100644 --- a/testbenches/project/pluto/waves/cfg1.wcfg +++ b/testbenches/project/pluto/waves/cfg1.wcfg @@ -20,7 +20,7 @@ - + diff --git a/testbenches/project/pulsar_adc_pmdz/Makefile b/testbenches/project/pulsar_adc_pmdz/Makefile index ffaeb4e1..3dfa2edf 100755 --- a/testbenches/project/pulsar_adc_pmdz/Makefile +++ b/testbenches/project/pulsar_adc_pmdz/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2021(c) Analog Devices, Inc. +## Copyright (C) 2021 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -20,7 +20,6 @@ ENV_DEPS += $(HDL_LIBRARY_PATH)/common/ad_edge_detect.v LIB_DEPS += axi_clkgen LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid LIB_DEPS += util_cdc LIB_DEPS += util_axis_fifo LIB_DEPS += axi_pulsar_lvds @@ -28,7 +27,6 @@ LIB_DEPS += spi_engine/axi_spi_engine LIB_DEPS += spi_engine/spi_engine_execution LIB_DEPS += spi_engine/spi_engine_interconnect LIB_DEPS += spi_engine/spi_engine_offload -LIB_DEPS += sysid_rom # default test programs # Format is: diff --git a/testbenches/project/pulsar_adc_pmdz/spi_engine.svh b/testbenches/project/pulsar_adc_pmdz/spi_engine.svh index 5d6096e0..beb517bc 100644 --- a/testbenches/project/pulsar_adc_pmdz/spi_engine.svh +++ b/testbenches/project/pulsar_adc_pmdz/spi_engine.svh @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/pulsar_adc_pmdz/system_bd.tcl b/testbenches/project/pulsar_adc_pmdz/system_bd.tcl index 64517339..40e64e4d 100755 --- a/testbenches/project/pulsar_adc_pmdz/system_bd.tcl +++ b/testbenches/project/pulsar_adc_pmdz/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2021 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/pulsar_adc_pmdz/system_tb.sv b/testbenches/project/pulsar_adc_pmdz/system_tb.sv index 3b05f965..646f19d2 100755 --- a/testbenches/project/pulsar_adc_pmdz/system_tb.sv +++ b/testbenches/project/pulsar_adc_pmdz/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 - 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv b/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv index e46538c4..de822a73 100755 --- a/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv +++ b/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 - 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/pulsar_adc_pmdz/waves/cfg1.wcfg b/testbenches/project/pulsar_adc_pmdz/waves/cfg1.wcfg index c17b4aeb..f36391be 100755 --- a/testbenches/project/pulsar_adc_pmdz/waves/cfg1.wcfg +++ b/testbenches/project/pulsar_adc_pmdz/waves/cfg1.wcfg @@ -12,7 +12,7 @@ - + From a5337ee9c1f6c0a2b4a736bddd9f037184c62808 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Thu, 30 Jan 2025 09:04:09 +0200 Subject: [PATCH 23/37] SPI VIP update Signed-off-by: Istvan-Zsolt Szekely --- library/includes/Makeinclude_spi_engine.mk | 1 - library/includes/sp_include_spi_engine.tcl | 1 - library/vip/adi/io_vip/io_vip_ip.tcl | 16 +- library/vip/adi/spi_vip/Makefile | 2 - library/vip/adi/spi_vip/adi_spi_vip.sv | 46 +- ...equencer.sv => adi_spi_vip_if_base_pkg.sv} | 78 +- library/vip/adi/spi_vip/adi_spi_vip_ip.tcl | 19 +- library/vip/adi/spi_vip/adi_spi_vip_pkg.sv | 223 ++-- library/vip/adi/spi_vip/adi_spi_vip_pkg.ttcl | 49 - library/vip/adi/spi_vip/spi_vip_if.sv | 158 ++- library/vip/amd/axis/m_axis_sequencer.sv | 2 + testbenches/ip/spi_engine/spi_environment.sv | 61 +- .../ip/spi_engine/tests/test_program.sv | 695 +++++++------ .../ip/spi_engine/tests/test_sleep_delay.sv | 820 +++++++-------- .../ip/spi_engine/tests/test_slowdata.sv | 949 +++++++++--------- .../project/ad57xx/ad57xx_environment.sv | 14 +- .../project/ad57xx/tests/test_program.sv | 10 +- 17 files changed, 1612 insertions(+), 1532 deletions(-) rename library/vip/adi/spi_vip/{s_spi_sequencer.sv => adi_spi_vip_if_base_pkg.sv} (53%) delete mode 100644 library/vip/adi/spi_vip/adi_spi_vip_pkg.ttcl diff --git a/library/includes/Makeinclude_spi_engine.mk b/library/includes/Makeinclude_spi_engine.mk index 543c325f..ba3cce29 100644 --- a/library/includes/Makeinclude_spi_engine.mk +++ b/library/includes/Makeinclude_spi_engine.mk @@ -7,7 +7,6 @@ include $(TB_LIBRARY_PATH)/includes/Makeinclude_regmap.mk # All test-bench dependencies except test programs SV_DEPS += $(TB_LIBRARY_PATH)/vip/adi/spi_vip/adi_spi_vip_pkg.sv -SV_DEPS += $(TB_LIBRARY_PATH)/vip/adi/spi_vip/s_spi_sequencer.sv SV_DEPS += $(TB_LIBRARY_PATH)/drivers/spi_engine/spi_engine_instr_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_spi_engine_pkg.sv diff --git a/library/includes/sp_include_spi_engine.tcl b/library/includes/sp_include_spi_engine.tcl index f090ec45..f6e411da 100644 --- a/library/includes/sp_include_spi_engine.tcl +++ b/library/includes/sp_include_spi_engine.tcl @@ -38,7 +38,6 @@ source $ad_tb_dir/library/includes/sp_include_regmap.tcl # Add test files to the project adi_sim_project_files [list \ "$ad_tb_dir/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv" \ - "$ad_tb_dir/library/vip/adi/spi_vip/s_spi_sequencer.sv" \ "$ad_tb_dir/library/drivers/spi_engine/spi_engine_instr_pkg.sv" \ "$ad_tb_dir/library/regmaps/adi_regmap_spi_engine_pkg.sv" \ ] diff --git a/library/vip/adi/io_vip/io_vip_ip.tcl b/library/vip/adi/io_vip/io_vip_ip.tcl index a99e8474..bf775d90 100644 --- a/library/vip/adi/io_vip/io_vip_ip.tcl +++ b/library/vip/adi/io_vip/io_vip_ip.tcl @@ -15,16 +15,21 @@ adi_ip_files io_vip [list \ adi_ip_properties_lite io_vip adi_ip_sim_ttcl io_vip "io_vip_pkg.ttcl" +set cc [ipx::current_core] + +set_property company_url {Unavailable} $cc + +set_property display_name "ADI IO VIP" $cc +set_property description "ADI IO Verification IP" $cc + # Remove all inferred interfaces -ipx::remove_all_bus_interface [ipx::current_core] +ipx::remove_all_bus_interface $cc ## Interface definitions adi_set_ports_dependency "in" \ "(spirit:decode(id('MODELPARAM_VALUE.MODE')) = 0)" -set cc [ipx::current_core] - ## MODE set_property -dict [list \ "value_validation_type" "pairs" \ @@ -35,11 +40,10 @@ set_property -dict [list \ ## Customize IP Layout ## Remove the automatically generated GUI page ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -ipx::save_core [ipx::current_core] - +ipx::save_core $cc ## Create general configuration page -ipgui::add_page -name {IO VIP} -component [ipx::current_core] -display_name {IO VIP} +ipgui::add_page -name {IO VIP} -component $cc -display_name {IO VIP} set page0 [ipgui::get_pagespec -name "IO VIP" -component $cc] set general_group [ipgui::add_group -name "General Configuration" -component $cc \ diff --git a/library/vip/adi/spi_vip/Makefile b/library/vip/adi/spi_vip/Makefile index 4be1d86f..049e237a 100644 --- a/library/vip/adi/spi_vip/Makefile +++ b/library/vip/adi/spi_vip/Makefile @@ -9,13 +9,11 @@ include ../../../../scripts/make_tb_path.mk LIBRARY_NAME := adi_spi_vip -GENERIC_DEPS += $(TB_LIBRARY_PATH)/utilities/utils.svh GENERIC_DEPS += adi_spi_vip_pkg.sv GENERIC_DEPS += spi_vip_if.sv GENERIC_DEPS += adi_spi_vip.sv XILINX_DEPS += adi_spi_vip_ip.tcl -XILINX_DEPS += adi_spi_vip_pkg.ttcl #TODO: INTEL_DEPS += adi_spi_vip_hw.tcl diff --git a/library/vip/adi/spi_vip/adi_spi_vip.sv b/library/vip/adi/spi_vip/adi_spi_vip.sv index fd3ec55c..40bcc7a1 100644 --- a/library/vip/adi/spi_vip/adi_spi_vip.sv +++ b/library/vip/adi/spi_vip/adi_spi_vip.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -33,8 +33,6 @@ // *************************************************************************** // *************************************************************************** -`include "utils.svh" - module adi_spi_vip #( parameter MODE = 0, // SLAVE=0 parameter CPOL = 0, @@ -49,11 +47,11 @@ module adi_spi_vip #( parameter DEFAULT_MISO_DATA = 'hCAFE ) ( input logic s_spi_sclk, - input wire s_spi_mosi, + input logic s_spi_mosi, output wire s_spi_miso, input logic s_spi_cs, output logic m_spi_sclk, - output wire m_spi_mosi, + output logic m_spi_mosi, input wire m_spi_miso, output logic m_spi_cs ); @@ -76,41 +74,33 @@ module adi_spi_vip #( .DEFAULT_MISO_DATA (DEFAULT_MISO_DATA) ) IF (); - initial begin : ASSERT_PARAMETERS - assert (MODE == MODE_SLAVE) - else begin - $error("Unsupported mode %s. Valid values are 0=SLAVE, 1=MASTER, 2=MONITOR. Only 0(SLAVE) is currently supported.", MODE); - end - end : ASSERT_PARAMETERS + if (MODE != MODE_SLAVE) begin + $error("Unsupported mode %s. Valid values are 0=SLAVE, 1=MASTER, 2=MONITOR. Only 0(SLAVE) is currently supported.", MODE); + end generate + + assign s_spi_miso = IF.s_miso; + assign IF.s_mosi = s_spi_mosi; + assign IF.s_cs = s_spi_cs; + assign IF.s_sclk = s_spi_sclk; + + assign IF.m_miso = m_spi_miso; + assign m_spi_mosi = IF.m_mosi; + assign m_spi_sclk = IF.m_sclk; + assign m_spi_cs = IF.m_cs; + if (MODE == MODE_SLAVE) begin - assign s_spi_miso = IF.miso; - assign IF.mosi = s_spi_mosi; - assign IF.sclk = s_spi_sclk; - assign IF.cs = s_spi_cs; initial begin IF.set_slave_mode(); end end else if (MODE == MODE_MASTER) begin - assign IF.miso = m_spi_miso; - assign m_spi_mosi = IF.mosi; - assign m_spi_sclk = IF.sclk; - assign m_spi_cs = IF.cs; initial begin IF.set_master_mode(); end end else if (MODE == MODE_MONITOR) begin - assign IF.miso = m_spi_miso; - assign IF.mosi = s_spi_mosi; - assign IF.miso = s_spi_miso; - assign IF.cs = s_spi_cs; - assign s_spi_miso = m_spi_miso; - assign m_spi_mosi = s_spi_mosi; - assign m_spi_sclk = s_spi_sclk; - assign m_spi_cs = s_spi_cs; initial begin - IF.intf_monitor_mode(); + IF.set_monitor_mode(); end end endgenerate diff --git a/library/vip/adi/spi_vip/s_spi_sequencer.sv b/library/vip/adi/spi_vip/adi_spi_vip_if_base_pkg.sv similarity index 53% rename from library/vip/adi/spi_vip/s_spi_sequencer.sv rename to library/vip/adi/spi_vip/adi_spi_vip_if_base_pkg.sv index bb0a2d73..05454939 100644 --- a/library/vip/adi/spi_vip/s_spi_sequencer.sv +++ b/library/vip/adi/spi_vip/adi_spi_vip_if_base_pkg.sv @@ -1,6 +1,5 @@ // *************************************************************************** -// *************************************************************************** -// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -33,52 +32,59 @@ // *************************************************************************** // *************************************************************************** -`include "utils.svh" +package adi_spi_vip_if_base_pkg; + + typedef enum {SPI_MODE_SLAVE, SPI_MODE_MASTER, SPI_MODE_MONITOR} spi_mode_t; + + virtual class adi_spi_vip_if_base; + + function new(); + endfunction + + pure virtual function int get_param_MODE(); + + pure virtual function int get_param_CPOL(); + + pure virtual function int get_param_CPHA(); -package s_spi_sequencer_pkg; + pure virtual function int get_param_INV_CS(); - import logger_pkg::*; - import adi_common_pkg::*; - import adi_spi_vip_pkg::*; + pure virtual function int get_param_DATA_DLENGTH(); - class s_spi_sequencer #(`SPI_VIP_PARAM_ORDER) extends adi_component; + pure virtual function int get_param_SLAVE_TIN(); - protected adi_spi_agent #(`SPI_VIP_PARAM_ORDER) agent; + pure virtual function int get_param_SLAVE_TOUT(); - function new( - input string name, - input adi_spi_agent #(`SPI_VIP_PARAM_ORDER) agent, - input adi_component parent = null); + pure virtual function int get_param_MASTER_TIN(); - super.new(name, parent); + pure virtual function int get_param_MASTER_TOUT(); - this.agent = agent; - endfunction: new + pure virtual function int get_param_CS_TO_MISO(); - virtual task automatic send_data(input int unsigned data); - this.agent.send_data(data); - endtask : send_data + pure virtual function int get_param_DEFAULT_MISO_DATA(); - virtual task automatic receive_data(output int unsigned data); - this.agent.receive_data(data); - endtask : receive_data + pure virtual function spi_mode_t get_mode(); - virtual task automatic receive_data_verify(input int unsigned expected); - int unsigned received; - this.agent.receive_data(received); - if (received !== expected) begin - this.error($sformatf("Data mismatch. Received : %h; expected %h", received, expected)); - end - endtask : receive_data_verify + pure virtual function logic get_cs_active(); - virtual task flush_send(); - this.agent.flush_send(); - endtask : flush_send + pure virtual task wait_cs_active(); - virtual function void set_default_miso_data(input int unsigned data); - this.agent.set_default_miso_data(data); - endfunction : set_default_miso_data + pure virtual task wait_cs_inactive(); + pure virtual task wait_for_sample_edge(); + + pure virtual function logic get_mosi_delayed(); + + pure virtual task set_miso_drive(bit val); + + pure virtual task set_miso_drive_instantaneous(bit val); + + pure virtual task wait_for_drive_edge(); + + pure virtual task wait_cs(); + + pure virtual task set_miso_oen(bit val); endclass -endpackage \ No newline at end of file + +endpackage diff --git a/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl b/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl index ec3e200a..4744ead2 100644 --- a/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl +++ b/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl @@ -8,21 +8,22 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl adi_ip_create adi_spi_vip adi_ip_files adi_spi_vip [list \ - "adi_spi_vip_pkg.sv" \ "adi_spi_vip.sv" \ "spi_vip_if.sv" \ - "adi_spi_vip_pkg.ttcl" \ - "$ad_tb_dir/library/utilities/utils.svh" \ - "$ad_tb_dir/library/utilities/logger_pkg.sv" \ + "adi_spi_vip_if_base_pkg.sv" \ ] adi_ip_properties_lite adi_spi_vip -adi_ip_sim_ttcl adi_spi_vip "adi_spi_vip_pkg.ttcl" -set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine} [ipx::current_core] +set cc [ipx::current_core] + +set_property company_url {Unavailable} $cc + +set_property display_name "ADI SPI VIP" $cc +set_property description "ADI SPI Verification IP" $cc # Remove all inferred interfaces -ipx::remove_all_bus_interface [ipx::current_core] +ipx::remove_all_bus_interface $cc ## Interface definitions @@ -52,8 +53,6 @@ adi_add_bus "m_spi" "master" \ ## Parameter validations -set cc [ipx::current_core] - ## MODE set_property -dict [list \ "value_validation_type" "pairs" \ @@ -157,7 +156,7 @@ set_property -dict [list \ ## DEFAULT_MISO_DATA set_property -dict [list \ "value_bit_string_length" "32" \ - "value_format" "bit_string" \ + "value_format" "bitString" \ "enablement_tcl_expr" "\$MODE==0" \ ] \ [ipx::get_user_parameters DEFAULT_MISO_DATA -of_objects $cc] diff --git a/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv b/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv index 4d66c3c6..20c0edd3 100644 --- a/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv +++ b/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -38,55 +38,36 @@ package adi_spi_vip_pkg; import logger_pkg::*; - import adi_common_pkg::*; - - `define SPI_VIP_PARAM_ORDER SPI_VIP_MODE ,\ - SPI_VIP_CPOL ,\ - SPI_VIP_CPHA ,\ - SPI_VIP_INV_CS ,\ - SPI_VIP_DATA_DLENGTH ,\ - SPI_VIP_SLAVE_TIN ,\ - SPI_VIP_SLAVE_TOUT ,\ - SPI_VIP_MASTER_TIN ,\ - SPI_VIP_MASTER_TOUT ,\ - SPI_VIP_CS_TO_MISO ,\ - SPI_VIP_DEFAULT_MISO_DATA - - `define SPI_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_MODE,\ - th``_``vip``_0_VIP_CPOL,\ - th``_``vip``_0_VIP_CPHA,\ - th``_``vip``_0_VIP_INV_CS,\ - th``_``vip``_0_VIP_DATA_DLENGTH,\ - th``_``vip``_0_VIP_SLAVE_TIN,\ - th``_``vip``_0_VIP_SLAVE_TOUT,\ - th``_``vip``_0_VIP_MASTER_TIN,\ - th``_``vip``_0_VIP_MASTER_TOUT,\ - th``_``vip``_0_VIP_CS_TO_MISO,\ - th``_``vip``_0_VIP_DEFAULT_MISO_DATA - - class adi_spi_driver #(int `SPI_VIP_PARAM_ORDER) extends adi_component; - - typedef mailbox #(logic [SPI_VIP_DATA_DLENGTH-1:0]) spi_mbx_t; - protected spi_mbx_t mosi_mbx; - spi_mbx_t miso_mbx; + import adi_vip_pkg::*; + import adi_environment_pkg::*; + import adi_spi_vip_if_base_pkg::*; + + // forward declaration to avoid errors + typedef class adi_spi_agent; + + class adi_spi_driver extends adi_driver; + + typedef bit bitqueue_t [$]; + protected mailbox mosi_mbx; + mailbox miso_mbx; protected bit active; protected bit stop_flag; - protected bit [SPI_VIP_DATA_DLENGTH-1:0] miso_reg; - protected bit [SPI_VIP_DATA_DLENGTH-1:0] default_miso_data; + protected int default_miso_data; protected event tx_mbx_updated; - virtual spi_vip_if #(`SPI_VIP_PARAM_ORDER) vif; + + adi_spi_vip_if_base vif; function new( input string name, - virtual spi_vip_if #(`SPI_VIP_PARAM_ORDER) intf, - input adi_component parent = null); + input adi_spi_vip_if_base intf, + input adi_spi_agent parent = null); super.new(name, parent); - + this.vif = intf; this.active = 0; this.stop_flag = 0; - this.default_miso_data = SPI_VIP_DEFAULT_MISO_DATA; + this.default_miso_data = vif.get_param_DEFAULT_MISO_DATA(); this.miso_mbx = new(); this.mosi_mbx = new(); endfunction @@ -105,19 +86,27 @@ package adi_spi_vip_pkg; endfunction : clear_active protected task rx_mosi(); - static logic [SPI_VIP_DATA_DLENGTH-1:0] mosi_data; + bitqueue_t mosi_bits; + logic mosi_logic; + bit mosi_bit; forever begin - if (vif.intf_slave_mode) begin - wait (vif.cs_active); - while (vif.cs_active) begin - for (int i = 0; itx_mbx_updated; endtask task get_rx_data( output int unsigned data); - bit [SPI_VIP_DATA_DLENGTH-1:0] rxdata; - mosi_mbx.get(rxdata); - data = rxdata; + mosi_mbx.get(data); endtask task flush_tx(); @@ -277,34 +265,93 @@ package adi_spi_vip_pkg; end endtask + automatic function int bitqueue_to_int(bitqueue_t bitq); + int idx = 0; + int data = 0; + while (bitq.size() != 0) begin + data |= (bitq.pop_front() << idx); + idx++; + end + return data; + endfunction + + automatic function bitqueue_t int_to_bitqueue(int data, int n_bits); + bitqueue_t bitq; + for (int i =0; i>i) & 1'b1); + end + return bitq; + endfunction + + automatic function bit bitqueue_pop_msb(ref bitqueue_t bitq); + bit data; + data = bitq.pop_back(); + return data; + endfunction + + automatic function void bitqueue_push_lsb(ref bitqueue_t bitq, bit lsb); + bitq.push_front(lsb); + endfunction endclass - class adi_spi_agent #(int `SPI_VIP_PARAM_ORDER) extends adi_component; + + class adi_spi_sequencer extends adi_sequencer; - protected adi_spi_driver #(`SPI_VIP_PARAM_ORDER) driver; + protected adi_spi_driver driver; function new( input string name, - virtual spi_vip_if #(`SPI_VIP_PARAM_ORDER) intf, - input adi_component parent = null); + input adi_spi_driver driver, + input adi_spi_agent parent = null); super.new(name, parent); - this.driver = new("Driver", intf, this); - endfunction + this.driver = driver; + endfunction: new - virtual task send_data(input int unsigned data); + virtual task automatic send_data(input int unsigned data); this.driver.put_tx_data(data); endtask : send_data - virtual task receive_data(output int unsigned data); + virtual task automatic receive_data(output int unsigned data); this.driver.get_rx_data(data); endtask : receive_data + virtual task automatic receive_data_verify(input int unsigned expected); + int unsigned received; + this.driver.get_rx_data(received); + if (received !== expected) begin + this.error($sformatf("Data mismatch. Received : %h; expected %h", received, expected)); + end + endtask : receive_data_verify + virtual task flush_send(); this.driver.flush_tx(); endtask : flush_send + virtual function void set_default_miso_data(input int unsigned data); + this.driver.set_default_miso_data(data); + endfunction : set_default_miso_data + + endclass + + + class adi_spi_agent extends adi_agent; + + protected adi_spi_driver driver; + adi_spi_sequencer sequencer; + + function new( + input string name, + input adi_spi_vip_if_base intf, + input adi_environment parent = null); + + super.new(name, parent); + + this.driver = new("Driver", intf, this); + this.sequencer = new("Sequencer", this.driver, this); + endfunction + virtual task start(); fork this.driver.start(); @@ -315,10 +362,6 @@ package adi_spi_vip_pkg; this.driver.stop(); endtask : stop - virtual function void set_default_miso_data(input int unsigned data); - this.driver.set_default_miso_data(data); - endfunction : set_default_miso_data - endclass endpackage diff --git a/library/vip/adi/spi_vip/adi_spi_vip_pkg.ttcl b/library/vip/adi/spi_vip/adi_spi_vip_pkg.ttcl deleted file mode 100644 index 5d9abd2f..00000000 --- a/library/vip/adi/spi_vip/adi_spi_vip_pkg.ttcl +++ /dev/null @@ -1,49 +0,0 @@ -############################################################################### -## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. -# SPDX short identifier: ADIBSD -############################################################################### - -<: :> -<: set ComponentName [getComponentNameString] :> -<: setOutputDirectory "./sim/" :> -<: setFileName ${ComponentName}_pkg :> -<: setFileExtension ".sv" :> -<: set mode [get_property MODELPARAM_VALUE.MODE] :> -<: set cpol [get_property MODELPARAM_VALUE.CPOL] :> -<: set cpha [get_property MODELPARAM_VALUE.CPHA] :> -<: set inv_cs [get_property MODELPARAM_VALUE.INV_CS] :> -<: set slave_tin [get_property MODELPARAM_VALUE.SLAVE_TIN] :> -<: set slave_tout [get_property MODELPARAM_VALUE.SLAVE_TOUT] :> -<: set master_tin [get_property MODELPARAM_VALUE.MASTER_TIN] :> -<: set master_tout [get_property MODELPARAM_VALUE.MASTER_TOUT] :> -<: set cs_to_miso [get_property MODELPARAM_VALUE.CS_TO_MISO] :> -<: set data_dlength [get_property MODELPARAM_VALUE.DATA_DLENGTH] :> -<: set default_miso_data [get_property MODELPARAM_VALUE.DEFAULT_MISO_DATA] :> - -<: proc b2i {b} { if {$b==true} {return 1} else {return 0}} :> -<: proc h2i {h} { return [format "%d" $h]} :> -/////////////////////////////////////////////////////////////////////////// -//NOTE: This file has been automatically generated by Vivado. -/////////////////////////////////////////////////////////////////////////// - -package <=: ComponentName :>_pkg; - - -/////////////////////////////////////////////////////////////////////////// -// These parameters are named after the component for use in your verification -// environment. -/////////////////////////////////////////////////////////////////////////// - parameter <=: ComponentName :>_VIP_MODE = <=: $mode :>; - parameter <=: ComponentName :>_VIP_CPOL = <=: b2i $cpol :>; - parameter <=: ComponentName :>_VIP_CPHA = <=: b2i $cpha :>; - parameter <=: ComponentName :>_VIP_INV_CS = <=: b2i $inv_cs :>; - parameter <=: ComponentName :>_VIP_SLAVE_TIN = <=: $slave_tin :>; - parameter <=: ComponentName :>_VIP_SLAVE_TOUT = <=: $slave_tout :>; - parameter <=: ComponentName :>_VIP_MASTER_TIN = <=: $master_tin :>; - parameter <=: ComponentName :>_VIP_MASTER_TOUT = <=: $master_tout :>; - parameter <=: ComponentName :>_VIP_CS_TO_MISO = <=: $cs_to_miso :>; - parameter <=: ComponentName :>_VIP_DATA_DLENGTH = <=: $data_dlength :>; - parameter <=: ComponentName :>_VIP_DEFAULT_MISO_DATA = <=: h2i $default_miso_data :>; -////////////////////////////////////////////////////////////////////////// - -endpackage : <=: ComponentName :>_pkg \ No newline at end of file diff --git a/library/vip/adi/spi_vip/spi_vip_if.sv b/library/vip/adi/spi_vip/spi_vip_if.sv index 3098778b..eb453024 100644 --- a/library/vip/adi/spi_vip/spi_vip_if.sv +++ b/library/vip/adi/spi_vip/spi_vip_if.sv @@ -32,8 +32,6 @@ // *************************************************************************** // *************************************************************************** -`include "utils.svh" - interface spi_vip_if #( int MODE = 0, CPOL = 0, @@ -47,52 +45,166 @@ interface spi_vip_if #( CS_TO_MISO = 0, DEFAULT_MISO_DATA = 'hCAFE ) (); - logic sclk; - wire miso; // need net types here in case tb wants to tristate this - wire mosi; // need net types here in case tb wants to tristate this - logic cs; + import adi_spi_vip_if_base_pkg::*; + + logic s_sclk; + wire s_miso; // need net types here in case tb wants to tristate this + logic s_mosi; + logic s_cs; + + logic m_sclk; + wire m_miso; // need net types here in case tb wants to tristate this + logic m_mosi; + logic m_cs; // internal - logic intf_slave_mode; - logic intf_master_mode; - logic intf_monitor_mode; + spi_mode_t spi_mode; logic miso_oen; logic miso_drive; + logic mosi_drive = 1'b0; + logic cs_drive = 1'b0; + logic sclk_drive = 1'b0; logic cs_active; - logic mosi_delayed; + logic s_mosi_delayed; + wire sclk; + wire cs; localparam CS_ACTIVE_LEVEL = (INV_CS) ? 1'b1 : 1'b0; + // cs, sclk sources + assign cs = (spi_mode != SPI_MODE_SLAVE) ? m_cs : s_cs; + assign sclk = (spi_mode != SPI_MODE_SLAVE) ? m_sclk : s_sclk; + // hack for parameterized edge. TODO: improve this logic sample_edge, drive_edge; assign sample_edge = (CPOL^CPHA) ? !sclk : sclk; assign drive_edge = (CPOL^CPHA) ? sclk : !sclk; assign cs_active = (cs == CS_ACTIVE_LEVEL); - // miso tri-state handling - assign miso = (!intf_slave_mode) ? 'z - : (miso_oen) ? miso_drive + // miso drive handling + assign s_miso = (spi_mode != SPI_MODE_SLAVE) ? m_miso + : (miso_oen) ? miso_drive /*default*/ : 'z; + // mosi drive handling + assign m_mosi = (spi_mode != SPI_MODE_MASTER) ? s_mosi : mosi_drive; + + // cs drive handling + assign m_cs = (spi_mode != SPI_MODE_MASTER) ? s_cs : cs_drive; + + // sclk drive handling + assign m_sclk = (spi_mode != SPI_MODE_MASTER) ? s_sclk : sclk_drive; + // mosi delay - assign #(SLAVE_TIN*1ns) mosi_delayed = mosi; + assign #(SLAVE_TIN*1ns) s_mosi_delayed = s_mosi; + + class adi_spi_vip_if #(int dummy = 10) extends adi_spi_vip_if_base; + + function new(); + endfunction + + virtual function int get_param_MODE(); + return MODE; + endfunction + + virtual function int get_param_CPOL(); + return CPOL; + endfunction + + virtual function int get_param_CPHA(); + return CPHA; + endfunction + + virtual function int get_param_INV_CS(); + return INV_CS; + endfunction + + virtual function int get_param_DATA_DLENGTH(); + return DATA_DLENGTH; + endfunction + + virtual function int get_param_SLAVE_TIN(); + return SLAVE_TIN; + endfunction + + virtual function int get_param_SLAVE_TOUT(); + return SLAVE_TOUT; + endfunction + + virtual function int get_param_MASTER_TIN(); + return MASTER_TIN; + endfunction + + virtual function int get_param_MASTER_TOUT(); + return MASTER_TOUT; + endfunction + + virtual function int get_param_CS_TO_MISO(); + return CS_TO_MISO; + endfunction + + virtual function int get_param_DEFAULT_MISO_DATA(); + return DEFAULT_MISO_DATA; + endfunction + + virtual function spi_mode_t get_mode(); + return spi_mode; + endfunction + + virtual function logic get_mosi_delayed(); + return s_mosi_delayed; + endfunction + + virtual function logic get_cs_active(); + return cs_active; + endfunction + + virtual task set_miso_drive(bit val); + miso_drive <= #(SLAVE_TOUT) val; + endtask + + virtual task set_miso_drive_instantaneous(bit val); + miso_drive <= val; + endtask + + virtual task wait_cs_active(); + wait(cs_active); + endtask + + virtual task wait_cs_inactive(); + wait(!cs_active); + endtask + + virtual task wait_for_sample_edge(); + @(posedge sample_edge); + endtask + + virtual task wait_for_drive_edge(); + @(posedge drive_edge); + endtask + + virtual task wait_cs(); + @(cs); + endtask + + virtual task set_miso_oen(bit val); + miso_oen <= #(CS_TO_MISO*1ns) val; + endtask + + endclass: adi_spi_vip_if + + adi_spi_vip_if vif = new(); function void set_slave_mode(); - intf_slave_mode = 1; - intf_master_mode = 0; - intf_monitor_mode = 0; + spi_mode = SPI_MODE_SLAVE; endfunction : set_slave_mode function void set_master_mode(); - intf_slave_mode = 0; - intf_master_mode = 1; - intf_monitor_mode = 0; + spi_mode = SPI_MODE_MASTER; $error("Unsupported mode master"); //TODO endfunction : set_master_mode function void set_monitor_mode(); - intf_slave_mode = 0; - intf_master_mode = 0; - intf_monitor_mode = 1; + spi_mode = SPI_MODE_MONITOR; $error("Unsupported mode monitor"); //TODO endfunction : set_monitor_mode diff --git a/library/vip/amd/axis/m_axis_sequencer.sv b/library/vip/amd/axis/m_axis_sequencer.sv index fa3e39b5..74db1702 100644 --- a/library/vip/amd/axis/m_axis_sequencer.sv +++ b/library/vip/amd/axis/m_axis_sequencer.sv @@ -102,6 +102,8 @@ package m_axis_sequencer_pkg; super.new(name, parent); + this.trans = new(); + this.enabled = 1'b0; this.data_gen_mode = DATA_GEN_MODE_AUTO_INCR; this.descriptor_gen_mode = 1'b0; diff --git a/testbenches/ip/spi_engine/spi_environment.sv b/testbenches/ip/spi_engine/spi_environment.sv index 27bea6bf..eca60f3e 100644 --- a/testbenches/ip/spi_engine/spi_environment.sv +++ b/testbenches/ip/spi_engine/spi_environment.sv @@ -34,18 +34,17 @@ // *************************************************************************** `include "utils.svh" +`include "axis_definitions.svh" package spi_environment_pkg; import logger_pkg::*; import adi_environment_pkg::*; - import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; - import s_spi_sequencer_pkg::*; + import adi_axis_agent_pkg::*; import adi_spi_vip_pkg::*; - - import `PKGIFY(test_harness, spi_s_vip)::*; + import adi_spi_vip_if_base_pkg::*; `ifdef DEF_SDO_STREAMING import `PKGIFY(test_harness, sdo_src)::*; @@ -54,15 +53,9 @@ package spi_environment_pkg; class spi_environment extends adi_environment; // Agents - adi_spi_agent #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_agent; + adi_spi_agent spi_agent; `ifdef DEF_SDO_STREAMING - `AGENT(test_harness, sdo_src, mst_t) sdo_src_agent; - `endif - - // Sequencers - s_spi_sequencer #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_seq; - `ifdef DEF_SDO_STREAMING - m_axis_sequencer #(`AXIS_VIP_PARAMS(test_harness, sdo_src)) sdo_src_seq; + adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(test_harness_sdo_src_0)) sdo_src_agent; `endif //============================================================================ @@ -72,29 +65,23 @@ package spi_environment_pkg; input string name, `ifdef DEF_SDO_STREAMING - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness_sdo_src_0)) sdo_src_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness_sdo_src_0)) sdo_src_axis_vip_if, `endif - virtual interface spi_vip_if #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_s_vip_if); + adi_spi_vip_if_base spi_s_vip_if); super.new(name); // Creating the agents this.spi_agent = new("SPI VIP Agent", spi_s_vip_if, this); `ifdef DEF_SDO_STREAMING - this.sdo_src_agent = new("SDO Source AXI Stream Agent", sdo_src_axis_vip_if); - `endif - - // Creating the sequencers - this.spi_seq = new("SPI VIP Agent", this.spi_agent, this); - `ifdef DEF_SDO_STREAMING - this.sdo_src_seq = new("SDO Source AXI Stream Sequencer", this.sdo_src_agent.driver); + this.sdo_src_agent = new("SDO Source AXI Stream Agent", sdo_src_axis_vip_if); `endif // downgrade reset check: we are currently using a clock generator for the SPI clock, // so it will come a bit after the reset and trigger the default error. // This is harmless for this test (we don't want to test any reset scheme) `ifdef DEF_SDO_STREAMING - sdo_src_axis_vip_if.set_xilinx_reset_check_to_warn(); + sdo_src_axis_vip_if.set_xilinx_reset_check_to_warn(); `endif endfunction @@ -104,8 +91,8 @@ package spi_environment_pkg; //============================================================================ task configure(); `ifdef DEF_SDO_STREAMING - this.sdo_src_seq.set_stop_policy(STOP_POLICY_PACKET); - this.sdo_src_seq.set_data_gen_mode(DATA_GEN_MODE_TEST_DATA); + this.sdo_src_agent.sequencer.set_stop_policy(STOP_POLICY_PACKET); + this.sdo_src_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_TEST_DATA); `endif endtask @@ -117,44 +104,28 @@ package spi_environment_pkg; task start(); this.spi_agent.start(); `ifdef DEF_SDO_STREAMING - this.sdo_src_agent.start_master(); + this.sdo_src_agent.start(); `endif endtask //============================================================================ - // Start the test - // - start the scoreboard - // - start the sequencers + // Run subroutine //============================================================================ - task test(); + task run(); fork `ifdef DEF_SDO_STREAMING - this.sdo_src_seq.run(); + this.sdo_src_agent.run(); `endif join_none endtask - //============================================================================ - // Post test subroutine - //============================================================================ - task post_test(); - endtask - - //============================================================================ - // Run subroutine - //============================================================================ - task run(); - test(); - endtask - //============================================================================ // Stop subroutine //============================================================================ task stop(); this.spi_agent.stop(); `ifdef DEF_SDO_STREAMING - this.sdo_src_seq.stop(); - this.sdo_src_agent.stop_master(); + this.sdo_src_agent.stop(); `endif endtask diff --git a/testbenches/ip/spi_engine/tests/test_program.sv b/testbenches/ip/spi_engine/tests/test_program.sv index 06dfdf4b..d5275b7c 100644 --- a/testbenches/ip/spi_engine/tests/test_program.sv +++ b/testbenches/ip/spi_engine/tests/test_program.sv @@ -37,6 +37,7 @@ `include "utils.svh" `include "axi_definitions.svh" +`include "axis_definitions.svh" import logger_pkg::*; import test_harness_env_pkg::*; @@ -64,381 +65,379 @@ program test_program ( inout [(`NUM_OF_CS - 1):0] spi_engine_spi_cs, inout spi_engine_spi_clk, `ifdef DEF_ECHO_SCLK - inout spi_engine_echo_sclk, + inout spi_engine_echo_sclk, `endif inout [(`NUM_OF_SDI - 1):0] spi_engine_spi_sdi); -timeunit 1ns; -timeprecision 100ps; - -// declare the class instances -test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; -spi_environment spi_env; - -// -------------------------- -// Wrapper function for AXI read verify -// -------------------------- -task axi_read_v( - input [31:0] raddr, - input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); -endtask - -task axi_read( - input [31:0] raddr, - output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); -endtask - -// -------------------------- -// Wrapper function for AXI write -// -------------------------- -task axi_write( - input [31:0] waddr, - input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); -endtask - -// -------------------------- -// Wrapper function for SPI receive (from DUT) -// -------------------------- -task spi_receive( - output [`DATA_DLENGTH:0] data); - spi_env.spi_seq.receive_data(data); -endtask - -// -------------------------- -// Wrapper function for SPI send (to DUT) -// -------------------------- -task spi_send( - input [`DATA_DLENGTH:0] data); - spi_env.spi_seq.send_data(data); -endtask - -// -------------------------- -// Wrapper function for waiting for all SPI -// -------------------------- -task spi_wait_send(); - spi_env.spi_seq.flush_send(); -endtask - - - -// -------------------------- -// Main procedure -// -------------------------- -initial begin - - //creating environment - base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); - - spi_env = new("SPI Engine Environment", - `ifdef DEF_SDO_STREAMING - `TH.`SDO_SRC.inst.IF, - `endif - `TH.`SPI_S.inst.IF); - - setLoggerVerbosity(ADI_VERBOSITY_NONE); - - base_env.start(); - spi_env.start(); - - base_env.sys_reset(); - - spi_env.configure(); - - spi_env.run(); - - spi_env.spi_seq.set_default_miso_data('h2AA55); - - // start sdo source (will wait for data enqueued) - `ifdef DEF_SDO_STREAMING - spi_env.sdo_src_seq.start(); - `endif - - sanity_test(); - - #100ns - - fifo_spi_test(); - - #100ns - - offload_spi_test(); - - spi_env.stop(); - base_env.stop(); - - `INFO(("Test Done"), ADI_VERBOSITY_NONE); - - $finish; - -end - -//--------------------------------------------------------------------------- -// Sanity test reg interface -//--------------------------------------------------------------------------- - -task sanity_test(); - bit [31:0] pcore_version = (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_PATCH) - | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MINOR)<<8 - | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR)<<16; - axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_VERSION), pcore_version); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); - axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); - `INFO(("Sanity Test Done"), ADI_VERBOSITY_LOW); -endtask - -//--------------------------------------------------------------------------- -// SPI Engine generate transfer -//--------------------------------------------------------------------------- - -task generate_transfer_cmd( - input [7:0] sync_id); - // assert CSN - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFE)); - // transfer data - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_WRD); - // de-assert CSN - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFF)); - // SYNC command to generate interrupt - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_SYNC | sync_id)); - `INFO(("Transfer generation finished."), ADI_VERBOSITY_LOW); -endtask + timeunit 1ns; + timeprecision 100ps; + + // declare the class instances + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + spi_environment spi_env; + + // -------------------------- + // Wrapper function for AXI read verify + // -------------------------- + task axi_read_v( + input [31:0] raddr, + input [31:0] vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + endtask + + task axi_read( + input [31:0] raddr, + output [31:0] data); + base_env.mng.sequencer.RegRead32(raddr,data); + endtask + + // -------------------------- + // Wrapper function for AXI write + // -------------------------- + task axi_write( + input [31:0] waddr, + input [31:0] wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); + endtask + + // -------------------------- + // Wrapper function for SPI receive (from DUT) + // -------------------------- + task spi_receive( + output [`DATA_DLENGTH:0] data); + spi_env.spi_agent.sequencer.receive_data(data); + endtask + + // -------------------------- + // Wrapper function for SPI send (to DUT) + // -------------------------- + task spi_send( + input [`DATA_DLENGTH:0] data); + spi_env.spi_agent.sequencer.send_data(data); + endtask + + // -------------------------- + // Wrapper function for waiting for all SPI + // -------------------------- + task spi_wait_send(); + spi_env.spi_agent.sequencer.flush_send(); + endtask + + + // -------------------------- + // Main procedure + // -------------------------- + initial begin + + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + spi_env = new("SPI Engine Environment", + `ifdef DEF_SDO_STREAMING + `TH.`SDO_SRC.inst.IF, + `endif + `TH.`SPI_S.inst.IF.vif); + + setLoggerVerbosity(ADI_VERBOSITY_NONE); + + base_env.start(); + spi_env.start(); + + base_env.sys_reset(); + + spi_env.configure(); + + spi_env.run(); + + spi_env.spi_agent.sequencer.set_default_miso_data('h2AA55); + + // start sdo source (will wait for data enqueued) + `ifdef DEF_SDO_STREAMING + spi_env.sdo_src_agent.sequencer.start(); + `endif + + sanity_test(); + + #100ns + + fifo_spi_test(); + + #100ns + + offload_spi_test(); + + spi_env.stop(); + base_env.stop(); + + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish(); -//--------------------------------------------------------------------------- -// SPI Engine SDO data -//--------------------------------------------------------------------------- - -task sdo_stream_gen( - input [`DATA_DLENGTH:0] tx_data); - xil_axi4stream_data_byte data[(`DATA_WIDTH/8)-1:0]; - `ifdef DEF_SDO_STREAMING - for (int i = 0; i<(`DATA_WIDTH/8);i++) begin - data[i] = (tx_data & (8'hFF << 8*i)) >> 8*i; - spi_env.sdo_src_seq.push_byte_for_stream(data[i]); end - spi_env.sdo_src_seq.add_xfer_descriptor_byte_count((`DATA_WIDTH/8),0,0); - `endif -endtask - -//--------------------------------------------------------------------------- -// IRQ callback -//--------------------------------------------------------------------------- - -reg [4:0] irq_pending = 0; -reg [7:0] sync_id = 0; - -initial begin - forever begin - @(posedge spi_engine_irq); - // read pending IRQs - axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); - // IRQ launched by Offload SYNC command - if (irq_pending & 5'b10000) begin - axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); - `INFO(("Offload SYNC %d IRQ. An offload transfer just finished.", sync_id), ADI_VERBOSITY_LOW); - end - // IRQ launched by SYNC command - if (irq_pending & 5'b01000) begin - axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); - `INFO(("SYNC %d IRQ. FIFO transfer just finished.", sync_id), ADI_VERBOSITY_LOW); - end - // IRQ launched by SDI FIFO - if (irq_pending & 5'b00100) begin - `INFO(("SDI FIFO IRQ."), ADI_VERBOSITY_LOW); - end - // IRQ launched by SDO FIFO - if (irq_pending & 5'b00010) begin - `INFO(("SDO FIFO IRQ."), ADI_VERBOSITY_LOW); - end - // IRQ launched by SDO FIFO - if (irq_pending & 5'b00001) begin - `INFO(("CMD FIFO IRQ."), ADI_VERBOSITY_LOW); + //--------------------------------------------------------------------------- + // Sanity test reg interface + //--------------------------------------------------------------------------- + + task sanity_test(); + bit [31:0] pcore_version = (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_PATCH) + | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MINOR)<<8 + | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR)<<16; + axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_VERSION), pcore_version); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); + axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); + `INFO(("Sanity Test Done"), ADI_VERBOSITY_LOW); + endtask + + //--------------------------------------------------------------------------- + // SPI Engine generate transfer + //--------------------------------------------------------------------------- + + task generate_transfer_cmd( + input [7:0] sync_id); + // assert CSN + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFE)); + // transfer data + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_WRD); + // de-assert CSN + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFF)); + // SYNC command to generate interrupt + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_SYNC | sync_id)); + `INFO(("Transfer generation finished."), ADI_VERBOSITY_LOW); + endtask + + //--------------------------------------------------------------------------- + // SPI Engine SDO data + //--------------------------------------------------------------------------- + + task sdo_stream_gen( + input [`DATA_DLENGTH:0] tx_data); + xil_axi4stream_data_byte data[(`DATA_WIDTH/8)-1:0]; + `ifdef DEF_SDO_STREAMING + for (int i = 0; i<(`DATA_WIDTH/8);i++) begin + data[i] = (tx_data & (8'hFF << 8*i)) >> 8*i; + spi_env.sdo_src_agent.sequencer.push_byte_for_stream(data[i]); + end + spi_env.sdo_src_agent.sequencer.add_xfer_descriptor_byte_count((`DATA_WIDTH/8),0,0); + `endif + endtask + + //--------------------------------------------------------------------------- + // IRQ callback + //--------------------------------------------------------------------------- + + reg [4:0] irq_pending = 0; + reg [7:0] sync_id = 0; + + initial begin + forever begin + @(posedge spi_engine_irq); + // read pending IRQs + + axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); + // IRQ launched by Offload SYNC command + if (irq_pending & 5'b10000) begin + axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); + `INFO(("Offload SYNC %d IRQ. An offload transfer just finished.", sync_id), ADI_VERBOSITY_LOW); + end + // IRQ launched by SYNC command + if (irq_pending & 5'b01000) begin + axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); + `INFO(("SYNC %d IRQ. FIFO transfer just finished.", sync_id), ADI_VERBOSITY_LOW); + end + // IRQ launched by SDI FIFO + if (irq_pending & 5'b00100) begin + `INFO(("SDI FIFO IRQ."), ADI_VERBOSITY_LOW); + end + // IRQ launched by SDO FIFO + if (irq_pending & 5'b00010) begin + `INFO(("SDO FIFO IRQ."), ADI_VERBOSITY_LOW); + end + // IRQ launched by SDO FIFO + if (irq_pending & 5'b00001) begin + `INFO(("CMD FIFO IRQ."), ADI_VERBOSITY_LOW); + end + // Clear all pending IRQs + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); end - // Clear all pending IRQs - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); end -end - -//--------------------------------------------------------------------------- -// Echo SCLK generation - we need this only if ECHO_SCLK is enabled -//--------------------------------------------------------------------------- -`ifdef DEF_ECHO_SCLK - assign #(`ECHO_SCLK_DELAY * 1ns) spi_engine_echo_sclk = spi_engine_spi_sclk; -`endif + //--------------------------------------------------------------------------- + // Echo SCLK generation - we need this only if ECHO_SCLK is enabled + //--------------------------------------------------------------------------- + `ifdef DEF_ECHO_SCLK + assign #(`ECHO_SCLK_DELAY * 1ns) spi_engine_echo_sclk = spi_engine_spi_sclk; + `endif -//--------------------------------------------------------------------------- -// Offload SPI Test -//--------------------------------------------------------------------------- -bit [`DATA_DLENGTH-1:0] sdi_read_data [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0] = '{default:'0}; -bit [`DATA_DLENGTH-1:0] sdo_write_data [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0] = '{default:'0}; -bit [`DATA_DLENGTH-1:0] sdi_read_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0]; -bit [`DATA_DLENGTH-1:0] sdo_write_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0]; -bit [`DATA_DLENGTH-1:0] rx_data; -bit [`DATA_DLENGTH-1:0] tx_data; - -task offload_spi_test(); - //Configure DMA - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), - `SET_DMAC_FLAGS_TLAST(1) | - `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) - ); // Use TLAST - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - - // Configure the Offload module - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_PRESCALE); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_DLENGTH); - if (`CS_ACTIVE_HIGH) begin - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_INV_MASK(8'hFF)); - end - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFE)); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_WRD); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFF)); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 2); - - // Enqueue transfers transfers to DUT - for (int i = 0; i<((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)) ; i=i+1) begin - rx_data = $urandom; - spi_send(rx_data); - sdi_read_data_store[i] = rx_data; - tx_data = $urandom; - `ifdef DEF_SDO_STREAMING - sdo_stream_gen(tx_data); - sdo_write_data_store[i] = tx_data; - `else - if (i<(`NUM_OF_WORDS)) begin + //--------------------------------------------------------------------------- + // Offload SPI Test + //--------------------------------------------------------------------------- + + bit [`DATA_DLENGTH-1:0] sdi_read_data [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0] = '{default:'0}; + bit [`DATA_DLENGTH-1:0] sdo_write_data [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0] = '{default:'0}; + bit [`DATA_DLENGTH-1:0] sdi_read_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0]; + bit [`DATA_DLENGTH-1:0] sdo_write_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0]; + bit [`DATA_DLENGTH-1:0] rx_data; + bit [`DATA_DLENGTH-1:0] tx_data; + + task offload_spi_test(); + //Configure DMA + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), + `SET_DMAC_FLAGS_TLAST(1) | + `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) + ); // Use TLAST + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + + // Configure the Offload module + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_PRESCALE); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_DLENGTH); + if (`CS_ACTIVE_HIGH) begin + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_INV_MASK(8'hFF)); + end + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFE)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_WRD); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFF)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 2); + + // Enqueue transfers transfers to DUT + for (int i = 0; i<((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)) ; i=i+1) begin + rx_data = $urandom; + spi_send(rx_data); + sdi_read_data_store[i] = rx_data; + tx_data = $urandom; + `ifdef DEF_SDO_STREAMING + sdo_stream_gen(tx_data); sdo_write_data_store[i] = tx_data; - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO), sdo_write_data_store[i]); - end else begin - sdo_write_data_store[i] = sdo_write_data_store[i%(`NUM_OF_WORDS)]; - end - `endif - end - - // Start the offload - #100ns - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(1)); - `INFO(("Offload started."), ADI_VERBOSITY_LOW); + `else + if (i<(`NUM_OF_WORDS)) begin + sdo_write_data_store[i] = tx_data; + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO), sdo_write_data_store[i]); + end else begin + sdo_write_data_store[i] = sdo_write_data_store[i%(`NUM_OF_WORDS)]; + end + `endif + end - spi_wait_send(); + // Start the offload + #100ns + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(1)); + `INFO(("Offload started."), ADI_VERBOSITY_LOW); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(0)); + spi_wait_send(); - `INFO(("Offload stopped."), ADI_VERBOSITY_LOW); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(0)); - #2000ns + `INFO(("Offload stopped."), ADI_VERBOSITY_LOW); - if (irq_pending == 'h0) begin - `FATAL(("IRQ Test FAILED")); - end else begin - `INFO(("IRQ Test PASSED"), ADI_VERBOSITY_LOW); - end + #2000ns - for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin - sdi_read_data[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); - if (sdi_read_data[i] != sdi_read_data_store[i]) begin - `INFO(("sdi_read_data[%d]: %x; sdi_read_data_store[%d]: %x", i, sdi_read_data[i], i, sdi_read_data_store[i]), ADI_VERBOSITY_LOW); - `ERROR(("Offload Read Test FAILED")); + if (irq_pending == 'h0) begin + `FATAL(("IRQ Test FAILED")); + end else begin + `INFO(("IRQ Test PASSED"), ADI_VERBOSITY_LOW); end - end - `INFO(("Offload Read Test PASSED"), ADI_VERBOSITY_LOW); - for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin - spi_receive(sdo_write_data[i]); - if (sdo_write_data[i] != sdo_write_data_store[i]) begin - `INFO(("sdo_write_data[%d]: %x; sdo_write_data_store[%d]: %x", i, sdo_write_data[i], i, sdo_write_data_store[i]), ADI_VERBOSITY_LOW); - `ERROR(("Offload Write Test FAILED")); + for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin + sdi_read_data[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); + if (sdi_read_data[i] != sdi_read_data_store[i]) begin + `INFO(("sdi_read_data[%d]: %x; sdi_read_data_store[%d]: %x", i, sdi_read_data[i], i, sdi_read_data_store[i]), ADI_VERBOSITY_LOW); + `ERROR(("Offload Read Test FAILED")); + end end - end - `INFO(("Offload Write Test PASSED"), ADI_VERBOSITY_LOW); -endtask - -//--------------------------------------------------------------------------- -// FIFO SPI Test -//--------------------------------------------------------------------------- + `INFO(("Offload Read Test PASSED"), ADI_VERBOSITY_LOW); -bit [`DATA_DLENGTH-1:0] sdi_fifo_data [`NUM_OF_WORDS-1:0]= '{default:'0}; -bit [`DATA_DLENGTH-1:0] sdo_fifo_data [`NUM_OF_WORDS-1:0]= '{default:'0}; -bit [`DATA_DLENGTH-1:0] sdi_fifo_data_store [`NUM_OF_WORDS-1:0]; -bit [`DATA_DLENGTH-1:0] sdo_fifo_data_store [`NUM_OF_WORDS-1:0]; - -task fifo_spi_test(); - // Start spi clk generator - axi_write (`SPI_ENGINE_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), - `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | - `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) - ); - - // Config pwm - axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); // PWM_GEN reset in regmap (ACTIVE HIGH) - axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_PULSE_X_PERIOD), `SET_AXI_PWM_GEN_REG_PULSE_X_PERIOD_PULSE_X_PERIOD('d121)); // set PWM period - axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_LOAD_CONFIG(1)); // load AXI_PWM_GEN configuration - `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); - - // Enable SPI Engine - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); - - // Configure the execution module - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH); - if (`CS_ACTIVE_HIGH) begin - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF)); - end + for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin + spi_receive(sdo_write_data[i]); + if (sdo_write_data[i] != sdo_write_data_store[i]) begin + `INFO(("sdo_write_data[%d]: %x; sdo_write_data_store[%d]: %x", i, sdo_write_data[i], i, sdo_write_data_store[i]), ADI_VERBOSITY_LOW); + `ERROR(("Offload Write Test FAILED")); + end + end + `INFO(("Offload Write Test PASSED"), ADI_VERBOSITY_LOW); + endtask + + //--------------------------------------------------------------------------- + // FIFO SPI Test + //--------------------------------------------------------------------------- + + bit [`DATA_DLENGTH-1:0] sdi_fifo_data [`NUM_OF_WORDS-1:0]= '{default:'0}; + bit [`DATA_DLENGTH-1:0] sdo_fifo_data [`NUM_OF_WORDS-1:0]= '{default:'0}; + bit [`DATA_DLENGTH-1:0] sdi_fifo_data_store [`NUM_OF_WORDS-1:0]; + bit [`DATA_DLENGTH-1:0] sdo_fifo_data_store [`NUM_OF_WORDS-1:0]; + + task fifo_spi_test(); + // Start spi clk generator + axi_write (`SPI_ENGINE_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), + `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | + `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) + ); + + // Config pwm + axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); // PWM_GEN reset in regmap (ACTIVE HIGH) + axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_PULSE_X_PERIOD), `SET_AXI_PWM_GEN_REG_PULSE_X_PERIOD_PULSE_X_PERIOD('d121)); // set PWM period + axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_LOAD_CONFIG(1)); // load AXI_PWM_GEN configuration + `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); + + // Enable SPI Engine + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); + + // Configure the execution module + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH); + if (`CS_ACTIVE_HIGH) begin + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF)); + end - // Set up the interrupts - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_MASK), - `SET_AXI_SPI_ENGINE_IRQ_MASK_SYNC_EVENT(1) | - `SET_AXI_SPI_ENGINE_IRQ_MASK_OFFLOAD_SYNC_ID_PENDING(1) - ); - - #100ns - // Generate a FIFO transaction, write SDO first - for (int i = 0; i<(`NUM_OF_WORDS) ; i=i+1) begin - rx_data = $urandom; - tx_data = $urandom; - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDO_FIFO), (tx_data));// << (`DATA_WIDTH - `DATA_DLENGTH))); - spi_send(rx_data); - sdi_fifo_data_store[i] = rx_data; - sdo_fifo_data_store[i] = tx_data; - end + // Set up the interrupts + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_MASK), + `SET_AXI_SPI_ENGINE_IRQ_MASK_SYNC_EVENT(1) | + `SET_AXI_SPI_ENGINE_IRQ_MASK_OFFLOAD_SYNC_ID_PENDING(1) + ); + + #100ns + // Generate a FIFO transaction, write SDO first + for (int i = 0; i<(`NUM_OF_WORDS) ; i=i+1) begin + rx_data = $urandom; + tx_data = $urandom; + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDO_FIFO), (tx_data));// << (`DATA_WIDTH - `DATA_DLENGTH))); + spi_send(rx_data); + sdi_fifo_data_store[i] = rx_data; + sdo_fifo_data_store[i] = tx_data; + end - generate_transfer_cmd(1); + generate_transfer_cmd(1); - `INFO(("Waiting for SPI VIP send..."), ADI_VERBOSITY_LOW); - spi_wait_send(); - `INFO(("SPI sent"), ADI_VERBOSITY_LOW); + `INFO(("Waiting for SPI VIP send..."), ADI_VERBOSITY_LOW); + spi_wait_send(); + `INFO(("SPI sent"), ADI_VERBOSITY_LOW); - for (int i = 0; i<(`NUM_OF_WORDS) ; i=i+1) begin - axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDI_FIFO), sdi_fifo_data[i]); - spi_receive(sdo_fifo_data[i]); - end + for (int i = 0; i<(`NUM_OF_WORDS) ; i=i+1) begin + axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDI_FIFO), sdi_fifo_data[i]); + spi_receive(sdo_fifo_data[i]); + end - if (sdi_fifo_data !== sdi_fifo_data_store) begin - `INFO(("sdi_fifo_data: %x; sdi_fifo_data_store %x", sdi_fifo_data, sdi_fifo_data_store), ADI_VERBOSITY_LOW); - `ERROR(("Fifo Read Test FAILED")); - end - `INFO(("Fifo Read Test PASSED"), ADI_VERBOSITY_LOW); + if (sdi_fifo_data !== sdi_fifo_data_store) begin + `INFO(("sdi_fifo_data: %x; sdi_fifo_data_store %x", sdi_fifo_data, sdi_fifo_data_store), ADI_VERBOSITY_LOW); + `FATAL(("Fifo Read Test FAILED")); + end + `INFO(("Fifo Read Test PASSED"), ADI_VERBOSITY_LOW); - if (sdo_fifo_data !== sdo_fifo_data_store) begin - `INFO(("sdo_fifo_data: %x; sdo_fifo_data_store %x", sdo_fifo_data, sdo_fifo_data_store), ADI_VERBOSITY_LOW); - `ERROR(("Fifo Write Test FAILED")); - end - `INFO(("Fifo Write Test PASSED"), ADI_VERBOSITY_LOW); -endtask + if (sdo_fifo_data !== sdo_fifo_data_store) begin + `INFO(("sdo_fifo_data: %x; sdo_fifo_data_store %x", sdo_fifo_data, sdo_fifo_data_store), ADI_VERBOSITY_LOW); + `FATAL(("Fifo Write Test FAILED")); + end + `INFO(("Fifo Write Test PASSED"), ADI_VERBOSITY_LOW); + endtask endprogram diff --git a/testbenches/ip/spi_engine/tests/test_sleep_delay.sv b/testbenches/ip/spi_engine/tests/test_sleep_delay.sv index 3dee7d3e..b2b4f846 100644 --- a/testbenches/ip/spi_engine/tests/test_sleep_delay.sv +++ b/testbenches/ip/spi_engine/tests/test_sleep_delay.sv @@ -35,6 +35,7 @@ `include "utils.svh" `include "axi_definitions.svh" +`include "axis_definitions.svh" import logger_pkg::*; import test_harness_env_pkg::*; @@ -62,468 +63,469 @@ program test_sleep_delay ( inout [(`NUM_OF_CS - 1):0] spi_engine_spi_cs, inout spi_engine_spi_clk, `ifdef DEF_ECHO_SCLK - inout spi_engine_echo_sclk, + inout spi_engine_echo_sclk, `endif inout [(`NUM_OF_SDI - 1):0] spi_engine_spi_sdi); -timeunit 1ns; -timeprecision 100ps; - -// declare the class instances -test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; -spi_environment spi_env; - -// -------------------------- -// Wrapper function for AXI read verify -// -------------------------- -task axi_read_v( - input [31:0] raddr, - input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); -endtask - -task axi_read( - input [31:0] raddr, - output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); -endtask - -// -------------------------- -// Wrapper function for AXI write -// -------------------------- -task axi_write( - input [31:0] waddr, - input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); -endtask - -// -------------------------- -// Wrapper function for SPI receive (from DUT) -// -------------------------- -task spi_receive( - output [`DATA_DLENGTH:0] data); - spi_env.spi_seq.receive_data(data); -endtask - -// -------------------------- -// Wrapper function for SPI send (to DUT) -// -------------------------- -task spi_send( - input [`DATA_DLENGTH:0] data); - spi_env.spi_seq.send_data(data); -endtask - -// -------------------------- -// Wrapper function for waiting for all SPI -// -------------------------- -task spi_wait_send(); - spi_env.spi_seq.flush_send(); -endtask - -// -------------------------- -// Main procedure -// -------------------------- -initial begin - - //creating environment - base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); - - spi_env = new("SPI Engine Environment", - `ifdef DEF_SDO_STREAMING - `TH.`SDO_SRC.inst.IF, - `endif - `TH.`SPI_S.inst.IF); - - setLoggerVerbosity(ADI_VERBOSITY_NONE); - - base_env.start(); - spi_env.start(); + timeunit 1ns; + timeprecision 100ps; + + // declare the class instances + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + spi_environment spi_env; + + // -------------------------- + // Wrapper function for AXI read verify + // -------------------------- + task axi_read_v( + input [31:0] raddr, + input [31:0] vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + endtask + + task axi_read( + input [31:0] raddr, + output [31:0] data); + base_env.mng.sequencer.RegRead32(raddr,data); + endtask + + // -------------------------- + // Wrapper function for AXI write + // -------------------------- + task axi_write( + input [31:0] waddr, + input [31:0] wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); + endtask + + // -------------------------- + // Wrapper function for SPI receive (from DUT) + // -------------------------- + task spi_receive( + output [`DATA_DLENGTH:0] data); + spi_env.spi_agent.sequencer.receive_data(data); + endtask + + // -------------------------- + // Wrapper function for SPI send (to DUT) + // -------------------------- + task spi_send( + input [`DATA_DLENGTH:0] data); + spi_env.spi_agent.sequencer.send_data(data); + endtask + + // -------------------------- + // Wrapper function for waiting for all SPI + // -------------------------- + task spi_wait_send(); + spi_env.spi_agent.sequencer.flush_send(); + endtask - base_env.sys_reset(); + + // -------------------------- + // Main procedure + // -------------------------- + initial begin - spi_env.configure(); + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + spi_env = new("SPI Engine Environment", + `ifdef DEF_SDO_STREAMING + `TH.`SDO_SRC.inst.IF, + `endif + `TH.`SPI_S.inst.IF.vif); - spi_env.run(); + setLoggerVerbosity(ADI_VERBOSITY_NONE); - spi_env.spi_seq.set_default_miso_data('h2AA55); + base_env.start(); + spi_env.start(); - // start sdo source (will wait for data enqueued) - `ifdef DEF_SDO_STREAMING - spi_env.sdo_src_seq.start(); - `endif + base_env.sys_reset(); - sanity_test(); + spi_env.configure(); - #100ns + spi_env.run(); - sleep_delay_test(7); + spi_env.spi_agent.sequencer.set_default_miso_data('h2AA55); - cs_delay_test(3,3); + // start sdo source (will wait for data enqueued) + `ifdef DEF_SDO_STREAMING + spi_env.sdo_src_agent.sequencer.start(); + `endif - spi_env.stop(); - base_env.stop(); + sanity_test(); - `INFO(("Test Done"), ADI_VERBOSITY_NONE); + #100ns - $finish; + sleep_delay_test(7); -end + cs_delay_test(3,3); -//--------------------------------------------------------------------------- -// Sanity test reg interface -//--------------------------------------------------------------------------- + spi_env.stop(); + base_env.stop(); -task sanity_test(); - bit [31:0] pcore_version = (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_PATCH) - | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MINOR)<<8 - | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR)<<16; - axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_VERSION), pcore_version); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); - axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); - `INFO(("Sanity Test Done"), ADI_VERBOSITY_LOW); -endtask + `INFO(("Test Done"), ADI_VERBOSITY_NONE); -//--------------------------------------------------------------------------- -// IRQ callback -//--------------------------------------------------------------------------- + $finish; -reg [4:0] irq_pending = 0; -reg [7:0] sync_id = 0; - -initial begin - forever begin - @(posedge spi_engine_irq); - // read pending IRQs - axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); - // IRQ launched by Offload SYNC command - if (irq_pending & 5'b10000) begin - axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD_SYNC_ID), sync_id); - `INFO(("Offload SYNC %d IRQ. An offload transfer just finished.", sync_id), ADI_VERBOSITY_LOW); - end - // IRQ launched by SYNC command - if (irq_pending & 5'b01000) begin - axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); - `INFO(("SYNC %d IRQ. FIFO transfer just finished.", sync_id), ADI_VERBOSITY_LOW); - end - // IRQ launched by SDI FIFO - if (irq_pending & 5'b00100) begin - `INFO(("SDI FIFO IRQ."), ADI_VERBOSITY_LOW); - end - // IRQ launched by SDO FIFO - if (irq_pending & 5'b00010) begin - `INFO(("SDO FIFO IRQ."), ADI_VERBOSITY_LOW); - end - // IRQ launched by SDO FIFO - if (irq_pending & 5'b00001) begin - `INFO(("CMD FIFO IRQ."), ADI_VERBOSITY_LOW); - end - // Clear all pending IRQs - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); end -end - -//--------------------------------------------------------------------------- -// Echo SCLK generation - we need this only if ECHO_SCLK is enabled -//--------------------------------------------------------------------------- -`ifdef DEF_ECHO_SCLK - assign #(`ECHO_SCLK_DELAY * 1ns) spi_engine_echo_sclk = spi_engine_spi_sclk; -`endif - -//--------------------------------------------------------------------------- -// Sleep and Chip Select Instruction time counter -//--------------------------------------------------------------------------- -int sleep_instr_time[$]; -int sleep_duration; -int sleep_current_duration; -bit sleeping; -int cs_instr_time[$]; -int cs_current_duration; -int cs_duration; -bit cs_sleeping; -wire [15:0] cmd, cmd_d1; -wire cmd_valid, cmd_ready; -wire idle; - -assign cmd = `TH.spi_engine.spi_engine_execution.inst.cmd; -assign cmd_d1 = `TH.spi_engine.spi_engine_execution.inst.cmd_d1; -assign cmd_valid = `TH.spi_engine.spi_engine_execution.inst.cmd_valid; -assign cmd_ready = `TH.spi_engine.spi_engine_execution.inst.cmd_ready; -assign idle = `TH.spi_engine.spi_engine_execution.inst.idle; - -initial begin - sleep_current_duration = 0; - sleep_duration = 0; - sleeping = 1'b0; - cs_current_duration = 0; - cs_duration = 0; - cs_sleeping = 1'b0; - forever begin - @(posedge spi_engine_spi_clk); - if (idle && (cmd_d1[15:8] == 8'h31) && sleeping) begin - sleeping <= 1'b0; - sleep_duration = sleep_current_duration+1; - sleep_instr_time.push_front(sleep_current_duration+1); // add one to account for this cycle + //--------------------------------------------------------------------------- + // Sanity test reg interface + //--------------------------------------------------------------------------- + + task sanity_test(); + bit [31:0] pcore_version = (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_PATCH) + | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MINOR)<<8 + | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR)<<16; + axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_VERSION), pcore_version); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); + axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); + `INFO(("Sanity Test Done"), ADI_VERBOSITY_LOW); + endtask + + //--------------------------------------------------------------------------- + // IRQ callback + //--------------------------------------------------------------------------- + + reg [4:0] irq_pending = 0; + reg [7:0] sync_id = 0; + + initial begin + forever begin + @(posedge spi_engine_irq); + // read pending IRQs + axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); + // IRQ launched by Offload SYNC command + if (irq_pending & 5'b10000) begin + axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD_SYNC_ID), sync_id); + `INFO(("Offload SYNC %d IRQ. An offload transfer just finished.", sync_id), ADI_VERBOSITY_LOW); + end + // IRQ launched by SYNC command + if (irq_pending & 5'b01000) begin + axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); + `INFO(("SYNC %d IRQ. FIFO transfer just finished.", sync_id), ADI_VERBOSITY_LOW); end - if (cmd_valid && cmd_ready && (cmd[15:8] == 8'h31)) begin - sleep_current_duration <= 0; - sleeping <= 1'b1; - end else begin - sleep_current_duration <= sleep_current_duration+1; + // IRQ launched by SDI FIFO + if (irq_pending & 5'b00100) begin + `INFO(("SDI FIFO IRQ."), ADI_VERBOSITY_LOW); end - if (idle && (cmd_d1[15:10] == 6'h4) && cs_sleeping) begin - cs_sleeping = 1'b0; - cs_duration = cs_current_duration+1; - cs_instr_time.push_front(cs_current_duration+1); // add one to account for this cycle + // IRQ launched by SDO FIFO + if (irq_pending & 5'b00010) begin + `INFO(("SDO FIFO IRQ."), ADI_VERBOSITY_LOW); end - if (cmd_valid && cmd_ready && (cmd[15:10] == 6'h4)) begin - cs_current_duration <= 0; - cs_sleeping <= 1'b1; - end else begin - cs_current_duration <= cs_current_duration+1; + // IRQ launched by SDO FIFO + if (irq_pending & 5'b00001) begin + `INFO(("CMD FIFO IRQ."), ADI_VERBOSITY_LOW); end + // Clear all pending IRQs + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); + end end -end - -//--------------------------------------------------------------------------- -// Sleep delay Test -//--------------------------------------------------------------------------- - -int sleep_time; -int expected_sleep_time; - -task sleep_delay_test( - input [7:0] sleep_param); - // Start spi clk generator - axi_write (`SPI_ENGINE_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), - `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | - `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) - ); - - // Config pwm - axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); // PWM_GEN reset in regmap (ACTIVE HIGH) - axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_PULSE_X_PERIOD), `SET_AXI_PWM_GEN_REG_PULSE_X_PERIOD_PULSE_X_PERIOD('d1000)); // set PWM period - axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_LOAD_CONFIG(1)); // load AXI_PWM_GEN configuration - `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); - // Enable SPI Engine - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); - - // Set up the interrupts - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_MASK), - `SET_AXI_SPI_ENGINE_IRQ_MASK_SYNC_EVENT(1) | - `SET_AXI_SPI_ENGINE_IRQ_MASK_OFFLOAD_SYNC_ID_PENDING(1) - ); + //--------------------------------------------------------------------------- + // Echo SCLK generation - we need this only if ECHO_SCLK is enabled + //--------------------------------------------------------------------------- + `ifdef DEF_ECHO_SCLK + assign #(`ECHO_SCLK_DELAY * 1ns) spi_engine_echo_sclk = spi_engine_spi_sclk; + `endif - // Write commands - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_DLENGTH(`DATA_WIDTH - `DATA_DLENGTH)); - if (`CS_ACTIVE_HIGH) begin - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF)); + //--------------------------------------------------------------------------- + // Sleep and Chip Select Instruction time counter + //--------------------------------------------------------------------------- + + int sleep_instr_time[$]; + int sleep_duration; + int sleep_current_duration; + bit sleeping; + int cs_instr_time[$]; + int cs_current_duration; + int cs_duration; + bit cs_sleeping; + wire [15:0] cmd, cmd_d1; + wire cmd_valid, cmd_ready; + wire idle; + + assign cmd = `TH.spi_engine.spi_engine_execution.inst.cmd; + assign cmd_d1 = `TH.spi_engine.spi_engine_execution.inst.cmd_d1; + assign cmd_valid = `TH.spi_engine.spi_engine_execution.inst.cmd_valid; + assign cmd_ready = `TH.spi_engine.spi_engine_execution.inst.cmd_ready; + assign idle = `TH.spi_engine.spi_engine_execution.inst.idle; + + initial begin + sleep_current_duration = 0; + sleep_duration = 0; + sleeping = 1'b0; + cs_current_duration = 0; + cs_duration = 0; + cs_sleeping = 1'b0; + forever begin + @(posedge spi_engine_spi_clk); + if (idle && (cmd_d1[15:8] == 8'h31) && sleeping) begin + sleeping <= 1'b0; + sleep_duration = sleep_current_duration+1; + sleep_instr_time.push_front(sleep_current_duration+1); // add one to account for this cycle + end + if (cmd_valid && cmd_ready && (cmd[15:8] == 8'h31)) begin + sleep_current_duration <= 0; + sleeping <= 1'b1; + end else begin + sleep_current_duration <= sleep_current_duration+1; + end + if (idle && (cmd_d1[15:10] == 6'h4) && cs_sleeping) begin + cs_sleeping = 1'b0; + cs_duration = cs_current_duration+1; + cs_instr_time.push_front(cs_current_duration+1); // add one to account for this cycle + end + if (cmd_valid && cmd_ready && (cmd[15:10] == 6'h4)) begin + cs_current_duration <= 0; + cs_sleeping <= 1'b1; + end else begin + cs_current_duration <= cs_current_duration+1; + end + end end - expected_sleep_time = 2+(sleep_param+1)*((`CLOCK_DIVIDER+1)*2); - // Start the test - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`SLEEP(sleep_param))); - - #2000ns - sleep_time = sleep_instr_time.pop_back(); - if ((sleep_time != expected_sleep_time)) begin - `FATAL(("Sleep Test FAILED: unexpected sleep instruction duration. Expected=%d, Got=%d",expected_sleep_time,sleep_time)); - end else begin - `INFO(("Sleep Test PASSED"), ADI_VERBOSITY_LOW); - end + //--------------------------------------------------------------------------- + // Sleep delay Test + //--------------------------------------------------------------------------- + + int sleep_time; + int expected_sleep_time; + + task sleep_delay_test( + input [7:0] sleep_param); + // Start spi clk generator + axi_write (`SPI_ENGINE_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), + `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | + `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) + ); + + // Config pwm + axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); // PWM_GEN reset in regmap (ACTIVE HIGH) + axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_PULSE_X_PERIOD), `SET_AXI_PWM_GEN_REG_PULSE_X_PERIOD_PULSE_X_PERIOD('d1000)); // set PWM period + axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_LOAD_CONFIG(1)); // load AXI_PWM_GEN configuration + `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); + + // Enable SPI Engine + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); + + // Set up the interrupts + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_MASK), + `SET_AXI_SPI_ENGINE_IRQ_MASK_SYNC_EVENT(1) | + `SET_AXI_SPI_ENGINE_IRQ_MASK_OFFLOAD_SYNC_ID_PENDING(1) + ); + + // Write commands + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_DLENGTH(`DATA_WIDTH - `DATA_DLENGTH)); + if (`CS_ACTIVE_HIGH) begin + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF)); + end - // change the SPI word size (this should not affect sleep delay) - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`SLEEP(sleep_param))); - #2000ns - sleep_time = sleep_instr_time.pop_back(); - #100ns - if ((sleep_time != expected_sleep_time)) begin - `FATAL(("Sleep Test FAILED: unexpected sleep instruction duration. Expected=%d, Got=%d",expected_sleep_time,sleep_time)); - end else begin - `INFO(("Sleep Test PASSED"), ADI_VERBOSITY_LOW); - end + expected_sleep_time = 2+(sleep_param+1)*((`CLOCK_DIVIDER+1)*2); + // Start the test + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`SLEEP(sleep_param))); - // Disable SPI Engine - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), 1); -endtask + #2000ns + sleep_time = sleep_instr_time.pop_back(); + if ((sleep_time != expected_sleep_time)) begin + `FATAL(("Sleep Test FAILED: unexpected sleep instruction duration. Expected=%d, Got=%d",expected_sleep_time,sleep_time)); + end else begin + `INFO(("Sleep Test PASSED"), ADI_VERBOSITY_LOW); + end -//--------------------------------------------------------------------------- -// CS delay Test -//--------------------------------------------------------------------------- + // change the SPI word size (this should not affect sleep delay) + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`SLEEP(sleep_param))); + #2000ns + sleep_time = sleep_instr_time.pop_back(); + #100ns + if ((sleep_time != expected_sleep_time)) begin + `FATAL(("Sleep Test FAILED: unexpected sleep instruction duration. Expected=%d, Got=%d",expected_sleep_time,sleep_time)); + end else begin + `INFO(("Sleep Test PASSED"), ADI_VERBOSITY_LOW); + end -bit [`DATA_DLENGTH:0] offload_captured_word_arr [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)-1:0]; -bit [`DATA_DLENGTH:0] offload_sdi_data_store_arr [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)-1:0]; -int cs_activate_time; -int expected_cs_activate_time; -int cs_deactivate_time; -int expected_cs_deactivate_time; -bit [`DATA_DLENGTH-1:0] temp_data; - -task cs_delay_test( - input [1:0] cs_activate_delay, - input [1:0] cs_deactivate_delay); - // Start spi clk generator - axi_write (`SPI_ENGINE_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), - `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | - `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) + // Disable SPI Engine + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), 1); + endtask + + //--------------------------------------------------------------------------- + // CS delay Test + //--------------------------------------------------------------------------- + + bit [`DATA_DLENGTH:0] offload_captured_word_arr [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)-1:0]; + bit [`DATA_DLENGTH:0] offload_sdi_data_store_arr [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)-1:0]; + int cs_activate_time; + int expected_cs_activate_time; + int cs_deactivate_time; + int expected_cs_deactivate_time; + bit [`DATA_DLENGTH-1:0] temp_data; + + task cs_delay_test( + input [1:0] cs_activate_delay, + input [1:0] cs_deactivate_delay); + // Start spi clk generator + axi_write (`SPI_ENGINE_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), + `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | + `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) + ); + + // Config cnv + axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); + axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_PULSE_X_PERIOD), `SET_AXI_PWM_GEN_REG_PULSE_X_PERIOD_PULSE_X_PERIOD('d1000)); // set PWM period + axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_LOAD_CONFIG(1)); + `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); + + //Configure DMA + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), + `SET_DMAC_FLAGS_TLAST(1) | + `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) + ); // Use TLAST + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + + // Enable SPI Engine + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); + + // Set up the interrupts + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_MASK), + `SET_AXI_SPI_ENGINE_IRQ_MASK_SYNC_EVENT(1) | + `SET_AXI_SPI_ENGINE_IRQ_MASK_OFFLOAD_SYNC_ID_PENDING(1) ); - // Config cnv - axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); - axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_PULSE_X_PERIOD), `SET_AXI_PWM_GEN_REG_PULSE_X_PERIOD_PULSE_X_PERIOD('d1000)); // set PWM period - axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_LOAD_CONFIG(1)); - `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); - - //Configure DMA - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), - `SET_DMAC_FLAGS_TLAST(1) | - `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) - ); // Use TLAST - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - - // Enable SPI Engine - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); - - // Set up the interrupts - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_MASK), - `SET_AXI_SPI_ENGINE_IRQ_MASK_SYNC_EVENT(1) | - `SET_AXI_SPI_ENGINE_IRQ_MASK_OFFLOAD_SYNC_ID_PENDING(1) - ); - - // Configure the Offload module - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(1)); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(0)); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_PRESCALE); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_DLENGTH); - if (`CS_ACTIVE_HIGH) begin - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_INV_MASK(8'hFF)); - end - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFE)); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_RD); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFF)); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 1); - - expected_cs_activate_time = 2; - expected_cs_deactivate_time = 2; - - // Enqueue transfers to DUT - for (int i = 0; i<((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)) ; i=i+1) begin - temp_data = $urandom; - spi_send(temp_data); - offload_sdi_data_store_arr[i] = temp_data; - end + // Configure the Offload module + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(1)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(0)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_PRESCALE); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_DLENGTH); + if (`CS_ACTIVE_HIGH) begin + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_INV_MASK(8'hFF)); + end + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFE)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_RD); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFF)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 1); + + expected_cs_activate_time = 2; + expected_cs_deactivate_time = 2; + + // Enqueue transfers to DUT + for (int i = 0; i<((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)) ; i=i+1) begin + temp_data = $urandom; + spi_send(temp_data); + offload_sdi_data_store_arr[i] = temp_data; + end - // Start the offload - #100ns - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(1)); - `INFO(("Offload started (no delay on CS change)."), ADI_VERBOSITY_LOW); + // Start the offload + #100ns + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(1)); + `INFO(("Offload started (no delay on CS change)."), ADI_VERBOSITY_LOW); - spi_wait_send(); + spi_wait_send(); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(0)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(0)); - `INFO(("Offload stopped (no delay on CS change)."), ADI_VERBOSITY_LOW); + `INFO(("Offload stopped (no delay on CS change)."), ADI_VERBOSITY_LOW); - #2000ns + #2000ns - for (int i=0; i<=(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS); i=i+1) begin - offload_captured_word_arr[i][`DATA_DLENGTH-1:0] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); - end + for (int i=0; i<=(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS); i=i+1) begin + offload_captured_word_arr[i][`DATA_DLENGTH-1:0] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); + end - if (irq_pending == 'h0) begin - `FATAL(("IRQ Test FAILED")); - end else begin - `INFO(("IRQ Test PASSED"), ADI_VERBOSITY_LOW); - end + if (irq_pending == 'h0) begin + `FATAL(("IRQ Test FAILED")); + end else begin + `INFO(("IRQ Test PASSED"), ADI_VERBOSITY_LOW); + end - if (offload_captured_word_arr [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) - 1:0] !== offload_sdi_data_store_arr [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) - 1:0]) begin - `ERROR(("CS Delay Test FAILED: bad data")); - end + if (offload_captured_word_arr [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) - 1:0] !== offload_sdi_data_store_arr [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) - 1:0]) begin + `FATAL(("CS Delay Test FAILED: bad data")); + end - repeat (`NUM_OF_TRANSFERS) begin - cs_activate_time = cs_instr_time.pop_back(); - cs_deactivate_time = cs_instr_time.pop_back(); - end - if ((cs_activate_time != expected_cs_activate_time)) begin - `FATAL(("CS Delay Test FAILED: unexpected chip select activate instruction duration. Expected=%d, Got=%d",expected_cs_activate_time,cs_activate_time)); - end - if (cs_deactivate_time != expected_cs_deactivate_time) begin - `FATAL(("CS Delay Test FAILED: unexpected chip select deactivate instruction duration. Expected=%d, Got=%d",expected_cs_deactivate_time,cs_deactivate_time)); - end - `INFO(("CS Delay Test PASSED"), ADI_VERBOSITY_LOW); - - #2000ns - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(1)); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(0)); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_DELAY(8'hFE,cs_activate_delay)); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_RD); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_DELAY(8'hFF,cs_deactivate_delay)); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 2); - - // breakdown: cs_activate_delay*(1+`CLOCK_DIVIDER)*2, times 2 since it's before and after cs transition, and added 3 cycles (1 for each timer comparison, plus one for fetching next instruction) - expected_cs_activate_time = 2+2*cs_activate_delay*(1+`CLOCK_DIVIDER)*2; - expected_cs_deactivate_time = 2+2*cs_deactivate_delay*(1+`CLOCK_DIVIDER)*2; - - // Enqueue transfers to DUT - for (int i = 0; i<((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)) ; i=i+1) begin - temp_data = $urandom; - spi_send(temp_data); - offload_sdi_data_store_arr[i] = temp_data; - end + repeat (`NUM_OF_TRANSFERS) begin + cs_activate_time = cs_instr_time.pop_back(); + cs_deactivate_time = cs_instr_time.pop_back(); + end + if ((cs_activate_time != expected_cs_activate_time)) begin + `FATAL(("CS Delay Test FAILED: unexpected chip select activate instruction duration. Expected=%d, Got=%d",expected_cs_activate_time,cs_activate_time)); + end + if (cs_deactivate_time != expected_cs_deactivate_time) begin + `FATAL(("CS Delay Test FAILED: unexpected chip select deactivate instruction duration. Expected=%d, Got=%d",expected_cs_deactivate_time,cs_deactivate_time)); + end + `INFO(("CS Delay Test PASSED"), ADI_VERBOSITY_LOW); + + #2000ns + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(1)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(0)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_DELAY(8'hFE,cs_activate_delay)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_RD); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_DELAY(8'hFF,cs_deactivate_delay)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 2); + + // breakdown: cs_activate_delay*(1+`CLOCK_DIVIDER)*2, times 2 since it's before and after cs transition, and added 3 cycles (1 for each timer comparison, plus one for fetching next instruction) + expected_cs_activate_time = 2+2*cs_activate_delay*(1+`CLOCK_DIVIDER)*2; + expected_cs_deactivate_time = 2+2*cs_deactivate_delay*(1+`CLOCK_DIVIDER)*2; + + // Enqueue transfers to DUT + for (int i = 0; i<((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)) ; i=i+1) begin + temp_data = $urandom; + spi_send(temp_data); + offload_sdi_data_store_arr[i] = temp_data; + end - // Start the offload - #100ns - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(1)); - `INFO(("Offload started (with delay on CS change)."), ADI_VERBOSITY_LOW); + // Start the offload + #100ns + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(1)); + `INFO(("Offload started (with delay on CS change)."), ADI_VERBOSITY_LOW); - spi_wait_send(); + spi_wait_send(); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(0)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(0)); - `INFO(("Offload stopped (with delay on CS change)."), ADI_VERBOSITY_LOW); + `INFO(("Offload stopped (with delay on CS change)."), ADI_VERBOSITY_LOW); - #2000ns + #2000ns - for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin - offload_captured_word_arr[i][`DATA_DLENGTH-1:0] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); - end + for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin + offload_captured_word_arr[i][`DATA_DLENGTH-1:0] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); + end - if (irq_pending == 'h0) begin - `FATAL(("IRQ Test FAILED")); - end else begin - `INFO(("IRQ Test PASSED"), ADI_VERBOSITY_LOW); - end + if (irq_pending == 'h0) begin + `FATAL(("IRQ Test FAILED")); + end else begin + `INFO(("IRQ Test PASSED"), ADI_VERBOSITY_LOW); + end - if (offload_captured_word_arr [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) - 1:0] !== offload_sdi_data_store_arr [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) - 1:0]) begin - `ERROR(("CS Delay Test FAILED: bad data")); - end - repeat (`NUM_OF_TRANSFERS) begin - cs_activate_time = cs_instr_time.pop_back(); - cs_deactivate_time = cs_instr_time.pop_back(); - end - if ((cs_activate_time != expected_cs_activate_time)) begin - `FATAL(("CS Delay Test FAILED: unexpected chip select activate instruction duration. Expected=%d, Got=%d",expected_cs_activate_time,cs_activate_time)); - end - if (cs_deactivate_time != expected_cs_deactivate_time) begin - `FATAL(("CS Delay Test FAILED: unexpected chip select deactivate instruction duration. Expected=%d, Got=%d",expected_cs_deactivate_time,cs_deactivate_time)); - end - `INFO(("CS Delay Test PASSED"), ADI_VERBOSITY_LOW); -endtask + if (offload_captured_word_arr [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) - 1:0] !== offload_sdi_data_store_arr [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) - 1:0]) begin + `FATAL(("CS Delay Test FAILED: bad data")); + end + repeat (`NUM_OF_TRANSFERS) begin + cs_activate_time = cs_instr_time.pop_back(); + cs_deactivate_time = cs_instr_time.pop_back(); + end + if ((cs_activate_time != expected_cs_activate_time)) begin + `FATAL(("CS Delay Test FAILED: unexpected chip select activate instruction duration. Expected=%d, Got=%d",expected_cs_activate_time,cs_activate_time)); + end + if (cs_deactivate_time != expected_cs_deactivate_time) begin + `FATAL(("CS Delay Test FAILED: unexpected chip select deactivate instruction duration. Expected=%d, Got=%d",expected_cs_deactivate_time,cs_deactivate_time)); + end + `INFO(("CS Delay Test PASSED"), ADI_VERBOSITY_LOW); + endtask endprogram diff --git a/testbenches/ip/spi_engine/tests/test_slowdata.sv b/testbenches/ip/spi_engine/tests/test_slowdata.sv index bd946ef5..fd023ccb 100644 --- a/testbenches/ip/spi_engine/tests/test_slowdata.sv +++ b/testbenches/ip/spi_engine/tests/test_slowdata.sv @@ -36,18 +36,24 @@ // `include "utils.svh" +`include "axi_definitions.svh" +`include "axis_definitions.svh" -import axi_vip_pkg::*; +import logger_pkg::*; +import test_harness_env_pkg::*; +import spi_environment_pkg::*; import axi4stream_vip_pkg::*; import adi_regmap_pkg::*; import adi_regmap_clkgen_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; import adi_regmap_spi_engine_pkg::*; -import logger_pkg::*; -import spi_environment_pkg::*; import spi_engine_instr_pkg::*; import adi_spi_vip_pkg::*; +import axi_vip_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; //--------------------------------------------------------------------------- // SPI Engine configuration parameters @@ -59,535 +65,542 @@ program test_slowdata ( inout [(`NUM_OF_CS - 1):0] spi_engine_spi_cs, inout spi_engine_spi_clk, `ifdef DEF_ECHO_SCLK - inout spi_engine_echo_sclk, + inout spi_engine_echo_sclk, `endif inout [(`NUM_OF_SDI - 1):0] spi_engine_spi_sdi); -timeunit 1ns; -timeprecision 100ps; - -spi_environment env; - -// -------------------------- -// Wrapper function for AXI read verify -// -------------------------- -task axi_read_v( - input [31:0] raddr, - input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); -endtask - -task axi_read( - input [31:0] raddr, - output [31:0] data); - env.mng.RegRead32(raddr,data); -endtask - -// -------------------------- -// Wrapper function for AXI write -// -------------------------- -task axi_write( - input [31:0] waddr, - input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); -endtask - -// -------------------------- -// Wrapper function for SPI receive (from DUT) -// -------------------------- -task spi_receive( - output [`DATA_DLENGTH:0] data); - env.spi_seq.receive_data(data); -endtask - -// -------------------------- -// Wrapper function for SPI send (to DUT) -// -------------------------- -task spi_send( - input [`DATA_DLENGTH:0] data); - env.spi_seq.send_data(data); -endtask - -// -------------------------- -// Wrapper function for waiting for all SPI -// -------------------------- -task spi_wait_send(); - env.spi_seq.flush_send(); -endtask - - - -// -------------------------- -// Main procedure -// -------------------------- -initial begin - - //creating environment - env = new("SPI Engine Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `ifdef DEF_SDO_STREAMING - `TH.`SDO_SRC.inst.IF, - `endif - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - `TH.`SPI_S.inst.IF - ); - - setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.configure(); - - env.sys_reset(); - - env.run(); - - env.spi_seq.set_default_miso_data('h2AA55); - - // start sdo source (will wait for data enqueued) - `ifdef DEF_SDO_STREAMING - env.sdo_src_seq.start(); - `endif + timeunit 1ns; + timeprecision 100ps; + + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + spi_environment spi_env; - sanity_test(); + // -------------------------- + // Wrapper function for AXI read verify + // -------------------------- + task axi_read_v( + input [31:0] raddr, + input [31:0] vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + endtask - #100ns + task axi_read( + input [31:0] raddr, + output [31:0] data); + base_env.mng.sequencer.RegRead32(raddr,data); + endtask - fifo_init_test(); + // -------------------------- + // Wrapper function for AXI write + // -------------------------- + task axi_write( + input [31:0] waddr, + input [31:0] wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); + endtask - fifo_single_read_test(); + // -------------------------- + // Wrapper function for SPI receive (from DUT) + // -------------------------- + task spi_receive( + output [`DATA_DLENGTH:0] data); + spi_env.spi_agent.sequencer.receive_data(data); + endtask - fifo_double_write_test(); + // -------------------------- + // Wrapper function for SPI send (to DUT) + // -------------------------- + task spi_send( + input [`DATA_DLENGTH:0] data); + spi_env.spi_agent.sequencer.send_data(data); + endtask - fifo_double_read_test(); + // -------------------------- + // Wrapper function for waiting for all SPI + // -------------------------- + task spi_wait_send(); + spi_env.spi_agent.sequencer.flush_send(); + endtask - fifo_double_write_test(); - offload_spi_test(); + // -------------------------- + // Main procedure + // -------------------------- + initial begin - #100ns - `INFO(("Test Done"), ADI_VERBOSITY_NONE); + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + spi_env = new("SPI Engine Environment", + `ifdef DEF_SDO_STREAMING + `TH.`SDO_SRC.inst.IF, + `endif + `TH.`SPI_S.inst.IF.vif); - $finish; + setLoggerVerbosity(ADI_VERBOSITY_NONE); -end + base_env.start(); + spi_env.start(); -//--------------------------------------------------------------------------- -// Sanity test reg interface -//--------------------------------------------------------------------------- + base_env.sys_reset(); -task sanity_test(); - bit [31:0] pcore_version = (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_PATCH) - | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MINOR)<<8 - | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR)<<16; - //axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_VERSION), pcore_version); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); - axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); - `INFO(("Sanity Test Done"), ADI_VERBOSITY_LOW); -endtask + spi_env.configure(); -//--------------------------------------------------------------------------- -// SPI Engine generate transfer -//--------------------------------------------------------------------------- + spi_env.run(); -task generate_init_transfer_cmd( - input [7:0] sync_id); - // configure cs - if (`CS_ACTIVE_HIGH) begin - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF)); - end - // write cfg - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG); - // assert CSN - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFE)); - // write prescaler - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE); - // write dlen - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH); - // transfer data - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_WR); - // de-assert CSN - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFF)); - // SYNC command to generate interrupt - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_SYNC | sync_id)); - `INFO(("Transfer generation finished."), ADI_VERBOSITY_LOW); -endtask - -task generate_single_rtransfer_cmd( - input [7:0] sync_id); - // configure cs - if (`CS_ACTIVE_HIGH) begin - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF)); - end - // write cfg - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG); - // assert CSN - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFE)); - // write prescaler - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE); - // write dlen - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH); - // transfer data - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_RD & 16'hFF00)); - // de-assert CSN - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFF)); - // SYNC command to generate interrupt - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_SYNC | sync_id)); - `INFO(("Transfer generation finished."), ADI_VERBOSITY_LOW); -endtask - - -task generate_double_rtransfer_cmd( - input [7:0] sync_id); - // configure cs - if (`CS_ACTIVE_HIGH) begin - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF)); - end - // write cfg - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG); - // assert CSN - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFE)); - // write prescaler - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE); - // write dlen - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH); - // transfer data - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_RD & 16'hFF00)); - // transfer data - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_RD & 16'hFF00)); - // de-assert CSN - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFF)); - // SYNC command to generate interrupt - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_SYNC | sync_id)); - `INFO(("Transfer generation finished."), ADI_VERBOSITY_LOW); -endtask - -task generate_double_wtransfer_cmd( - input [7:0] sync_id); - // configure cs - if (`CS_ACTIVE_HIGH) begin - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF)); - end - // write cfg - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG); - // assert CSN - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFE)); - // write prescaler - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE); - // write dlen - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH); - // transfer data - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_WR & 16'hFF00)); - // transfer data - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_WR & 16'hFF00)); - // de-assert CSN - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFF)); - // SYNC command to generate interrupt - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_SYNC | sync_id)); - `INFO(("Transfer generation finished."), ADI_VERBOSITY_LOW); -endtask + spi_env.spi_agent.sequencer.set_default_miso_data('h2AA55); -//--------------------------------------------------------------------------- -// IRQ callback -//--------------------------------------------------------------------------- + // start sdo source (will wait for data enqueued) + `ifdef DEF_SDO_STREAMING + spi_env.sdo_src_agent.sequencer.start(); + `endif -reg [4:0] irq_pending = 0; -reg [7:0] sync_id = 0; + sanity_test(); -initial begin - forever begin - @(posedge spi_engine_irq); - // read pending IRQs + #100ns - axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); - // IRQ launched by Offload SYNC command - if (irq_pending & 5'b10000) begin - axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); - `INFO(("Offload SYNC %d IRQ. An offload transfer just finished.", sync_id), ADI_VERBOSITY_LOW); - end - // IRQ launched by SYNC command - if (irq_pending & 5'b01000) begin - axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); - `INFO(("SYNC %d IRQ. FIFO transfer just finished.", sync_id), ADI_VERBOSITY_LOW); - end - // IRQ launched by SDI FIFO - if (irq_pending & 5'b00100) begin - `INFO(("SDI FIFO IRQ."), ADI_VERBOSITY_LOW); - end - // IRQ launched by SDO FIFO - if (irq_pending & 5'b00010) begin - `INFO(("SDO FIFO IRQ."), ADI_VERBOSITY_LOW); - end - // IRQ launched by SDO FIFO - if (irq_pending & 5'b00001) begin - `INFO(("CMD FIFO IRQ."), ADI_VERBOSITY_LOW); - end - // Clear all pending IRQs - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); - end -end - -//--------------------------------------------------------------------------- -// SPI Engine SDO data -//--------------------------------------------------------------------------- + fifo_init_test(); -task sdo_stream_gen( - input [`DATA_DLENGTH:0] tx_data); - xil_axi4stream_data_byte data[(`DATA_WIDTH/8)-1:0]; - `ifdef DEF_SDO_STREAMING - for (int i = 0; i<(`DATA_WIDTH/8);i++) begin - data[i] = (tx_data & (8'hFF << 8*i)) >> 8*i; - env.sdo_src_seq.push_byte_for_stream(data[i]); - end - env.sdo_src_seq.add_xfer_descriptor((`DATA_WIDTH/8),0,0); - `endif -endtask + fifo_single_read_test(); -//--------------------------------------------------------------------------- -// Echo SCLK generation - we need this only if ECHO_SCLK is enabled -//--------------------------------------------------------------------------- -`ifdef DEF_ECHO_SCLK - assign #(`ECHO_SCLK_DELAY * 1ns) spi_engine_echo_sclk = spi_engine_spi_sclk; -`endif - -//--------------------------------------------------------------------------- -// FIFO SPI Test -//--------------------------------------------------------------------------- + fifo_double_write_test(); -bit [`DATA_DLENGTH-1:0] sdi_fifo_data [`NUM_OF_WORDS-1:0]= '{default:'0}; -bit [`DATA_DLENGTH-1:0] sdo_fifo_data [`NUM_OF_WORDS-1:0]= '{default:'0}; -bit [`DATA_DLENGTH-1:0] sdi_fifo_data_store [`NUM_OF_WORDS-1:0]; -bit [`DATA_DLENGTH-1:0] sdo_fifo_data_store [`NUM_OF_WORDS-1:0]; -bit [`DATA_DLENGTH-1:0] rx_data; -bit [`DATA_DLENGTH-1:0] tx_data; - -task fifo_init_test(); - // Start spi clk generator - axi_write (`SPI_ENGINE_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), - `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | - `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) - ); - - // Enable SPI Engine - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); - - // Set up the interrupts - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_MASK), - `SET_AXI_SPI_ENGINE_IRQ_MASK_SYNC_EVENT(1) | - `SET_AXI_SPI_ENGINE_IRQ_MASK_OFFLOAD_SYNC_ID_PENDING(1) - ); - - #100ns - - // send cmd before data - generate_init_transfer_cmd(1); - - // write sdo fifo - for (int i = 0; i<(`NUM_OF_WORDS) ; i=i+1) begin - tx_data = ((i%6) == 5) ? 8'hFE : 8'hFF; - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDO_FIFO), (tx_data));// << (`DATA_WIDTH - `DATA_DLENGTH))); - sdo_fifo_data_store[i] = tx_data; - end + fifo_double_read_test(); - `INFO(("Wait for SPI VIP receiving data"), ADI_VERBOSITY_LOW); - for (int i = 0; i<(`NUM_OF_WORDS) ; i=i+1) begin - spi_receive(sdo_fifo_data[i]); - end + fifo_double_write_test(); - if (sdo_fifo_data !== sdo_fifo_data_store) begin - `INFO(("sdo_fifo_data: %x; sdo_fifo_data_store %x", sdo_fifo_data, sdo_fifo_data_store), ADI_VERBOSITY_LOW); - `ERROR(("Fifo Write Test FAILED")); - end - `INFO(("Fifo Write Test PASSED"), ADI_VERBOSITY_LOW); -endtask + offload_spi_test(); -bit [`DATA_DLENGTH-1:0] sdo_2_fifo_data [2-1:0]= '{default:'0}; -bit [`DATA_DLENGTH-1:0] sdo_2_fifo_data_store [2-1:0]; -task fifo_double_write_test(); + #100ns - #100ns + spi_env.stop(); + base_env.stop(); - // send cmd before data - generate_double_wtransfer_cmd(1); + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish(); - // write sdo fifo - for (int i = 0; i<(2) ; i=i+1) begin - tx_data = $urandom; - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDO_FIFO), (tx_data));// << (`DATA_WIDTH - `DATA_DLENGTH))); - sdo_2_fifo_data_store[i] = tx_data; end - `INFO(("Wait for SPI VIP receiving data"), ADI_VERBOSITY_LOW); - for (int i = 0; i<(2) ; i=i+1) begin - spi_receive(sdo_2_fifo_data[i]); + //--------------------------------------------------------------------------- + // Sanity test reg interface + //--------------------------------------------------------------------------- + + task sanity_test(); + bit [31:0] pcore_version = (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_PATCH) + | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MINOR)<<8 + | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR)<<16; + //axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_VERSION), pcore_version); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); + axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); + `INFO(("Sanity Test Done"), ADI_VERBOSITY_LOW); + endtask + + //--------------------------------------------------------------------------- + // SPI Engine generate transfer + //--------------------------------------------------------------------------- + + task generate_init_transfer_cmd( + input [7:0] sync_id); + // configure cs + if (`CS_ACTIVE_HIGH) begin + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF)); + end + // write cfg + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG); + // assert CSN + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFE)); + // write prescaler + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE); + // write dlen + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH); + // transfer data + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_WR); + // de-assert CSN + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFF)); + // SYNC command to generate interrupt + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_SYNC | sync_id)); + `INFO(("Transfer generation finished."), ADI_VERBOSITY_LOW); + endtask + + task generate_single_rtransfer_cmd( + input [7:0] sync_id); + // configure cs + if (`CS_ACTIVE_HIGH) begin + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF)); + end + // write cfg + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG); + // assert CSN + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFE)); + // write prescaler + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE); + // write dlen + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH); + // transfer data + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_RD & 16'hFF00)); + // de-assert CSN + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFF)); + // SYNC command to generate interrupt + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_SYNC | sync_id)); + `INFO(("Transfer generation finished."), ADI_VERBOSITY_LOW); + endtask + + + task generate_double_rtransfer_cmd( + input [7:0] sync_id); + // configure cs + if (`CS_ACTIVE_HIGH) begin + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF)); + end + // write cfg + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG); + // assert CSN + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFE)); + // write prescaler + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE); + // write dlen + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH); + // transfer data + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_RD & 16'hFF00)); + // transfer data + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_RD & 16'hFF00)); + // de-assert CSN + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFF)); + // SYNC command to generate interrupt + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_SYNC | sync_id)); + `INFO(("Transfer generation finished."), ADI_VERBOSITY_LOW); + endtask + + task generate_double_wtransfer_cmd( + input [7:0] sync_id); + // configure cs + if (`CS_ACTIVE_HIGH) begin + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF)); + end + // write cfg + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG); + // assert CSN + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFE)); + // write prescaler + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE); + // write dlen + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH); + // transfer data + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_WR & 16'hFF00)); + // transfer data + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_WR & 16'hFF00)); + // de-assert CSN + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFF)); + // SYNC command to generate interrupt + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_SYNC | sync_id)); + `INFO(("Transfer generation finished."), ADI_VERBOSITY_LOW); + endtask + + //--------------------------------------------------------------------------- + // IRQ callback + //--------------------------------------------------------------------------- + + reg [4:0] irq_pending = 0; + reg [7:0] sync_id = 0; + + initial begin + forever begin + @(posedge spi_engine_irq); + // read pending IRQs + + axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); + // IRQ launched by Offload SYNC command + if (irq_pending & 5'b10000) begin + axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); + `INFO(("Offload SYNC %d IRQ. An offload transfer just finished.", sync_id), ADI_VERBOSITY_LOW); + end + // IRQ launched by SYNC command + if (irq_pending & 5'b01000) begin + axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); + `INFO(("SYNC %d IRQ. FIFO transfer just finished.", sync_id), ADI_VERBOSITY_LOW); + end + // IRQ launched by SDI FIFO + if (irq_pending & 5'b00100) begin + `INFO(("SDI FIFO IRQ."), ADI_VERBOSITY_LOW); + end + // IRQ launched by SDO FIFO + if (irq_pending & 5'b00010) begin + `INFO(("SDO FIFO IRQ."), ADI_VERBOSITY_LOW); + end + // IRQ launched by SDO FIFO + if (irq_pending & 5'b00001) begin + `INFO(("CMD FIFO IRQ."), ADI_VERBOSITY_LOW); + end + // Clear all pending IRQs + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); + end end - if (sdo_2_fifo_data !== sdo_2_fifo_data_store) begin - `INFO(("sdo_2_fifo_data: %x; sdo_2_fifo_data_store %x", sdo_2_fifo_data, sdo_2_fifo_data_store), ADI_VERBOSITY_LOW); - `ERROR(("Double Write Test FAILED")); - end - `INFO(("Double Write Test PASSED"), ADI_VERBOSITY_LOW); -endtask + //--------------------------------------------------------------------------- + // SPI Engine SDO data + //--------------------------------------------------------------------------- + + task sdo_stream_gen( + input [`DATA_DLENGTH:0] tx_data); + xil_axi4stream_data_byte data[(`DATA_WIDTH/8)-1:0]; + `ifdef DEF_SDO_STREAMING + for (int i = 0; i<(`DATA_WIDTH/8);i++) begin + data[i] = (tx_data & (8'hFF << 8*i)) >> 8*i; + spi_env.sdo_src_agent.sequencer.push_byte_for_stream(data[i]); + end + spi_env.sdo_src_agent.sequencer.add_xfer_descriptor_byte_count((`DATA_WIDTH/8),0,0); + `endif + endtask -bit [`DATA_DLENGTH-1:0] sdi_2_fifo_data [2-1:0]= '{default:'0}; -bit [`DATA_DLENGTH-1:0] sdi_2_fifo_data_store [2-1:0]; -bit [`DATA_DLENGTH-1:0] foo; -task fifo_double_read_test(); + //--------------------------------------------------------------------------- + // Echo SCLK generation - we need this only if ECHO_SCLK is enabled + //--------------------------------------------------------------------------- + `ifdef DEF_ECHO_SCLK + assign #(`ECHO_SCLK_DELAY * 1ns) spi_engine_echo_sclk = spi_engine_spi_sclk; + `endif - #100ns + //--------------------------------------------------------------------------- + // FIFO SPI Test + //--------------------------------------------------------------------------- + + bit [`DATA_DLENGTH-1:0] sdi_fifo_data [`NUM_OF_WORDS-1:0]= '{default:'0}; + bit [`DATA_DLENGTH-1:0] sdo_fifo_data [`NUM_OF_WORDS-1:0]= '{default:'0}; + bit [`DATA_DLENGTH-1:0] sdi_fifo_data_store [`NUM_OF_WORDS-1:0]; + bit [`DATA_DLENGTH-1:0] sdo_fifo_data_store [`NUM_OF_WORDS-1:0]; + bit [`DATA_DLENGTH-1:0] rx_data; + bit [`DATA_DLENGTH-1:0] tx_data; + + task fifo_init_test(); + // Start spi clk generator + axi_write (`SPI_ENGINE_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), + `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | + `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) + ); + + // Enable SPI Engine + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); + + // Set up the interrupts + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_MASK), + `SET_AXI_SPI_ENGINE_IRQ_MASK_SYNC_EVENT(1) | + `SET_AXI_SPI_ENGINE_IRQ_MASK_OFFLOAD_SYNC_ID_PENDING(1) + ); + + #100ns + + // send cmd before data + generate_init_transfer_cmd(1); + + // write sdo fifo + for (int i = 0; i<(`NUM_OF_WORDS) ; i=i+1) begin + tx_data = ((i%6) == 5) ? 8'hFE : 8'hFF; + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDO_FIFO), (tx_data));// << (`DATA_WIDTH - `DATA_DLENGTH))); + sdo_fifo_data_store[i] = tx_data; + end + `INFO(("Wait for SPI VIP receiving data"), ADI_VERBOSITY_LOW); + for (int i = 0; i<(`NUM_OF_WORDS) ; i=i+1) begin + spi_receive(sdo_fifo_data[i]); + end + if (sdo_fifo_data !== sdo_fifo_data_store) begin + `INFO(("sdo_fifo_data: %x; sdo_fifo_data_store %x", sdo_fifo_data, sdo_fifo_data_store), ADI_VERBOSITY_LOW); + `FATAL(("Fifo Write Test FAILED")); + end + `INFO(("Fifo Write Test PASSED"), ADI_VERBOSITY_LOW); + endtask - for (int i = 0; i<(2) ; i=i+1) begin - rx_data = $urandom; - spi_send(rx_data); - sdi_2_fifo_data_store[i] = rx_data; - end + bit [`DATA_DLENGTH-1:0] sdo_2_fifo_data [2-1:0]= '{default:'0}; + bit [`DATA_DLENGTH-1:0] sdo_2_fifo_data_store [2-1:0]; + task fifo_double_write_test(); - generate_double_rtransfer_cmd(1); + #100ns - `INFO(("Wait for SPI VIP data send"), ADI_VERBOSITY_LOW); - spi_wait_send(); - `INFO(("SPI sent"), ADI_VERBOSITY_LOW); + // send cmd before data + generate_double_wtransfer_cmd(1); - for (int i = 0; i<(2) ; i=i+1) begin - spi_receive(foo); // dummy tx, just for clearing the VIP queue - axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDI_FIFO), sdi_2_fifo_data[i]); - end + // write sdo fifo + for (int i = 0; i<(2) ; i=i+1) begin + tx_data = $urandom; + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDO_FIFO), (tx_data));// << (`DATA_WIDTH - `DATA_DLENGTH))); + sdo_2_fifo_data_store[i] = tx_data; + end - if (sdi_2_fifo_data !== sdi_2_fifo_data_store) begin - `INFO(("sdi_2_fifo_data: %x; sdi_2_fifo_data_store %x", sdi_2_fifo_data, sdi_2_fifo_data_store), ADI_VERBOSITY_LOW); - `ERROR(("Double Read Test FAILED")); - end - `INFO(("Double Read Test PASSED"), ADI_VERBOSITY_LOW); -endtask + `INFO(("Wait for SPI VIP receiving data"), ADI_VERBOSITY_LOW); + for (int i = 0; i<(2) ; i=i+1) begin + spi_receive(sdo_2_fifo_data[i]); + end -bit [`DATA_DLENGTH-1:0] sdi_1_fifo_data = '{default:'0}; -bit [`DATA_DLENGTH-1:0] sdi_1_fifo_data_store ; -task fifo_single_read_test(); + if (sdo_2_fifo_data !== sdo_2_fifo_data_store) begin + `INFO(("sdo_2_fifo_data: %x; sdo_2_fifo_data_store %x", sdo_2_fifo_data, sdo_2_fifo_data_store), ADI_VERBOSITY_LOW); + `FATAL(("Double Write Test FAILED")); + end + `INFO(("Double Write Test PASSED"), ADI_VERBOSITY_LOW); + endtask - #100ns + bit [`DATA_DLENGTH-1:0] sdi_2_fifo_data [2-1:0]= '{default:'0}; + bit [`DATA_DLENGTH-1:0] sdi_2_fifo_data_store [2-1:0]; + bit [`DATA_DLENGTH-1:0] foo; + task fifo_double_read_test(); - rx_data = $urandom; - spi_send(rx_data); - sdi_1_fifo_data_store = rx_data; + #100ns - generate_single_rtransfer_cmd(1); - `INFO(("Wait for SPI VIP data send"), ADI_VERBOSITY_LOW); - spi_wait_send(); - `INFO(("SPI sent"), ADI_VERBOSITY_LOW); - spi_receive(foo); // dummy tx, just for clearing the VIP queue - axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDI_FIFO), sdi_1_fifo_data); + for (int i = 0; i<(2) ; i=i+1) begin + rx_data = $urandom; + spi_send(rx_data); + sdi_2_fifo_data_store[i] = rx_data; + end - if (sdi_1_fifo_data !== sdi_1_fifo_data_store) begin - `INFO(("sdi_1_fifo_data: %x; sdi_1_fifo_data_store %x", sdi_1_fifo_data, sdi_1_fifo_data_store), ADI_VERBOSITY_LOW); - `ERROR(("Single Read Test FAILED")); - end - `INFO(("Single Read Test PASSED"), ADI_VERBOSITY_LOW); -endtask + generate_double_rtransfer_cmd(1); -//--------------------------------------------------------------------------- -// Offload SPI Test -//--------------------------------------------------------------------------- + `INFO(("Wait for SPI VIP data send"), ADI_VERBOSITY_LOW); + spi_wait_send(); + `INFO(("SPI sent"), ADI_VERBOSITY_LOW); -bit [`DATA_DLENGTH-1:0] sdi_read_data [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0] = '{default:'0}; -bit [`DATA_DLENGTH-1:0] sdo_write_data [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0] = '{default:'0}; -bit [`DATA_DLENGTH-1:0] sdi_read_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0]; -bit [`DATA_DLENGTH-1:0] sdo_write_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0]; -bit [`DATA_DLENGTH-1:0] rx_data; -bit [`DATA_DLENGTH-1:0] tx_data; - -task offload_spi_test(); - - // Config pwm - axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); // PWM_GEN reset in regmap (ACTIVE HIGH) - axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_PULSE_X_PERIOD), `SET_AXI_PWM_GEN_REG_PULSE_X_PERIOD_PULSE_X_PERIOD('d105)); // set PWM period - axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_LOAD_CONFIG(1)); // load AXI_PWM_GEN configuration - `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); - - //Configure DMA - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), - `SET_DMAC_FLAGS_TLAST(1) | - `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) - ); // Use TLAST - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - - // Configure the Offload module - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFE)); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_PRESCALE); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_DLENGTH); - if (`CS_ACTIVE_HIGH) begin - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_INV_MASK(8'hFF)); - end - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_WRD); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFF)); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_DLENGTH); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 2); + for (int i = 0; i<(2) ; i=i+1) begin + spi_receive(foo); // dummy tx, just for clearing the VIP queue + axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDI_FIFO), sdi_2_fifo_data[i]); + end + + if (sdi_2_fifo_data !== sdi_2_fifo_data_store) begin + `INFO(("sdi_2_fifo_data: %x; sdi_2_fifo_data_store %x", sdi_2_fifo_data, sdi_2_fifo_data_store), ADI_VERBOSITY_LOW); + `FATAL(("Double Read Test FAILED")); + end + `INFO(("Double Read Test PASSED"), ADI_VERBOSITY_LOW); + endtask + + bit [`DATA_DLENGTH-1:0] sdi_1_fifo_data = '{default:'0}; + bit [`DATA_DLENGTH-1:0] sdi_1_fifo_data_store ; + task fifo_single_read_test(); + + #100ns - // Enqueue transfers transfers to DUT - for (int i = 0; i<((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)) ; i=i+1) begin rx_data = $urandom; spi_send(rx_data); - sdi_read_data_store[i] = rx_data; - tx_data = $urandom; - `ifdef DEF_SDO_STREAMING - sdo_stream_gen(tx_data); - sdo_write_data_store[i] = tx_data; - `else - if (i<(`NUM_OF_WORDS)) begin - sdo_write_data_store[i] = tx_data; - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO), sdo_write_data_store[i]); - end else begin - sdo_write_data_store[i] = sdo_write_data_store[i%(`NUM_OF_WORDS)]; - end - `endif - end + sdi_1_fifo_data_store = rx_data; + + generate_single_rtransfer_cmd(1); + + `INFO(("Wait for SPI VIP data send"), ADI_VERBOSITY_LOW); + spi_wait_send(); + `INFO(("SPI sent"), ADI_VERBOSITY_LOW); + + spi_receive(foo); // dummy tx, just for clearing the VIP queue + axi_read (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDI_FIFO), sdi_1_fifo_data); - // Start the offload - #100ns - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(1)); - `INFO(("Offload started."), ADI_VERBOSITY_LOW); + if (sdi_1_fifo_data !== sdi_1_fifo_data_store) begin + `INFO(("sdi_1_fifo_data: %x; sdi_1_fifo_data_store %x", sdi_1_fifo_data, sdi_1_fifo_data_store), ADI_VERBOSITY_LOW); + `FATAL(("Single Read Test FAILED")); + end + `INFO(("Single Read Test PASSED"), ADI_VERBOSITY_LOW); + endtask + + //--------------------------------------------------------------------------- + // Offload SPI Test + //--------------------------------------------------------------------------- + + bit [`DATA_DLENGTH-1:0] sdi_read_data [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0] = '{default:'0}; + bit [`DATA_DLENGTH-1:0] sdo_write_data [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0] = '{default:'0}; + bit [`DATA_DLENGTH-1:0] sdi_read_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0]; + bit [`DATA_DLENGTH-1:0] sdo_write_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0]; + bit [`DATA_DLENGTH-1:0] rx_data; + bit [`DATA_DLENGTH-1:0] tx_data; + + task offload_spi_test(); + + // Config pwm + axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); // PWM_GEN reset in regmap (ACTIVE HIGH) + axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_PULSE_X_PERIOD), `SET_AXI_PWM_GEN_REG_PULSE_X_PERIOD_PULSE_X_PERIOD('d105)); // set PWM period + axi_write (`SPI_ENGINE_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_LOAD_CONFIG(1)); // load AXI_PWM_GEN configuration + `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); + + //Configure DMA + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), + `SET_DMAC_FLAGS_TLAST(1) | + `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) + ); // Use TLAST + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + + // Configure the Offload module + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFE)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_PRESCALE); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_DLENGTH); + if (`CS_ACTIVE_HIGH) begin + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_INV_MASK(8'hFF)); + end + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_WRD); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFF)); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_DLENGTH); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 2); + + // Enqueue transfers transfers to DUT + for (int i = 0; i<((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)) ; i=i+1) begin + rx_data = $urandom; + spi_send(rx_data); + sdi_read_data_store[i] = rx_data; + tx_data = $urandom; + `ifdef DEF_SDO_STREAMING + sdo_stream_gen(tx_data); + sdo_write_data_store[i] = tx_data; + `else + if (i<(`NUM_OF_WORDS)) begin + sdo_write_data_store[i] = tx_data; + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO), sdo_write_data_store[i]); + end else begin + sdo_write_data_store[i] = sdo_write_data_store[i%(`NUM_OF_WORDS)]; + end + `endif + end - spi_wait_send(); + // Start the offload + #100ns + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(1)); + `INFO(("Offload started."), ADI_VERBOSITY_LOW); - axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(0)); + spi_wait_send(); - `INFO(("Offload stopped."), ADI_VERBOSITY_LOW); + axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(0)); - #2000ns + `INFO(("Offload stopped."), ADI_VERBOSITY_LOW); - if (irq_pending == 'h0) begin - `ERROR(("IRQ Test FAILED")); - end else begin - `INFO(("IRQ Test PASSED"), ADI_VERBOSITY_LOW); - end + #2000ns - for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin - sdi_read_data[i] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); - if (sdi_read_data[i] != sdi_read_data_store[i]) begin - `INFO(("sdi_read_data[%d]: %x; sdi_read_data_store[%d]: %x", i, sdi_read_data[i], i, sdi_read_data_store[i]), ADI_VERBOSITY_LOW); - `ERROR(("Offload Read Test FAILED")); + if (irq_pending == 'h0) begin + `FATAL(("IRQ Test FAILED")); + end else begin + `INFO(("IRQ Test PASSED"), ADI_VERBOSITY_LOW); end - end - `INFO(("Offload Read Test PASSED"), ADI_VERBOSITY_LOW); - for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin - spi_receive(sdo_write_data[i]); - if (sdo_write_data[i] != sdo_write_data_store[i]) begin - `INFO(("sdo_write_data[%d]: %x; sdo_write_data_store[%d]: %x", i, sdo_write_data[i], i, sdo_write_data_store[i]), ADI_VERBOSITY_LOW); - `ERROR(("Offload Write Test FAILED")); + for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin + sdi_read_data[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); + if (sdi_read_data[i] != sdi_read_data_store[i]) begin + `INFO(("sdi_read_data[%d]: %x; sdi_read_data_store[%d]: %x", i, sdi_read_data[i], i, sdi_read_data_store[i]), ADI_VERBOSITY_LOW); + `FATAL(("Offload Read Test FAILED")); + end end - end - `INFO(("Offload Write Test PASSED"), ADI_VERBOSITY_LOW); -endtask + `INFO(("Offload Read Test PASSED"), ADI_VERBOSITY_LOW); + + for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin + spi_receive(sdo_write_data[i]); + if (sdo_write_data[i] != sdo_write_data_store[i]) begin + `INFO(("sdo_write_data[%d]: %x; sdo_write_data_store[%d]: %x", i, sdo_write_data[i], i, sdo_write_data_store[i]), ADI_VERBOSITY_LOW); + `FATAL(("Offload Write Test FAILED")); + end + end + `INFO(("Offload Write Test PASSED"), ADI_VERBOSITY_LOW); + endtask -endprogram \ No newline at end of file +endprogram diff --git a/testbenches/project/ad57xx/ad57xx_environment.sv b/testbenches/project/ad57xx/ad57xx_environment.sv index 3978ce52..e5da6dae 100644 --- a/testbenches/project/ad57xx/ad57xx_environment.sv +++ b/testbenches/project/ad57xx/ad57xx_environment.sv @@ -40,18 +40,13 @@ package ad57xx_environment_pkg; import logger_pkg::*; import adi_environment_pkg::*; - import s_spi_sequencer_pkg::*; import adi_spi_vip_pkg::*; - - import `PKGIFY(test_harness, spi_s_vip)::*; + import adi_spi_vip_if_base_pkg::*; class ad57xx_environment extends adi_environment; // Agents - adi_spi_agent #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_agent; - - // Sequencers - s_spi_sequencer #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_seq; + adi_spi_agent spi_agent; //============================================================================ // Constructor @@ -59,16 +54,13 @@ package ad57xx_environment_pkg; function new( input string name, - virtual interface spi_vip_if #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_s_vip_if); + adi_spi_vip_if_base spi_s_vip_if); super.new(name); // Creating the agents this.spi_agent = new("SPI VIP Agent", spi_s_vip_if, this); - // Creating the sequencers - this.spi_seq = new("SPI VIP Sequencer", this.spi_agent, this); - endfunction //============================================================================ diff --git a/testbenches/project/ad57xx/tests/test_program.sv b/testbenches/project/ad57xx/tests/test_program.sv index 18f27f53..dd564468 100644 --- a/testbenches/project/ad57xx/tests/test_program.sv +++ b/testbenches/project/ad57xx/tests/test_program.sv @@ -96,7 +96,7 @@ endtask // -------------------------- task spi_receive( output [`DATA_DLENGTH:0] data); - spi_env.spi_seq.receive_data(data); + spi_env.spi_agent.sequencer.receive_data(data); endtask // -------------------------- @@ -104,14 +104,14 @@ endtask // -------------------------- task spi_send( input [`DATA_DLENGTH:0] data); - spi_env.spi_seq.send_data(data); + spi_env.spi_agent.sequencer.send_data(data); endtask // -------------------------- // Wrapper function for waiting for all SPI // -------------------------- task spi_wait_send(); - spi_env.spi_seq.flush_send(); + spi_env.spi_agent.sequencer.flush_send(); endtask @@ -131,14 +131,14 @@ initial begin `TH.`DDR_AXI.inst.IF); spi_env = new("SPI Environment", - `TH.`SPI_S.inst.IF); + `TH.`SPI_S.inst.IF.vif); setLoggerVerbosity(ADI_VERBOSITY_NONE); base_env.start(); spi_env.start(); - spi_env.spi_seq.set_default_miso_data('h0); + spi_env.spi_agent.sequencer.set_default_miso_data('h0); base_env.sys_reset(); From a888f41a27d7308350698f68904a5003ac033028 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Tue, 11 Feb 2025 11:50:33 +0200 Subject: [PATCH 24/37] General updates: Updated VIP clocking and reset calls Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/axi_tdd/tests/test_program.sv | 4 +-- .../ip/data_offload/tests/test_program.sv | 34 +++++++++---------- .../ip/data_offload_2/tests/test_program.sv | 28 +++++++-------- .../data_offload_2/tests/test_program_sync.sv | 24 ++++++------- .../ip/dma_flock/tests/test_program.sv | 8 ++--- .../tests/test_program_frame_delay.sv | 10 +++--- .../ip/dma_loopback/tests/test_program.sv | 4 +-- .../ip/dma_sg/tests/test_program_1d.sv | 1 + .../ip/dma_sg/tests/test_program_2d.sv | 1 + .../ip/dma_sg/tests/test_program_tr_queue.sv | 1 + testbenches/ip/hbm/tests/test_program.sv | 17 +++++----- .../ip/i3c_controller/tests/test_program.sv | 3 +- .../ip/jesd_loopback/tests/test_program.sv | 18 +++++----- .../jesd_loopback_64b/tests/test_program.sv | 27 ++++++++++----- .../ip/spi_engine/tests/test_sleep_delay.sv | 3 +- testbenches/ip/util_axis_fifo/environment.sv | 3 ++ .../ip/util_axis_fifo_asym/environment.sv | 3 ++ .../project/ad7606x/tests/test_program_6ch.sv | 2 ++ .../project/ad7606x/tests/test_program_8ch.sv | 2 ++ .../project/ad7606x/tests/test_program_si.sv | 2 ++ .../project/ad9083/tests/test_program.sv | 15 +++++--- .../ad_quadmxfe1_ebz/tests/test_dma.sv | 17 ++++++---- .../ad_quadmxfe1_ebz/tests/test_program.sv | 15 +++++--- .../tests/test_program_64b66b.sv | 13 ++++--- .../project/adrv9001/tests/test_program.sv | 6 ++-- .../project/adrv9009/tests/test_program.sv | 19 +++++++---- .../project/fmcomms2/tests/test_program.sv | 3 +- .../project/mxfe/tests/test_program.sv | 10 ++++-- .../project/pluto/tests/test_program.sv | 3 +- 29 files changed, 176 insertions(+), 120 deletions(-) diff --git a/testbenches/ip/axi_tdd/tests/test_program.sv b/testbenches/ip/axi_tdd/tests/test_program.sv index a27562f4..67cafea4 100644 --- a/testbenches/ip/axi_tdd/tests/test_program.sv +++ b/testbenches/ip/axi_tdd/tests/test_program.sv @@ -569,12 +569,12 @@ program test_program; task start_clocks(); - `TH.`DEVICE_CLK.inst.IF.start_clock; + `TH.`DEVICE_CLK.inst.IF.start_clock(); endtask task stop_clocks(); - `TH.`DEVICE_CLK.inst.IF.stop_clock; + `TH.`DEVICE_CLK.inst.IF.stop_clock(); endtask diff --git a/testbenches/ip/data_offload/tests/test_program.sv b/testbenches/ip/data_offload/tests/test_program.sv index 152fb9f1..5c511b16 100644 --- a/testbenches/ip/data_offload/tests/test_program.sv +++ b/testbenches/ip/data_offload/tests/test_program.sv @@ -127,7 +127,7 @@ module test_program(); setLoggerVerbosity(ADI_VERBOSITY_NONE); - `TH.`PLDDR_RST.inst.IF.assert_reset; + `TH.`PLDDR_RST.inst.IF.assert_reset(); #1; start_clocks(); @@ -174,33 +174,33 @@ module test_program(); task start_clocks(); #1 - `TH.`SRC_CLK.inst.IF.start_clock; + `TH.`SRC_CLK.inst.IF.start_clock(); #1 - `TH.`DST_CLK.inst.IF.start_clock; + `TH.`DST_CLK.inst.IF.start_clock(); #1 - `TH.`SYS_CLK.inst.IF.start_clock; + `TH.`SYS_CLK.inst.IF.start_clock(); #1 - `TH.`PLDDR_CLK.inst.IF.start_clock; + `TH.`PLDDR_CLK.inst.IF.start_clock(); endtask task stop_clocks(); - `TH.`SRC_CLK.inst.IF.stop_clock; - `TH.`DST_CLK.inst.IF.stop_clock; - `TH.`SYS_CLK.inst.IF.stop_clock; - `TH.`PLDDR_CLK.inst.IF.stop_clock; + `TH.`SRC_CLK.inst.IF.stop_clock(); + `TH.`DST_CLK.inst.IF.stop_clock(); + `TH.`SYS_CLK.inst.IF.stop_clock(); + `TH.`PLDDR_CLK.inst.IF.stop_clock(); endtask task sys_reset(); - `TH.`SRC_RST.inst.IF.assert_reset; - `TH.`DST_RST.inst.IF.assert_reset; - `TH.`SYS_RST.inst.IF.assert_reset; - `TH.`PLDDR_RST.inst.IF.assert_reset; + `TH.`SRC_RST.inst.IF.assert_reset(); + `TH.`DST_RST.inst.IF.assert_reset(); + `TH.`SYS_RST.inst.IF.assert_reset(); + `TH.`PLDDR_RST.inst.IF.assert_reset(); #500 - `TH.`SRC_RST.inst.IF.deassert_reset; - `TH.`DST_RST.inst.IF.deassert_reset; - `TH.`SYS_RST.inst.IF.deassert_reset; - `TH.`PLDDR_RST.inst.IF.deassert_reset; + `TH.`SRC_RST.inst.IF.deassert_reset(); + `TH.`DST_RST.inst.IF.deassert_reset(); + `TH.`SYS_RST.inst.IF.deassert_reset(); + `TH.`PLDDR_RST.inst.IF.deassert_reset(); endtask task systemBringUp(); diff --git a/testbenches/ip/data_offload_2/tests/test_program.sv b/testbenches/ip/data_offload_2/tests/test_program.sv index 29ea8db1..cb05ee0a 100644 --- a/testbenches/ip/data_offload_2/tests/test_program.sv +++ b/testbenches/ip/data_offload_2/tests/test_program.sv @@ -152,31 +152,31 @@ module test_program( task start_clocks(); #1 - `TH.`SRC_CLK.inst.IF.start_clock; + `TH.`SRC_CLK.inst.IF.start_clock(); #1 - `TH.`DST_CLK.inst.IF.start_clock; + `TH.`DST_CLK.inst.IF.start_clock(); #1 - `TH.`SYS_CLK.inst.IF.start_clock; + `TH.`SYS_CLK.inst.IF.start_clock(); #1 - `TH.`MEM_CLK.inst.IF.start_clock; + `TH.`MEM_CLK.inst.IF.start_clock(); endtask task stop_clocks(); - `TH.`SRC_CLK.inst.IF.stop_clock; - `TH.`DST_CLK.inst.IF.stop_clock; - `TH.`SYS_CLK.inst.IF.stop_clock; - `TH.`MEM_CLK.inst.IF.stop_clock; + `TH.`SRC_CLK.inst.IF.stop_clock(); + `TH.`DST_CLK.inst.IF.stop_clock(); + `TH.`SYS_CLK.inst.IF.stop_clock(); + `TH.`MEM_CLK.inst.IF.stop_clock(); endtask task sys_reset(); - `TH.`SRC_RST.inst.IF.assert_reset; - `TH.`DST_RST.inst.IF.assert_reset; - `TH.`SYS_RST.inst.IF.assert_reset; + `TH.`SRC_RST.inst.IF.assert_reset(); + `TH.`DST_RST.inst.IF.assert_reset(); + `TH.`SYS_RST.inst.IF.assert_reset(); #500 - `TH.`SRC_RST.inst.IF.deassert_reset; - `TH.`DST_RST.inst.IF.deassert_reset; - `TH.`SYS_RST.inst.IF.deassert_reset; + `TH.`SRC_RST.inst.IF.deassert_reset(); + `TH.`DST_RST.inst.IF.deassert_reset(); + `TH.`SYS_RST.inst.IF.deassert_reset(); mem_rst_n = 1'b1; endtask diff --git a/testbenches/ip/data_offload_2/tests/test_program_sync.sv b/testbenches/ip/data_offload_2/tests/test_program_sync.sv index 4ce9c4f9..d802dddd 100644 --- a/testbenches/ip/data_offload_2/tests/test_program_sync.sv +++ b/testbenches/ip/data_offload_2/tests/test_program_sync.sv @@ -163,28 +163,28 @@ module test_program_sync ( task start_clocks(); #1 - `TH.`SRC_CLK.inst.IF.start_clock; + `TH.`SRC_CLK.inst.IF.start_clock(); #1 - `TH.`DST_CLK.inst.IF.start_clock; + `TH.`DST_CLK.inst.IF.start_clock(); #1 - `TH.`SYS_CLK.inst.IF.start_clock; + `TH.`SYS_CLK.inst.IF.start_clock(); endtask task stop_clocks(); - `TH.`SRC_CLK.inst.IF.stop_clock; - `TH.`DST_CLK.inst.IF.stop_clock; - `TH.`SYS_CLK.inst.IF.stop_clock; + `TH.`SRC_CLK.inst.IF.stop_clock(); + `TH.`DST_CLK.inst.IF.stop_clock(); + `TH.`SYS_CLK.inst.IF.stop_clock(); endtask task sys_reset(); - `TH.`SRC_RST.inst.IF.assert_reset; - `TH.`DST_RST.inst.IF.assert_reset; - `TH.`SYS_RST.inst.IF.assert_reset; + `TH.`SRC_RST.inst.IF.assert_reset(); + `TH.`DST_RST.inst.IF.assert_reset(); + `TH.`SYS_RST.inst.IF.assert_reset(); #500 - `TH.`SRC_RST.inst.IF.deassert_reset; - `TH.`DST_RST.inst.IF.deassert_reset; - `TH.`SYS_RST.inst.IF.deassert_reset; + `TH.`SRC_RST.inst.IF.deassert_reset(); + `TH.`DST_RST.inst.IF.deassert_reset(); + `TH.`SYS_RST.inst.IF.deassert_reset(); endtask task systemBringUp(); diff --git a/testbenches/ip/dma_flock/tests/test_program.sv b/testbenches/ip/dma_flock/tests/test_program.sv index a0a7b268..4370cb11 100644 --- a/testbenches/ip/dma_flock/tests/test_program.sv +++ b/testbenches/ip/dma_flock/tests/test_program.sv @@ -283,15 +283,15 @@ program test_program; set_dst_clock(100000000); set_ddr_clock(600000000); - `TH.`SRC_CLK.inst.IF.start_clock; - `TH.`DST_CLK.inst.IF.start_clock; + `TH.`SRC_CLK.inst.IF.start_clock(); + `TH.`DST_CLK.inst.IF.start_clock(); #100ns; endtask // Stop all clocks task stop_clocks(); - `TH.`SRC_CLK.inst.IF.stop_clock; - `TH.`DST_CLK.inst.IF.stop_clock; + `TH.`SRC_CLK.inst.IF.stop_clock(); + `TH.`DST_CLK.inst.IF.stop_clock(); endtask // Assert external sync for one clock cycle diff --git a/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv b/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv index d25cf0cd..6595545f 100644 --- a/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv +++ b/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv @@ -159,8 +159,8 @@ program test_program_frame_delay; `ERROR(("Both DMACs must be set in autorun mode.")); end - stop_clocks(); base_env.stop(); + stop_clocks(); `INFO(("Testbench done!"), ADI_VERBOSITY_NONE); $finish(); @@ -337,15 +337,15 @@ program test_program_frame_delay; set_dst_clock(100000000); set_ddr_clock(500000000); - `TH.`SRC_CLK.inst.IF.start_clock; - `TH.`DST_CLK.inst.IF.start_clock; + `TH.`SRC_CLK.inst.IF.start_clock(); + `TH.`DST_CLK.inst.IF.start_clock(); #100ns; endtask // Stop all clocks task stop_clocks(); - `TH.`SRC_CLK.inst.IF.stop_clock; - `TH.`DST_CLK.inst.IF.stop_clock; + `TH.`SRC_CLK.inst.IF.stop_clock(); + `TH.`DST_CLK.inst.IF.stop_clock(); endtask // Assert external sync for one clock cycle diff --git a/testbenches/ip/dma_loopback/tests/test_program.sv b/testbenches/ip/dma_loopback/tests/test_program.sv index 3201e808..d8c01de1 100644 --- a/testbenches/ip/dma_loopback/tests/test_program.sv +++ b/testbenches/ip/dma_loopback/tests/test_program.sv @@ -161,11 +161,11 @@ program test_program; endtask task start_clocks; - `TH.`DEVICE_CLK.inst.IF.start_clock; + `TH.`DEVICE_CLK.inst.IF.start_clock(); endtask task stop_clocks; - `TH.`DEVICE_CLK.inst.IF.stop_clock; + `TH.`DEVICE_CLK.inst.IF.stop_clock(); endtask endprogram diff --git a/testbenches/ip/dma_sg/tests/test_program_1d.sv b/testbenches/ip/dma_sg/tests/test_program_1d.sv index b3d7bbf7..54aaac2e 100644 --- a/testbenches/ip/dma_sg/tests/test_program_1d.sv +++ b/testbenches/ip/dma_sg/tests/test_program_1d.sv @@ -148,6 +148,7 @@ program test_program_1d; ); base_env.stop(); + `TH.`DEVICE_CLK.inst.IF.stop_clock(); `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/ip/dma_sg/tests/test_program_2d.sv b/testbenches/ip/dma_sg/tests/test_program_2d.sv index f225caf6..4b898d98 100644 --- a/testbenches/ip/dma_sg/tests/test_program_2d.sv +++ b/testbenches/ip/dma_sg/tests/test_program_2d.sv @@ -142,6 +142,7 @@ program test_program_2d; ); base_env.stop(); + `TH.`DEVICE_CLK.inst.IF.stop_clock(); `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv b/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv index ba5c8c34..791ea803 100644 --- a/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv +++ b/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv @@ -154,6 +154,7 @@ program test_program_tr_queue; ); base_env.stop(); + `TH.`DEVICE_CLK.inst.IF.stop_clock(); `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/ip/hbm/tests/test_program.sv b/testbenches/ip/hbm/tests/test_program.sv index 1314ab12..2382b674 100644 --- a/testbenches/ip/hbm/tests/test_program.sv +++ b/testbenches/ip/hbm/tests/test_program.sv @@ -70,9 +70,7 @@ program test_program; setLoggerVerbosity(ADI_VERBOSITY_NONE); base_env.start(); - - `TH.`HBM_CLK.inst.IF.start_clock; - + `TH.`HBM_CLK.inst.IF.start_clock(); base_env.sys_reset(); // // ------------------------------------------------------- @@ -97,12 +95,13 @@ program test_program; // .dest_addr(`DDR_BASE+'h2000), // .length('h1000) // ); -// -// base_env.stop(); -// -// `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); -// $finish(); -// + + base_env.stop(); + `TH.`HBM_CLK.inst.IF.stop_clock(); + + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); + $finish(); + end // task do_transfer(bit [31:0] src_addr, diff --git a/testbenches/ip/i3c_controller/tests/test_program.sv b/testbenches/ip/i3c_controller/tests/test_program.sv index 21d7a395..9914da5f 100755 --- a/testbenches/ip/i3c_controller/tests/test_program.sv +++ b/testbenches/ip/i3c_controller/tests/test_program.sv @@ -291,8 +291,7 @@ initial begin base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - - $finish; + $finish(); end diff --git a/testbenches/ip/jesd_loopback/tests/test_program.sv b/testbenches/ip/jesd_loopback/tests/test_program.sv index fcec78de..173237e3 100644 --- a/testbenches/ip/jesd_loopback/tests/test_program.sv +++ b/testbenches/ip/jesd_loopback/tests/test_program.sv @@ -118,9 +118,9 @@ program test_program; `TH.`DEVICE_CLK.inst.IF.set_clk_frq(.user_frequency(rx_ll.calc_device_clk())); `TH.`SYSREF_CLK.inst.IF.set_clk_frq(.user_frequency(rx_ll.calc_sysref_clk())); - `TH.`REF_CLK.inst.IF.start_clock; - `TH.`DEVICE_CLK.inst.IF.start_clock; - `TH.`SYSREF_CLK.inst.IF.start_clock; + `TH.`REF_CLK.inst.IF.start_clock(); + `TH.`DEVICE_CLK.inst.IF.start_clock(); + `TH.`SYSREF_CLK.inst.IF.start_clock(); rx_xcvr.setup_clocks(lane_rate, `REF_CLK_RATE*1000000); @@ -145,13 +145,13 @@ program test_program; // TPL SYNC control test // ======================= arm_disarm_test(); - - - `INFO(("======================="), ADI_VERBOSITY_LOW); - `INFO((" TB DONE "), ADI_VERBOSITY_LOW); - `INFO(("======================="), ADI_VERBOSITY_LOW); - + base_env.stop(); + `TH.`REF_CLK.inst.IF.stop_clock(); + `TH.`DEVICE_CLK.inst.IF.stop_clock(); + `TH.`SYSREF_CLK.inst.IF.stop_clock(); + + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); end diff --git a/testbenches/ip/jesd_loopback_64b/tests/test_program.sv b/testbenches/ip/jesd_loopback_64b/tests/test_program.sv index c93f33ce..7f817687 100644 --- a/testbenches/ip/jesd_loopback_64b/tests/test_program.sv +++ b/testbenches/ip/jesd_loopback_64b/tests/test_program.sv @@ -81,9 +81,9 @@ program test_program; base_env.start(); base_env.sys_reset(); - `TH.`SYS_CLK.inst.IF.start_clock; - `TH.`DMA_CLK.inst.IF.start_clock; - `TH.`DDR_CLK.inst.IF.start_clock; + `TH.`SYS_CLK.inst.IF.start_clock(); + `TH.`DMA_CLK.inst.IF.start_clock(); + `TH.`DDR_CLK.inst.IF.start_clock(); link_clk_freq_khz = lane_rate_khz/66; data_path_width = 8; @@ -95,10 +95,10 @@ program test_program; `TH.`DEVICE_CLK.inst.IF.set_clk_frq(.user_frequency(device_clk_freq_khz*1000)); `TH.`SYSREF_CLK.inst.IF.set_clk_frq(.user_frequency(sysref_freq_khz*1000)); - `TH.`REF_CLK.inst.IF.start_clock; - `TH.`DRP_CLK.inst.IF.start_clock; - `TH.`DEVICE_CLK.inst.IF.start_clock; - `TH.`SYSREF_CLK.inst.IF.start_clock; + `TH.`REF_CLK.inst.IF.start_clock(); + `TH.`DRP_CLK.inst.IF.start_clock(); + `TH.`DEVICE_CLK.inst.IF.start_clock(); + `TH.`SYSREF_CLK.inst.IF.start_clock(); for (int i = 0; i < `JESD_M; i++) begin if (use_dds) begin @@ -199,10 +199,19 @@ program test_program; // Read status back base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_STATUS), `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); - - `INFO(("Test Done"), ADI_VERBOSITY_NONE); base_env.stop(); + + `TH.`SYS_CLK.inst.IF.stop_clock(); + `TH.`DMA_CLK.inst.IF.stop_clock(); + `TH.`DDR_CLK.inst.IF.stop_clock(); + + `TH.`REF_CLK.inst.IF.stop_clock(); + `TH.`DRP_CLK.inst.IF.stop_clock(); + `TH.`DEVICE_CLK.inst.IF.stop_clock(); + `TH.`SYSREF_CLK.inst.IF.stop_clock(); + + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); end diff --git a/testbenches/ip/spi_engine/tests/test_sleep_delay.sv b/testbenches/ip/spi_engine/tests/test_sleep_delay.sv index b2b4f846..c185d788 100644 --- a/testbenches/ip/spi_engine/tests/test_sleep_delay.sv +++ b/testbenches/ip/spi_engine/tests/test_sleep_delay.sv @@ -172,8 +172,7 @@ program test_sleep_delay ( base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - - $finish; + $finish(); end diff --git a/testbenches/ip/util_axis_fifo/environment.sv b/testbenches/ip/util_axis_fifo/environment.sv index be53ef02..41412bea 100644 --- a/testbenches/ip/util_axis_fifo/environment.sv +++ b/testbenches/ip/util_axis_fifo/environment.sv @@ -136,6 +136,9 @@ package environment_pkg; // Stop subroutine //============================================================================ task stop(); + this.input_clk_vip_if.stop_clock(); + this.output_clk_vip_if.stop_clock(); + this.input_axis_agent.stop(); this.output_axis_agent.stop(); endtask diff --git a/testbenches/ip/util_axis_fifo_asym/environment.sv b/testbenches/ip/util_axis_fifo_asym/environment.sv index 9da1f018..40e014ed 100644 --- a/testbenches/ip/util_axis_fifo_asym/environment.sv +++ b/testbenches/ip/util_axis_fifo_asym/environment.sv @@ -136,6 +136,9 @@ package environment_pkg; // Stop subroutine //============================================================================ task stop(); + this.input_clk_vip_if.stop_clock(); + this.output_clk_vip_if.stop_clock(); + this.input_axis_agent.stop(); this.output_axis_agent.stop(); endtask diff --git a/testbenches/project/ad7606x/tests/test_program_6ch.sv b/testbenches/project/ad7606x/tests/test_program_6ch.sv index 140783da..df0266d1 100755 --- a/testbenches/project/ad7606x/tests/test_program_6ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_6ch.sv @@ -138,6 +138,8 @@ program test_program_6ch ( #100 db_transmission_test(); + base_env.stop(); + `INFO(("Test Done"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/project/ad7606x/tests/test_program_8ch.sv b/testbenches/project/ad7606x/tests/test_program_8ch.sv index a3eec321..98deb30a 100755 --- a/testbenches/project/ad7606x/tests/test_program_8ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_8ch.sv @@ -140,6 +140,8 @@ program test_program_8ch ( #100 db_transmission_test(); + base_env.stop(); + `INFO(("Test Done"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/project/ad7606x/tests/test_program_si.sv b/testbenches/project/ad7606x/tests/test_program_si.sv index 341c6a0f..494b5524 100755 --- a/testbenches/project/ad7606x/tests/test_program_si.sv +++ b/testbenches/project/ad7606x/tests/test_program_si.sv @@ -161,6 +161,8 @@ program test_program_si ( offload_spi_test(); + base_env.stop(); + `INFO(("Test Done"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/project/ad9083/tests/test_program.sv b/testbenches/project/ad9083/tests/test_program.sv index 530dce4d..400cd195 100644 --- a/testbenches/project/ad9083/tests/test_program.sv +++ b/testbenches/project/ad9083/tests/test_program.sv @@ -95,10 +95,10 @@ program test_program; `TH.`DEVICE_CLK.inst.IF.set_clk_frq(.user_frequency(device_clk_freq)); `TH.`SYSREF_CLK.inst.IF.set_clk_frq(.user_frequency(sysref_freq)); - `TH.`DRP_CLK.inst.IF.start_clock; - `TH.`REF_CLK.inst.IF.start_clock; - `TH.`DEVICE_CLK.inst.IF.start_clock; - `TH.`SYSREF_CLK.inst.IF.start_clock; + `TH.`DRP_CLK.inst.IF.start_clock(); + `TH.`REF_CLK.inst.IF.start_clock(); + `TH.`DEVICE_CLK.inst.IF.start_clock(); + `TH.`SYSREF_CLK.inst.IF.start_clock(); base_env.sys_reset(); @@ -372,9 +372,14 @@ program test_program; .step (1), .max_sample(496) ); - + base_env.stop(); + `TH.`DRP_CLK.inst.IF.stop_clock(); + `TH.`REF_CLK.inst.IF.stop_clock(); + `TH.`DEVICE_CLK.inst.IF.stop_clock(); + `TH.`SYSREF_CLK.inst.IF.stop_clock(); + `INFO(("Test Done"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv b/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv index d7a66cc2..d64bde4c 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv @@ -108,16 +108,16 @@ program test_dma; `TH.`DEVICE_CLK.inst.IF.set_clk_frq(.user_frequency(device_clk_freq)); `TH.`SYSREF_CLK.inst.IF.set_clk_frq(.user_frequency(sysref_freq)); - `TH.`DRP_CLK.inst.IF.start_clock; - `TH.`REF_CLK.inst.IF.start_clock; - `TH.`DEVICE_CLK.inst.IF.start_clock; - `TH.`SYSREF_CLK.inst.IF.start_clock; + `TH.`DRP_CLK.inst.IF.start_clock(); + `TH.`REF_CLK.inst.IF.start_clock(); + `TH.`DEVICE_CLK.inst.IF.start_clock(); + `TH.`SYSREF_CLK.inst.IF.start_clock(); //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; + `TH.`SYS_RST.inst.IF.assert_reset(); #100 - `TH.`SYS_RST.inst.IF.deassert_reset; + `TH.`SYS_RST.inst.IF.deassert_reset(); #1us; @@ -280,6 +280,11 @@ program test_dma; #2us; base_env.stop(); + + `TH.`DRP_CLK.inst.IF.stop_clock(); + `TH.`REF_CLK.inst.IF.stop_clock(); + `TH.`DEVICE_CLK.inst.IF.stop_clock(); + `TH.`SYSREF_CLK.inst.IF.stop_clock(); `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv index ba9ffd3c..2f865d3c 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv @@ -112,10 +112,10 @@ program test_program; `TH.`DEVICE_CLK.inst.IF.set_clk_frq(.user_frequency(rx_ll.calc_device_clk())); `TH.`SYSREF_CLK.inst.IF.set_clk_frq(.user_frequency(rx_ll.calc_sysref_clk())); - `TH.`REF_CLK.inst.IF.start_clock; - `TH.`DEVICE_CLK.inst.IF.start_clock; - `TH.`SYSREF_CLK.inst.IF.start_clock; - `TH.`DRP_CLK.inst.IF.start_clock; + `TH.`REF_CLK.inst.IF.start_clock(); + `TH.`DEVICE_CLK.inst.IF.start_clock(); + `TH.`SYSREF_CLK.inst.IF.start_clock(); + `TH.`DRP_CLK.inst.IF.start_clock(); if (`JESD_MODE != "64B66B") begin rx_xcvr.setup_clocks(lane_rate, `REF_CLK_RATE*1000000); @@ -141,8 +141,13 @@ program test_program; // JESD LINK TEST - DMA - EXT_SYNC // ======================= jesd_link_test_ext_sync(0); - + base_env.stop(); + + `TH.`DRP_CLK.inst.IF.stop_clock(); + `TH.`REF_CLK.inst.IF.stop_clock(); + `TH.`DEVICE_CLK.inst.IF.stop_clock(); + `TH.`SYSREF_CLK.inst.IF.stop_clock(); `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv index 661b9c70..da8b62e0 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv @@ -71,10 +71,10 @@ program test_program_64b66b; `TH.`MNG_AXI.inst.IF, `TH.`DDR_AXI.inst.IF); - `TH.`DEVICE_CLK.inst.IF.start_clock; - `TH.`REF_CLK.inst.IF.start_clock; - `TH.`DRP_CLK.inst.IF.start_clock; - `TH.`SYSREF_CLK.inst.IF.start_clock; + `TH.`DEVICE_CLK.inst.IF.start_clock(); + `TH.`REF_CLK.inst.IF.start_clock(); + `TH.`DRP_CLK.inst.IF.start_clock(); + `TH.`SYSREF_CLK.inst.IF.start_clock(); setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -306,6 +306,11 @@ program test_program_64b66b; base_env.stop(); + `TH.`DRP_CLK.inst.IF.stop_clock(); + `TH.`REF_CLK.inst.IF.stop_clock(); + `TH.`DEVICE_CLK.inst.IF.stop_clock(); + `TH.`SYSREF_CLK.inst.IF.stop_clock(); + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/project/adrv9001/tests/test_program.sv b/testbenches/project/adrv9001/tests/test_program.sv index 296d9629..c53081a6 100644 --- a/testbenches/project/adrv9001/tests/test_program.sv +++ b/testbenches/project/adrv9001/tests/test_program.sv @@ -152,7 +152,7 @@ program test_program; //set source synchronous interface clock frequency `TH.`SSI_CLK.inst.IF.set_clk_frq(.user_frequency(80000000)); - `TH.`SSI_CLK.inst.IF.start_clock; + `TH.`SSI_CLK.inst.IF.start_clock(); base_env.sys_reset(); @@ -194,8 +194,10 @@ program test_program; `SET_ADC_CHANNEL_REG_CHAN_CNTRL_3_ADC_DATA_SEL(1)); dma_test_ch2(); end - + base_env.stop(); + + `TH.`SSI_CLK.inst.IF.stop_clock(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/project/adrv9009/tests/test_program.sv b/testbenches/project/adrv9009/tests/test_program.sv index 6804367b..dce37aae 100755 --- a/testbenches/project/adrv9009/tests/test_program.sv +++ b/testbenches/project/adrv9009/tests/test_program.sv @@ -212,12 +212,12 @@ program test_program; `TH.`SYSREF_CLK.inst.IF.set_clk_frq(.user_frequency(common_sysref_clk)); - `TH.`REF_CLK.inst.IF.start_clock; - `TH.`RX_DEVICE_CLK.inst.IF.start_clock; - `TH.`TX_DEVICE_CLK.inst.IF.start_clock; - `TH.`TX_LINK_CLK.inst.IF.start_clock; - `TH.`TX_OS_DEVICE_CLK.inst.IF.start_clock; - `TH.`SYSREF_CLK.inst.IF.start_clock; + `TH.`REF_CLK.inst.IF.start_clock(); + `TH.`RX_DEVICE_CLK.inst.IF.start_clock(); + `TH.`TX_DEVICE_CLK.inst.IF.start_clock(); + `TH.`TX_LINK_CLK.inst.IF.start_clock(); + `TH.`TX_OS_DEVICE_CLK.inst.IF.start_clock(); + `TH.`SYSREF_CLK.inst.IF.start_clock(); ex_rx_xcvr.setup_clocks(lane_rate, `REF_CLK_RATE*1000000); @@ -243,6 +243,13 @@ program test_program; base_env.stop(); + `TH.`REF_CLK.inst.IF.stop_clock(); + `TH.`RX_DEVICE_CLK.inst.IF.stop_clock(); + `TH.`TX_DEVICE_CLK.inst.IF.stop_clock(); + `TH.`TX_LINK_CLK.inst.IF.stop_clock(); + `TH.`TX_OS_DEVICE_CLK.inst.IF.stop_clock(); + `TH.`SYSREF_CLK.inst.IF.stop_clock(); + `INFO(("Test Done"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/project/fmcomms2/tests/test_program.sv b/testbenches/project/fmcomms2/tests/test_program.sv index ead8416b..9b12bfb4 100644 --- a/testbenches/project/fmcomms2/tests/test_program.sv +++ b/testbenches/project/fmcomms2/tests/test_program.sv @@ -116,7 +116,7 @@ program test_program; //set source synchronous interface clock frequency `TH.`SSI_CLK.inst.IF.set_clk_frq(.user_frequency(80000000)); - `TH.`SSI_CLK.inst.IF.start_clock; + `TH.`SSI_CLK.inst.IF.start_clock(); base_env.sys_reset(); @@ -133,6 +133,7 @@ program test_program; dma_test(); base_env.stop(); + `TH.`SSI_CLK.inst.IF.stop_clock(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/project/mxfe/tests/test_program.sv b/testbenches/project/mxfe/tests/test_program.sv index cbfa6728..cb170b7b 100644 --- a/testbenches/project/mxfe/tests/test_program.sv +++ b/testbenches/project/mxfe/tests/test_program.sv @@ -112,9 +112,9 @@ program test_program; `TH.`SYSREF_CLK.inst.IF.set_clk_frq(.user_frequency(rx_ll.calc_sysref_clk())); `TH.`DMA_CLK.inst.IF.set_clk_frq(.user_frequency(rx_ll.calc_device_clk())); - `TH.`REF_CLK.inst.IF.start_clock; - `TH.`DEVICE_CLK.inst.IF.start_clock; - `TH.`SYSREF_CLK.inst.IF.start_clock; + `TH.`REF_CLK.inst.IF.start_clock(); + `TH.`DEVICE_CLK.inst.IF.start_clock(); + `TH.`SYSREF_CLK.inst.IF.start_clock(); rx_xcvr.setup_clocks(lane_rate, `REF_CLK_RATE*1000000); @@ -154,6 +154,10 @@ program test_program; base_env.stop(); + `TH.`REF_CLK.inst.IF.stop_clock(); + `TH.`DEVICE_CLK.inst.IF.stop_clock(); + `TH.`SYSREF_CLK.inst.IF.stop_clock(); + `INFO(("Test Done"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/project/pluto/tests/test_program.sv b/testbenches/project/pluto/tests/test_program.sv index 8dd72e0a..e76780d4 100644 --- a/testbenches/project/pluto/tests/test_program.sv +++ b/testbenches/project/pluto/tests/test_program.sv @@ -116,7 +116,7 @@ program test_program; // Set source synchronous interface clock frequency `TH.`SSI_CLK.inst.IF.set_clk_frq(.user_frequency(61440000)); - `TH.`SSI_CLK.inst.IF.start_clock; + `TH.`SSI_CLK.inst.IF.start_clock(); // Initial system reset base_env.sys_reset(); @@ -148,6 +148,7 @@ program test_program; tdd_test(); base_env.stop(); + `TH.`SSI_CLK.inst.IF.stop_clock(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); $finish(); From 46b53bb6f6badfb7fabc42cddc93d1a0c8cfa73c Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Tue, 11 Feb 2025 11:28:03 +0200 Subject: [PATCH 25/37] general: Change while(1) calls to forever Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/data_offload/environment.sv | 2 +- testbenches/ip/data_offload_2/environment.sv | 2 +- testbenches/project/ad738x/tests/test_program.sv | 16 ++++++++-------- .../project/ad7616/tests/test_program_pi.sv | 6 +++--- .../project/ad7616/tests/test_program_si.sv | 16 ++++++++-------- .../pulsar_adc_pmdz/tests/test_program.sv | 16 ++++++++-------- 6 files changed, 29 insertions(+), 29 deletions(-) diff --git a/testbenches/ip/data_offload/environment.sv b/testbenches/ip/data_offload/environment.sv index 66c3fafe..ff4def5b 100644 --- a/testbenches/ip/data_offload/environment.sv +++ b/testbenches/ip/data_offload/environment.sv @@ -117,7 +117,7 @@ package environment_pkg; task adc_stream_gen(); - while(1) begin + forever begin if (adc_src_axis_agent.driver.is_driver_idle) begin rx_transaction = adc_src_axis_agent.driver.create_transaction(""); ADC_TRANSACTION_FAIL: assert(rx_transaction.randomize()); diff --git a/testbenches/ip/data_offload_2/environment.sv b/testbenches/ip/data_offload_2/environment.sv index 5da43a2c..028c97aa 100644 --- a/testbenches/ip/data_offload_2/environment.sv +++ b/testbenches/ip/data_offload_2/environment.sv @@ -140,7 +140,7 @@ package environment_pkg; task adc_stream_gen(); - while(1) begin + forever begin if (src_axis_agent.driver.is_driver_idle) begin rx_transaction = src_axis_agent.driver.create_transaction(""); TRANSACTION_FAIL: assert(rx_transaction.randomize()); diff --git a/testbenches/project/ad738x/tests/test_program.sv b/testbenches/project/ad738x/tests/test_program.sv index 4f4ea8e8..dc8058bb 100644 --- a/testbenches/project/ad738x/tests/test_program.sv +++ b/testbenches/project/ad738x/tests/test_program.sv @@ -249,7 +249,7 @@ end // Add an arbitrary delay to the echo_sclk signal initial begin - while(1) begin + forever begin @(posedge delay_clk) begin echo_delay_sclk <= {echo_delay_sclk, m_rx_sclk}; end @@ -258,7 +258,7 @@ end assign ad738x_echo_sclk = echo_delay_sclk[SDI_PHY_DELAY-1]; initial begin - while(1) begin + forever begin #0.5 delay_clk = ~delay_clk; end end @@ -279,7 +279,7 @@ bit [31:0] sdi_preg[$]; bit [31:0] sdi_nreg[$]; initial begin - while(1) begin + forever begin @(posedge ad738x_spi_clk); m_spi_csn_int_d <= m_spi_csn_int_s; end @@ -297,7 +297,7 @@ assign end_of_word = (CPOL ^ CPHA) ? (spi_sclk_neg_counter == DATA_DLENGTH); initial begin - while(1) begin + forever begin @(posedge spi_sclk_bfm or posedge m_spi_csn_negedge_s); if (m_spi_csn_negedge_s) begin spi_sclk_pos_counter <= 8'b0; @@ -308,7 +308,7 @@ initial begin end initial begin - while(1) begin + forever begin @(negedge spi_sclk_bfm or posedge m_spi_csn_negedge_s); if (m_spi_csn_negedge_s) begin spi_sclk_neg_counter <= 8'b0; @@ -320,7 +320,7 @@ end // SDI shift register initial begin - while(1) begin + forever begin // synchronization if (CPHA ^ CPOL) @(posedge spi_sclk_bfm or posedge m_spi_csn_negedge_s); @@ -372,7 +372,7 @@ bit [31:0] sdi_shiftreg_old; assign sdi_shiftreg2 = {1'b0, sdi_shiftreg[31:1]}; initial begin - while(1) begin + forever begin @(posedge ad738x_echo_sclk); sdi_data_store <= {sdi_shiftreg[27:0], 4'b0}; if (sdi_data_store == 'h0 && shiftreg_sampled == 'h1 && sdi_shiftreg != 'h0) begin @@ -399,7 +399,7 @@ end bit [31:0] offload_transfer_cnt; initial begin - while(1) begin + forever begin @(posedge shiftreg_sampled && offload_status); offload_transfer_cnt <= offload_transfer_cnt + 'h1; end diff --git a/testbenches/project/ad7616/tests/test_program_pi.sv b/testbenches/project/ad7616/tests/test_program_pi.sv index 1d9c557d..d954fb4c 100755 --- a/testbenches/project/ad7616/tests/test_program_pi.sv +++ b/testbenches/project/ad7616/tests/test_program_pi.sv @@ -137,7 +137,7 @@ bit transfer_status = 0; assign rx_db_i = tx_data_buf; initial begin - while(1) begin + forever begin @(posedge sys_clk); rx_rd_n_tmp <= rx_rd_n; fork @@ -150,7 +150,7 @@ assign rx_rd_n_negedge_s = ~rx_rd_n & rx_rd_n_d; assign rx_rd_n_posedge_s = rx_rd_n & ~rx_rd_n_d; initial begin - while(1) begin + forever begin @(negedge rx_rd_n); tx_data_buf <= tx_data_buf + 16'h0808; if (transfer_status) @@ -179,7 +179,7 @@ endtask //--------------------------------------------------------------------------- initial begin - while(1) begin + forever begin @(posedge rx_rd_n); if (transfer_status) transfer_cnt <= transfer_cnt + 'h1; diff --git a/testbenches/project/ad7616/tests/test_program_si.sv b/testbenches/project/ad7616/tests/test_program_si.sv index bb2544d9..02eabb5c 100755 --- a/testbenches/project/ad7616/tests/test_program_si.sv +++ b/testbenches/project/ad7616/tests/test_program_si.sv @@ -252,7 +252,7 @@ end // Add an arbitrary delay to the echo_sclk signal initial begin - while(1) begin + forever begin @(posedge delay_clk) begin echo_delay_sclk <= {echo_delay_sclk, m_rx_sclk}; end @@ -261,7 +261,7 @@ end assign ad7616_echo_sclk = echo_delay_sclk[SDI_PHY_DELAY-1]; initial begin - while(1) begin + forever begin #0.5 delay_clk = ~delay_clk; end end @@ -283,7 +283,7 @@ bit [31:0] sdi_preg[$]; bit [31:0] sdi_nreg[$]; initial begin - while(1) begin + forever begin @(posedge spi_clk); m_spi_csn_int_d <= m_spi_csn_int_s; end @@ -299,7 +299,7 @@ assign end_of_word = (CPOL ^ CPHA) ? (rx_sclk_neg_counter == 16); initial begin - while(1) begin + forever begin @(posedge rx_sclk_bfm or posedge m_spi_csn_negedge_s); if (m_spi_csn_negedge_s) begin rx_sclk_pos_counter <= 8'b0; @@ -310,7 +310,7 @@ initial begin end initial begin - while(1) begin + forever begin @(negedge rx_sclk_bfm or posedge m_spi_csn_negedge_s); if (m_spi_csn_negedge_s) begin rx_sclk_neg_counter <= 8'b0; @@ -322,7 +322,7 @@ end // SDI shift register initial begin - while(1) begin + forever begin // synchronization if (CPHA ^ CPOL) @(posedge rx_sclk_bfm or posedge m_spi_csn_negedge_s); @@ -371,7 +371,7 @@ bit [31:0] sdi_fifo_data_store; bit [31:0] sdi_data_store; initial begin - while(1) begin + forever begin @(posedge rx_sclk_bfm); sdi_data_store <= {sdi_shiftreg[13:0], 2'b00}; if (sdi_data_store == 'h0 && shiftreg_sampled == 'h1 && sdi_shiftreg != 'h0) begin @@ -399,7 +399,7 @@ end bit [31:0] offload_transfer_cnt; initial begin - while(1) begin + forever begin @(posedge shiftreg_sampled && offload_status); offload_transfer_cnt <= offload_transfer_cnt + 'h1; end diff --git a/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv b/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv index de822a73..3a99e60a 100755 --- a/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv +++ b/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv @@ -249,7 +249,7 @@ end // Add an arbitrary delay to the echo_sclk signal initial begin - while(1) begin + forever begin @(posedge delay_clk) begin echo_delay_sclk <= {echo_delay_sclk, m_spi_sclk}; end @@ -258,7 +258,7 @@ end assign pulsar_adc_echo_sclk = echo_delay_sclk[SDI_PHY_DELAY-1]; initial begin - while(1) begin + forever begin #0.5 delay_clk = ~delay_clk; end end @@ -279,7 +279,7 @@ bit [31:0] sdi_preg[$]; bit [31:0] sdi_nreg[$]; initial begin - while(1) begin + forever begin @(posedge pulsar_adc_spi_clk); m_spi_csn_int_d <= m_spi_csn_int_s; end @@ -297,7 +297,7 @@ assign end_of_word = (CPOL ^ CPHA) ? (spi_sclk_neg_counter == DATA_DLENGTH); initial begin - while(1) begin + forever begin @(posedge spi_sclk_bfm or posedge m_spi_csn_negedge_s); if (m_spi_csn_negedge_s) begin spi_sclk_pos_counter <= 8'b0; @@ -308,7 +308,7 @@ initial begin end initial begin - while(1) begin + forever begin @(negedge spi_sclk_bfm or posedge m_spi_csn_negedge_s); if (m_spi_csn_negedge_s) begin spi_sclk_neg_counter <= 8'b0; @@ -320,7 +320,7 @@ end // SDI shift register initial begin - while(1) begin + forever begin // synchronization if (CPHA ^ CPOL) @(posedge spi_sclk_bfm or posedge m_spi_csn_negedge_s); @@ -366,7 +366,7 @@ bit [31:0] sdi_fifo_data_store; bit [DATA_DLENGTH-1:0] sdi_data_store; initial begin - while(1) begin + forever begin @(posedge pulsar_adc_echo_sclk); sdi_data_store <= {sdi_shiftreg[27:0], 4'b0}; if (sdi_data_store == 'h0 && shiftreg_sampled == 'h1 && sdi_shiftreg != 'h0) begin @@ -392,7 +392,7 @@ end bit [31:0] offload_transfer_cnt; initial begin - while(1) begin + forever begin @(posedge shiftreg_sampled && offload_status); offload_transfer_cnt <= offload_transfer_cnt + 'h1; end From afcd1befc0f07f84691f9a5af2b40b9e8b77bf48 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Wed, 12 Feb 2025 13:28:18 +0200 Subject: [PATCH 26/37] ADI AMD agent abstractization Signed-off-by: Istvan-Zsolt Szekely --- library/utilities/test_harness_env.sv | 27 +-- library/vip/amd/axi/adi_axi_agent.sv | 183 ++++++++++++--- library/vip/amd/axi/adi_axi_monitor.sv | 35 ++- library/vip/amd/axis/adi_axis_agent.sv | 191 +++++++++++---- library/vip/amd/axis/adi_axis_monitor.sv | 35 ++- library/vip/amd/axis/m_axis_sequencer.sv | 222 +++++++++--------- library/vip/amd/axis/s_axis_sequencer.sv | 18 +- testbenches/ip/base/tests/test_program.sv | 24 +- testbenches/ip/scoreboard/environment.sv | 54 ++--- .../ip/scoreboard/tests/test_program.sv | 127 +++++++--- 10 files changed, 609 insertions(+), 307 deletions(-) diff --git a/library/utilities/test_harness_env.sv b/library/utilities/test_harness_env.sv index 17545cbe..e8d3cce8 100644 --- a/library/utilities/test_harness_env.sv +++ b/library/utilities/test_harness_env.sv @@ -43,11 +43,11 @@ package test_harness_env_pkg; import adi_axi_agent_pkg::*; - class test_harness_env #(int `AXI_VIP_PARAM_ORDER(mng), int `AXI_VIP_PARAM_ORDER(ddr)) extends adi_environment; + class test_harness_env extends adi_environment; // Agents - adi_axi_master_agent #(`AXI_VIP_PARAM_ORDER(mng)) mng; - adi_axi_slave_mem_agent #(`AXI_VIP_PARAM_ORDER(ddr)) ddr; + adi_axi_agent_base mng; + adi_axi_agent_base ddr; virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if; virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if; @@ -65,10 +65,7 @@ package test_harness_env_pkg; virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, - virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, - - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(mng)) mng_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(ddr)) ddr_vip_if); + virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if); super.new(name); @@ -78,8 +75,8 @@ package test_harness_env_pkg; this.sys_rst_vip_if = sys_rst_vip_if; // Creating the agents - this.mng = new("AXI Manager agent", mng_vip_if, this); - this.ddr = new("AXI DDR stub agent", ddr_vip_if, this); + this.mng = new("AXI Manager agent", adi_axi_agent_pkg::MASTER, this); + this.ddr = new("AXI DDR stub agent", adi_axi_agent_pkg::SLAVE, this); endfunction //============================================================================ @@ -88,8 +85,8 @@ package test_harness_env_pkg; // - Start the agents //============================================================================ task start(); - this.mng.agent.start_master(); - this.ddr.agent.start_slave(); + this.mng.start_master(); + this.ddr.start_slave(); this.sys_clk_vip_if.start_clock(); this.dma_clk_vip_if.start_clock(); @@ -100,8 +97,8 @@ package test_harness_env_pkg; // Stop subroutine //============================================================================ task stop(); - this.mng.agent.stop_master(); - this.ddr.agent.stop_slave(); + this.mng.stop_master(); + this.ddr.stop_slave(); this.sys_clk_vip_if.stop_clock(); this.dma_clk_vip_if.stop_clock(); @@ -114,9 +111,9 @@ package test_harness_env_pkg; task sys_reset(); //asserts all the resets for 100 ns this.sys_rst_vip_if.assert_reset(); - #200; + #200ns; this.sys_rst_vip_if.deassert_reset(); - #800; + #800ns; endtask endclass diff --git a/library/vip/amd/axi/adi_axi_agent.sv b/library/vip/amd/axi/adi_axi_agent.sv index 90b77e56..01a33f27 100644 --- a/library/vip/amd/axi/adi_axi_agent.sv +++ b/library/vip/amd/axi/adi_axi_agent.sv @@ -46,11 +46,75 @@ package adi_axi_agent_pkg; import s_axi_sequencer_pkg::*; import adi_axi_monitor_pkg::*; + typedef enum {MASTER, SLAVE, PASSTHROUGH} axi_agent_typedef; + + class adi_axi_agent_base extends adi_agent; - class adi_axi_master_agent #(int `AXI_VIP_PARAM_ORDER(master)) extends adi_agent; + m_axi_sequencer_base master_sequencer; + s_axi_sequencer_base slave_sequencer; + adi_axi_monitor_base monitor; + + local axi_agent_typedef agent_type; + + function new( + input string name, + input axi_agent_typedef agent_type, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent_type = agent_type; + endfunction: new + + virtual task start_master(); + if (agent_type == SLAVE) begin + this.fatal($sformatf("Agent is in slave mode!")); + end + this.monitor.start(); + endtask: start_master + + virtual task start_slave(); + if (agent_type == MASTER) begin + this.fatal($sformatf("Agent is in master mode!")); + end + this.monitor.start(); + endtask: start_slave + + virtual task start_monitor(); + if (agent_type != PASSTHROUGH) begin + this.fatal($sformatf("Agent is not in passthrough mode!")); + end + this.monitor.start(); + endtask: start_monitor + + virtual task stop_master(); + if (agent_type == SLAVE) begin + this.fatal($sformatf("Agent is in slave mode!")); + end + this.monitor.stop(); + endtask: stop_master + + virtual task stop_slave(); + if (agent_type == MASTER) begin + this.fatal($sformatf("Agent is in master mode!")); + end + this.monitor.stop(); + endtask: stop_slave + + virtual task stop_monitor(); + if (agent_type != PASSTHROUGH) begin + this.fatal($sformatf("Agent is not in passthrough mode!")); + end + this.monitor.stop(); + endtask: stop_monitor + + endclass: adi_axi_agent_base + + + class adi_axi_master_agent #(int `AXI_VIP_PARAM_ORDER(master)) extends adi_axi_agent_base; axi_mst_agent #(`AXI_VIP_PARAM_ORDER(master)) agent; - m_axi_sequencer #(`AXI_VIP_PARAM_ORDER(master)) sequencer; + m_axi_sequencer #(`AXI_VIP_PARAM_ORDER(master)) master_sequencer; adi_axi_monitor #(`AXI_VIP_PARAM_ORDER(master)) monitor; function new( @@ -58,33 +122,40 @@ package adi_axi_agent_pkg; virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(master)) master_vip_if, input adi_environment parent = null); - super.new(name, parent); + super.new(name, MASTER, parent); this.agent = new("Agent", master_vip_if); - this.sequencer = new("Sequencer", this.agent.wr_driver, this.agent.rd_driver, this); + this.master_sequencer = new("Master Sequencer", this.agent.wr_driver, this.agent.rd_driver, this); this.monitor = new("Monitor TX", this.agent.monitor, this); endfunction: new - task start(); - this.agent.start_master(); - endtask: start + function void pre_link_agent(adi_axi_agent_base adi_axi_agent); + this.name = adi_axi_agent.name; + this.parent = adi_axi_agent.parent; + endfunction: pre_link_agent - task run(); - this.monitor.run(); - endtask: run + function void post_link_agent(adi_axi_agent_base adi_axi_agent); + adi_axi_agent.master_sequencer = this.master_sequencer; + adi_axi_agent.monitor = this.monitor; + endfunction: post_link_agent - task stop(); - this.monitor.stop(); + virtual task start_master(); + super.start_master(); + this.agent.start_master(); + endtask: start_master + + virtual task stop_master(); + super.stop_master(); this.agent.stop_master(); - endtask: stop + endtask: stop_master endclass: adi_axi_master_agent - class adi_axi_slave_mem_agent #(int `AXI_VIP_PARAM_ORDER(slave)) extends adi_agent; + class adi_axi_slave_mem_agent #(int `AXI_VIP_PARAM_ORDER(slave)) extends adi_axi_agent_base; axi_slv_mem_agent #(`AXI_VIP_PARAM_ORDER(slave)) agent; - s_axi_sequencer #(`AXI_VIP_PARAM_ORDER(slave)) sequencer; + s_axi_sequencer #(`AXI_VIP_PARAM_ORDER(slave)) slave_sequencer; adi_axi_monitor #(`AXI_VIP_PARAM_ORDER(slave)) monitor; function new( @@ -92,30 +163,37 @@ package adi_axi_agent_pkg; virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(slave)) slave_vip_if, input adi_environment parent = null); - super.new(name, parent); + super.new(name, SLAVE, parent); this.agent = new("Agent", slave_vip_if); - this.sequencer = new("Sequencer", this.agent.mem_model, this); + this.slave_sequencer = new("Slave Sequencer", this.agent.mem_model, this); this.monitor = new("Monitor TX", this.agent.monitor, this); endfunction: new - task start(); - this.agent.start_slave(); - endtask: start + function void pre_link_agent(adi_axi_agent_base adi_axi_agent); + this.name = adi_axi_agent.name; + this.parent = adi_axi_agent.parent; + endfunction: pre_link_agent - task run(); - this.monitor.run(); - endtask: run + function void post_link_agent(adi_axi_agent_base adi_axi_agent); + adi_axi_agent.slave_sequencer = this.slave_sequencer; + adi_axi_agent.monitor = this.monitor; + endfunction: post_link_agent - task stop(); - this.monitor.stop(); + virtual task start_slave(); + super.start_slave(); + this.agent.start_slave(); + endtask: start_slave + + virtual task stop_slave(); + super.stop_slave(); this.agent.stop_slave(); - endtask: stop + endtask: stop_slave endclass: adi_axi_slave_mem_agent - class adi_axi_passthrough_mem_agent #(int `AXI_VIP_PARAM_ORDER(passthrough)) extends adi_agent; + class adi_axi_passthrough_mem_agent #(int `AXI_VIP_PARAM_ORDER(passthrough)) extends adi_axi_agent_base; axi_passthrough_mem_agent #(`AXI_VIP_PARAM_ORDER(passthrough)) agent; m_axi_sequencer #(`AXI_VIP_PARAM_ORDER(passthrough)) master_sequencer; @@ -127,27 +205,54 @@ package adi_axi_agent_pkg; virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(passthrough)) passthrough_vip_if, input adi_environment parent = null); - super.new(name, parent); + super.new(name, PASSTHROUGH, parent); this.agent = new("Agent", passthrough_vip_if); - this.master_sequencer = new("Slave Sequencer", this.agent.mst_wr_driver, this.agent.mst_rd_driver, this); + this.master_sequencer = new("Master Sequencer", this.agent.mst_wr_driver, this.agent.mst_rd_driver, this); this.slave_sequencer = new("Slave Sequencer", this.agent.mem_model, this); this.monitor = new("Monitor TX", this.agent.monitor, this); endfunction: new - task start(); - this.warning($sformatf("Start must called manually in the test program or environment")); - endtask: start + function void pre_link_agent(adi_axi_agent_base adi_axi_agent); + this.name = adi_axi_agent.name; + this.parent = adi_axi_agent.parent; + endfunction: pre_link_agent - task run(); - this.monitor.run(); - endtask: run + function void post_link_agent(adi_axi_agent_base adi_axi_agent); + adi_axi_agent.master_sequencer = this.master_sequencer; + adi_axi_agent.slave_sequencer = this.slave_sequencer; + adi_axi_agent.monitor = this.monitor; + endfunction: post_link_agent - task stop(); - this.monitor.stop(); - this.agent.stop_slave(); + virtual task start_master(); + super.start_master(); + this.agent.start_master(); + endtask: start_master + + virtual task start_slave(); + super.start_slave(); + this.agent.start_slave(); + endtask: start_slave + + virtual task start_monitor(); + super.start_monitor(); + this.agent.start_monitor(); + endtask: start_monitor + + virtual task stop_master(); + super.stop_master(); this.agent.stop_master(); - endtask: stop + endtask: stop_master + + virtual task stop_slave(); + super.stop_slave(); + this.agent.stop_slave(); + endtask: stop_slave + + virtual task stop_monitor(); + super.stop_monitor(); + this.agent.stop_monitor(); + endtask: stop_monitor endclass: adi_axi_passthrough_mem_agent diff --git a/library/vip/amd/axi/adi_axi_monitor.sv b/library/vip/amd/axi/adi_axi_monitor.sv index 8c440d22..afcfb044 100644 --- a/library/vip/amd/axi/adi_axi_monitor.sv +++ b/library/vip/amd/axi/adi_axi_monitor.sv @@ -42,10 +42,8 @@ package adi_axi_monitor_pkg; import adi_vip_pkg::*; import pub_sub_pkg::*; - class adi_axi_monitor #(int `AXI_VIP_PARAM_ORDER(axi)) extends adi_monitor; - // analysis port from the monitor - protected axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor; + class adi_axi_monitor_base extends adi_monitor; adi_publisher #(logic [7:0]) publisher_tx; adi_publisher #(logic [7:0]) publisher_rx; @@ -56,20 +54,17 @@ package adi_axi_monitor_pkg; // constructor function new( input string name, - input axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor, input adi_agent parent = null); super.new(name, parent); - this.monitor = monitor; - this.publisher_tx = new("Publisher TX", this); this.publisher_rx = new("Publisher RX", this); this.enabled = 0; endfunction - task run(); + task start(); if (this.enabled) begin this.error($sformatf("Monitor is already running!")); return; @@ -89,16 +84,38 @@ package adi_axi_monitor_pkg; disable fork; end join_none - endtask: run + endtask: start function void stop(); this.enabled = 0; -> enable_ev; endfunction: stop + virtual task get_transaction(); + endtask: get_transaction + + endclass: adi_axi_monitor_base + + + class adi_axi_monitor #(int `AXI_VIP_PARAM_ORDER(axi)) extends adi_axi_monitor_base; + + // analysis port from the monitor + protected axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor; + + // constructor + function new( + input string name, + input axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor, + input adi_agent parent = null); + + super.new(name, parent); + + this.monitor = monitor; + endfunction + // collect data from the DDR interface, all WRITE transaction are coming // from the ADC and all READ transactions are going to the DAC - task get_transaction(); + virtual task get_transaction(); axi_monitor_transaction transaction; xil_axi_data_beat data_beat; xil_axi_strb_beat strb_beat; diff --git a/library/vip/amd/axis/adi_axis_agent.sv b/library/vip/amd/axis/adi_axis_agent.sv index 96ce1b25..85d91fd0 100644 --- a/library/vip/amd/axis/adi_axis_agent.sv +++ b/library/vip/amd/axis/adi_axis_agent.sv @@ -46,11 +46,77 @@ package adi_axis_agent_pkg; import s_axis_sequencer_pkg::*; import adi_axis_monitor_pkg::*; + typedef enum {MASTER, SLAVE, PASSTHROUGH} axis_agent_typedef; - class adi_axis_master_agent #(`AXIS_VIP_PARAM_DECL(master)) extends adi_agent; + class adi_axis_agent_base extends adi_agent; + + m_axis_sequencer_base master_sequencer; + s_axis_sequencer_base slave_sequencer; + adi_axis_monitor_base monitor; + + local axis_agent_typedef agent_type; + + function new( + input string name, + input axis_agent_typedef agent_type, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent_type = agent_type; + endfunction: new + + virtual task start_master(); + if (agent_type == SLAVE) begin + this.fatal($sformatf("Agent is in slave mode!")); + end + this.monitor.start(); + endtask: start_master + + virtual task start_slave(); + if (agent_type == MASTER) begin + this.fatal($sformatf("Agent is in master mode!")); + end + this.monitor.start(); + endtask: start_slave + + virtual task start_monitor(); + if (agent_type != PASSTHROUGH) begin + this.fatal($sformatf("Agent is not in passthrough mode!")); + end + this.monitor.start(); + endtask: start_monitor + + virtual task stop_master(); + if (agent_type == SLAVE) begin + this.fatal($sformatf("Agent is in slave mode!")); + end + this.master_sequencer.stop(); + this.monitor.stop(); + endtask: stop_master + + virtual task stop_slave(); + if (agent_type == MASTER) begin + this.fatal($sformatf("Agent is in master mode!")); + end + this.slave_sequencer.stop(); + this.monitor.stop(); + endtask: stop_slave + + virtual task stop_monitor(); + if (agent_type != PASSTHROUGH) begin + this.fatal($sformatf("Agent is not in passthrough mode!")); + end + this.monitor.stop(); + endtask: stop_monitor + + endclass: adi_axis_agent_base + + + class adi_axis_master_agent #(`AXIS_VIP_PARAM_DECL(master)) extends adi_axis_agent_base; axi4stream_mst_agent #(`AXIS_VIP_IF_PARAMS(master)) agent; - m_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(master)) sequencer; + m_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(master)) master_sequencer; adi_axis_monitor #(`AXIS_VIP_PARAM_ORDER(master)) monitor; function new( @@ -58,35 +124,40 @@ package adi_axis_agent_pkg; virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(master)) master_vip_if, input adi_environment parent = null); - super.new(name, parent); + super.new(name, MASTER, parent); this.agent = new("Agent", master_vip_if); - this.sequencer = new("Sequencer", this.agent.driver, this); + this.master_sequencer = new("Sequencer", this.agent.driver, this); this.monitor = new("Monitor", this.agent.monitor, this); endfunction: new - task start(); - this.agent.start_master(); - endtask: start + function void pre_link_agent(adi_axis_agent_base adi_axis_agent); + this.name = adi_axis_agent.name; + this.parent = adi_axis_agent.parent; + endfunction: pre_link_agent - task run(); - this.sequencer.run(); - this.monitor.run(); - endtask: run + function void post_link_agent(adi_axis_agent_base adi_axis_agent); + adi_axis_agent.master_sequencer = this.master_sequencer; + adi_axis_agent.monitor = this.monitor; + endfunction: post_link_agent - task stop(); - this.monitor.stop(); - this.sequencer.stop(); + virtual task start_master(); + super.start_master(); + this.agent.start_master(); + endtask: start_master + + virtual task stop_master(); + super.stop_master(); this.agent.stop_master(); - endtask: stop + endtask: stop_master endclass: adi_axis_master_agent - class adi_axis_slave_agent #(`AXIS_VIP_PARAM_DECL(slave)) extends adi_agent; + class adi_axis_slave_agent #(`AXIS_VIP_PARAM_DECL(slave)) extends adi_axis_agent_base; axi4stream_slv_agent #(`AXIS_VIP_IF_PARAMS(slave)) agent; - s_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(slave)) sequencer; + s_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(slave)) slave_sequencer; adi_axis_monitor #(`AXIS_VIP_PARAM_ORDER(slave)) monitor; function new( @@ -94,31 +165,37 @@ package adi_axis_agent_pkg; virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(slave)) slave_vip_if, input adi_environment parent = null); - super.new(name, parent); + super.new(name, SLAVE, parent); this.agent = new("Agent", slave_vip_if); - this.sequencer = new("Sequencer", this.agent.driver, this); + this.slave_sequencer = new("Sequencer", this.agent.driver, this); this.monitor = new("Monitor", this.agent.monitor, this); endfunction: new - task start(); - this.agent.start_slave(); - endtask: start + function void pre_link_agent(adi_axis_agent_base adi_axis_agent); + this.name = adi_axis_agent.name; + this.parent = adi_axis_agent.parent; + endfunction: pre_link_agent - task run(); - this.sequencer.run(); - this.monitor.run(); - endtask: run + function void post_link_agent(adi_axis_agent_base adi_axis_agent); + adi_axis_agent.slave_sequencer = this.slave_sequencer; + adi_axis_agent.monitor = this.monitor; + endfunction: post_link_agent - task stop(); - this.monitor.stop(); + virtual task start_slave(); + super.start_slave(); + this.agent.start_slave(); + endtask: start_slave + + virtual task stop_slave(); + super.stop_slave(); this.agent.stop_slave(); - endtask: stop + endtask: stop_slave endclass: adi_axis_slave_agent - class adi_axis_passthrough_mem_agent #(`AXIS_VIP_PARAM_DECL(passthrough)) extends adi_agent; + class adi_axis_passthrough_mem_agent #(`AXIS_VIP_PARAM_DECL(passthrough)) extends adi_axis_agent_base; axi4stream_passthrough_agent #(`AXIS_VIP_IF_PARAMS(passthrough)) agent; m_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(passthrough)) master_sequencer; @@ -130,7 +207,7 @@ package adi_axis_agent_pkg; virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(passthrough)) passthrough_vip_if, input adi_environment parent = null); - super.new(name, parent); + super.new(name, PASSTHROUGH, parent); this.agent = new("Agent", passthrough_vip_if); this.master_sequencer = new("Master Sequencer", this.agent.mst_driver, this); @@ -138,22 +215,48 @@ package adi_axis_agent_pkg; this.monitor = new("Monitor", this.agent.monitor, this); endfunction: new - task start(); - this.warning($sformatf("Start must called manually in the test program or environment")); - endtask: start + function void pre_link_agent(adi_axis_agent_base adi_axis_agent); + this.name = adi_axis_agent.name; + this.parent = adi_axis_agent.parent; + endfunction: pre_link_agent - task run(); - this.master_sequencer.run(); - this.slave_sequencer.run(); - this.monitor.run(); - endtask: run + function void post_link_agent(adi_axis_agent_base adi_axis_agent); + adi_axis_agent.master_sequencer = this.master_sequencer; + adi_axis_agent.slave_sequencer = this.slave_sequencer; + adi_axis_agent.monitor = this.monitor; + endfunction: post_link_agent - task stop(); - this.monitor.stop(); - this.master_sequencer.stop(); - this.agent.stop_slave(); + virtual task start_master(); + super.start_master(); + this.agent.start_master(); + this.warning($sformatf("Sequencer must be started manually!")); + endtask: start_master + + virtual task start_slave(); + super.start_slave(); + this.agent.start_slave(); + this.warning($sformatf("Sequencer must be started manually!")); + endtask: start_slave + + virtual task start_monitor(); + super.start_monitor(); + this.agent.start_monitor(); + endtask: start_monitor + + virtual task stop_master(); + super.stop_master(); this.agent.stop_master(); - endtask: stop + endtask: stop_master + + virtual task stop_slave(); + super.stop_slave(); + this.agent.stop_slave(); + endtask: stop_slave + + virtual task stop_monitor(); + super.stop_monitor(); + this.agent.stop_monitor(); + endtask: stop_monitor endclass: adi_axis_passthrough_mem_agent diff --git a/library/vip/amd/axis/adi_axis_monitor.sv b/library/vip/amd/axis/adi_axis_monitor.sv index c038ce62..9a4386f9 100644 --- a/library/vip/amd/axis/adi_axis_monitor.sv +++ b/library/vip/amd/axis/adi_axis_monitor.sv @@ -42,10 +42,8 @@ package adi_axis_monitor_pkg; import adi_vip_pkg::*; import pub_sub_pkg::*; - class adi_axis_monitor #(`AXIS_VIP_PARAM_DECL(AXIS)) extends adi_monitor; - // analysis port from the monitor - protected axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(AXIS)) monitor; + class adi_axis_monitor_base extends adi_monitor; adi_publisher #(logic [7:0]) publisher; @@ -55,19 +53,16 @@ package adi_axis_monitor_pkg; // constructor function new( input string name, - input axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(AXIS)) monitor, input adi_agent parent = null); super.new(name, parent); - this.monitor = monitor; - this.publisher = new("Publisher", this); this.enabled = 0; endfunction: new - task run(); + task start(); if (this.enabled) begin this.error($sformatf("Monitor is already running!")); return; @@ -87,16 +82,38 @@ package adi_axis_monitor_pkg; disable fork; end join_none - endtask: run + endtask: start function void stop(); this.enabled = 0; -> enable_ev; endfunction: stop + virtual task get_transaction(); + endtask: get_transaction + + endclass: adi_axis_monitor_base + + + class adi_axis_monitor #(`AXIS_VIP_PARAM_DECL(AXIS)) extends adi_axis_monitor_base; + + // analysis port from the monitor + protected axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(AXIS)) monitor; + + // constructor + function new( + input string name, + input axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(AXIS)) monitor, + input adi_agent parent = null); + + super.new(name, parent); + + this.monitor = monitor; + endfunction: new + // collect data from the AXI4Strean interface of the stub, this task // handles both ONESHOT and CYCLIC scenarios - task get_transaction(); + virtual task get_transaction(); axi4stream_transaction transaction; xil_axi4stream_data_beat data_beat; xil_axi4stream_strb_beat keep_beat; diff --git a/library/vip/amd/axis/m_axis_sequencer.sv b/library/vip/amd/axis/m_axis_sequencer.sv index 74db1702..4d275345 100644 --- a/library/vip/amd/axis/m_axis_sequencer.sv +++ b/library/vip/amd/axis/m_axis_sequencer.sv @@ -58,8 +58,9 @@ package m_axis_sequencer_pkg; class m_axis_sequencer_base extends adi_sequencer; protected bit enabled; + protected bit generator_running; + protected bit sender_running; protected bit queue_empty_sig; - protected event enable_ev; protected event disable_ev; protected data_gen_mode_t data_gen_mode; @@ -162,16 +163,18 @@ package m_axis_sequencer_pkg; // set disable policy function void set_stop_policy(input stop_policy_t stop_policy); - if (enabled) + if (enabled) begin this.error($sformatf("Sequencer must be disabled before configuring stop policy")); + end this.stop_policy = stop_policy; this.info($sformatf("Disable policy configured"), ADI_VERBOSITY_HIGH); endfunction: set_stop_policy // set data generation mode function void set_data_gen_mode(input data_gen_mode_t data_gen_mode); - if (enabled) + if (enabled) begin this.error($sformatf("Sequencer must be disabled before configuring data generation mode")); + end this.data_gen_mode = data_gen_mode; this.info($sformatf("Data generation mode configured"), ADI_VERBOSITY_HIGH); endfunction: set_data_gen_mode @@ -198,15 +201,17 @@ package m_axis_sequencer_pkg; // set all bytes valid in a sample, sets keep to 1 function void set_keep_all(); - if (enabled) + if (enabled) begin this.error($sformatf("Sequencer must be disabled before configuring keep all parameter")); + end this.keep_all = 1; endfunction: set_keep_all // bytes in a sample may not be valid, sets some bits of keep to 0 function void set_keep_some(); - if (enabled) + if (enabled) begin this.error($sformatf("Sequencer must be disabled before configuring keep all parameter")); + end this.keep_all = 0; endfunction: set_keep_some @@ -236,8 +241,9 @@ package m_axis_sequencer_pkg; // wait until queue is empty task wait_empty_descriptor_queue(); - if (this.queue_empty_sig) + if (this.queue_empty_sig) begin return; + end @queue_empty; endtask: wait_empty_descriptor_queue @@ -248,38 +254,34 @@ package m_axis_sequencer_pkg; // generate transfer with transfer descriptors protected task generator(); - this.info($sformatf("generator start"), ADI_VERBOSITY_HIGH); - forever begin - this.info($sformatf("Waiting for enable"), ADI_VERBOSITY_HIGH); - @enable_ev; - this.info($sformatf("Enable found"), ADI_VERBOSITY_HIGH); - fork begin - fork - begin - @disable_ev; - case (stop_policy) - STOP_POLICY_DESCRIPTOR_QUEUE: wait_empty_descriptor_queue(); - STOP_POLICY_PACKET: packet_sent(); - STOP_POLICY_DATA_BEAT: beat_sent(); - endcase - end - forever begin - if (descriptor_q.size() > 0) begin - if (enabled || (!enabled && stop_policy == STOP_POLICY_DESCRIPTOR_QUEUE)) begin - packetize(); - descriptor_delay_subroutine(); - end else - @enable_ev; - end else begin - this.queue_empty_sig = 1; - ->> queue_empty; - @queue_ev; + this.info($sformatf("Generator started"), ADI_VERBOSITY_HIGH); + this.generator_running = 1; + fork begin + fork + begin + @disable_ev; + case (stop_policy) + STOP_POLICY_DESCRIPTOR_QUEUE: wait_empty_descriptor_queue(); + STOP_POLICY_PACKET: packet_sent(); + STOP_POLICY_DATA_BEAT: beat_sent(); + endcase + end + forever begin + if (descriptor_q.size() > 0) begin + if (enabled || (!enabled && stop_policy == STOP_POLICY_DESCRIPTOR_QUEUE)) begin + packetize(); + descriptor_delay_subroutine(); end + end else begin + this.queue_empty_sig = 1; + ->> queue_empty; + @queue_ev; end - join_any - disable fork; - end join - end + end + join_any + disable fork; + end join + this.generator_running = 0; endtask: generator // function @@ -295,26 +297,30 @@ package m_axis_sequencer_pkg; endtask: data_beat_delay_subroutine task start(); - this.info($sformatf("enable sequencer"), ADI_VERBOSITY_HIGH); - enabled = 1; - ->> enable_ev; + this.info($sformatf("Sequencer started"), ADI_VERBOSITY_HIGH); + if (this.generator_running || this.sender_running) begin + if (this.enabled) begin + this.warning($sformatf("Sequencer is already running!")); + end else begin + this.warning($sformatf("Sequencer is still running!")); + end + return; + end + this.enabled = 1; + fork + generator(); + sender(); + join_none endtask: start task stop(); - this.info($sformatf("disable sequencer"), ADI_VERBOSITY_HIGH); - enabled = 0; - byte_count = 0; - ->> disable_ev; + this.info($sformatf("Sequencer stopped"), ADI_VERBOSITY_HIGH); + this.enabled = 0; + this.byte_count = 0; + ->> this.disable_ev; #1step; endtask: stop - task run(); - fork - generator(); - sender(); - join_none - endtask: run - endclass: m_axis_sequencer_base @@ -388,44 +394,48 @@ package m_axis_sequencer_pkg; this.info($sformatf("packetize start"), ADI_VERBOSITY_HIGH); byte_per_beat = AXIS_VIP_DATA_WIDTH/8; - descriptor = descriptor_q.pop_front(); + descriptor = this.descriptor_q.pop_front(); // put a copy of the descriptor back into the queue and continue processing - if (this.descriptor_gen_mode == 1 && enabled) - descriptor_q.push_back(descriptor); + if (this.descriptor_gen_mode == 1 && enabled) begin + this.descriptor_q.push_back(descriptor); + end packet_length = descriptor.num_bytes / byte_per_beat; - if (packet_length*byte_per_beat < descriptor.num_bytes) + if (packet_length*byte_per_beat < descriptor.num_bytes) begin packet_length++; + end - if (keep_all) + if (this.keep_all) begin descriptor.num_bytes = packet_length*byte_per_beat; + end for (int tc=0; tc> packet_done; - STOP_POLICY_DATA_BEAT: ->> beat_done; + STOP_POLICY_PACKET: ->> this.packet_done; + STOP_POLICY_DATA_BEAT: ->> this.beat_done; default: ; endcase end @@ -434,8 +444,9 @@ package m_axis_sequencer_pkg; disable fork; end join end + end DATA_GEN_MODE_AUTO_INCR: begin - data[i] = byte_count++; + data[i] = this.byte_count++; keep[i] = 1'b1; end DATA_GEN_MODE_AUTO_RAND: begin @@ -446,57 +457,58 @@ package m_axis_sequencer_pkg; end this.info($sformatf("generating axis transaction"), ADI_VERBOSITY_HIGH); - trans = this.driver.create_transaction(); - trans.set_data(data); - trans.set_id('h0); - trans.set_dest('h0); - data_beat_delay_subroutine(); + this.trans = this.driver.create_transaction(); + this.trans.set_data(data); + this.trans.set_id('h0); + this.trans.set_dest('h0); - if (AXIS_VIP_HAS_TKEEP) - trans.set_keep(keep); + this.data_beat_delay_subroutine(); - if (AXIS_VIP_HAS_TLAST) - trans.set_last((tc == packet_length-1) & descriptor.gen_last); + if (AXIS_VIP_HAS_TKEEP) begin + this.trans.set_keep(keep); + end - if (AXIS_VIP_USER_WIDTH > 0) - trans.set_user_beat((tc == 0) & descriptor.gen_sync); + if (AXIS_VIP_HAS_TLAST) begin + this.trans.set_last((tc == packet_length-1) & descriptor.gen_last); + end + + if (AXIS_VIP_USER_WIDTH > 0) begin + this.trans.set_user_beat((tc == 0) & descriptor.gen_sync); + end ->> data_av_ev; this.info($sformatf("waiting transfer to complete"), ADI_VERBOSITY_HIGH); - @beat_done; + @this.beat_done; end endtask: packetize // packet sender function virtual protected task sender(); - this.info($sformatf("sender start"), ADI_VERBOSITY_HIGH); - forever begin - this.info($sformatf("Waiting for enable"), ADI_VERBOSITY_HIGH); - @enable_ev; - this.info($sformatf("Enable found"), ADI_VERBOSITY_HIGH); - fork begin - fork - begin - @disable_ev; - case (stop_policy) - STOP_POLICY_DESCRIPTOR_QUEUE: wait_empty_descriptor_queue(); - STOP_POLICY_PACKET: packet_sent(); - STOP_POLICY_DATA_BEAT: beat_sent(); - endcase - end - forever begin - @data_av_ev; - this.info($sformatf("sending axis transaction"), ADI_VERBOSITY_HIGH); - this.driver.send(trans); - ->> beat_done; - if (this.trans.get_last()) begin - ->> packet_done; - end + this.info($sformatf("Sender started"), ADI_VERBOSITY_HIGH); + this.sender_running = 1; + fork begin + fork + begin + @this.disable_ev; + case (this.stop_policy) + STOP_POLICY_DESCRIPTOR_QUEUE: wait_empty_descriptor_queue(); + STOP_POLICY_PACKET: packet_sent(); + STOP_POLICY_DATA_BEAT: beat_sent(); + endcase + end + forever begin + @this.data_av_ev; + this.info($sformatf("sending axis transaction"), ADI_VERBOSITY_HIGH); + this.driver.send(this.trans); + ->> this.beat_done; + if (this.trans.get_last()) begin + ->> this.packet_done; end - join_any - disable fork; - end join - end + end + join_any + disable fork; + end join + this.sender_running = 0; endtask: sender endclass: m_axis_sequencer diff --git a/library/vip/amd/axis/s_axis_sequencer.sv b/library/vip/amd/axis/s_axis_sequencer.sv index 6745caa2..6f914a6b 100644 --- a/library/vip/amd/axis/s_axis_sequencer.sv +++ b/library/vip/amd/axis/s_axis_sequencer.sv @@ -143,9 +143,9 @@ package s_axis_sequencer_pkg; endtask: verify_byte // call ready generation function - task run(); - user_gen_tready(); - endtask: run + virtual task start(); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: start // virtual tasks to be implemented @@ -153,9 +153,9 @@ package s_axis_sequencer_pkg; this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endtask: user_gen_tready - virtual task get_transfer(); + virtual task stop(); this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); - endtask: get_transfer + endtask: stop endclass: s_axis_sequencer_base @@ -176,7 +176,7 @@ package s_axis_sequencer_pkg; endfunction: new - virtual task user_gen_tready(); + virtual task start(); axi4stream_ready_gen tready_gen; tready_gen = this.driver.create_ready("TREADY"); @@ -196,7 +196,11 @@ package s_axis_sequencer_pkg; tready_gen.set_high_time_range(this.high_time_min, this.high_time_max); end this.driver.send_tready(tready_gen); - endtask: user_gen_tready + endtask: start + + virtual task stop(); + this.driver.vif_proxy.reset(); + endtask: stop endclass: s_axis_sequencer diff --git a/testbenches/ip/base/tests/test_program.sv b/testbenches/ip/base/tests/test_program.sv index cfd43413..4abd1c01 100644 --- a/testbenches/ip/base/tests/test_program.sv +++ b/testbenches/ip/base/tests/test_program.sv @@ -38,6 +38,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import `PKGIFY(test_harness, mng_axi_vip)::*; import `PKGIFY(test_harness, ddr_axi_vip)::*; @@ -45,7 +46,10 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program; // Declare the class instances - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // Process variables process current_process; @@ -61,20 +65,24 @@ program test_program; `INFO(("Randomization state: %s", current_process_random_state), ADI_VERBOSITY_NONE); // Create environment - env = new("Base Environment", + base_env = new("Base Environment", `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + mng.link_agent(base_env.mng); + ddr.link_agent(base_env.ddr); - env.start(); - env.sys_reset(); + base_env.start(); + base_env.sys_reset(); /* Add stimulus tasks */ - env.stop(); + base_env.stop(); `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv index cd4405ad..63e435c4 100644 --- a/testbenches/ip/scoreboard/environment.sv +++ b/testbenches/ip/scoreboard/environment.sv @@ -53,13 +53,13 @@ package environment_pkg; import scoreboard_pkg::*; - class scoreboard_environment #(`AXIS_VIP_PARAM_DECL(adc_src), `AXIS_VIP_PARAM_DECL(dac_dst), `AXI_VIP_PARAM_DECL(adc_dst_pt), `AXI_VIP_PARAM_DECL(dac_src_pt)) extends adi_environment; + class scoreboard_environment extends adi_environment; // Agents - adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(adc_src)) adc_src_axis_agent; - adi_axis_slave_agent #(`AXIS_VIP_PARAM_ORDER(dac_dst)) dac_dst_axis_agent; - adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAM_ORDER(adc_dst_pt)) adc_dst_axi_pt_agent; - adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAM_ORDER(dac_src_pt)) dac_src_axi_pt_agent; + adi_axis_agent_base adc_src_axis_agent; + adi_axis_agent_base dac_dst_axis_agent; + adi_axi_agent_base adc_dst_axi_pt_agent; + adi_axi_agent_base dac_src_axi_pt_agent; scoreboard #(logic [7:0]) scoreboard_tx; scoreboard #(logic [7:0]) scoreboard_rx; @@ -67,21 +67,15 @@ package environment_pkg; //============================================================================ // Constructor //============================================================================ - function new ( - input string name, - - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(adc_src)) adc_src_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(dac_dst)) dac_dst_axis_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(adc_dst_pt)) adc_dst_axi_pt_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(dac_src_pt)) dac_src_axi_pt_vip_if); + function new (input string name); // creating the agents super.new(name); - this.adc_src_axis_agent = new("ADC Source AXI Stream Agent", adc_src_axis_vip_if, this); - this.dac_dst_axis_agent = new("DAC Destination AXI Stream Agent", dac_dst_axis_vip_if, this); - this.adc_dst_axi_pt_agent = new("ADC Destination AXI Agent", adc_dst_axi_pt_vip_if, this); - this.dac_src_axi_pt_agent = new("DAC Source AXI Agent", dac_src_axi_pt_vip_if, this); + this.adc_src_axis_agent = new("ADC Source AXI Stream Agent", adi_axis_agent_pkg::MASTER, this); + this.dac_dst_axis_agent = new("DAC Destination AXI Stream Agent", adi_axis_agent_pkg::SLAVE, this); + this.adc_dst_axi_pt_agent = new("ADC Destination AXI Agent", adi_axi_agent_pkg::PASSTHROUGH, this); + this.dac_src_axi_pt_agent = new("DAC Source AXI Agent", adi_axi_agent_pkg::PASSTHROUGH, this); this.scoreboard_tx = new("Data Offload TX Scoreboard", this); this.scoreboard_rx = new("Data Offload RX Scoreboard", this); @@ -93,11 +87,11 @@ package environment_pkg; //============================================================================ task configure(int bytes_to_generate); // ADC stub - this.adc_src_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - this.adc_src_axis_agent.sequencer.add_xfer_descriptor_byte_count(bytes_to_generate, 0, 0); + this.adc_src_axis_agent.master_sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); + this.adc_src_axis_agent.master_sequencer.add_xfer_descriptor_byte_count(bytes_to_generate, 0, 0); // DAC stub - this.dac_dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + this.dac_dst_axis_agent.slave_sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); endtask //============================================================================ @@ -106,10 +100,10 @@ package environment_pkg; // - Start the agents //============================================================================ task start(); - this.adc_src_axis_agent.agent.start_master(); - this.dac_dst_axis_agent.agent.start_slave(); - this.adc_dst_axi_pt_agent.agent.start_monitor(); - this.dac_src_axi_pt_agent.agent.start_monitor(); + this.adc_src_axis_agent.start_master(); + this.dac_dst_axis_agent.start_slave(); + this.adc_dst_axi_pt_agent.start_monitor(); + this.dac_src_axi_pt_agent.start_monitor(); this.dac_src_axi_pt_agent.monitor.publisher_rx.subscribe(this.scoreboard_tx.subscriber_source); this.dac_dst_axis_agent.monitor.publisher.subscribe(this.scoreboard_tx.subscriber_sink); @@ -123,13 +117,8 @@ package environment_pkg; //============================================================================ task run(); fork - this.adc_src_axis_agent.sequencer.run(); - this.dac_dst_axis_agent.sequencer.run(); - - this.adc_src_axis_agent.monitor.run(); - this.dac_dst_axis_agent.monitor.run(); - this.adc_dst_axi_pt_agent.monitor.run(); - this.dac_src_axi_pt_agent.monitor.run(); + this.adc_src_axis_agent.master_sequencer.start(); + this.dac_dst_axis_agent.slave_sequencer.start(); this.scoreboard_tx.run(); this.scoreboard_rx.run(); @@ -140,9 +129,8 @@ package environment_pkg; // Stop subroutine //============================================================================ task stop(); - this.adc_src_axis_agent.sequencer.stop(); - this.adc_src_axis_agent.agent.stop_master(); - this.dac_dst_axis_agent.agent.stop_slave(); + this.adc_src_axis_agent.stop_master(); + this.dac_dst_axis_agent.stop_slave(); endtask endclass diff --git a/testbenches/ip/scoreboard/tests/test_program.sv b/testbenches/ip/scoreboard/tests/test_program.sv index 48f580e6..c4001b28 100644 --- a/testbenches/ip/scoreboard/tests/test_program.sv +++ b/testbenches/ip/scoreboard/tests/test_program.sv @@ -40,6 +40,8 @@ import logger_pkg::*; import test_harness_env_pkg::*; import environment_pkg::*; +import adi_axi_agent_pkg::*; +import adi_axis_agent_pkg::*; import dmac_api_pkg::*; import data_offload_api_pkg::*; @@ -61,9 +63,24 @@ import `PKGIFY(test_harness, dac_src_axi_pt_1)::*; program test_program(); // declare the class instances - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; - scoreboard_environment #(`AXIS_VIP_PARAMS(test_harness, adc_src_axis_0), `AXIS_VIP_PARAMS(test_harness, dac_dst_axis_0), `AXI_VIP_PARAMS(test_harness, adc_dst_axi_pt_0), `AXI_VIP_PARAMS(test_harness, dac_src_axi_pt_0)) scb_env_0; - scoreboard_environment #(`AXIS_VIP_PARAMS(test_harness, adc_src_axis_1), `AXIS_VIP_PARAMS(test_harness, dac_dst_axis_1), `AXI_VIP_PARAMS(test_harness, adc_dst_axi_pt_1), `AXI_VIP_PARAMS(test_harness, dac_src_axi_pt_1)) scb_env_1; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + + scoreboard_environment scb_env_0; + + adi_axis_master_agent #(`AXIS_VIP_PARAMS(test_harness, adc_src_axis_0)) adc_src_axis_agent_0; + adi_axis_slave_agent #(`AXIS_VIP_PARAMS(test_harness, dac_dst_axis_0)) dac_dst_axis_agent_0; + adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAMS(test_harness, adc_dst_axi_pt_0)) adc_dst_axi_pt_agent_0; + adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAMS(test_harness, dac_src_axi_pt_0)) dac_src_axi_pt_agent_0; + + scoreboard_environment scb_env_1; + + adi_axis_master_agent #(`AXIS_VIP_PARAMS(test_harness, adc_src_axis_1)) adc_src_axis_agent_1; + adi_axis_slave_agent #(`AXIS_VIP_PARAMS(test_harness, dac_dst_axis_1)) dac_dst_axis_agent_1; + adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAMS(test_harness, adc_dst_axi_pt_1)) adc_dst_axi_pt_agent_1; + adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAMS(test_harness, dac_src_axi_pt_1)) dac_src_axi_pt_agent_1; dmac_api dmac_tx_0; dmac_api dmac_rx_0; @@ -82,31 +99,67 @@ program test_program(); `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); - - scb_env_0 = new("Scoreboard Environment 0", - `TH.`ADC_SRC_AXIS_0.inst.IF, - `TH.`DAC_DST_AXIS_0.inst.IF, - `TH.`ADC_DST_AXI_PT_0.inst.IF, - `TH.`DAC_SRC_AXI_PT_0.inst.IF); - - scb_env_1 = new("Scoreboard Environment 1", - `TH.`ADC_SRC_AXIS_1.inst.IF, - `TH.`DAC_DST_AXIS_1.inst.IF, - `TH.`ADC_DST_AXI_PT_1.inst.IF, - `TH.`DAC_SRC_AXI_PT_1.inst.IF); - - dmac_tx_0 = new("DMAC TX 0", base_env.mng.sequencer, `TX_DMA_BA_0); - dmac_rx_0 = new("DMAC RX 0", base_env.mng.sequencer, `RX_DMA_BA_0); - dmac_tx_1 = new("DMAC TX 1", base_env.mng.sequencer, `TX_DMA_BA_1); - dmac_rx_1 = new("DMAC RX 1", base_env.mng.sequencer, `RX_DMA_BA_1); - - do_tx_0 = new("Data Offload TX 0", base_env.mng.sequencer, `TX_DOFF_BA_0); - do_rx_0 = new("Data Offload RX 0", base_env.mng.sequencer, `RX_DOFF_BA_0); - do_tx_1 = new("Data Offload TX 1", base_env.mng.sequencer, `TX_DOFF_BA_1); - do_rx_1 = new("Data Offload RX 1", base_env.mng.sequencer, `RX_DOFF_BA_1); + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + mng.pre_link_agent(base_env.mng); + ddr.pre_link_agent(base_env.ddr); + base_env.mng = mng; + base_env.ddr = ddr; + mng.post_link_agent(base_env.mng); + ddr.post_link_agent(base_env.ddr); + + scb_env_0 = new("Scoreboard Environment 0"); + + adc_src_axis_agent_0 = new("", `TH.`ADC_SRC_AXIS_0.inst.IF); + dac_dst_axis_agent_0 = new("", `TH.`DAC_DST_AXIS_0.inst.IF); + adc_dst_axi_pt_agent_0 = new("", `TH.`ADC_DST_AXI_PT_0.inst.IF); + dac_src_axi_pt_agent_0 = new("", `TH.`DAC_SRC_AXI_PT_0.inst.IF); + + adc_src_axis_agent_0.pre_link_agent(scb_env_0.adc_src_axis_agent); + dac_dst_axis_agent_0.pre_link_agent(scb_env_0.dac_dst_axis_agent); + adc_dst_axi_pt_agent_0.pre_link_agent(scb_env_0.adc_dst_axi_pt_agent); + dac_src_axi_pt_agent_0.pre_link_agent(scb_env_0.dac_src_axi_pt_agent); + scb_env_0.adc_src_axis_agent = adc_src_axis_agent_0; + scb_env_0.dac_dst_axis_agent = dac_dst_axis_agent_0; + scb_env_0.adc_dst_axi_pt_agent = adc_dst_axi_pt_agent_0; + scb_env_0.dac_src_axi_pt_agent = dac_src_axi_pt_agent_0; + adc_src_axis_agent_0.post_link_agent(scb_env_0.adc_src_axis_agent); + dac_dst_axis_agent_0.post_link_agent(scb_env_0.dac_dst_axis_agent); + adc_dst_axi_pt_agent_0.post_link_agent(scb_env_0.adc_dst_axi_pt_agent); + dac_src_axi_pt_agent_0.post_link_agent(scb_env_0.dac_src_axi_pt_agent); + + scb_env_1 = new("Scoreboard Environment 1"); + + adc_src_axis_agent_1 = new("", `TH.`ADC_SRC_AXIS_1.inst.IF); + dac_dst_axis_agent_1 = new("", `TH.`DAC_DST_AXIS_1.inst.IF); + adc_dst_axi_pt_agent_1 = new("", `TH.`ADC_DST_AXI_PT_1.inst.IF); + dac_src_axi_pt_agent_1 = new("", `TH.`DAC_SRC_AXI_PT_1.inst.IF); + + adc_src_axis_agent_1.pre_link_agent(scb_env_1.adc_src_axis_agent); + dac_dst_axis_agent_1.pre_link_agent(scb_env_1.dac_dst_axis_agent); + adc_dst_axi_pt_agent_1.pre_link_agent(scb_env_1.adc_dst_axi_pt_agent); + dac_src_axi_pt_agent_1.pre_link_agent(scb_env_1.dac_src_axi_pt_agent); + scb_env_1.adc_src_axis_agent = adc_src_axis_agent_1; + scb_env_1.dac_dst_axis_agent = dac_dst_axis_agent_1; + scb_env_1.adc_dst_axi_pt_agent = adc_dst_axi_pt_agent_1; + scb_env_1.dac_src_axi_pt_agent = dac_src_axi_pt_agent_1; + adc_src_axis_agent_1.post_link_agent(scb_env_1.adc_src_axis_agent); + dac_dst_axis_agent_1.post_link_agent(scb_env_1.dac_dst_axis_agent); + adc_dst_axi_pt_agent_1.post_link_agent(scb_env_1.adc_dst_axi_pt_agent); + dac_src_axi_pt_agent_1.post_link_agent(scb_env_1.dac_src_axi_pt_agent); + + dmac_tx_0 = new("DMAC TX 0", base_env.mng.master_sequencer, `TX_DMA_BA_0); + dmac_rx_0 = new("DMAC RX 0", base_env.mng.master_sequencer, `RX_DMA_BA_0); + dmac_tx_1 = new("DMAC TX 1", base_env.mng.master_sequencer, `TX_DMA_BA_1); + dmac_rx_1 = new("DMAC RX 1", base_env.mng.master_sequencer, `RX_DMA_BA_1); + + do_tx_0 = new("Data Offload TX 0", base_env.mng.master_sequencer, `TX_DOFF_BA_0); + do_rx_0 = new("Data Offload RX 0", base_env.mng.master_sequencer, `RX_DOFF_BA_0); + do_tx_1 = new("Data Offload TX 1", base_env.mng.master_sequencer, `TX_DOFF_BA_1); + do_rx_1 = new("Data Offload RX 1", base_env.mng.master_sequencer, `RX_DOFF_BA_1); //========================================================================= // Setup generator/monitor stubs @@ -133,15 +186,12 @@ program test_program(); do_set_transfer_length(`ADC_TRANSFER_LENGTH/64); // Start the ADC/DAC stubs - `INFO(("Call the run() ..."), ADI_VERBOSITY_LOW); - scb_env_0.run(); - scb_env_1.run(); - - scb_env_0.adc_src_axis_agent.sequencer.start(); - scb_env_1.adc_src_axis_agent.sequencer.start(); + `INFO(("Start the sequencer"), ADI_VERBOSITY_LOW); + scb_env_0.adc_src_axis_agent.master_sequencer.start(); + scb_env_1.adc_src_axis_agent.master_sequencer.start(); // Generate DMA transfers - `INFO(("Start RX DMA ..."), ADI_VERBOSITY_LOW); + `INFO(("Start RX DMA"), ADI_VERBOSITY_LOW); rx_dma_transfer(dmac_rx_0, 32'h80000000, `ADC_TRANSFER_LENGTH); rx_dma_transfer(dmac_rx_1, 32'h80000000, `ADC_TRANSFER_LENGTH); @@ -150,10 +200,10 @@ program test_program(); scb_env_1.scoreboard_rx.wait_until_complete(); join - `INFO(("Initialize the memory ..."), ADI_VERBOSITY_LOW); + `INFO(("Initialize the memory"), ADI_VERBOSITY_LOW); init_mem_64(32'h80000000, 1024); - `INFO(("Start TX DMA ..."), ADI_VERBOSITY_LOW); + `INFO(("Start TX DMA"), ADI_VERBOSITY_LOW); tx_dma_transfer(dmac_tx_0, 32'h80000000, 1024); tx_dma_transfer(dmac_tx_1, 32'h80000000, 1024); @@ -233,7 +283,8 @@ program test_program(); input int byte_length); `INFO(("Initial address: %x", addr), ADI_VERBOSITY_LOW); for (int i=0; i Date: Thu, 13 Feb 2025 09:44:09 +0200 Subject: [PATCH 27/37] ADI AMD agent abstractization: Added linker macro to simplify VIP linking Signed-off-by: Istvan-Zsolt Szekely --- library/utilities/utils.svh | 6 +++ testbenches/ip/base/tests/test_program.sv | 4 +- .../ip/scoreboard/tests/test_program.sv | 40 +++++-------------- 3 files changed, 18 insertions(+), 32 deletions(-) diff --git a/library/utilities/utils.svh b/library/utilities/utils.svh index 804a60d8..1bda6ee5 100644 --- a/library/utilities/utils.svh +++ b/library/utilities/utils.svh @@ -48,6 +48,12 @@ // Help build VIP parameter name e.g. test_harness_dst_axis_vip_0_VIP_DATA_WIDTH `define GETPARAM(th,vip,param) th``_``vip``_0_``param +// Help link AMD AXI and AXIS VIPs to ADI Environment VIPs +`define LINK(top,env,inst) \ + top``.pre_link_agent(``env``.``inst``); \ + env``.``inst`` = ``top``; \ + top``.post_link_agent(``env``.``inst``); + // Macros used in Simulation files during simulation `define INFO(m,v) \ PrintInfo($sformatf("%s", \ diff --git a/testbenches/ip/base/tests/test_program.sv b/testbenches/ip/base/tests/test_program.sv index 4abd1c01..a3bac90d 100644 --- a/testbenches/ip/base/tests/test_program.sv +++ b/testbenches/ip/base/tests/test_program.sv @@ -74,8 +74,8 @@ program test_program; mng = new("", `TH.`MNG_AXI.inst.IF); ddr = new("", `TH.`DDR_AXI.inst.IF); - mng.link_agent(base_env.mng); - ddr.link_agent(base_env.ddr); + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) base_env.start(); base_env.sys_reset(); diff --git a/testbenches/ip/scoreboard/tests/test_program.sv b/testbenches/ip/scoreboard/tests/test_program.sv index c4001b28..b902be64 100644 --- a/testbenches/ip/scoreboard/tests/test_program.sv +++ b/testbenches/ip/scoreboard/tests/test_program.sv @@ -104,12 +104,8 @@ program test_program(); mng = new("", `TH.`MNG_AXI.inst.IF); ddr = new("", `TH.`DDR_AXI.inst.IF); - mng.pre_link_agent(base_env.mng); - ddr.pre_link_agent(base_env.ddr); - base_env.mng = mng; - base_env.ddr = ddr; - mng.post_link_agent(base_env.mng); - ddr.post_link_agent(base_env.ddr); + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) scb_env_0 = new("Scoreboard Environment 0"); @@ -118,18 +114,10 @@ program test_program(); adc_dst_axi_pt_agent_0 = new("", `TH.`ADC_DST_AXI_PT_0.inst.IF); dac_src_axi_pt_agent_0 = new("", `TH.`DAC_SRC_AXI_PT_0.inst.IF); - adc_src_axis_agent_0.pre_link_agent(scb_env_0.adc_src_axis_agent); - dac_dst_axis_agent_0.pre_link_agent(scb_env_0.dac_dst_axis_agent); - adc_dst_axi_pt_agent_0.pre_link_agent(scb_env_0.adc_dst_axi_pt_agent); - dac_src_axi_pt_agent_0.pre_link_agent(scb_env_0.dac_src_axi_pt_agent); - scb_env_0.adc_src_axis_agent = adc_src_axis_agent_0; - scb_env_0.dac_dst_axis_agent = dac_dst_axis_agent_0; - scb_env_0.adc_dst_axi_pt_agent = adc_dst_axi_pt_agent_0; - scb_env_0.dac_src_axi_pt_agent = dac_src_axi_pt_agent_0; - adc_src_axis_agent_0.post_link_agent(scb_env_0.adc_src_axis_agent); - dac_dst_axis_agent_0.post_link_agent(scb_env_0.dac_dst_axis_agent); - adc_dst_axi_pt_agent_0.post_link_agent(scb_env_0.adc_dst_axi_pt_agent); - dac_src_axi_pt_agent_0.post_link_agent(scb_env_0.dac_src_axi_pt_agent); + `LINK(adc_src_axis_agent_0, scb_env_0, adc_src_axis_agent) + `LINK(dac_dst_axis_agent_0, scb_env_0, dac_dst_axis_agent) + `LINK(adc_dst_axi_pt_agent_0, scb_env_0, adc_dst_axi_pt_agent) + `LINK(dac_src_axi_pt_agent_0, scb_env_0, dac_src_axi_pt_agent) scb_env_1 = new("Scoreboard Environment 1"); @@ -138,18 +126,10 @@ program test_program(); adc_dst_axi_pt_agent_1 = new("", `TH.`ADC_DST_AXI_PT_1.inst.IF); dac_src_axi_pt_agent_1 = new("", `TH.`DAC_SRC_AXI_PT_1.inst.IF); - adc_src_axis_agent_1.pre_link_agent(scb_env_1.adc_src_axis_agent); - dac_dst_axis_agent_1.pre_link_agent(scb_env_1.dac_dst_axis_agent); - adc_dst_axi_pt_agent_1.pre_link_agent(scb_env_1.adc_dst_axi_pt_agent); - dac_src_axi_pt_agent_1.pre_link_agent(scb_env_1.dac_src_axi_pt_agent); - scb_env_1.adc_src_axis_agent = adc_src_axis_agent_1; - scb_env_1.dac_dst_axis_agent = dac_dst_axis_agent_1; - scb_env_1.adc_dst_axi_pt_agent = adc_dst_axi_pt_agent_1; - scb_env_1.dac_src_axi_pt_agent = dac_src_axi_pt_agent_1; - adc_src_axis_agent_1.post_link_agent(scb_env_1.adc_src_axis_agent); - dac_dst_axis_agent_1.post_link_agent(scb_env_1.dac_dst_axis_agent); - adc_dst_axi_pt_agent_1.post_link_agent(scb_env_1.adc_dst_axi_pt_agent); - dac_src_axi_pt_agent_1.post_link_agent(scb_env_1.dac_src_axi_pt_agent); + `LINK(adc_src_axis_agent_1, scb_env_1, adc_src_axis_agent) + `LINK(dac_dst_axis_agent_1, scb_env_1, dac_dst_axis_agent) + `LINK(adc_dst_axi_pt_agent_1, scb_env_1, adc_dst_axi_pt_agent) + `LINK(dac_src_axi_pt_agent_1, scb_env_1, dac_src_axi_pt_agent) dmac_tx_0 = new("DMAC TX 0", base_env.mng.master_sequencer, `TX_DMA_BA_0); dmac_rx_0 = new("DMAC RX 0", base_env.mng.master_sequencer, `RX_DMA_BA_0); From a6483d770e839f81aa362ef48dc3d64f6376af9f Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Thu, 13 Feb 2025 11:14:07 +0200 Subject: [PATCH 28/37] ADI AMD agent abstractication: Updated testbenches for the base environment Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/axi_tdd/tests/test_program.sv | 140 +++++++++------- .../ip/axis_sequencers/tests/test_program.sv | 23 ++- testbenches/ip/base/tests/test_program.sv | 8 +- .../ip/dma_flock/tests/test_program.sv | 35 ++-- .../tests/test_program_frame_delay.sv | 35 ++-- .../ip/dma_loopback/tests/test_program.sv | 26 ++- .../ip/dma_sg/tests/test_program_1d.sv | 46 ++--- .../ip/dma_sg/tests/test_program_2d.sv | 46 ++--- .../ip/dma_sg/tests/test_program_tr_queue.sv | 58 ++++--- testbenches/ip/hbm/tests/test_program.sv | 42 +++-- .../ip/i3c_controller/tests/test_program.sv | 28 ++-- .../ip/jesd_loopback/tests/test_program.sv | 135 ++++++++------- .../jesd_loopback_64b/tests/test_program.sv | 77 +++++---- .../ip/scoreboard/tests/test_program.sv | 10 +- .../ip/spi_engine/tests/test_program.sv | 39 +++-- .../ip/spi_engine/tests/test_sleep_delay.sv | 35 ++-- .../ip/spi_engine/tests/test_slowdata.sv | 33 ++-- .../ip/util_axis_fifo/tests/test_program.sv | 23 ++- .../util_axis_fifo_asym/tests/test_program.sv | 23 ++- .../ip/util_pack/tests/test_program.sv | 27 ++- .../project/ad463x/tests/test_program.sv | 38 +++-- .../project/ad57xx/tests/test_program.sv | 39 +++-- .../project/ad738x/tests/test_program.sv | 38 +++-- .../project/ad7606x/tests/test_program_4ch.sv | 28 ++-- .../project/ad7606x/tests/test_program_6ch.sv | 28 ++-- .../project/ad7606x/tests/test_program_8ch.sv | 28 ++-- .../project/ad7606x/tests/test_program_si.sv | 38 +++-- .../project/ad7616/tests/test_program_pi.sv | 38 +++-- .../project/ad7616/tests/test_program_si.sv | 38 +++-- .../project/ad9083/tests/test_program.sv | 154 +++++++++-------- .../ad_quadmxfe1_ebz/tests/test_dma.sv | 98 ++++++----- .../ad_quadmxfe1_ebz/tests/test_program.sv | 117 +++++++------ .../tests/test_program_64b66b.sv | 157 +++++++++--------- .../project/adrv9001/tests/test_program.sv | 75 +++++---- .../project/adrv9009/tests/test_program.sv | 127 +++++++------- .../project/fmcomms2/tests/test_program.sv | 26 ++- .../project/mxfe/tests/test_program.sv | 155 +++++++++-------- .../project/pluto/tests/test_program.sv | 28 ++-- .../pulsar_adc_pmdz/tests/test_program.sv | 32 ++-- 39 files changed, 1245 insertions(+), 926 deletions(-) diff --git a/testbenches/ip/axi_tdd/tests/test_program.sv b/testbenches/ip/axi_tdd/tests/test_program.sv index 67cafea4..88302d78 100644 --- a/testbenches/ip/axi_tdd/tests/test_program.sv +++ b/testbenches/ip/axi_tdd/tests/test_program.sv @@ -37,6 +37,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import adi_regmap_tdd_gen_pkg::*; @@ -46,7 +47,10 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program; //instantiate the environment - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; //written variables int unsigned ch_on [32]; @@ -88,12 +92,22 @@ program test_program; //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -107,7 +121,7 @@ program test_program; // Init test data // Read the interface description - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_INTERFACE_DESCRIPTION), val); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_INTERFACE_DESCRIPTION), val); channel_count = `GET_TDDN_CNTRL_INTERFACE_DESCRIPTION_CHANNEL_COUNT_EXTRA(val); reg_count_width = `GET_TDDN_CNTRL_INTERFACE_DESCRIPTION_REGISTER_WIDTH(val); burst_count_width = `GET_TDDN_CNTRL_INTERFACE_DESCRIPTION_BURST_COUNT_WIDTH(val); @@ -117,41 +131,41 @@ program test_program; sync_ext_cdc = `GET_TDDN_CNTRL_INTERFACE_DESCRIPTION_SYNC_EXTERNAL_CDC(val); // Register configuration - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), `SET_TDDN_CNTRL_CHANNEL_ENABLE_CHANNEL_ENABLE(32'hFFFFFFFF)); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'h00000000)); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), `SET_TDDN_CNTRL_BURST_COUNT_BURST_COUNT(channel_count+1)); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), `SET_TDDN_CNTRL_STARTUP_DELAY_STARTUP_DELAY(32'h0000007F)); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), `SET_TDDN_CNTRL_FRAME_LENGTH_FRAME_LENGTH(32'h0000007F)); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), `SET_TDDN_CNTRL_SYNC_COUNTER_LOW_SYNC_COUNTER_LOW(32'h000001FF)); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_HIGH), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_HIGH), `SET_TDDN_CNTRL_SYNC_COUNTER_HIGH_SYNC_COUNTER_HIGH(32'h00000000)); // Reading back the actual register values (the values may change depending on the synthesis configuration) - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), ch_en); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), ch_en); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), burst_count); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), burst_count); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), startup_delay); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), startup_delay); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), frame_length); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), frame_length); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), sync_count_low); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), sync_count_low); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_HIGH), sync_count_high); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_HIGH), sync_count_high); // ------------------------------------------------------- @@ -167,17 +181,17 @@ program test_program; end for (int i=0; i<32; i++) begin - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, `SET_TDDN_CNTRL_CH0_ON_CH0_ON(ch_on[i])); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, `SET_TDDN_CNTRL_CH0_OFF_CH0_OFF(ch_off[i])); end // Read back the values; unimplemented channels should not store these values for (int i=0; i<32; i++) begin - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, val); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, val); if (i <= channel_count) begin expected_val = ch_on[i]; @@ -191,7 +205,7 @@ program test_program; success_count++; end - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, val); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, val); if (i <= channel_count) begin expected_val = ch_off[i]; @@ -207,7 +221,7 @@ program test_program; end // Read the status register to validate the current state - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b00) begin `FATAL(("Idle state: Expected 2'b00 found 2'b%b", current_state)); @@ -217,7 +231,7 @@ program test_program; // Enable the module; use internal sync for transfer triggering - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(1)| @@ -233,7 +247,7 @@ program test_program; // Read the status register to validate the current state repeat (8) @(posedge `TH.dut_tdd.inst.up_clk); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b10) begin `FATAL(("Waiting state: Expected 2'b10 found 2'b%b", current_state)); @@ -259,7 +273,7 @@ program test_program; // Read the status register to validate the current state issuing a parallel thread repeat (8) @(posedge `TH.dut_tdd.inst.up_clk); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b11) begin `FATAL(("Running state: Expected 2'b11 found 2'b%b", current_state)); @@ -276,7 +290,7 @@ program test_program; //*******// // Read the status register to validate the current state repeat (8) @(posedge `TH.dut_tdd.inst.up_clk); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b01) begin `FATAL(("Armed state: Expected 2'b01 found 2'b%b", current_state)); @@ -285,17 +299,17 @@ program test_program; end // Disable the module to change the polarity - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); // Switch to inverted polarity - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'hFFFFFFFF)); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); // Re-enable the module - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(1)| @@ -316,14 +330,14 @@ program test_program; // ARMED // //*******// // Disable the module - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); // Switch to direct polarity - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'h00000000)); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); // ------------------------------------------------------- @@ -339,16 +353,16 @@ program test_program; end for (int i=0; i<32; i++) begin - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, `SET_TDDN_CNTRL_CH0_ON_CH0_ON(ch_on[i])); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, `SET_TDDN_CNTRL_CH0_OFF_CH0_OFF(ch_off[i])); end // Read back the values; unimplemented channels should not store these values for (int i=0; i<32; i++) begin - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, val); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, val); if (i <= channel_count) begin expected_val = ch_on[i]; @@ -362,7 +376,7 @@ program test_program; success_count++; end - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, val); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, val); if (i <= channel_count) begin expected_val = ch_off[i]; @@ -379,7 +393,7 @@ program test_program; // Enable the module; use external sync for transfer triggering - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(0)| @@ -403,17 +417,17 @@ program test_program; // ARMED // //*******// // Disable the module - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); // Switch to inverted polarity - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'hFFFFFFFF)); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); // Keep the module enabled; issue a software sync - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(0)| @@ -434,14 +448,14 @@ program test_program; // ARMED // //*******// // Disable the module - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); // Switch to direct polarity - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'h00000000)); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); // ------------------------------------------------------- @@ -449,11 +463,11 @@ program test_program; // ------------------------------------------------------- // Increase the burst count value by 1 - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), `SET_TDDN_CNTRL_BURST_COUNT_BURST_COUNT(channel_count+2)); // Keep the module enabled; issue a software sync; enable external sync and reset on sync - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(0)| @@ -482,7 +496,7 @@ program test_program; end // Disable the module before the end of the burst - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); @(posedge `TH.dut_tdd.inst.tdd_endof_frame); @@ -490,24 +504,24 @@ program test_program; // Check the pulse length using a loop on all available channels check_pulse_length(); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), `SET_TDDN_CNTRL_CHANNEL_ENABLE_CHANNEL_ENABLE(0)); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), ch_en); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), ch_en); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), `SET_TDDN_CNTRL_BURST_COUNT_BURST_COUNT(0)); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), burst_count); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), burst_count); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), `SET_TDDN_CNTRL_STARTUP_DELAY_STARTUP_DELAY(0)); - base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), startup_delay); + base_env.mng.master_sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), startup_delay); // Enable the module with external synchronization actived - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(0)| @@ -530,7 +544,7 @@ program test_program; success_count++; end - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), `SET_TDDN_CNTRL_CHANNEL_ENABLE_CHANNEL_ENABLE(ch_en)); ch_en = (ch_en << 1) | 32'b1; @@ -548,7 +562,7 @@ program test_program; success_count++; end - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), `SET_TDDN_CNTRL_CHANNEL_ENABLE_CHANNEL_ENABLE(ch_en)); ch_en = (ch_en >> 1); @@ -556,7 +570,7 @@ program test_program; end // Disable the module - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); base_env.stop(); diff --git a/testbenches/ip/axis_sequencers/tests/test_program.sv b/testbenches/ip/axis_sequencers/tests/test_program.sv index 08600126..034918d1 100644 --- a/testbenches/ip/axis_sequencers/tests/test_program.sv +++ b/testbenches/ip/axis_sequencers/tests/test_program.sv @@ -37,6 +37,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import environment_pkg::*; import watchdog_pkg::*; import axi4stream_vip_pkg::*; @@ -52,7 +53,11 @@ import `PKGIFY(test_harness, dst_axis)::*; program test_program; // declare the class instances - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + axis_sequencer_environment #(`AXIS_VIP_PARAMS(test_harness, src_axis), `AXIS_VIP_PARAMS(test_harness, dst_axis)) axis_seq_env; watchdog send_data_wd; @@ -61,12 +66,16 @@ program test_program; // create environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) axis_seq_env = new("Axis Sequencers Environment", `TH.`SRC_AXIS.inst.IF, diff --git a/testbenches/ip/base/tests/test_program.sv b/testbenches/ip/base/tests/test_program.sv index a3bac90d..69cd3667 100644 --- a/testbenches/ip/base/tests/test_program.sv +++ b/testbenches/ip/base/tests/test_program.sv @@ -66,10 +66,10 @@ program test_program; // Create environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); mng = new("", `TH.`MNG_AXI.inst.IF); ddr = new("", `TH.`DDR_AXI.inst.IF); diff --git a/testbenches/ip/dma_flock/tests/test_program.sv b/testbenches/ip/dma_flock/tests/test_program.sv index 4370cb11..8fcd5c4b 100644 --- a/testbenches/ip/dma_flock/tests/test_program.sv +++ b/testbenches/ip/dma_flock/tests/test_program.sv @@ -38,6 +38,7 @@ import logger_pkg::*; import environment_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; import adi_regmap_pkg::*; @@ -54,7 +55,11 @@ import `PKGIFY(test_harness, dst_axis_vip)::*; program test_program; // declare the class instances - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + dma_flock_environment #(`AXIS_VIP_PARAMS(test_harness, src_axis_vip), `AXIS_VIP_PARAMS(test_harness, dst_axis_vip)) dma_flock_env; // Register accessors @@ -69,12 +74,16 @@ program test_program; initial begin //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) dma_flock_env = new("DMA Flock Environment", `TH.`SRC_AXIS.inst.IF, @@ -94,10 +103,10 @@ program test_program; dma_flock_env.run(); - m_dmac_api = new("TX_DMA_BA", base_env.mng.sequencer, `TX_DMA_BA); + m_dmac_api = new("TX_DMA_BA", base_env.mng.master_sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA_BA", base_env.mng.sequencer, `RX_DMA_BA); + s_dmac_api = new("RX_DMA_BA", base_env.mng.master_sequencer, `RX_DMA_BA); s_dmac_api.probe(); sanity_test; @@ -249,16 +258,16 @@ program test_program; bit [63:0] mtestWData; // Write Data bit [31:0] rdData; - base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); + base_env.mng.master_sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); mtestWData = 0; repeat (10) begin - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); - base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); + base_env.mng.master_sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); mtestWData += 4; end - base_env.mng.sequencer.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); + base_env.mng.master_sequencer.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); endtask diff --git a/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv b/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv index 6595545f..ae7a895f 100644 --- a/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv +++ b/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv @@ -38,6 +38,7 @@ import logger_pkg::*; import environment_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; @@ -54,7 +55,11 @@ import `PKGIFY(test_harness, dst_axis_vip)::*; program test_program_frame_delay; // declare the class instances - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + dma_flock_environment #(`AXIS_VIP_PARAMS(test_harness, src_axis_vip), `AXIS_VIP_PARAMS(test_harness, dst_axis_vip)) dma_flock_env; // Register accessors @@ -72,12 +77,16 @@ program test_program_frame_delay; //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) dma_flock_env = new("DMA Flock Environment", `TH.`SRC_AXIS.inst.IF, @@ -99,10 +108,10 @@ program test_program_frame_delay; dma_flock_env.run(); - m_dmac_api = new("TX_DMA_BA", base_env.mng.sequencer, `TX_DMA_BA); + m_dmac_api = new("TX_DMA_BA", base_env.mng.master_sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA_BA", base_env.mng.sequencer, `RX_DMA_BA); + s_dmac_api = new("RX_DMA_BA", base_env.mng.master_sequencer, `RX_DMA_BA); s_dmac_api.probe(); @@ -303,16 +312,16 @@ program test_program_frame_delay; bit [63:0] mtestWData; // Write Data bit [31:0] rdData; - base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); + base_env.mng.master_sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); mtestWData = 0; repeat (10) begin - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); - base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); + base_env.mng.master_sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); mtestWData += 4; end - base_env.mng.sequencer.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); + base_env.mng.master_sequencer.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); endtask diff --git a/testbenches/ip/dma_loopback/tests/test_program.sv b/testbenches/ip/dma_loopback/tests/test_program.sv index d8c01de1..4e403c3b 100644 --- a/testbenches/ip/dma_loopback/tests/test_program.sv +++ b/testbenches/ip/dma_loopback/tests/test_program.sv @@ -37,6 +37,7 @@ `include "axi_definitions.svh" import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import logger_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; @@ -49,7 +50,10 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // Register accessors dmac_api m_dmac_api; @@ -59,12 +63,16 @@ program test_program; //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -72,10 +80,10 @@ program test_program; start_clocks(); base_env.sys_reset(); - m_dmac_api = new("TX_DMA", base_env.mng.sequencer, `TX_DMA_BA); + m_dmac_api = new("TX_DMA", base_env.mng.master_sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA", base_env.mng.sequencer, `RX_DMA_BA); + s_dmac_api = new("RX_DMA", base_env.mng.master_sequencer, `RX_DMA_BA); s_dmac_api.probe(); // ------------------------------------------------------- diff --git a/testbenches/ip/dma_sg/tests/test_program_1d.sv b/testbenches/ip/dma_sg/tests/test_program_1d.sv index 54aaac2e..2c46d74a 100644 --- a/testbenches/ip/dma_sg/tests/test_program_1d.sv +++ b/testbenches/ip/dma_sg/tests/test_program_1d.sv @@ -37,6 +37,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; @@ -48,7 +49,10 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program_1d; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // Register accessors dmac_api m_dmac_api; @@ -58,12 +62,16 @@ program test_program_1d; // Creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -71,10 +79,10 @@ program test_program_1d; `TH.`DEVICE_CLK.inst.IF.start_clock(); base_env.sys_reset(); - m_dmac_api = new("TX_DMA", base_env.mng.sequencer, `TX_DMA_BA); + m_dmac_api = new("TX_DMA", base_env.mng.master_sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA", base_env.mng.sequencer, `RX_DMA_BA); + s_dmac_api = new("RX_DMA", base_env.mng.master_sequencer, `RX_DMA_BA); s_dmac_api.probe(); #1us; @@ -187,25 +195,25 @@ program test_program_1d; dma_segment m_seg, s_seg; int m_tid, s_tid; - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr); //TX descriptor first address - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr); //TX descriptor first address + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC `SET_DMAC_CONTROL_HWDESC(1) | `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr); //RX descriptor first address - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr); //RX descriptor first address + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC `SET_DMAC_CONTROL_HWDESC(1) | `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr+'hC0); //RX descriptor first address - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr+'hC0); //RX descriptor first address + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); m_dmac_api.transfer_id_get(m_tid); diff --git a/testbenches/ip/dma_sg/tests/test_program_2d.sv b/testbenches/ip/dma_sg/tests/test_program_2d.sv index 4b898d98..bb5a6ee8 100644 --- a/testbenches/ip/dma_sg/tests/test_program_2d.sv +++ b/testbenches/ip/dma_sg/tests/test_program_2d.sv @@ -37,6 +37,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; @@ -48,7 +49,10 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program_2d; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // Register accessors dmac_api m_dmac_api; @@ -58,12 +62,16 @@ program test_program_2d; // Creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -71,10 +79,10 @@ program test_program_2d; `TH.`DEVICE_CLK.inst.IF.start_clock(); base_env.sys_reset(); - m_dmac_api = new("TX_DMA", base_env.mng.sequencer, `TX_DMA_BA); + m_dmac_api = new("TX_DMA", base_env.mng.master_sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA", base_env.mng.sequencer, `RX_DMA_BA); + s_dmac_api = new("RX_DMA", base_env.mng.master_sequencer, `RX_DMA_BA); s_dmac_api.probe(); #1us; @@ -181,25 +189,25 @@ program test_program_2d; dma_segment m_seg, s_seg; int m_tid, s_tid; - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr); //TX descriptor first address - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr); //TX descriptor first address + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC `SET_DMAC_CONTROL_HWDESC(1) | `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr); //RX descriptor first address - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr); //RX descriptor first address + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC `SET_DMAC_CONTROL_HWDESC(1) | `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr+'h90); //RX descriptor first address - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr+'h90); //RX descriptor first address + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); m_dmac_api.transfer_id_get(m_tid); diff --git a/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv b/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv index 791ea803..e2986a48 100644 --- a/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv +++ b/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv @@ -37,6 +37,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; @@ -48,7 +49,10 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program_tr_queue; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // Register accessors dmac_api m_dmac_api; @@ -58,12 +62,16 @@ program test_program_tr_queue; // Creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -71,10 +79,10 @@ program test_program_tr_queue; `TH.`DEVICE_CLK.inst.IF.start_clock(); base_env.sys_reset(); - m_dmac_api = new("TX_DMA", base_env.mng.sequencer, `TX_DMA_BA); + m_dmac_api = new("TX_DMA", base_env.mng.master_sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA", base_env.mng.sequencer, `RX_DMA_BA); + s_dmac_api = new("RX_DMA", base_env.mng.master_sequencer, `RX_DMA_BA); s_dmac_api.probe(); #1us; @@ -193,37 +201,37 @@ program test_program_tr_queue; dma_segment m_seg, s_seg; int m_tid, s_tid; - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr); //TX descriptor first address - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr); //TX descriptor first address + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC `SET_DMAC_CONTROL_HWDESC(1) | `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr); //RX descriptor first address - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr); //RX descriptor first address + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC `SET_DMAC_CONTROL_HWDESC(1) | `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), //Test 4 consecutive TX transfers in queue + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), //Test 4 consecutive TX transfers in queue `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr+'h60); //TX descriptor first address - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr+'h60); //TX descriptor first address + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr+'hC0); //TX descriptor first address - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr+'hC0); //TX descriptor first address + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr+'h120); //TX descriptor first address - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr+'h120); //TX descriptor first address + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr+'h90); //RX descriptor first address - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr+'h90); //RX descriptor first address + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); m_dmac_api.transfer_id_get(m_tid); diff --git a/testbenches/ip/hbm/tests/test_program.sv b/testbenches/ip/hbm/tests/test_program.sv index 2382b674..475dea9a 100644 --- a/testbenches/ip/hbm/tests/test_program.sv +++ b/testbenches/ip/hbm/tests/test_program.sv @@ -36,6 +36,7 @@ `include "utils.svh" import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; @@ -51,7 +52,10 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; bit [31:0] val; bit [31:0] src_addr; @@ -60,12 +64,16 @@ program test_program; //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -109,27 +117,27 @@ program test_program; // bit [31:0] length); // // // Configure TX DMA -// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_CONTROL), +// base_env.mng.master_sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_CONTROL), // `SET_dmac_CONTROL_ENABLE(1)); -// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_FLAGS), +// base_env.mng.master_sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_FLAGS), // `SET_dmac_FLAGS_TLAST(32'h00000006)); -// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_X_LENGTH), +// base_env.mng.master_sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_X_LENGTH), // `SET_dmac_X_LENGTH_X_LENGTH(length-1)); -// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_SRC_ADDRESS), +// base_env.mng.master_sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_SRC_ADDRESS), // `SET_dmac_SRC_ADDRESS_SRC_ADDRESS(src_addr)); -// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), +// base_env.mng.master_sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), // `SET_dmac_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // // // Configure RX DMA -// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_CONTROL), +// base_env.mng.master_sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_CONTROL), // `SET_dmac_CONTROL_ENABLE(1)); -// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_FLAGS), +// base_env.mng.master_sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_FLAGS), // `SET_dmac_FLAGS_TLAST(32'h00000006)); -// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_X_LENGTH), +// base_env.mng.master_sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_X_LENGTH), // `SET_dmac_X_LENGTH_X_LENGTH(length-1)); -// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_DEST_ADDRESS), +// base_env.mng.master_sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_DEST_ADDRESS), // `SET_dmac_DEST_ADDRESS_DEST_ADDRESS(dest_addr)); -// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), +// base_env.mng.master_sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), // `SET_dmac_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // endtask // diff --git a/testbenches/ip/i3c_controller/tests/test_program.sv b/testbenches/ip/i3c_controller/tests/test_program.sv index 9914da5f..bf4f4cc6 100755 --- a/testbenches/ip/i3c_controller/tests/test_program.sv +++ b/testbenches/ip/i3c_controller/tests/test_program.sv @@ -43,6 +43,7 @@ import axi_vip_pkg::*; import axi4stream_vip_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import `PKGIFY(test_harness, mng_axi_vip)::*; import `PKGIFY(test_harness, ddr_axi_vip)::*; @@ -146,7 +147,10 @@ program test_program ( output offload_sdi_ready, output offload_trigger); -test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; +test_harness_env base_env; + +adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; +adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; //--------------------------------------------------------------------------- // Wrapper function for AXI read verify using dword @@ -156,7 +160,7 @@ task axi_read_v( input [13:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(baddr+{raddr,2'b00},vdata); + base_env.mng.master_sequencer.RegReadVerify32(baddr+{raddr,2'b00},vdata); endtask task axi_read( @@ -164,7 +168,7 @@ task axi_read( input [13:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(baddr+{raddr,2'b00},data); + base_env.mng.master_sequencer.RegRead32(baddr+{raddr,2'b00},data); endtask //--------------------------------------------------------------------------- @@ -175,7 +179,7 @@ task axi_write( input [13:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(baddr+{waddr,2'b00},wdata); + base_env.mng.master_sequencer.RegWrite32(baddr+{waddr,2'b00},wdata); endtask //--------------------------------------------------------------------------- @@ -254,12 +258,16 @@ initial begin // Creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); diff --git a/testbenches/ip/jesd_loopback/tests/test_program.sv b/testbenches/ip/jesd_loopback/tests/test_program.sv index 173237e3..42dd5022 100644 --- a/testbenches/ip/jesd_loopback/tests/test_program.sv +++ b/testbenches/ip/jesd_loopback/tests/test_program.sv @@ -37,6 +37,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import adi_regmap_jesd_tx_pkg::*; import adi_regmap_jesd_rx_pkg::*; @@ -62,7 +63,11 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + bit [31:0] val; jesd_link link; @@ -79,12 +84,16 @@ program test_program; //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -102,16 +111,16 @@ program test_program; link.set_encoding(`LINK_MODE == `MODE_8B10B ? enc8b10b : enc64b66b); link.set_lane_rate(lane_rate); - rx_ll = new("RX_LINK_LAYER", base_env.mng.sequencer, `AXI_JESD_RX_BA, link); + rx_ll = new("RX_LINK_LAYER", base_env.mng.master_sequencer, `AXI_JESD_RX_BA, link); rx_ll.probe(); - tx_ll = new("TX_LINK_LAYER", base_env.mng.sequencer, `AXI_JESD_TX_BA, link); + tx_ll = new("TX_LINK_LAYER", base_env.mng.master_sequencer, `AXI_JESD_TX_BA, link); tx_ll.probe(); - rx_xcvr = new("RX_XCVR", base_env.mng.sequencer, `ADC_XCVR_BA); + rx_xcvr = new("RX_XCVR", base_env.mng.master_sequencer, `ADC_XCVR_BA); rx_xcvr.probe(); - tx_xcvr = new("TX_XCVR", base_env.mng.sequencer, `DAC_XCVR_BA); + tx_xcvr = new("TX_XCVR", base_env.mng.master_sequencer, `DAC_XCVR_BA); tx_xcvr.probe(); `TH.`REF_CLK.inst.IF.set_clk_frq(.user_frequency(`REF_CLK_RATE*1000000)); @@ -139,7 +148,7 @@ program test_program; jesd_link_test(); // Check link restart counter - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + 'h2c4, 1); + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA + 'h2c4, 1); // ======================= // TPL SYNC control test @@ -175,26 +184,26 @@ program test_program; for (int i = 0; i < `JESD_M; i++) begin if (use_dds) begin // Select DDS as source - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h0fff)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); end else begin // Set DMA as source for DAC TPL - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); end end - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(1)); if (use_dds) begin // Sync DDS cores - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); end @@ -209,11 +218,11 @@ program test_program; // Configure ADC TPL // ----------------------- for (int i = 0; i < `JESD_M; i++) begin - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + 'h40 * i + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + 'h40 * i + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); end - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1)); rx_ll.link_up(); @@ -225,13 +234,13 @@ program test_program; #5us; // Arm external sync - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1),2); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + 'h48,2); + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1),2); + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + 'h48,2); #1us; // Check if armed - base_env.mng.sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), `SET_DAC_COMMON_REG_SYNC_STATUS_DAC_SYNC_STATUS(1)); - base_env.mng.sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), `SET_ADC_COMMON_REG_SYNC_STATUS_ADC_SYNC(1)); #1us; // Trigger external sync @@ -242,7 +251,7 @@ program test_program; #1us; // Check if trigger captured - base_env.mng.sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), `SET_DAC_COMMON_REG_SYNC_STATUS_DAC_SYNC_STATUS(0)); #5us; @@ -259,17 +268,17 @@ program test_program; @(posedge system_tb.sysref); @(negedge system_tb.sysref); // Check SYSREF alignment ERROR - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), `SET_JESD_TX_SYSREF_STATUS_SYSREF_ALIGNMENT_ERROR(1) | `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), `SET_JESD_RX_SYSREF_STATUS_SYSREF_ALIGNMENT_ERROR(1) | `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), `SET_JESD_TX_SYSREF_STATUS_SYSREF_ALIGNMENT_ERROR(1) | `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), `SET_JESD_RX_SYSREF_STATUS_SYSREF_ALIGNMENT_ERROR(1) | `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); @@ -280,17 +289,17 @@ program test_program; @(posedge system_tb.sysref); @(negedge system_tb.sysref); // Check SYSREF alignment ERROR - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), `SET_JESD_TX_SYSREF_STATUS_SYSREF_ALIGNMENT_ERROR(1) | `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), `SET_JESD_RX_SYSREF_STATUS_SYSREF_ALIGNMENT_ERROR(1) | `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), `SET_JESD_TX_SYSREF_STATUS_SYSREF_ALIGNMENT_ERROR(1) | `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), `SET_JESD_RX_SYSREF_STATUS_SYSREF_ALIGNMENT_ERROR(1) | `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); @@ -310,25 +319,25 @@ program test_program; // ----------------- task arm_disarm_test(); // Arm external sync - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1),2); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + 'h48,2); + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1),2); + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + 'h48,2); #1us; // Check if armed - base_env.mng.sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), `SET_DAC_COMMON_REG_SYNC_STATUS_DAC_SYNC_STATUS(1)); - base_env.mng.sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), `SET_ADC_COMMON_REG_SYNC_STATUS_ADC_SYNC(1)); // DisArm external sync - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1),4); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + 'h48,4); + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1),4); + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + 'h48,4); #1us; // Check if disarmed - base_env.mng.sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), `SET_DAC_COMMON_REG_SYNC_STATUS_DAC_SYNC_STATUS(0)); - base_env.mng.sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), `SET_ADC_COMMON_REG_SYNC_STATUS_ADC_SYNC(0)); `INFO(("======================="), ADI_VERBOSITY_LOW); `INFO((" ARM-DISARM TEST DONE "), ADI_VERBOSITY_LOW); @@ -371,18 +380,18 @@ program test_program; ); end // set TXOUTCLKSEL to 3'b010 (TXOUTCLKPMA) - base_env.mng.sequencer.RegRead32(`DAC_XCVR_BA + GetAddrs(XCVR_CONTROL), val); + base_env.mng.master_sequencer.RegRead32(`DAC_XCVR_BA + GetAddrs(XCVR_CONTROL), val); tx_out_clk_sel = `GET_XCVR_CONTROL_OUTCLK_SEL(val); - base_env.mng.sequencer.RegWrite32(`DAC_XCVR_BA + GetAddrs(XCVR_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`DAC_XCVR_BA + GetAddrs(XCVR_CONTROL), val & (~{32'b111} << 0) | `SET_XCVR_CONTROL_OUTCLK_SEL(2)); // set RXOUTCLKSEL to 3'b010 (RXOUTCLKPMA) - base_env.mng.sequencer.RegRead32(`ADC_XCVR_BA + GetAddrs(XCVR_CONTROL), val); + base_env.mng.master_sequencer.RegRead32(`ADC_XCVR_BA + GetAddrs(XCVR_CONTROL), val); rx_out_clk_sel = `GET_XCVR_CONTROL_OUTCLK_SEL(val); - base_env.mng.sequencer.RegWrite32(`ADC_XCVR_BA + GetAddrs(XCVR_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`ADC_XCVR_BA + GetAddrs(XCVR_CONTROL), val & (~{32'b111} << 0) | `SET_XCVR_CONTROL_OUTCLK_SEL(2)); @@ -396,36 +405,36 @@ program test_program; // ----------------------- // Put XCVR in PRBS mode // ----------------------- - base_env.mng.sequencer.RegWrite32(`DAC_XCVR_BA + 32'h0180, `PRBS_9); - base_env.mng.sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, `PRBS_7); + base_env.mng.master_sequencer.RegWrite32(`DAC_XCVR_BA + 32'h0180, `PRBS_9); + base_env.mng.master_sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, `PRBS_7); #1us; // Error should be detected - base_env.mng.sequencer.RegReadVerify32(`ADC_XCVR_BA + 32'h0184, 1<<8 | 0); + base_env.mng.master_sequencer.RegReadVerify32(`ADC_XCVR_BA + 32'h0184, 1<<8 | 0); // Check if error can be cleared - base_env.mng.sequencer.RegWrite32(`DAC_XCVR_BA + 32'h0180, `PRBS_7); - base_env.mng.sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, `PRBS_7 | 1 << 8); // Set prbs err cntr reset - base_env.mng.sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, `PRBS_7 | 0 << 8); // Clear prbs err cntr reset + base_env.mng.master_sequencer.RegWrite32(`DAC_XCVR_BA + 32'h0180, `PRBS_7); + base_env.mng.master_sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, `PRBS_7 | 1 << 8); // Set prbs err cntr reset + base_env.mng.master_sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, `PRBS_7 | 0 << 8); // Clear prbs err cntr reset #1us; // No error should be detected, Lock should be set - base_env.mng.sequencer.RegReadVerify32(`ADC_XCVR_BA + 32'h0184, 0<<8 | 1); + base_env.mng.master_sequencer.RegReadVerify32(`ADC_XCVR_BA + 32'h0184, 0<<8 | 1); // ----------------------- // Check Error injection // ----------------------- - base_env.mng.sequencer.RegWrite32(`DAC_XCVR_BA + 32'h0180, `PRBS_7 | 1<<16 ); // Enable Error inject - base_env.mng.sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, 1 << 8); // Clear prbs err - base_env.mng.sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, `PRBS_7); + base_env.mng.master_sequencer.RegWrite32(`DAC_XCVR_BA + 32'h0180, `PRBS_7 | 1<<16 ); // Enable Error inject + base_env.mng.master_sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, 1 << 8); // Clear prbs err + base_env.mng.master_sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, `PRBS_7); #1us; // Error should be detected - base_env.mng.sequencer.RegReadVerify32(`ADC_XCVR_BA + 32'h0184, 1<<8 | 0); + base_env.mng.master_sequencer.RegReadVerify32(`ADC_XCVR_BA + 32'h0184, 1<<8 | 0); - base_env.mng.sequencer.RegWrite32(`DAC_XCVR_BA + 32'h0180, `PRBS_OFF); - base_env.mng.sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, 1 << 8); // Clear prbs err - base_env.mng.sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, `PRBS_OFF); + base_env.mng.master_sequencer.RegWrite32(`DAC_XCVR_BA + 32'h0180, `PRBS_OFF); + base_env.mng.master_sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, 1 << 8); // Clear prbs err + base_env.mng.master_sequencer.RegWrite32(`ADC_XCVR_BA + 32'h0180, `PRBS_OFF); rx_xcvr.down(); tx_xcvr.down(); @@ -451,14 +460,14 @@ program test_program; ); end // set TXOUTCLKSEL old value - base_env.mng.sequencer.RegRead32(`DAC_XCVR_BA + GetAddrs(XCVR_CONTROL), val); - base_env.mng.sequencer.RegWrite32(`DAC_XCVR_BA + GetAddrs(XCVR_CONTROL), + base_env.mng.master_sequencer.RegRead32(`DAC_XCVR_BA + GetAddrs(XCVR_CONTROL), val); + base_env.mng.master_sequencer.RegWrite32(`DAC_XCVR_BA + GetAddrs(XCVR_CONTROL), val & (~{32'b111} << 0) | `SET_XCVR_CONTROL_OUTCLK_SEL(tx_out_clk_sel)); // set RXOUTCLKSEL to 3'b010 (RXOUTCLKPMA) - base_env.mng.sequencer.RegRead32(`ADC_XCVR_BA + GetAddrs(XCVR_CONTROL), val); - base_env.mng.sequencer.RegWrite32(`ADC_XCVR_BA + GetAddrs(XCVR_CONTROL), + base_env.mng.master_sequencer.RegRead32(`ADC_XCVR_BA + GetAddrs(XCVR_CONTROL), val); + base_env.mng.master_sequencer.RegWrite32(`ADC_XCVR_BA + GetAddrs(XCVR_CONTROL), val & (~{32'b111} << 0) | `SET_XCVR_CONTROL_OUTCLK_SEL(rx_out_clk_sel)); diff --git a/testbenches/ip/jesd_loopback_64b/tests/test_program.sv b/testbenches/ip/jesd_loopback_64b/tests/test_program.sv index 7f817687..5496b9d4 100644 --- a/testbenches/ip/jesd_loopback_64b/tests/test_program.sv +++ b/testbenches/ip/jesd_loopback_64b/tests/test_program.sv @@ -37,6 +37,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_jesd_tx_pkg::*; @@ -52,7 +53,11 @@ parameter OUT_BYTES = (`JESD_F % 3 != 0) ? 8 : 12; program test_program; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + bit [31:0] val; int link_clk_freq_khz; int device_clk_freq_khz; @@ -69,12 +74,16 @@ program test_program; //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -103,77 +112,77 @@ program test_program; for (int i = 0; i < `JESD_M; i++) begin if (use_dds) begin // Select DDS as source - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h0fff)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); end else begin // Set DMA as source for DAC TPL - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); end end for (int i = 0; i < `JESD_M; i++) begin - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA+'h40*i+GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+'h40*i+GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); end - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA+GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1)); // Sync DDS cores - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); //LINK DISABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); //SYSREFCONF - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_CONF), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_CONF), `SET_JESD_RX_SYSREF_CONF_SYSREF_DISABLE(0)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_CONF), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_CONF), `SET_JESD_TX_SYSREF_CONF_SYSREF_DISABLE(0)); //CONF0 - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF0), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF0), `SET_JESD_RX_LINK_CONF0_OCTETS_PER_FRAME(`JESD_F-1) | `SET_JESD_RX_LINK_CONF0_OCTETS_PER_MULTIFRAME(`JESD_F*`JESD_K-1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF0), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF0), `SET_JESD_TX_LINK_CONF0_OCTETS_PER_FRAME(`JESD_F-1) | `SET_JESD_TX_LINK_CONF0_OCTETS_PER_MULTIFRAME(`JESD_F*`JESD_K-1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF4), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF4), `SET_JESD_RX_LINK_CONF4_TPL_BEATS_PER_MULTIFRAME((`JESD_F*`JESD_K)/`LL_OUT_BYTES-1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF4), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF4), `SET_JESD_TX_LINK_CONF4_TPL_BEATS_PER_MULTIFRAME((`JESD_F*`JESD_K)/`LL_OUT_BYTES-1)); //CONF1 - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF1), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF1), `SET_JESD_RX_LINK_CONF1_DESCRAMBLER_DISABLE(0)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF1), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF1), `SET_JESD_TX_LINK_CONF1_SCRAMBLER_DISABLE(0)); //CONF2 - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF2), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF2), `SET_JESD_TX_LINK_CONF2_CONTINUOUS_CGS(0)); //LINK ENABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); #25us; // Read status back - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_STATUS), `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); #1us; @@ -182,22 +191,22 @@ program test_program; // -------------------------------------- //LINK DISABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); #1us; //LINK ENABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); #25us; // Read status back - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_STATUS), `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); base_env.stop(); diff --git a/testbenches/ip/scoreboard/tests/test_program.sv b/testbenches/ip/scoreboard/tests/test_program.sv index b902be64..dff3d1f8 100644 --- a/testbenches/ip/scoreboard/tests/test_program.sv +++ b/testbenches/ip/scoreboard/tests/test_program.sv @@ -96,14 +96,14 @@ program test_program(); // create environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); mng = new("", `TH.`MNG_AXI.inst.IF); ddr = new("", `TH.`DDR_AXI.inst.IF); - + `LINK(mng, base_env, mng) `LINK(ddr, base_env, ddr) diff --git a/testbenches/ip/spi_engine/tests/test_program.sv b/testbenches/ip/spi_engine/tests/test_program.sv index d5275b7c..74eed918 100644 --- a/testbenches/ip/spi_engine/tests/test_program.sv +++ b/testbenches/ip/spi_engine/tests/test_program.sv @@ -41,6 +41,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import spi_environment_pkg::*; import axi4stream_vip_pkg::*; import adi_regmap_pkg::*; @@ -73,7 +74,11 @@ program test_program ( timeprecision 100ps; // declare the class instances - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + spi_environment spi_env; // -------------------------- @@ -82,13 +87,13 @@ program test_program ( task axi_read_v( input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); + base_env.mng.master_sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -97,7 +102,7 @@ program test_program ( task axi_write( input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -131,12 +136,16 @@ program test_program ( //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) spi_env = new("SPI Engine Environment", `ifdef DEF_SDO_STREAMING @@ -288,14 +297,14 @@ program test_program ( task offload_spi_test(); //Configure DMA - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Configure the Offload module axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG); diff --git a/testbenches/ip/spi_engine/tests/test_sleep_delay.sv b/testbenches/ip/spi_engine/tests/test_sleep_delay.sv index c185d788..73c84ebe 100644 --- a/testbenches/ip/spi_engine/tests/test_sleep_delay.sv +++ b/testbenches/ip/spi_engine/tests/test_sleep_delay.sv @@ -39,6 +39,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import spi_environment_pkg::*; import axi4stream_vip_pkg::*; import adi_regmap_pkg::*; @@ -71,7 +72,11 @@ program test_sleep_delay ( timeprecision 100ps; // declare the class instances - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + spi_environment spi_env; // -------------------------- @@ -80,13 +85,13 @@ program test_sleep_delay ( task axi_read_v( input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); + base_env.mng.master_sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -95,7 +100,7 @@ program test_sleep_delay ( task axi_write( input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -132,9 +137,13 @@ program test_sleep_delay ( `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) spi_env = new("SPI Engine Environment", `ifdef DEF_SDO_STREAMING @@ -386,14 +395,14 @@ program test_sleep_delay ( `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); //Configure DMA - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Enable SPI Engine axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); @@ -468,7 +477,7 @@ program test_sleep_delay ( `INFO(("CS Delay Test PASSED"), ADI_VERBOSITY_LOW); #2000ns - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(1)); axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(0)); diff --git a/testbenches/ip/spi_engine/tests/test_slowdata.sv b/testbenches/ip/spi_engine/tests/test_slowdata.sv index fd023ccb..82f87453 100644 --- a/testbenches/ip/spi_engine/tests/test_slowdata.sv +++ b/testbenches/ip/spi_engine/tests/test_slowdata.sv @@ -41,6 +41,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import spi_environment_pkg::*; import axi4stream_vip_pkg::*; import adi_regmap_pkg::*; @@ -72,7 +73,11 @@ program test_slowdata ( timeunit 1ns; timeprecision 100ps; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + spi_environment spi_env; // -------------------------- @@ -81,13 +86,13 @@ program test_slowdata ( task axi_read_v( input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); + base_env.mng.master_sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -96,7 +101,7 @@ program test_slowdata ( task axi_write( input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -133,9 +138,13 @@ program test_slowdata ( `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) spi_env = new("SPI Engine Environment", `ifdef DEF_SDO_STREAMING @@ -524,14 +533,14 @@ program test_slowdata ( `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); //Configure DMA - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Configure the Offload module axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG); diff --git a/testbenches/ip/util_axis_fifo/tests/test_program.sv b/testbenches/ip/util_axis_fifo/tests/test_program.sv index 3f124c2d..7caf952a 100644 --- a/testbenches/ip/util_axis_fifo/tests/test_program.sv +++ b/testbenches/ip/util_axis_fifo/tests/test_program.sv @@ -38,6 +38,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import environment_pkg::*; import watchdog_pkg::*; @@ -50,7 +51,11 @@ import `PKGIFY(test_harness, output_axis)::*; program test_program (); // declare the class instances - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + util_axis_fifo_environment #(`AXIS_VIP_PARAMS(test_harness, input_axis), `AXIS_VIP_PARAMS(test_harness, output_axis), `INPUT_CLK, `OUTPUT_CLK) uaf_env; watchdog send_data_wd; @@ -59,12 +64,16 @@ program test_program (); // create environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) uaf_env = new("Util AXIS FIFO Environment", `TH.`INPUT_CLK_VIP.inst.IF, diff --git a/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv index 9caafd9b..3c95833f 100644 --- a/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv +++ b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv @@ -38,6 +38,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import environment_pkg::*; import watchdog_pkg::*; @@ -50,7 +51,11 @@ import `PKGIFY(test_harness, output_axis)::*; program test_program (); // declare the class instances - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + util_axis_fifo_environment #(`AXIS_VIP_PARAMS(test_harness, input_axis), `AXIS_VIP_PARAMS(test_harness, output_axis), `INPUT_CLK, `OUTPUT_CLK) uaf_env; watchdog send_data_wd; @@ -59,12 +64,16 @@ program test_program (); // create environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) uaf_env = new("Util AXIS FIFO Environment", `TH.`INPUT_CLK_VIP.inst.IF, diff --git a/testbenches/ip/util_pack/tests/test_program.sv b/testbenches/ip/util_pack/tests/test_program.sv index 83e520d6..a0ce7f92 100644 --- a/testbenches/ip/util_pack/tests/test_program.sv +++ b/testbenches/ip/util_pack/tests/test_program.sv @@ -39,6 +39,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import environment_pkg::*; import dmac_api_pkg::*; import watchdog_pkg::*; @@ -54,7 +55,11 @@ import `PKGIFY(test_harness, rx_dst_axis)::*; program test_program; // declare the class instances - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + util_pack_environment #(`AXIS_VIP_PARAMS(test_harness, tx_src_axis), `AXIS_VIP_PARAMS(test_harness, tx_dst_axis), `AXIS_VIP_PARAMS(test_harness, rx_src_axis), `AXIS_VIP_PARAMS(test_harness, rx_dst_axis)) pack_env; watchdog packer_scoreboard_wd; @@ -70,12 +75,16 @@ program test_program; // create environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) pack_env = new("Util Pack Environment", `TH.`TX_SRC_AXIS.inst.IF, @@ -83,8 +92,8 @@ program test_program; `TH.`RX_SRC_AXIS.inst.IF, `TH.`RX_DST_AXIS.inst.IF); - dmac_tx = new("DMAC TX 0", base_env.mng.sequencer, `TX_DMA_BA); - dmac_rx = new("DMAC RX 0", base_env.mng.sequencer, `RX_DMA_BA); + dmac_tx = new("DMAC TX 0", base_env.mng.master_sequencer, `TX_DMA_BA); + dmac_rx = new("DMAC RX 0", base_env.mng.master_sequencer, `RX_DMA_BA); base_env.start(); pack_env.start(); diff --git a/testbenches/project/ad463x/tests/test_program.sv b/testbenches/project/ad463x/tests/test_program.sv index 0b19dd4d..0146395e 100644 --- a/testbenches/project/ad463x/tests/test_program.sv +++ b/testbenches/project/ad463x/tests/test_program.sv @@ -46,6 +46,7 @@ import adi_regmap_pwm_gen_pkg::*; import adi_regmap_spi_engine_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import `PKGIFY(test_harness, mng_axi_vip)::*; import `PKGIFY(test_harness, ddr_axi_vip)::*; @@ -101,7 +102,10 @@ program test_program ( input ad463x_spi_clk, input [(`NUM_OF_SDI - 1):0] ad463x_spi_sdi); -test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; +test_harness_env base_env; + +adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; +adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // -------------------------- // Wrapper function for AXI read verify @@ -110,14 +114,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); + base_env.mng.master_sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -127,7 +131,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -137,12 +141,16 @@ initial begin //creating environment base_env = new("AD463X Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -445,14 +453,14 @@ bit [31:0] offload_captured_word_arr [(2 * NUM_OF_TRANSFERS) -1 :0]; task offload_spi_test(); //Configure DMA - base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.master_sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*2)-1)); // X_LENGHTH = 1024-1 - base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.master_sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*2)-1)); // X_LENGHTH = 1024-1 + base_env.mng.master_sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.master_sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module diff --git a/testbenches/project/ad57xx/tests/test_program.sv b/testbenches/project/ad57xx/tests/test_program.sv index dd564468..88a9bc5b 100644 --- a/testbenches/project/ad57xx/tests/test_program.sv +++ b/testbenches/project/ad57xx/tests/test_program.sv @@ -37,6 +37,7 @@ import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import ad57xx_environment_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; @@ -64,7 +65,11 @@ timeprecision 100ps; typedef enum {DATA_MODE_RANDOM, DATA_MODE_RAMP, DATA_MODE_PATTERN} offload_test_t; -test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; +test_harness_env base_env; + +adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; +adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + ad57xx_environment spi_env; // -------------------------- @@ -73,13 +78,13 @@ ad57xx_environment spi_env; task axi_read_v( input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); + base_env.mng.master_sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -88,7 +93,7 @@ endtask task axi_write( input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -123,12 +128,16 @@ initial begin //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) spi_env = new("SPI Environment", `TH.`SPI_S.inst.IF.vif); @@ -285,14 +294,14 @@ task offload_spi_test( end //Configure TX DMA - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA)); - base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA)); + base_env.mng.master_sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Configure the Offload module axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG); diff --git a/testbenches/project/ad738x/tests/test_program.sv b/testbenches/project/ad738x/tests/test_program.sv index dc8058bb..579c4757 100644 --- a/testbenches/project/ad738x/tests/test_program.sv +++ b/testbenches/project/ad738x/tests/test_program.sv @@ -46,6 +46,7 @@ import adi_regmap_pwm_gen_pkg::*; import adi_regmap_spi_engine_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import `PKGIFY(test_harness, mng_axi_vip)::*; import `PKGIFY(test_harness, ddr_axi_vip)::*; @@ -101,7 +102,10 @@ program test_program ( input ad738x_spi_cs); -test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; +test_harness_env base_env; + +adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; +adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // -------------------------- // Wrapper function for AXI read verif @@ -110,14 +114,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); + base_env.mng.master_sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -127,7 +131,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -137,12 +141,16 @@ initial begin //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -419,14 +427,14 @@ task offload_spi_test(); `INFO(("Axi_pwm_gen started"), ADI_VERBOSITY_LOW); //Configure DMA - base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.master_sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*2)-1)); // X_LENGHTH = 1024-1 - base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.master_sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*2)-1)); // X_LENGHTH = 1024-1 + base_env.mng.master_sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.master_sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module axi_write (`SPI_AD738x_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), INST_CFG); diff --git a/testbenches/project/ad7606x/tests/test_program_4ch.sv b/testbenches/project/ad7606x/tests/test_program_4ch.sv index b259a2bc..6f694cac 100755 --- a/testbenches/project/ad7606x/tests/test_program_4ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_4ch.sv @@ -41,6 +41,7 @@ import axi_vip_pkg::*; import axi4stream_vip_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import adi_regmap_adc_pkg::*; import adi_regmap_common_pkg::*; @@ -72,7 +73,10 @@ program test_program_4ch ( output rx_busy, output logic [2:0] adc_config_mode); - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // -------------------------- // Wrapper function for AXI read verif @@ -81,14 +85,14 @@ program test_program_4ch ( input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); + base_env.mng.master_sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -98,7 +102,7 @@ program test_program_4ch ( input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -108,12 +112,16 @@ program test_program_4ch ( //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); diff --git a/testbenches/project/ad7606x/tests/test_program_6ch.sv b/testbenches/project/ad7606x/tests/test_program_6ch.sv index df0266d1..cf60751d 100755 --- a/testbenches/project/ad7606x/tests/test_program_6ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_6ch.sv @@ -41,6 +41,7 @@ import axi_vip_pkg::*; import axi4stream_vip_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import adi_regmap_adc_pkg::*; import adi_regmap_common_pkg::*; @@ -74,7 +75,10 @@ program test_program_6ch ( output rx_busy, output logic [2:0] adc_config_mode); - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // -------------------------- // Wrapper function for AXI read verif @@ -83,14 +87,14 @@ program test_program_6ch ( input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); + base_env.mng.master_sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -100,7 +104,7 @@ program test_program_6ch ( input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -110,12 +114,16 @@ program test_program_6ch ( //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); diff --git a/testbenches/project/ad7606x/tests/test_program_8ch.sv b/testbenches/project/ad7606x/tests/test_program_8ch.sv index 98deb30a..c8240cd8 100755 --- a/testbenches/project/ad7606x/tests/test_program_8ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_8ch.sv @@ -41,6 +41,7 @@ import axi_vip_pkg::*; import axi4stream_vip_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import adi_regmap_adc_pkg::*; import adi_regmap_common_pkg::*; @@ -76,7 +77,10 @@ program test_program_8ch ( output rx_busy, output logic [2:0] adc_config_mode); - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // -------------------------- // Wrapper function for AXI read verif @@ -85,14 +89,14 @@ program test_program_8ch ( input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); + base_env.mng.master_sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -102,7 +106,7 @@ program test_program_8ch ( input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -112,12 +116,16 @@ program test_program_8ch ( //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); diff --git a/testbenches/project/ad7606x/tests/test_program_si.sv b/testbenches/project/ad7606x/tests/test_program_si.sv index 494b5524..ad903d93 100755 --- a/testbenches/project/ad7606x/tests/test_program_si.sv +++ b/testbenches/project/ad7606x/tests/test_program_si.sv @@ -46,6 +46,7 @@ import adi_regmap_pwm_gen_pkg::*; import adi_regmap_spi_engine_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import `PKGIFY(test_harness, mng_axi_vip)::*; import `PKGIFY(test_harness, ddr_axi_vip)::*; @@ -103,7 +104,10 @@ program test_program_si ( input rx_busy, output rx_cnvst_n); - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // -------------------------- // Wrapper function for AXI read verify @@ -112,14 +116,14 @@ program test_program_si ( input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); + base_env.mng.master_sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -129,7 +133,7 @@ program test_program_si ( input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -139,12 +143,16 @@ program test_program_si ( //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -435,14 +443,14 @@ program test_program_si ( task offload_spi_test(); //Configure DMA - base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.master_sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*`NUM_OF_SDI)-1)); // X_LENGHTH - base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.master_sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*`NUM_OF_SDI)-1)); // X_LENGHTH + base_env.mng.master_sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.master_sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), INST_CFG); diff --git a/testbenches/project/ad7616/tests/test_program_pi.sv b/testbenches/project/ad7616/tests/test_program_pi.sv index d954fb4c..649990dd 100755 --- a/testbenches/project/ad7616/tests/test_program_pi.sv +++ b/testbenches/project/ad7616/tests/test_program_pi.sv @@ -46,6 +46,7 @@ import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import `PKGIFY(test_harness, mng_axi_vip)::*; import `PKGIFY(test_harness, ddr_axi_vip)::*; @@ -64,7 +65,10 @@ program test_program_pi ( input sys_clk, input rx_busy); -test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; +test_harness_env base_env; + +adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; +adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // -------------------------- // Wrapper function for AXI read verif @@ -73,14 +77,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); + base_env.mng.master_sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -90,7 +94,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -100,12 +104,16 @@ initial begin //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -203,13 +211,13 @@ task data_acquisition_test(); `INFO(("Axi_pwm_gen started"), ADI_VERBOSITY_LOW); // Configure DMA - base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.master_sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 - base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.master_sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 + base_env.mng.master_sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS // Configure AXI_AD7616 axi_write (`AXI_AD7616_BA + GetAddrs(AXI_AD7616_REG_UP_CNTRL), @@ -226,7 +234,7 @@ task data_acquisition_test(); transfer_status = 1; - base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.master_sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA wait(transfer_cnt == 2 * NUM_OF_TRANSFERS ); diff --git a/testbenches/project/ad7616/tests/test_program_si.sv b/testbenches/project/ad7616/tests/test_program_si.sv index 02eabb5c..ea014777 100755 --- a/testbenches/project/ad7616/tests/test_program_si.sv +++ b/testbenches/project/ad7616/tests/test_program_si.sv @@ -46,6 +46,7 @@ import adi_regmap_pwm_gen_pkg::*; import adi_regmap_spi_engine_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import `PKGIFY(test_harness, mng_axi_vip)::*; import `PKGIFY(test_harness, ddr_axi_vip)::*; @@ -104,7 +105,10 @@ program test_program_si ( output rx_busy); -test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; +test_harness_env base_env; + +adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; +adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // -------------------------- // Wrapper function for AXI read verif @@ -113,14 +117,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); + base_env.mng.master_sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -130,7 +134,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -140,12 +144,16 @@ initial begin //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -419,14 +427,14 @@ task offload_spi_test(); `INFO(("Axi_pwm_gen started"), ADI_VERBOSITY_LOW); //Configure DMA - base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.master_sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 - base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.master_sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 + base_env.mng.master_sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.master_sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module axi_write (`SPI_AD7616_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), INST_CFG); diff --git a/testbenches/project/ad9083/tests/test_program.sv b/testbenches/project/ad9083/tests/test_program.sv index 400cd195..8635876e 100644 --- a/testbenches/project/ad9083/tests/test_program.sv +++ b/testbenches/project/ad9083/tests/test_program.sv @@ -36,6 +36,7 @@ `include "utils.svh" import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; @@ -58,7 +59,10 @@ parameter TX_OUT_BYTES = 8; program test_program; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; bit [31:0] val; int link_clk_freq; @@ -74,12 +78,16 @@ program test_program; //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -110,29 +118,29 @@ program test_program; // // Enable Rx channel - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); // Select DDS as source - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(32'h00000fff)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INIT_1(16'h0000)| `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); // Pull out TPL cores from reset - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_ADC_COMMON_REG_RSTN_RSTN(1)); // Sync DDS cores - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); // @@ -140,25 +148,25 @@ program test_program; // //LINK DISABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); //SYSREFCONF - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_CONF), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_CONF), `SET_JESD_TX_SYSREF_CONF_SYSREF_DISABLE(0)); // Enable SYSREF handling //CONF0 - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF0), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF0), `SET_JESD_TX_LINK_CONF0_OCTETS_PER_FRAME(`TX_JESD_F-1)| `SET_JESD_TX_LINK_CONF0_OCTETS_PER_MULTIFRAME(`TX_JESD_F*`TX_JESD_K-1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF4), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF4), `SET_JESD_TX_LINK_CONF4_TPL_BEATS_PER_MULTIFRAME((`TX_JESD_F*`TX_JESD_K)/TX_OUT_BYTES-1)); //CONF1 - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF1), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF1), `SET_JESD_TX_LINK_CONF1_SCRAMBLER_DISABLE(0)); // Scrambler enable //LINK ENABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); // @@ -166,39 +174,39 @@ program test_program; // //LINK DISABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); //SYSREFCONF - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_CONF), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_CONF), `SET_JESD_RX_SYSREF_CONF_SYSREF_DISABLE(0)); // Enable SYSREF handling //CONF0 - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF0), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF0), `SET_JESD_RX_LINK_CONF0_OCTETS_PER_FRAME(`RX_JESD_F-1)| `SET_JESD_RX_LINK_CONF0_OCTETS_PER_MULTIFRAME(`RX_JESD_F*`RX_JESD_K-1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF4), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF4), `SET_JESD_RX_LINK_CONF4_TPL_BEATS_PER_MULTIFRAME((`RX_JESD_F*`RX_JESD_K)/RX_OUT_BYTES-1)); // Beats per multiframe //CONF1 - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF1), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF1), `SET_JESD_RX_LINK_CONF1_DESCRAMBLER_DISABLE(0)); // Scrambler enable //LINK ENABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); //XCVR INIT //REG CTRL - base_env.mng.sequencer.RegWrite32(`RX_XCVR_BA + GetAddrs(XCVR_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`RX_XCVR_BA + GetAddrs(XCVR_CONTROL), `SET_XCVR_CONTROL_LPM_DFE_N(1)| `SET_XCVR_CONTROL_OUTCLK_SEL(4)); // RXOUTCLK uses DIV2 - base_env.mng.sequencer.RegWrite32(`TX_XCVR_BA + GetAddrs(XCVR_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TX_XCVR_BA + GetAddrs(XCVR_CONTROL), `SET_XCVR_CONTROL_LPM_DFE_N(1)| `SET_XCVR_CONTROL_OUTCLK_SEL(4)); // TXOUTCLK uses DIV2 - base_env.mng.sequencer.RegWrite32(`RX_XCVR_BA + GetAddrs(XCVR_RESETN), + base_env.mng.master_sequencer.RegWrite32(`RX_XCVR_BA + GetAddrs(XCVR_RESETN), `SET_XCVR_RESETN_RESETN(1)); - base_env.mng.sequencer.RegWrite32(`TX_XCVR_BA + GetAddrs(XCVR_RESETN), + base_env.mng.master_sequencer.RegWrite32(`TX_XCVR_BA + GetAddrs(XCVR_RESETN), `SET_XCVR_RESETN_RESETN(1)); // Give time the PLLs to lock @@ -206,22 +214,22 @@ program test_program; //Read status back // Check SYSREF_STATUS - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); // Check if in DATA state and SYNC is 1 - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_STATUS), `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_STATUS), `SET_JESD_TX_LINK_STATUS_STATUS_SYNC(1)| `SET_JESD_TX_LINK_STATUS_STATUS_STATE(3)); //LINK DISABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); // ------------------------------------------------------- @@ -238,79 +246,79 @@ program test_program; #5us; // Reset TPL cores - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_DAC_COMMON_REG_RSTN_RSTN(0)); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_ADC_COMMON_REG_RSTN_RSTN(0)); // Pull out TPL cores from reset - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_ADC_COMMON_REG_RSTN_RSTN(1)); // Configure Transport Layer for DMA - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); #1us; // Configure TX DMA - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(0)| `SET_DMAC_FLAGS_TLAST(1)); // use TLAST, disable CYCLIC - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); // X_LENGTH = 992-1 - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA)); // SRC_ADDRESS - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer // Configure RX DMA - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(0)| `SET_DMAC_FLAGS_TLAST(1)); // use TLAST, disable CYCLIC - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); // X_LENGTH = 992-1 - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00001000)); // DEST_ADDRESS - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer //LINK ENABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); #25us; //Read status back // Check SYSREF_STATUS - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); #1us; // Check if in DATA state and SYNC is 1 - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_STATUS), `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_STATUS), `SET_JESD_TX_LINK_STATUS_STATUS_SYNC(1)| `SET_JESD_TX_LINK_STATUS_STATUS_STATE(3)); #5us; - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(0)); #5us; @@ -323,45 +331,45 @@ program test_program; //LINK DISABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); #5us; // Configure TX DMA - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(0)| `SET_DMAC_FLAGS_TLAST(1)); // use TLAST, disable CYCLIC - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); // X_LENGTH = 992-1 - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA)); // SRC_ADDRESS - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer // Configure RX DMA - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(0)| `SET_DMAC_FLAGS_TLAST(1)); // use TLAST, disable CYCLIC - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); // X_LENGTH = 992-1 - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00002000)); // DEST_ADDRESS - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA //LINK ENABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); #10us; diff --git a/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv b/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv index d64bde4c..92f4b700 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv @@ -36,6 +36,7 @@ `include "utils.svh" import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; @@ -59,7 +60,10 @@ parameter TX_OUT_BYTES = (`TX_JESD_F % 3 != 0) ? (`JESD_MODE == "64B66B") ? 8 : program test_dma; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; bit [31:0] val; bit [31:0] link_clk_freq; @@ -80,12 +84,16 @@ program test_dma; // create environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -135,36 +143,36 @@ program test_dma; // Configure TX DMA - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h00000FFF)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA+32'h00000000)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Configure Transport Layer to send DMA data on CH0-CH_COUNT-1 for (int i=0;i<`CH_COUNT;i=i+1) begin - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+((30'h0106+('h10*i))<<2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+((30'h0106+('h10*i))<<2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); // Enable Rx channel - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA+((30'h0100+('h10*i))<<2), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+((30'h0100+('h10*i))<<2), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); end // Pull out TPL cores from reset - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA+GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1)); // Sync DDS cores - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); // @@ -172,54 +180,54 @@ program test_dma; // //LINK DISABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); //SYSREFCONF - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_CONF), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_CONF), `SET_JESD_TX_SYSREF_CONF_SYSREF_DISABLE(0)); //CONF0 - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF0), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF0), `SET_JESD_TX_LINK_CONF0_OCTETS_PER_FRAME(`TX_JESD_F-1) | `SET_JESD_TX_LINK_CONF0_OCTETS_PER_MULTIFRAME(`TX_JESD_F*`TX_JESD_K-1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF4), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF4), `SET_JESD_TX_LINK_CONF4_TPL_BEATS_PER_MULTIFRAME((`TX_JESD_F*`TX_JESD_K)/TX_OUT_BYTES-1)); //CONF1 - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF1), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF1), `SET_JESD_TX_LINK_CONF1_SCRAMBLER_DISABLE(0)); //LINK ENABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); // // Configure RX Link Layer // //LINK DISABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); //SYSREFCONF - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_CONF), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_CONF), `SET_JESD_RX_SYSREF_CONF_SYSREF_DISABLE(0)); //CONF0 - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF0), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF0), `SET_JESD_RX_LINK_CONF0_OCTETS_PER_FRAME(`RX_JESD_F-1) | `SET_JESD_RX_LINK_CONF0_OCTETS_PER_MULTIFRAME(`RX_JESD_F*`RX_JESD_K-1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF4), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF4), `SET_JESD_RX_LINK_CONF4_TPL_BEATS_PER_MULTIFRAME((`RX_JESD_F*`RX_JESD_K)/RX_OUT_BYTES-1)); //CONF1 - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF1), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF1), `SET_JESD_RX_LINK_CONF1_DESCRAMBLER_DISABLE(0)); //LINK ENABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); //XCVR INIT //REG CTRL if (`JESD_MODE != "64B66B") begin - base_env.mng.sequencer.RegWrite32(`RX_XCVR_BA+32'h0020,32'h00001004); // RXOUTCLK uses DIV2 - base_env.mng.sequencer.RegWrite32(`TX_XCVR_BA+32'h0020,32'h00001004); + base_env.mng.master_sequencer.RegWrite32(`RX_XCVR_BA+32'h0020,32'h00001004); // RXOUTCLK uses DIV2 + base_env.mng.master_sequencer.RegWrite32(`TX_XCVR_BA+32'h0020,32'h00001004); - base_env.mng.sequencer.RegWrite32(`RX_XCVR_BA+32'h0010,32'h00000001); - base_env.mng.sequencer.RegWrite32(`TX_XCVR_BA+32'h0010,32'h00000001); + base_env.mng.master_sequencer.RegWrite32(`RX_XCVR_BA+32'h0010,32'h00000001); + base_env.mng.master_sequencer.RegWrite32(`TX_XCVR_BA+32'h0010,32'h00000001); end // Wait until link is up @@ -235,31 +243,31 @@ program test_dma; //Read status back // Check SYSREF_STATUS - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_STATUS), `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_STATUS), `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); // Check if in DATA state and SYNC is 1 - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_STATUS), `SET_JESD_TX_LINK_STATUS_STATUS_STATE('h3)); - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_STATUS), `SET_JESD_TX_LINK_STATUS_STATUS_STATE('h3) | `SET_JESD_TX_LINK_STATUS_STATUS_SYNC(ref_sync_status)); // Configure RX DMA - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003FF)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00001000)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); #5us; for (int i=0;i<`CH_COUNT;i=i+1) begin // Disable Rx channels - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA+((30'h0100+('h10*i))<<2), 32'h0000000); + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+((30'h0100+('h10*i))<<2), 32'h0000000); end #5us; @@ -271,9 +279,9 @@ program test_dma; ); //LINK DISABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); diff --git a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv index 2f865d3c..2c4bd187 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv @@ -36,6 +36,7 @@ `include "utils.svh" import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; @@ -54,7 +55,11 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + bit [31:0] val; jesd_link link; @@ -74,9 +79,13 @@ program test_program; `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -94,17 +103,17 @@ program test_program; link.set_encoding(`JESD_MODE != "64B66B" ? enc8b10b : enc64b66b); link.set_lane_rate(lane_rate); - rx_ll = new("RX_LINK_LAYER", base_env.mng.sequencer, `AXI_JESD_RX_BA, link); + rx_ll = new("RX_LINK_LAYER", base_env.mng.master_sequencer, `AXI_JESD_RX_BA, link); rx_ll.probe(); - tx_ll = new("TX_LINK_LAYER", base_env.mng.sequencer, `AXI_JESD_TX_BA, link); + tx_ll = new("TX_LINK_LAYER", base_env.mng.master_sequencer, `AXI_JESD_TX_BA, link); tx_ll.probe(); if (`JESD_MODE != "64B66B") begin - rx_xcvr = new("RX_XCVR", base_env.mng.sequencer, `RX_XCVR_BA); + rx_xcvr = new("RX_XCVR", base_env.mng.master_sequencer, `RX_XCVR_BA); rx_xcvr.probe(); - tx_xcvr = new("TX_XCVR", base_env.mng.sequencer, `TX_XCVR_BA); + tx_xcvr = new("TX_XCVR", base_env.mng.master_sequencer, `TX_XCVR_BA); tx_xcvr.probe(); end @@ -175,26 +184,26 @@ program test_program; for (int i = 0; i < `RX_JESD_M; i++) begin if (use_dds) begin // Select DDS as source - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h0fff)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); end else begin // Set DMA as source for DAC TPL - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); end end - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(1)); if (use_dds) begin // Sync DDS cores - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); end @@ -212,37 +221,37 @@ program test_program; end // Reset TPL cores - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(0)); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(0)); // Pull out TPL cores from reset - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1)); // Configure TX DMA - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h00000FFF)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA+32'h00000000)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Configure RX DMA - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00001000)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Wait until data propagates through the dma #5us; @@ -261,11 +270,11 @@ program test_program; // Configure ADC TPL // ----------------------- for (int i = 0; i < `RX_JESD_M; i++) begin - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + 'h40 * i + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + 'h40 * i + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); end - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1)); rx_ll.link_up(); @@ -323,26 +332,26 @@ program test_program; for (int i = 0; i < `RX_JESD_M; i++) begin if (use_dds) begin // Select DDS as source - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h0fff)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); end else begin // Set DMA as source for DAC TPL - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); end end - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(1)); if (use_dds) begin // Sync DDS cores - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); end @@ -359,11 +368,11 @@ program test_program; // Configure ADC TPL // ----------------------- for (int i = 0; i < `RX_JESD_M; i++) begin - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + 'h40 * i + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + 'h40 * i + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); end - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1)); rx_ll.link_up(); @@ -378,13 +387,13 @@ program test_program; // Move data around for a while #5us; - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1),2); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + 'h48,2); + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1),2); + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + 'h48,2); #1us; // Check if armed - base_env.mng.sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), `SET_DAC_COMMON_REG_SYNC_STATUS_DAC_SYNC_STATUS(1)); - base_env.mng.sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), `SET_ADC_COMMON_REG_SYNC_STATUS_ADC_SYNC(1)); #1us; @@ -402,26 +411,26 @@ program test_program; end // Configure TX DMA - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h00000FFF)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA+32'h00000000)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Configure RX DMA - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00001000)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Wait until data propagates through the dma #5us; @@ -435,9 +444,9 @@ program test_program; #2us; // Check if trigger captured - base_env.mng.sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), `SET_DAC_COMMON_REG_SYNC_STATUS_DAC_SYNC_STATUS(0)); - base_env.mng.sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), `SET_ADC_COMMON_REG_SYNC_STATUS_ADC_SYNC(0)); #5us; diff --git a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv index da8b62e0..50a3452a 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv @@ -36,6 +36,7 @@ `include "utils.svh" import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; @@ -56,7 +57,11 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program_64b66b; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + bit [31:0] val; int tmp; @@ -64,12 +69,16 @@ program test_program_64b66b; // create environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) `TH.`DEVICE_CLK.inst.IF.start_clock(); `TH.`REF_CLK.inst.IF.start_clock(); @@ -82,16 +91,16 @@ program test_program_64b66b; base_env.sys_reset(); #1us; - base_env.mng.sequencer.RegRead32(`DAC_TPL_BA+'h0c,tmp); + base_env.mng.master_sequencer.RegRead32(`DAC_TPL_BA+'h0c,tmp); `INFO(("DAC TPL CONFIG is %h",tmp), ADI_VERBOSITY_LOW); - base_env.mng.sequencer.RegRead32(`DAC_TPL_BA+'h418,tmp); + base_env.mng.master_sequencer.RegRead32(`DAC_TPL_BA+'h418,tmp); `INFO(("DAC TPL CH0 SEL is %h",tmp), ADI_VERBOSITY_LOW); - base_env.mng.sequencer.RegRead32(`DAC_TPL_BA+'h458,tmp); + base_env.mng.master_sequencer.RegRead32(`DAC_TPL_BA+'h458,tmp); `INFO(("DAC TPL CH1 SEL is %h",tmp), ADI_VERBOSITY_LOW); - base_env.mng.sequencer.RegRead32(`RX_DMA_BA+32'h0010,tmp); + base_env.mng.master_sequencer.RegRead32(`RX_DMA_BA+32'h0010,tmp); `INFO(("RX_DMA_BA interface setup is %h",tmp), ADI_VERBOSITY_LOW); - base_env.mng.sequencer.RegRead32(`TX_DMA_BA+32'h0010,tmp); + base_env.mng.master_sequencer.RegRead32(`TX_DMA_BA+32'h0010,tmp); `INFO(("TX_DMA_BA interface setup is %h",tmp), ADI_VERBOSITY_LOW); // ------------------------------------------------------- @@ -102,62 +111,62 @@ program test_program_64b66b; // // Enable Rx channel CH0 - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA+(30'h0100<<2), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+(30'h0100<<2), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); // Enable Rx channel CH31 - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA+(30'h02F0<<2), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+(30'h02F0<<2), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); // Enable Rx channel CH63 - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA+(30'h04F0<<2), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+(30'h04F0<<2), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); // Select DDS as source CH0 - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + (30'h0106<<2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h0106<<2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency CH0 - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + (30'h0100<<2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h0100<<2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h4000)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + (30'h0101<<2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h0101<<2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h28f5)); // Select DDS as source CH31 - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + (30'h02F6<<2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h02F6<<2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Select DDS as source CH63 - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + (30'h04F6<<2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h04F6<<2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency CH31 - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + (30'h02F0<<2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h02F0<<2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h4000)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + (30'h02F1<<2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h02F1<<2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h3333)); // Configure tone amplitude and frequency CH63 - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + (30'h04F0<<2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h04F0<<2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h02ff)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + (30'h04F1<<2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h04F1<<2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0020)); // Arm external sync - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_CNTRL), `SET_ADC_COMMON_REG_CNTRL_SYNC(1)); // Configure RX DMA - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003FF)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1)); // Sync DDS cores - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); // @@ -165,69 +174,69 @@ program test_program_64b66b; // //LINK DISABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); //SYSREFCONF - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_CONF), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_CONF), `SET_JESD_RX_SYSREF_CONF_SYSREF_DISABLE(0)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_CONF), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_CONF), `SET_JESD_TX_SYSREF_CONF_SYSREF_DISABLE(0)); //CONF0 - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF0), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF0), `SET_JESD_TX_LINK_CONF0_OCTETS_PER_FRAME('h3) | `SET_JESD_TX_LINK_CONF0_OCTETS_PER_MULTIFRAME('hff)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF0), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF0), `SET_JESD_RX_LINK_CONF0_OCTETS_PER_FRAME('h3) | `SET_JESD_RX_LINK_CONF0_OCTETS_PER_MULTIFRAME('hff)); //CONF1 - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF1), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF1), `SET_JESD_TX_LINK_CONF1_SCRAMBLER_DISABLE(0)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF1), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF1), `SET_JESD_RX_LINK_CONF1_DESCRAMBLER_DISABLE(0)); //LINK ENABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); //enable near end loopback // for (int i=0;i<8;i++) begin -// base_env.mng.sequencer.RegWrite32(`PHY121+32'h0024, i); -// base_env.mng.sequencer.RegWrite32(`PHY121+32'h041c, 32'h00000001); -// base_env.mng.sequencer.RegWrite32(`PHY125+32'h0024, i); -// base_env.mng.sequencer.RegWrite32(`PHY125+32'h041c, 32'h00000001); +// base_env.mng.master_sequencer.RegWrite32(`PHY121+32'h0024, i); +// base_env.mng.master_sequencer.RegWrite32(`PHY121+32'h041c, 32'h00000001); +// base_env.mng.master_sequencer.RegWrite32(`PHY125+32'h0024, i); +// base_env.mng.master_sequencer.RegWrite32(`PHY125+32'h041c, 32'h00000001); // end //XCVR INIT //REG CTRL -// base_env.mng.sequencer.RegWrite32(`RX_XCVR_BA+32'h0020,32'h00001004); // RXOUTCLK uses DIV2 -// base_env.mng.sequencer.RegWrite32(`TX_XCVR_BA+32'h0020,32'h00001004); +// base_env.mng.master_sequencer.RegWrite32(`RX_XCVR_BA+32'h0020,32'h00001004); // RXOUTCLK uses DIV2 +// base_env.mng.master_sequencer.RegWrite32(`TX_XCVR_BA+32'h0020,32'h00001004); -// base_env.mng.sequencer.RegWrite32(`RX_XCVR_BA+32'h0010,32'h00000001); -// base_env.mng.sequencer.RegWrite32(`TX_XCVR_BA+32'h0010,32'h00000001); +// base_env.mng.master_sequencer.RegWrite32(`RX_XCVR_BA+32'h0010,32'h00000001); +// base_env.mng.master_sequencer.RegWrite32(`TX_XCVR_BA+32'h0010,32'h00000001); #35us; //Read status back // Check SYSREF_STATUS - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_STATUS), `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_STATUS), `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); // Check if in DATA state - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_STATUS), `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_STATUS), `SET_JESD_TX_LINK_STATUS_STATUS_STATE(3)); //LINK DISABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); // ------------------------------------------------------- @@ -242,65 +251,65 @@ program test_program_64b66b; end // Arm external sync - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_CNTRL), `SET_ADC_COMMON_REG_CNTRL_SYNC(1)); // Configure RX DMA - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003FF)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Configure TX DMA - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003FF)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); #5us; // Configure Transport Layer for DMA CH0 - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+(30'h0106<<2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+(30'h0106<<2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); // Configure Transport Layer for DMA CH31 - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+(30'h02F6<<2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+(30'h02F6<<2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); // Enable broadcast of channel 0 to all others for (int i = 1; i < 31; i++) begin - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+((30'h0106<<2)+(i*'h40)), 32'h00010000); + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+((30'h0106<<2)+(i*'h40)), 32'h00010000); end #1us; //LINK ENABLE - base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); - base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); #35us; //Read status back // Check SYSREF_STATUS - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_STATUS), `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_STATUS), `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); #1us; // Check if in DATA state - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_STATUS), `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); - base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_STATUS), `SET_JESD_TX_LINK_STATUS_STATUS_STATE(3)); #2us; diff --git a/testbenches/project/adrv9001/tests/test_program.sv b/testbenches/project/adrv9001/tests/test_program.sv index c53081a6..eff26d3f 100644 --- a/testbenches/project/adrv9001/tests/test_program.sv +++ b/testbenches/project/adrv9001/tests/test_program.sv @@ -39,6 +39,7 @@ import axi_vip_pkg::*; import axi4stream_vip_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_dac_pkg::*; @@ -91,7 +92,11 @@ program test_program; parameter TDD1 = `AXI_ADRV9001_BA + 'h12_00 * 4; parameter TDD2 = `AXI_ADRV9001_BA + 'h13_00 * 4; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + bit [31:0] val; int R1_MODE = 0; @@ -102,7 +107,7 @@ program test_program; input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask // -------------------------- @@ -112,7 +117,7 @@ program test_program; input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask integer rate; @@ -139,12 +144,16 @@ program test_program; //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -481,11 +490,11 @@ program test_program; end // Configure TX DMA - base_env.mng.sequencer.RegWrite32(`TX1_DMA_BA+32'h400, 32'h00000001); // Enable DMA - base_env.mng.sequencer.RegWrite32(`TX1_DMA_BA+32'h40c, 32'h00000001); // use CYCLIC - base_env.mng.sequencer.RegWrite32(`TX1_DMA_BA+32'h418, 32'h00000FFF); // X_LENGHT = 4k - base_env.mng.sequencer.RegWrite32(`TX1_DMA_BA+32'h414, `DDR_BA+32'h00000000); // SRC_ADDRESS - base_env.mng.sequencer.RegWrite32(`TX1_DMA_BA+32'h408, 32'h00000001); // Submit transfer DMA + base_env.mng.master_sequencer.RegWrite32(`TX1_DMA_BA+32'h400, 32'h00000001); // Enable DMA + base_env.mng.master_sequencer.RegWrite32(`TX1_DMA_BA+32'h40c, 32'h00000001); // use CYCLIC + base_env.mng.master_sequencer.RegWrite32(`TX1_DMA_BA+32'h418, 32'h00000FFF); // X_LENGHT = 4k + base_env.mng.master_sequencer.RegWrite32(`TX1_DMA_BA+32'h414, `DDR_BA+32'h00000000); // SRC_ADDRESS + base_env.mng.master_sequencer.RegWrite32(`TX1_DMA_BA+32'h408, 32'h00000001); // Submit transfer DMA // Select DMA as source axi_write (TX1_CHANNEL + CH0 + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), @@ -540,16 +549,16 @@ program test_program; #20us; // Configure RX DMA - base_env.mng.sequencer.RegWrite32(`RX1_DMA_BA+32'h080, 32'h00000001); // Mask SOT IRQ, Enable EOT IRQ - base_env.mng.sequencer.RegWrite32(`RX1_DMA_BA+32'h400, 32'h00000001); // Enable DMA - base_env.mng.sequencer.RegWrite32(`RX1_DMA_BA+32'h40c, 32'h00000006); // use TLAST - base_env.mng.sequencer.RegWrite32(`RX1_DMA_BA+32'h418, 32'h000003FF); // X_LENGHTH = 1024-1 - base_env.mng.sequencer.RegWrite32(`RX1_DMA_BA+32'h410, `DDR_BA+32'h00002000); // DEST_ADDRESS - base_env.mng.sequencer.RegWrite32(`RX1_DMA_BA+32'h408, 32'h00000001); // Submit transfer DMA + base_env.mng.master_sequencer.RegWrite32(`RX1_DMA_BA+32'h080, 32'h00000001); // Mask SOT IRQ, Enable EOT IRQ + base_env.mng.master_sequencer.RegWrite32(`RX1_DMA_BA+32'h400, 32'h00000001); // Enable DMA + base_env.mng.master_sequencer.RegWrite32(`RX1_DMA_BA+32'h40c, 32'h00000006); // use TLAST + base_env.mng.master_sequencer.RegWrite32(`RX1_DMA_BA+32'h418, 32'h000003FF); // X_LENGHTH = 1024-1 + base_env.mng.master_sequencer.RegWrite32(`RX1_DMA_BA+32'h410, `DDR_BA+32'h00002000); // DEST_ADDRESS + base_env.mng.master_sequencer.RegWrite32(`RX1_DMA_BA+32'h408, 32'h00000001); // Submit transfer DMA @(posedge system_tb.test_harness.axi_adrv9001_rx1_dma.irq); //Clear interrupt - base_env.mng.sequencer.RegWrite32(`RX1_DMA_BA+32'h084, 32'h00000002); + base_env.mng.master_sequencer.RegWrite32(`RX1_DMA_BA+32'h084, 32'h00000002); check_captured_data( .address (`DDR_BA+'h00002000), @@ -580,11 +589,11 @@ program test_program; end // Configure TX DMA - base_env.mng.sequencer.RegWrite32(`TX2_DMA_BA+32'h400, 32'h00000001); // Enable DMA - base_env.mng.sequencer.RegWrite32(`TX2_DMA_BA+32'h40c, 32'h00000001); // use CYCLIC - base_env.mng.sequencer.RegWrite32(`TX2_DMA_BA+32'h418, 32'h00000FFF); // X_LENGHT = 4k - base_env.mng.sequencer.RegWrite32(`TX2_DMA_BA+32'h414, `DDR_BA+32'h00000000); // SRC_ADDRESS - base_env.mng.sequencer.RegWrite32(`TX2_DMA_BA+32'h408, 32'h00000001); // Submit transfer DMA + base_env.mng.master_sequencer.RegWrite32(`TX2_DMA_BA+32'h400, 32'h00000001); // Enable DMA + base_env.mng.master_sequencer.RegWrite32(`TX2_DMA_BA+32'h40c, 32'h00000001); // use CYCLIC + base_env.mng.master_sequencer.RegWrite32(`TX2_DMA_BA+32'h418, 32'h00000FFF); // X_LENGHT = 4k + base_env.mng.master_sequencer.RegWrite32(`TX2_DMA_BA+32'h414, `DDR_BA+32'h00000000); // SRC_ADDRESS + base_env.mng.master_sequencer.RegWrite32(`TX2_DMA_BA+32'h408, 32'h00000001); // Submit transfer DMA // Select DDS as source axi_write (TX2_CHANNEL + CH0 + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), @@ -615,16 +624,16 @@ program test_program; #20us; // Configure RX DMA - base_env.mng.sequencer.RegWrite32(`RX2_DMA_BA+32'h080, 32'h00000001); // Mask SOT IRQ, Enable EOT IRQ - base_env.mng.sequencer.RegWrite32(`RX2_DMA_BA+32'h400, 32'h00000001); // Enable DMA - base_env.mng.sequencer.RegWrite32(`RX2_DMA_BA+32'h40c, 32'h00000006); // use TLAST - base_env.mng.sequencer.RegWrite32(`RX2_DMA_BA+32'h418, 32'h000003FF); // X_LENGHTH = 1024-1 - base_env.mng.sequencer.RegWrite32(`RX2_DMA_BA+32'h410, `DDR_BA+32'h00002000); // DEST_ADDRESS - base_env.mng.sequencer.RegWrite32(`RX2_DMA_BA+32'h408, 32'h00000001); // Submit transfer DMA + base_env.mng.master_sequencer.RegWrite32(`RX2_DMA_BA+32'h080, 32'h00000001); // Mask SOT IRQ, Enable EOT IRQ + base_env.mng.master_sequencer.RegWrite32(`RX2_DMA_BA+32'h400, 32'h00000001); // Enable DMA + base_env.mng.master_sequencer.RegWrite32(`RX2_DMA_BA+32'h40c, 32'h00000006); // use TLAST + base_env.mng.master_sequencer.RegWrite32(`RX2_DMA_BA+32'h418, 32'h000003FF); // X_LENGHTH = 1024-1 + base_env.mng.master_sequencer.RegWrite32(`RX2_DMA_BA+32'h410, `DDR_BA+32'h00002000); // DEST_ADDRESS + base_env.mng.master_sequencer.RegWrite32(`RX2_DMA_BA+32'h408, 32'h00000001); // Submit transfer DMA @(posedge system_tb.test_harness.axi_adrv9001_rx2_dma.irq); //Clear interrupt - base_env.mng.sequencer.RegWrite32(`RX2_DMA_BA+32'h084, 32'h00000002); + base_env.mng.master_sequencer.RegWrite32(`RX2_DMA_BA+32'h084, 32'h00000002); check_captured_data( .address (`DDR_BA+'h00002000), diff --git a/testbenches/project/adrv9009/tests/test_program.sv b/testbenches/project/adrv9009/tests/test_program.sv index dce37aae..63abaa58 100755 --- a/testbenches/project/adrv9009/tests/test_program.sv +++ b/testbenches/project/adrv9009/tests/test_program.sv @@ -36,6 +36,7 @@ `include "utils.svh" import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; @@ -60,7 +61,11 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + bit [31:0] val; bit [31:0] lane_rate_khz = `LANE_RATE*1000000; @@ -92,12 +97,16 @@ program test_program; //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -137,40 +146,40 @@ program test_program; rx_os_link.set_encoding(enc8b10b); rx_os_link.set_lane_rate(lane_rate); - ex_rx_ll = new("EX RX_LINK_LAYER", base_env.mng.sequencer, `EX_AXI_JESD_RX_BA, tx_link); + ex_rx_ll = new("EX RX_LINK_LAYER", base_env.mng.master_sequencer, `EX_AXI_JESD_RX_BA, tx_link); ex_rx_ll.probe(); - ex_tx_ll = new("EX TX_LINK_LAYER", base_env.mng.sequencer, `EX_AXI_JESD_TX_BA, rx_link); + ex_tx_ll = new("EX TX_LINK_LAYER", base_env.mng.master_sequencer, `EX_AXI_JESD_TX_BA, rx_link); ex_tx_ll.probe(); - ex_tx_os_ll = new("EX TX_OS_LINK_LAYER", base_env.mng.sequencer, `EX_AXI_JESD_TX_OS_BA, rx_os_link); + ex_tx_os_ll = new("EX TX_OS_LINK_LAYER", base_env.mng.master_sequencer, `EX_AXI_JESD_TX_OS_BA, rx_os_link); ex_tx_os_ll.probe(); - ex_rx_xcvr = new("EX RX_XCVR", base_env.mng.sequencer, `EX_AXI_XCVR_RX_BA); + ex_rx_xcvr = new("EX RX_XCVR", base_env.mng.master_sequencer, `EX_AXI_XCVR_RX_BA); ex_rx_xcvr.probe(); - ex_tx_xcvr = new("EX TX_XCVR", base_env.mng.sequencer, `EX_AXI_XCVR_TX_BA); + ex_tx_xcvr = new("EX TX_XCVR", base_env.mng.master_sequencer, `EX_AXI_XCVR_TX_BA); ex_tx_xcvr.probe(); - ex_tx_os_xcvr = new("EX TX_OS_XCVR", base_env.mng.sequencer, `EX_AXI_XCVR_TX_OS_BA); + ex_tx_os_xcvr = new("EX TX_OS_XCVR", base_env.mng.master_sequencer, `EX_AXI_XCVR_TX_OS_BA); ex_tx_os_xcvr.probe(); - dut_rx_xcvr = new("DUT RX_XCVR", base_env.mng.sequencer, `DUT_AXI_XCVR_RX_BA); + dut_rx_xcvr = new("DUT RX_XCVR", base_env.mng.master_sequencer, `DUT_AXI_XCVR_RX_BA); dut_rx_xcvr.probe(); - dut_rx_os_xcvr = new("DUT RX_OS_XCVR", base_env.mng.sequencer, `DUT_AXI_XCVR_RX_OS_BA); + dut_rx_os_xcvr = new("DUT RX_OS_XCVR", base_env.mng.master_sequencer, `DUT_AXI_XCVR_RX_OS_BA); dut_rx_os_xcvr.probe(); - dut_tx_xcvr = new("DUT TX_XCVR", base_env.mng.sequencer, `DUT_AXI_XCVR_TX_BA); + dut_tx_xcvr = new("DUT TX_XCVR", base_env.mng.master_sequencer, `DUT_AXI_XCVR_TX_BA); dut_tx_xcvr.probe(); - dut_rx_ll = new("DUT RX_LINK_LAYER", base_env.mng.sequencer, `AXI_JESD_RX_BA, rx_link); + dut_rx_ll = new("DUT RX_LINK_LAYER", base_env.mng.master_sequencer, `AXI_JESD_RX_BA, rx_link); dut_rx_ll.probe(); - dut_rx_os_ll = new("DUT RX_OS_LINK_LAYER", base_env.mng.sequencer, `AXI_JESD_RX_OS_BA, rx_os_link); + dut_rx_os_ll = new("DUT RX_OS_LINK_LAYER", base_env.mng.master_sequencer, `AXI_JESD_RX_OS_BA, rx_os_link); dut_rx_os_ll.probe(); - dut_tx_ll = new("DUT TX_LINK_LAYER", base_env.mng.sequencer, `AXI_JESD_TX_BA, tx_link); + dut_tx_ll = new("DUT TX_LINK_LAYER", base_env.mng.master_sequencer, `AXI_JESD_TX_BA, tx_link); dut_tx_ll.probe(); `TH.`REF_CLK.inst.IF.set_clk_frq(.user_frequency(`REF_CLK_RATE*1000000)); @@ -262,15 +271,15 @@ program test_program; end // Configure TX DMA - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h00000FFF)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA+32'h00000000)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); #5us; end @@ -278,42 +287,42 @@ program test_program; for (int i = 0; i < `TX_JESD_M; i++) begin if (use_dds) begin // Select DDS as source - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h0fff)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); end else begin // Set DMA as source for DAC TPL - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); end end for (int i = 0; i < `TX_JESD_M; i++) begin - base_env.mng.sequencer.RegWrite32(`EX_ADC_TPL_BA+'h40*i+GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`EX_ADC_TPL_BA+'h40*i+GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); end - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - base_env.mng.sequencer.RegWrite32(`EX_ADC_TPL_BA+GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`EX_ADC_TPL_BA+GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1)); if (use_dds) begin // Sync DDS cores - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); end // ----------------------- // bringup DUT TX path // ----------------------- - base_env.mng.sequencer.RegWrite32(`AXI_CLKGEN_TX_BA + 'h40, 3); + base_env.mng.master_sequencer.RegWrite32(`AXI_CLKGEN_TX_BA + 'h40, 3); dut_tx_xcvr.up(); dut_tx_ll.link_up(); @@ -333,35 +342,35 @@ program test_program; for (int i = 0; i < `RX_JESD_M; i++) begin if (use_dds) begin // Select DDS as source - base_env.mng.sequencer.RegWrite32(`EX_DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`EX_DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency - base_env.mng.sequencer.RegWrite32(`EX_DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`EX_DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h0fff)); - base_env.mng.sequencer.RegWrite32(`EX_DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + base_env.mng.master_sequencer.RegWrite32(`EX_DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); end else begin // Set DMA as source for DAC TPL - base_env.mng.sequencer.RegWrite32(`EX_DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`EX_DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); end end for (int i = 0; i < `RX_JESD_M; i++) begin - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA+'h40*i+GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+'h40*i+GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); end - base_env.mng.sequencer.RegWrite32(`EX_DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`EX_DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA+GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1)); // ----------------------- // bringup DUT RX path // ----------------------- - base_env.mng.sequencer.RegWrite32(`AXI_CLKGEN_RX_BA + 'h40, 3); + base_env.mng.master_sequencer.RegWrite32(`AXI_CLKGEN_RX_BA + 'h40, 3); ex_tx_xcvr.up(); ex_tx_ll.link_up(); @@ -375,15 +384,15 @@ program test_program; // Configure RX DMA if (!use_dds) begin - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00001000)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); #5us; @@ -406,35 +415,35 @@ program test_program; for (int i = 0; i < `RX_OS_JESD_M; i++) begin if (use_dds) begin // Select DDS as source - base_env.mng.sequencer.RegWrite32(`EX_DAC_OS_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`EX_DAC_OS_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency - base_env.mng.sequencer.RegWrite32(`EX_DAC_OS_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`EX_DAC_OS_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h0fff)); - base_env.mng.sequencer.RegWrite32(`EX_DAC_OS_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + base_env.mng.master_sequencer.RegWrite32(`EX_DAC_OS_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); end else begin // Set DMA as source for DAC TPL - base_env.mng.sequencer.RegWrite32(`EX_DAC_OS_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`EX_DAC_OS_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); end end for (int i = 0; i < `RX_OS_JESD_M; i++) begin - base_env.mng.sequencer.RegWrite32(`ADC_OS_TPL_BA+'h40*i+GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`ADC_OS_TPL_BA+'h40*i+GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); end - base_env.mng.sequencer.RegWrite32(`EX_DAC_OS_TPL_BA+GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`EX_DAC_OS_TPL_BA+GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - base_env.mng.sequencer.RegWrite32(`ADC_OS_TPL_BA+GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_OS_TPL_BA+GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1)); // ----------------------- // bringup DUT RX OBS path // ----------------------- - base_env.mng.sequencer.RegWrite32(`AXI_CLKGEN_RX_OS_BA + 'h40, 3); + base_env.mng.master_sequencer.RegWrite32(`AXI_CLKGEN_RX_OS_BA + 'h40, 3); ex_tx_os_xcvr.up(); ex_tx_os_ll.link_up(); @@ -448,15 +457,15 @@ program test_program; // Configure RX OBS DMA if (!use_dds) begin - base_env.mng.sequencer.RegWrite32(`RX_OS_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`RX_OS_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`RX_OS_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`RX_OS_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.sequencer.RegWrite32(`RX_OS_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`RX_OS_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); - base_env.mng.sequencer.RegWrite32(`RX_OS_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`RX_OS_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00001000)); - base_env.mng.sequencer.RegWrite32(`RX_OS_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_OS_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); #5us; diff --git a/testbenches/project/fmcomms2/tests/test_program.sv b/testbenches/project/fmcomms2/tests/test_program.sv index 9b12bfb4..90ed8df7 100644 --- a/testbenches/project/fmcomms2/tests/test_program.sv +++ b/testbenches/project/fmcomms2/tests/test_program.sv @@ -36,6 +36,7 @@ `include "utils.svh" import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; @@ -67,7 +68,10 @@ program test_program; parameter TDD1 = `AXI_AD9361_BA + 'h12_00 * 4; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; bit [31:0] val; @@ -78,7 +82,7 @@ program test_program; input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask // -------------------------- @@ -88,7 +92,7 @@ program test_program; input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask integer rate; @@ -103,12 +107,16 @@ program test_program; //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); diff --git a/testbenches/project/mxfe/tests/test_program.sv b/testbenches/project/mxfe/tests/test_program.sv index cb170b7b..46e7e8e2 100644 --- a/testbenches/project/mxfe/tests/test_program.sv +++ b/testbenches/project/mxfe/tests/test_program.sv @@ -36,6 +36,7 @@ `include "utils.svh" import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import adi_regmap_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; @@ -55,7 +56,11 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + bit [31:0] val; jesd_link link; @@ -72,12 +77,16 @@ program test_program; //creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -95,16 +104,16 @@ program test_program; link.set_encoding(`JESD_MODE != "64B66B" ? enc8b10b : enc64b66b); link.set_lane_rate(lane_rate); - rx_ll = new("RX_LINK_LAYER", base_env.mng.sequencer, `AXI_JESD_RX_BA, link); + rx_ll = new("RX_LINK_LAYER", base_env.mng.master_sequencer, `AXI_JESD_RX_BA, link); rx_ll.probe(); - tx_ll = new("TX_LINK_LAYER", base_env.mng.sequencer, `AXI_JESD_TX_BA, link); + tx_ll = new("TX_LINK_LAYER", base_env.mng.master_sequencer, `AXI_JESD_TX_BA, link); tx_ll.probe(); - rx_xcvr = new("RX_XCVR", base_env.mng.sequencer, `RX_XCVR_BA); + rx_xcvr = new("RX_XCVR", base_env.mng.master_sequencer, `RX_XCVR_BA); rx_xcvr.probe(); - tx_xcvr = new("TX_XCVR", base_env.mng.sequencer, `TX_XCVR_BA); + tx_xcvr = new("TX_XCVR", base_env.mng.master_sequencer, `TX_XCVR_BA); tx_xcvr.probe(); `TH.`REF_CLK.inst.IF.set_clk_frq(.user_frequency(`REF_CLK_RATE*1000000)); @@ -186,26 +195,26 @@ program test_program; for (int i = 0; i < `RX_JESD_M; i++) begin if (use_dds) begin // Select DDS as source - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h0fff)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); end else begin // Set DMA as source for DAC TPL - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); end end - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(1)); if (use_dds) begin // Sync DDS cores - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); end @@ -213,41 +222,41 @@ program test_program; // Configure Offload // // Transfer length - //base_env.mng.sequencer.RegWrite32(`RX_OFFLOAD_BA+'h1C, 'h1000/64); + //base_env.mng.master_sequencer.RegWrite32(`RX_OFFLOAD_BA+'h1C, 'h1000/64); // Set One shot and bypass - base_env.mng.sequencer.RegWrite32(`RX_OFFLOAD_BA+'h88, 2 | rx_bypass); + base_env.mng.master_sequencer.RegWrite32(`RX_OFFLOAD_BA+'h88, 2 | rx_bypass); // Set Tx offload bypass // for TDD set single shot - base_env.mng.sequencer.RegWrite32(`TX_OFFLOAD_BA+'h88, 2*tdd_enabled | tx_bypass); + base_env.mng.master_sequencer.RegWrite32(`TX_OFFLOAD_BA+'h88, 2*tdd_enabled | tx_bypass); // Sync option set for hw sync - base_env.mng.sequencer.RegWrite32(`TX_OFFLOAD_BA+'h104, tdd_enabled); - base_env.mng.sequencer.RegWrite32(`RX_OFFLOAD_BA+'h104, tdd_enabled); + base_env.mng.master_sequencer.RegWrite32(`TX_OFFLOAD_BA+'h104, tdd_enabled); + base_env.mng.master_sequencer.RegWrite32(`RX_OFFLOAD_BA+'h104, tdd_enabled); if (tdd_enabled) begin - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), `SET_TDDN_CNTRL_FRAME_LENGTH_FRAME_LENGTH(2048)); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON), `SET_TDDN_CNTRL_CH0_ON_CH0_ON(0)); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF), `SET_TDDN_CNTRL_CH0_OFF_CH0_OFF(10)); // Trigger RX capture later due rountrip latency ~96 cycles - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH1_ON), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH1_ON), `SET_TDDN_CNTRL_CH1_ON_CH1_ON(96)); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH1_OFF), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH1_OFF), `SET_TDDN_CNTRL_CH1_OFF_CH1_OFF(106)); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), `SET_TDDN_CNTRL_CHANNEL_ENABLE_CHANNEL_ENABLE(3)); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), `SET_TDDN_CNTRL_SYNC_COUNTER_LOW_SYNC_COUNTER_LOW(8192)); - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_INT(1) | `SET_TDDN_CNTRL_CONTROL_ENABLE(1)); end @@ -265,27 +274,27 @@ program test_program; end end // Configure TX DMA - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(tx_bypass) | `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h00001FFF)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA+32'h00000000)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Configure RX DMA - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000007FF)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00002000)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Wait until data propagates through the dma+offload #5us; @@ -302,11 +311,11 @@ program test_program; // Configure ADC TPL // ----------------------- for (int i = 0; i < `RX_JESD_M; i++) begin - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + 'h40 * i + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + 'h40 * i + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); end - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1)); rx_ll.link_up(); @@ -327,16 +336,16 @@ program test_program; end if (tdd_enabled) begin - base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); end rx_ll.link_down(); tx_ll.link_down(); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(0)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(0)); rx_xcvr.down(); @@ -367,26 +376,26 @@ program test_program; for (int i = 0; i < `RX_JESD_M; i++) begin if (use_dds) begin // Select DDS as source - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h0fff)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); end else begin // Set DMA as source for DAC TPL - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); end end - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(1)); if (use_dds) begin // Sync DDS cores - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); end @@ -394,9 +403,9 @@ program test_program; // Configure Offload // // Transfer length - base_env.mng.sequencer.RegWrite32(`RX_OFFLOAD_BA+'h1C, 'h1000/64); + base_env.mng.master_sequencer.RegWrite32(`RX_OFFLOAD_BA+'h1C, 'h1000/64); // One shot - base_env.mng.sequencer.RegWrite32(`RX_OFFLOAD_BA+'h88, 2); + base_env.mng.master_sequencer.RegWrite32(`RX_OFFLOAD_BA+'h88, 2); tx_ll.link_up(); @@ -409,11 +418,11 @@ program test_program; // Configure ADC TPL // ----------------------- for (int i = 0; i < `RX_JESD_M; i++) begin - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + 'h40 * i + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + 'h40 * i + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); end - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1)); rx_ll.link_up(); @@ -424,13 +433,13 @@ program test_program; // Move data around for a while #5us; - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1),2); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + 'h48,2); + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1),2); + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + 'h48,2); #1us; // Check if armed - base_env.mng.sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), `SET_DAC_COMMON_REG_SYNC_STATUS_DAC_SYNC_STATUS(1)); - base_env.mng.sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), `SET_ADC_COMMON_REG_SYNC_STATUS_ADC_SYNC(1)); #1us; @@ -448,26 +457,26 @@ program test_program; end // Configure TX DMA - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h00000FFF)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA+32'h00000000)); - base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Configure RX DMA - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00002000)); - base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Wait until data propagates through the dma+offload #5us; @@ -481,18 +490,18 @@ program test_program; #1us; // Check if trigger captured - base_env.mng.sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_SYNC_STATUS), `SET_DAC_COMMON_REG_SYNC_STATUS_DAC_SYNC_STATUS(0)); - base_env.mng.sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), + base_env.mng.master_sequencer.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), `SET_ADC_COMMON_REG_SYNC_STATUS_ADC_SYNC(0)); #5us; rx_ll.link_down(); tx_ll.link_down(); - base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(0)); - base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_RSTN(0)); rx_xcvr.down(); diff --git a/testbenches/project/pluto/tests/test_program.sv b/testbenches/project/pluto/tests/test_program.sv index e76780d4..626c33cd 100644 --- a/testbenches/project/pluto/tests/test_program.sv +++ b/testbenches/project/pluto/tests/test_program.sv @@ -36,6 +36,7 @@ `include "utils.svh" import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; import logger_pkg::*; @@ -62,7 +63,10 @@ program test_program; localparam TX1_CHANNEL = `AXI_AD9361_BA + 'h4000; localparam TDD1 = `AXI_AD9361_BA + 'h8000; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; bit [31:0] val = 32'h0; int r1_mode, rate; @@ -74,7 +78,7 @@ program test_program; input [31:0] raddr, output [31:0] rdata); - base_env.mng.sequencer.RegRead32(raddr,rdata); + base_env.mng.master_sequencer.RegRead32(raddr,rdata); endtask // -------------------------- @@ -84,7 +88,7 @@ program test_program; input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask // -------------------------- @@ -94,7 +98,7 @@ program test_program; input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -104,12 +108,16 @@ program test_program; // Creating environment base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); base_env.start(); diff --git a/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv b/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv index 3a99e60a..c7747a1b 100755 --- a/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv +++ b/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv @@ -47,6 +47,7 @@ import adi_regmap_pwm_gen_pkg::*; import adi_regmap_spi_engine_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; import `PKGIFY(test_harness, mng_axi_vip)::*; import `PKGIFY(test_harness, ddr_axi_vip)::*; @@ -101,7 +102,10 @@ program test_program ( input pulsar_adc_spi_clk, input [(`NUM_OF_SDI - 1):0] pulsar_adc_spi_sdi); -test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; +test_harness_env base_env; + +adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; +adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; // -------------------------- // Wrapper function for AXI read verify @@ -110,14 +114,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - base_env.mng.sequencer.RegReadVerify32(raddr,vdata); + base_env.mng.master_sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.sequencer.RegRead32(raddr,data); + base_env.mng.master_sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -127,7 +131,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - base_env.mng.sequencer.RegWrite32(waddr,wdata); + base_env.mng.master_sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -140,9 +144,13 @@ initial begin `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) setLoggerVerbosity(ADI_VERBOSITY_NONE); @@ -406,14 +414,14 @@ bit [31:0] offload_captured_word_arr [(NUM_OF_TRANSFERS) -1 :0]; task offload_spi_test(); //Configure DMA - base_env.mng.sequencer.RegWrite32(`PULSAR_ADC_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - base_env.mng.sequencer.RegWrite32(`PULSAR_ADC_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.master_sequencer.RegWrite32(`PULSAR_ADC_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.master_sequencer.RegWrite32(`PULSAR_ADC_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - base_env.mng.sequencer.RegWrite32(`PULSAR_ADC_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 - base_env.mng.sequencer.RegWrite32(`PULSAR_ADC_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - base_env.mng.sequencer.RegWrite32(`PULSAR_ADC_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.master_sequencer.RegWrite32(`PULSAR_ADC_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 + base_env.mng.master_sequencer.RegWrite32(`PULSAR_ADC_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.master_sequencer.RegWrite32(`PULSAR_ADC_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module axi_write (`PULSAR_ADC_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), INST_CFG); From a8c9d2dfa9b524d3007c8323989b92419ee0c6a3 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Thu, 13 Feb 2025 11:49:52 +0200 Subject: [PATCH 29/37] library/vip/amd/axi/s_axi_sequencer: Added memory access functions - Updated testbenches as well Signed-off-by: Istvan-Zsolt Szekely --- library/vip/amd/axi/s_axi_sequencer.sv | 72 +++++-------------- library/vip/amd/axis/s_axis_sequencer.sv | 13 ---- .../ip/data_offload/tests/test_program.sv | 2 +- .../ip/dma_loopback/tests/test_program.sv | 6 +- .../ip/dma_sg/tests/test_program_1d.sv | 30 ++++---- .../ip/dma_sg/tests/test_program_2d.sv | 32 ++++----- .../ip/dma_sg/tests/test_program_tr_queue.sv | 30 ++++---- testbenches/ip/hbm/tests/test_program.sv | 6 +- .../ip/scoreboard/tests/test_program.sv | 4 +- .../ip/spi_engine/tests/test_program.sv | 2 +- .../ip/spi_engine/tests/test_sleep_delay.sv | 4 +- .../ip/spi_engine/tests/test_slowdata.sv | 2 +- .../project/ad463x/tests/test_program.sv | 2 +- .../project/ad57xx/tests/test_program.sv | 2 +- .../project/ad738x/tests/test_program.sv | 2 +- .../project/ad7606x/tests/test_program_si.sv | 2 +- .../project/ad7616/tests/test_program_pi.sv | 2 +- .../project/ad7616/tests/test_program_si.sv | 2 +- .../project/ad9083/tests/test_program.sv | 4 +- .../ad_quadmxfe1_ebz/tests/test_dma.sv | 4 +- .../ad_quadmxfe1_ebz/tests/test_program.sv | 10 +-- .../tests/test_program_64b66b.sv | 2 +- .../project/adrv9001/tests/test_program.sv | 14 ++-- .../project/adrv9009/tests/test_program.sv | 4 +- .../project/fmcomms2/tests/test_program.sv | 4 +- .../project/mxfe/tests/test_program.sv | 10 +-- .../project/pluto/tests/test_program.sv | 6 +- .../pulsar_adc_pmdz/tests/test_program.sv | 2 +- 28 files changed, 111 insertions(+), 164 deletions(-) diff --git a/library/vip/amd/axi/s_axi_sequencer.sv b/library/vip/amd/axi/s_axi_sequencer.sv index 90786f96..19db5bf0 100644 --- a/library/vip/amd/axi/s_axi_sequencer.sv +++ b/library/vip/amd/axi/s_axi_sequencer.sv @@ -52,26 +52,14 @@ package s_axi_sequencer_pkg; super.new(name, parent); endfunction: new - virtual task get_byte_from_mem( - input xil_axi_ulong addr, - output bit [7:0] data); - - this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); - endtask: get_byte_from_mem + virtual function logic [31:0] get_reg_data_from_mem(input xil_axi_ulong addr); + endfunction: get_reg_data_from_mem - virtual task set_byte_in_mem( + virtual function void set_reg_data_in_mem( input xil_axi_ulong addr, - input bit [7:0] data); - - this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); - endtask: set_byte_in_mem - - virtual task verify_byte( - input xil_axi_ulong addr, - input bit [7:0] refdata); - - this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); - endtask: verify_byte + input logic [31:0] data, + input bit [3:0] strb); + endfunction: set_reg_data_in_mem endclass: s_axi_sequencer_base @@ -90,47 +78,19 @@ package s_axi_sequencer_pkg; this.mem_model = mem_model; endfunction: new - task get_byte_from_mem( - input xil_axi_ulong addr, - output bit [7:0] data); - - bit [31:0] four_bytes; - four_bytes = this.mem_model.backdoor_memory_read_4byte(addr); - case (addr[1:0]) - 2'b00: data = four_bytes[0+:8]; - 2'b01: data = four_bytes[8+:8]; - 2'b10: data = four_bytes[16+:8]; - 2'b11: data = four_bytes[24+:8]; - endcase - endtask: get_byte_from_mem - - task set_byte_in_mem( - input xil_axi_ulong addr, - input bit [7:0] data); - - bit [3:0] strb; - case (addr[1:0]) - 2'b00: strb = 'b0001; - 2'b01: strb = 'b0010; - 2'b10: strb = 'b0100; - 2'b11: strb = 'b1000; - endcase - this.mem_model.backdoor_memory_write_4byte(.addr(addr), - .payload({4{data}}), - .strb(strb)); - endtask: set_byte_in_mem + virtual function logic [31:0] get_reg_data_from_mem(input xil_axi_ulong addr); + return this.mem_model.backdoor_memory_read_4byte(addr); + endfunction: get_reg_data_from_mem - task verify_byte( + virtual function void set_reg_data_in_mem( input xil_axi_ulong addr, - input bit [7:0] refdata); - - bit [7:0] data; + input logic [31:0] data, + input bit [3:0] strb); - get_byte_from_mem (addr, data); - if (data !== refdata) begin - this.error($sformatf("Unexpected value at address %0h . Expected: %0h Found: %0h", addr, refdata, data)); - end - endtask: verify_byte + this.mem_model.backdoor_memory_write_4byte(.addr(addr), + .payload(data), + .strb(strb)); + endfunction: set_reg_data_in_mem endclass: s_axi_sequencer diff --git a/library/vip/amd/axis/s_axis_sequencer.sv b/library/vip/amd/axis/s_axis_sequencer.sv index 6f914a6b..97286ebe 100644 --- a/library/vip/amd/axis/s_axis_sequencer.sv +++ b/library/vip/amd/axis/s_axis_sequencer.sv @@ -129,19 +129,6 @@ package s_axis_sequencer_pkg; this.low_time_max = low_time_max; endfunction: set_low_time_range - // function for verifying bytes - task verify_byte(input bit [7:0] refdata); - bit [7:0] data; - if (byte_stream.size() == 0) begin - this.error($sformatf("Byte steam empty !!!")); - end else begin - data = byte_stream.pop_front(); - if (data !== refdata) begin - this.error($sformatf("Unexpected data received. Expected: %0h Found: %0h Left : %0d", refdata, data, byte_stream.size())); - end - end - endtask: verify_byte - // call ready generation function virtual task start(); this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); diff --git a/testbenches/ip/data_offload/tests/test_program.sv b/testbenches/ip/data_offload/tests/test_program.sv index 5c511b16..47a84d4f 100644 --- a/testbenches/ip/data_offload/tests/test_program.sv +++ b/testbenches/ip/data_offload/tests/test_program.sv @@ -245,7 +245,7 @@ module test_program(); // Memory initialization function for a 8byte DATA_WIDTH AXI4 bus task init_mem_64(longint unsigned addr, int byte_length); for (int i=0; i Date: Thu, 13 Feb 2025 14:27:07 +0200 Subject: [PATCH 30/37] library/vip/amd/axi/s_axi_sequencer: Cosmetic change Signed-off-by: Istvan-Zsolt Szekely --- library/vip/amd/axi/s_axi_sequencer.sv | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/library/vip/amd/axi/s_axi_sequencer.sv b/library/vip/amd/axi/s_axi_sequencer.sv index 19db5bf0..998d0720 100644 --- a/library/vip/amd/axi/s_axi_sequencer.sv +++ b/library/vip/amd/axi/s_axi_sequencer.sv @@ -87,9 +87,10 @@ package s_axi_sequencer_pkg; input logic [31:0] data, input bit [3:0] strb); - this.mem_model.backdoor_memory_write_4byte(.addr(addr), - .payload(data), - .strb(strb)); + this.mem_model.backdoor_memory_write_4byte( + .addr(addr), + .payload(data), + .strb(strb)); endfunction: set_reg_data_in_mem endclass: s_axi_sequencer From 85d89c165d4cbb2dd9c5e4505c5259b009ad7d62 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Thu, 20 Feb 2025 12:03:48 +0200 Subject: [PATCH 31/37] library/vip/amd: Updated ADI agent function calls to fix a null-object access Signed-off-by: Istvan-Zsolt Szekely --- library/vip/amd/axi/adi_axi_agent.sv | 16 ++++++++++------ library/vip/amd/axis/adi_axis_agent.sv | 22 ++++++++++++++-------- 2 files changed, 24 insertions(+), 14 deletions(-) diff --git a/library/vip/amd/axi/adi_axi_agent.sv b/library/vip/amd/axi/adi_axi_agent.sv index 01a33f27..d66783b4 100644 --- a/library/vip/amd/axi/adi_axi_agent.sv +++ b/library/vip/amd/axi/adi_axi_agent.sv @@ -70,42 +70,36 @@ package adi_axi_agent_pkg; if (agent_type == SLAVE) begin this.fatal($sformatf("Agent is in slave mode!")); end - this.monitor.start(); endtask: start_master virtual task start_slave(); if (agent_type == MASTER) begin this.fatal($sformatf("Agent is in master mode!")); end - this.monitor.start(); endtask: start_slave virtual task start_monitor(); if (agent_type != PASSTHROUGH) begin this.fatal($sformatf("Agent is not in passthrough mode!")); end - this.monitor.start(); endtask: start_monitor virtual task stop_master(); if (agent_type == SLAVE) begin this.fatal($sformatf("Agent is in slave mode!")); end - this.monitor.stop(); endtask: stop_master virtual task stop_slave(); if (agent_type == MASTER) begin this.fatal($sformatf("Agent is in master mode!")); end - this.monitor.stop(); endtask: stop_slave virtual task stop_monitor(); if (agent_type != PASSTHROUGH) begin this.fatal($sformatf("Agent is not in passthrough mode!")); end - this.monitor.stop(); endtask: stop_monitor endclass: adi_axi_agent_base @@ -142,11 +136,13 @@ package adi_axi_agent_pkg; virtual task start_master(); super.start_master(); this.agent.start_master(); + this.monitor.start(); endtask: start_master virtual task stop_master(); super.stop_master(); this.agent.stop_master(); + this.monitor.stop(); endtask: stop_master endclass: adi_axi_master_agent @@ -183,11 +179,13 @@ package adi_axi_agent_pkg; virtual task start_slave(); super.start_slave(); this.agent.start_slave(); + this.monitor.start(); endtask: start_slave virtual task stop_slave(); super.stop_slave(); this.agent.stop_slave(); + this.monitor.stop(); endtask: stop_slave endclass: adi_axi_slave_mem_agent @@ -227,31 +225,37 @@ package adi_axi_agent_pkg; virtual task start_master(); super.start_master(); this.agent.start_master(); + this.monitor.start(); endtask: start_master virtual task start_slave(); super.start_slave(); this.agent.start_slave(); + this.monitor.start(); endtask: start_slave virtual task start_monitor(); super.start_monitor(); this.agent.start_monitor(); + this.monitor.start(); endtask: start_monitor virtual task stop_master(); super.stop_master(); this.agent.stop_master(); + this.monitor.stop(); endtask: stop_master virtual task stop_slave(); super.stop_slave(); this.agent.stop_slave(); + this.monitor.stop(); endtask: stop_slave virtual task stop_monitor(); super.stop_monitor(); this.agent.stop_monitor(); + this.monitor.stop(); endtask: stop_monitor endclass: adi_axi_passthrough_mem_agent diff --git a/library/vip/amd/axis/adi_axis_agent.sv b/library/vip/amd/axis/adi_axis_agent.sv index 85d91fd0..c19d83ad 100644 --- a/library/vip/amd/axis/adi_axis_agent.sv +++ b/library/vip/amd/axis/adi_axis_agent.sv @@ -70,44 +70,36 @@ package adi_axis_agent_pkg; if (agent_type == SLAVE) begin this.fatal($sformatf("Agent is in slave mode!")); end - this.monitor.start(); endtask: start_master virtual task start_slave(); if (agent_type == MASTER) begin this.fatal($sformatf("Agent is in master mode!")); end - this.monitor.start(); endtask: start_slave virtual task start_monitor(); if (agent_type != PASSTHROUGH) begin this.fatal($sformatf("Agent is not in passthrough mode!")); end - this.monitor.start(); endtask: start_monitor virtual task stop_master(); if (agent_type == SLAVE) begin this.fatal($sformatf("Agent is in slave mode!")); end - this.master_sequencer.stop(); - this.monitor.stop(); endtask: stop_master virtual task stop_slave(); if (agent_type == MASTER) begin this.fatal($sformatf("Agent is in master mode!")); end - this.slave_sequencer.stop(); - this.monitor.stop(); endtask: stop_slave virtual task stop_monitor(); if (agent_type != PASSTHROUGH) begin this.fatal($sformatf("Agent is not in passthrough mode!")); end - this.monitor.stop(); endtask: stop_monitor endclass: adi_axis_agent_base @@ -144,11 +136,14 @@ package adi_axis_agent_pkg; virtual task start_master(); super.start_master(); this.agent.start_master(); + this.monitor.start(); endtask: start_master virtual task stop_master(); super.stop_master(); this.agent.stop_master(); + this.master_sequencer.stop(); + this.monitor.stop(); endtask: stop_master endclass: adi_axis_master_agent @@ -185,11 +180,14 @@ package adi_axis_agent_pkg; virtual task start_slave(); super.start_slave(); this.agent.start_slave(); + this.monitor.start(); endtask: start_slave virtual task stop_slave(); super.stop_slave(); this.agent.stop_slave(); + this.slave_sequencer.stop(); + this.monitor.stop(); endtask: stop_slave endclass: adi_axis_slave_agent @@ -229,33 +227,41 @@ package adi_axis_agent_pkg; virtual task start_master(); super.start_master(); this.agent.start_master(); + this.monitor.start(); this.warning($sformatf("Sequencer must be started manually!")); endtask: start_master virtual task start_slave(); super.start_slave(); this.agent.start_slave(); + this.monitor.start(); this.warning($sformatf("Sequencer must be started manually!")); endtask: start_slave virtual task start_monitor(); super.start_monitor(); this.agent.start_monitor(); + this.monitor.start(); endtask: start_monitor virtual task stop_master(); super.stop_master(); this.agent.stop_master(); + this.master_sequencer.stop(); + this.monitor.stop(); endtask: stop_master virtual task stop_slave(); super.stop_slave(); this.agent.stop_slave(); + this.slave_sequencer.stop(); + this.monitor.stop(); endtask: stop_slave virtual task stop_monitor(); super.stop_monitor(); this.agent.stop_monitor(); + this.monitor.stop(); endtask: stop_monitor endclass: adi_axis_passthrough_mem_agent From 13863e72eadae9de59432956f6e63a7ca30abaf6 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Thu, 20 Feb 2025 12:04:36 +0200 Subject: [PATCH 32/37] scoreboard: Simplified to AXIS datastream verification Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/scoreboard/Makefile | 9 - testbenches/ip/scoreboard/cfgs/cfg1.tcl | 18 -- testbenches/ip/scoreboard/environment.sv | 138 ------------ testbenches/ip/scoreboard/system_bd.tcl | 171 ++------------- testbenches/ip/scoreboard/system_project.tcl | 3 - .../ip/scoreboard/tests/test_program.sv | 206 +++--------------- testbenches/ip/scoreboard/waves/cfg1.wcfg | 101 ++------- 7 files changed, 64 insertions(+), 582 deletions(-) delete mode 100644 testbenches/ip/scoreboard/environment.sv diff --git a/testbenches/ip/scoreboard/Makefile b/testbenches/ip/scoreboard/Makefile index b39c6e04..70b5861b 100644 --- a/testbenches/ip/scoreboard/Makefile +++ b/testbenches/ip/scoreboard/Makefile @@ -12,15 +12,6 @@ include $(TB_LIBRARY_PATH)/includes/Makeinclude_scoreboard.mk include $(TB_LIBRARY_PATH)/includes/Makeinclude_dmac.mk include $(TB_LIBRARY_PATH)/includes/Makeinclude_data_offload.mk -# Remaining test-bench dependencies except test programs -SV_DEPS += environment.sv - -LIB_DEPS := util_cdc -LIB_DEPS += util_axis_fifo -LIB_DEPS += axi_dmac -LIB_DEPS += data_offload -LIB_DEPS += util_do_ram - # default test program TP := test_program diff --git a/testbenches/ip/scoreboard/cfgs/cfg1.tcl b/testbenches/ip/scoreboard/cfgs/cfg1.tcl index 2418b5b4..d040d253 100644 --- a/testbenches/ip/scoreboard/cfgs/cfg1.tcl +++ b/testbenches/ip/scoreboard/cfgs/cfg1.tcl @@ -1,19 +1 @@ global ad_project_params - -set ad_project_params(ADC_DATA_PATH_WIDTH) 16 ; ## -set ad_project_params(DAC_DATA_PATH_WIDTH) 16 ; ## - -set ad_project_params(ADC_PATH_TYPE) 0 ; ## RX -set ad_project_params(ADC_OFFLOAD_MEM_TYPE) 0 ; ## External storage -set ad_project_params(ADC_OFFLOAD_SIZE) 2048 ; ## Storage size in bytes -set ad_project_params(ADC_OFFLOAD_SRC_DWIDTH) 128 ; ## Source data width -set ad_project_params(ADC_OFFLOAD_DST_DWIDTH) 128 ; ## Destination data width - -set ad_project_params(DAC_PATH_TYPE) 0 ; ## TX -set ad_project_params(DAC_OFFLOAD_MEM_TYPE) 0 ; ## External storage -set ad_project_params(DAC_OFFLOAD_SIZE) 2048 ; ## Storage size in bytes -set ad_project_params(DAC_OFFLOAD_SRC_DWIDTH) 128 ; ## Source data width -set ad_project_params(DAC_OFFLOAD_DST_DWIDTH) 128 ; ## Destination data width - -set ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) 512 ; ## PLDDR's AXI4 interface data width - diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv deleted file mode 100644 index 63e435c4..00000000 --- a/testbenches/ip/scoreboard/environment.sv +++ /dev/null @@ -1,138 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`include "utils.svh" -`include "axi_definitions.svh" -`include "axis_definitions.svh" - -package environment_pkg; - - import logger_pkg::*; - import adi_environment_pkg::*; - - import axi_vip_pkg::*; - import axi4stream_vip_pkg::*; - import m_axi_sequencer_pkg::*; - import s_axi_sequencer_pkg::*; - import m_axis_sequencer_pkg::*; - import s_axis_sequencer_pkg::*; - import adi_axi_agent_pkg::*; - import adi_axis_agent_pkg::*; - import scoreboard_pkg::*; - - - class scoreboard_environment extends adi_environment; - - // Agents - adi_axis_agent_base adc_src_axis_agent; - adi_axis_agent_base dac_dst_axis_agent; - adi_axi_agent_base adc_dst_axi_pt_agent; - adi_axi_agent_base dac_src_axi_pt_agent; - - scoreboard #(logic [7:0]) scoreboard_tx; - scoreboard #(logic [7:0]) scoreboard_rx; - - //============================================================================ - // Constructor - //============================================================================ - function new (input string name); - - // creating the agents - super.new(name); - - this.adc_src_axis_agent = new("ADC Source AXI Stream Agent", adi_axis_agent_pkg::MASTER, this); - this.dac_dst_axis_agent = new("DAC Destination AXI Stream Agent", adi_axis_agent_pkg::SLAVE, this); - this.adc_dst_axi_pt_agent = new("ADC Destination AXI Agent", adi_axi_agent_pkg::PASSTHROUGH, this); - this.dac_src_axi_pt_agent = new("DAC Source AXI Agent", adi_axi_agent_pkg::PASSTHROUGH, this); - - this.scoreboard_tx = new("Data Offload TX Scoreboard", this); - this.scoreboard_rx = new("Data Offload RX Scoreboard", this); - endfunction - - //============================================================================ - // Configure environment - // - Configure the sequencer VIPs with an initial configuration before starting them - //============================================================================ - task configure(int bytes_to_generate); - // ADC stub - this.adc_src_axis_agent.master_sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - this.adc_src_axis_agent.master_sequencer.add_xfer_descriptor_byte_count(bytes_to_generate, 0, 0); - - // DAC stub - this.dac_dst_axis_agent.slave_sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); - endtask - - //============================================================================ - // Start environment - // - Connect all the agents to the scoreboard - // - Start the agents - //============================================================================ - task start(); - this.adc_src_axis_agent.start_master(); - this.dac_dst_axis_agent.start_slave(); - this.adc_dst_axi_pt_agent.start_monitor(); - this.dac_src_axi_pt_agent.start_monitor(); - - this.dac_src_axi_pt_agent.monitor.publisher_rx.subscribe(this.scoreboard_tx.subscriber_source); - this.dac_dst_axis_agent.monitor.publisher.subscribe(this.scoreboard_tx.subscriber_sink); - - this.adc_src_axis_agent.monitor.publisher.subscribe(this.scoreboard_rx.subscriber_source); - this.adc_dst_axi_pt_agent.monitor.publisher_tx.subscribe(this.scoreboard_rx.subscriber_sink); - endtask - - //============================================================================ - // Run subroutine - //============================================================================ - task run(); - fork - this.adc_src_axis_agent.master_sequencer.start(); - this.dac_dst_axis_agent.slave_sequencer.start(); - - this.scoreboard_tx.run(); - this.scoreboard_rx.run(); - join_none - endtask - - //============================================================================ - // Stop subroutine - //============================================================================ - task stop(); - this.adc_src_axis_agent.stop_master(); - this.dac_dst_axis_agent.stop_slave(); - endtask - - endclass - -endpackage diff --git a/testbenches/ip/scoreboard/system_bd.tcl b/testbenches/ip/scoreboard/system_bd.tcl index a0d7856a..ec2ae2c4 100644 --- a/testbenches/ip/scoreboard/system_bd.tcl +++ b/testbenches/ip/scoreboard/system_bd.tcl @@ -35,159 +35,28 @@ global ad_project_params -source "$ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl" - -## DUT configuration - -set adc_data_path_width $ad_project_params(ADC_DATA_PATH_WIDTH) -set dac_data_path_width $ad_project_params(DAC_DATA_PATH_WIDTH) - -set adc_path_type $ad_project_params(ADC_PATH_TYPE) -set adc_offload_mem_type $ad_project_params(ADC_OFFLOAD_MEM_TYPE) -set adc_offload_size $ad_project_params(ADC_OFFLOAD_SIZE) -set adc_offload_src_dwidth $ad_project_params(ADC_OFFLOAD_SRC_DWIDTH) -set adc_offload_dst_dwidth $ad_project_params(ADC_OFFLOAD_DST_DWIDTH) - -set dac_path_type $ad_project_params(DAC_PATH_TYPE) -set dac_offload_mem_type $ad_project_params(DAC_OFFLOAD_MEM_TYPE) -set dac_offload_size $ad_project_params(DAC_OFFLOAD_SIZE) -set dac_offload_src_dwidth $ad_project_params(DAC_OFFLOAD_SRC_DWIDTH) -set dac_offload_dst_dwidth $ad_project_params(DAC_OFFLOAD_DST_DWIDTH) - -set plddr_offload_data_width $ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) - -set ddr_axi_pt_cfg [list \ - INTERFACE_MODE {PASS_THROUGH} \ +ad_ip_instance axi4stream_vip adc_src_axis [list \ + INTERFACE_MODE {MASTER} \ + TDATA_NUM_BYTES 2 \ + HAS_TREADY {1} \ + HAS_TKEEP {1} \ + HAS_TLAST {1} \ ] +adi_sim_add_define "ADC_SRC_AXIS=adc_src_axis" -ad_ip_instance xlconstant GND [list \ - CONST_VAL 0 \ -] -ad_connect gnd GND/dout - -for {set i 0} {$i < 2} {incr i} { - ad_ip_instance axi_dmac i_rx_dmac_${i} [list \ - DMA_TYPE_SRC 1 \ - DMA_TYPE_DEST 0 \ - ID 0 \ - AXI_SLICE_SRC 1 \ - AXI_SLICE_DEST 1 \ - SYNC_TRANSFER_START 0 \ - DMA_LENGTH_WIDTH 24 \ - DMA_2D_TRANSFER 0 \ - MAX_BYTES_PER_BURST 4096 \ - CYCLIC 0 \ - DMA_DATA_WIDTH_SRC $adc_offload_dst_dwidth \ - DMA_DATA_WIDTH_DEST 64 \ - ] - - ad_ip_instance axi_dmac i_tx_dmac_${i} [list \ - DMA_TYPE_SRC 0 \ - DMA_TYPE_DEST 1 \ - ID 0 \ - AXI_SLICE_SRC 1 \ - AXI_SLICE_DEST 1 \ - SYNC_TRANSFER_START 0 \ - DMA_LENGTH_WIDTH 24 \ - DMA_2D_TRANSFER 0 \ - MAX_BYTES_PER_BURST 4096 \ - CYCLIC 1 \ - DMA_DATA_WIDTH_SRC 64 \ - DMA_DATA_WIDTH_DEST $dac_offload_src_dwidth \ - ] - - ad_data_offload_create RX_DUT_${i} \ - 0 \ - $adc_offload_mem_type \ - $adc_offload_size \ - $adc_offload_src_dwidth \ - $adc_offload_dst_dwidth \ - $plddr_offload_data_width - - ad_data_offload_create TX_DUT_${i} \ - 1 \ - $dac_offload_mem_type \ - $dac_offload_size \ - $dac_offload_src_dwidth \ - $dac_offload_dst_dwidth \ - $plddr_offload_data_width - - set BA 0x50000000 - ad_cpu_interconnect [expr ${BA} + 0x00000 + $i*0x40000] i_rx_dmac_${i} - ad_cpu_interconnect [expr ${BA} + 0x10000 + $i*0x40000] i_tx_dmac_${i} - ad_cpu_interconnect [expr ${BA} + 0x20000 + $i*0x40000] RX_DUT_${i} - ad_cpu_interconnect [expr ${BA} + 0x30000 + $i*0x40000] TX_DUT_${i} - - adi_sim_add_define "RX_DMA_BA_${i}=[format "%d" [expr ${BA} + 0x00000 + $i*0x40000]]" - adi_sim_add_define "TX_DMA_BA_${i}=[format "%d" [expr ${BA} + 0x10000 + $i*0x40000]]" - adi_sim_add_define "RX_DOFF_BA_${i}=[format "%d" [expr ${BA} + 0x20000 + $i*0x40000]]" - adi_sim_add_define "TX_DOFF_BA_${i}=[format "%d" [expr ${BA} + 0x30000 + $i*0x40000]]" - - ad_ip_instance axi4stream_vip adc_src_axis_${i} [list \ - INTERFACE_MODE {MASTER} \ - HAS_TREADY {1} \ - HAS_TLAST {0} \ - TDATA_NUM_BYTES $adc_data_path_width \ - ] - adi_sim_add_define "ADC_SRC_AXIS_${i}=adc_src_axis_${i}" - - ad_connect adc_src_axis_${i}/m_axis RX_DUT_${i}/s_axis - ad_connect RX_DUT_${i}/m_axis i_rx_dmac_${i}/s_axis - - ad_connect sys_dma_clk adc_src_axis_${i}/aclk - ad_connect sys_dma_resetn adc_src_axis_${i}/aresetn - - ad_connect sys_dma_clk RX_DUT_${i}/s_axis_aclk - ad_connect sys_dma_resetn RX_DUT_${i}/s_axis_aresetn - ad_connect sys_cpu_clk RX_DUT_${i}/m_axis_aclk - ad_connect sys_cpu_resetn RX_DUT_${i}/m_axis_aresetn - - ad_connect sys_cpu_clk i_rx_dmac_${i}/s_axis_aclk - ad_connect sys_mem_clk i_rx_dmac_${i}/m_dest_axi_aclk - ad_connect sys_mem_resetn i_rx_dmac_${i}/m_dest_axi_aresetn - - ad_connect i_rx_dmac_${i}/s_axis_xfer_req RX_DUT_${i}/init_req - ad_connect gnd RX_DUT_${i}/sync_ext +ad_connect sys_dma_clk adc_src_axis/aclk +ad_connect sys_dma_resetn adc_src_axis/aresetn - ad_ip_instance axi_vip adc_dst_axi_pt_${i} $ddr_axi_pt_cfg - adi_sim_add_define "ADC_DST_AXI_PT_${i}=adc_dst_axi_pt_${i}" - - ad_connect i_rx_dmac_${i}/m_dest_axi adc_dst_axi_pt_${i}/S_AXI - - ad_mem_hp0_interconnect sys_mem_clk adc_dst_axi_pt_${i}/M_AXI - ad_connect sys_mem_resetn adc_dst_axi_pt_${i}/aresetn - - ad_ip_instance axi4stream_vip dac_dst_axis_${i} [list \ - INTERFACE_MODE {SLAVE} \ - TDATA_NUM_BYTES $dac_data_path_width \ - HAS_TLAST {1} \ - HAS_TKEEP {0} \ - ] - adi_sim_add_define "DAC_DST_AXIS_${i}=dac_dst_axis_${i}" - - ad_connect sys_dma_clk dac_dst_axis_${i}/aclk - ad_connect sys_dma_resetn dac_dst_axis_${i}/aresetn - - ad_connect sys_dma_clk TX_DUT_${i}/m_axis_aclk - ad_connect sys_dma_resetn TX_DUT_${i}/m_axis_aresetn - ad_connect sys_cpu_clk TX_DUT_${i}/s_axis_aclk - ad_connect sys_cpu_resetn TX_DUT_${i}/s_axis_aresetn - - ad_connect sys_cpu_clk i_tx_dmac_${i}/m_axis_aclk - ad_connect sys_mem_clk i_tx_dmac_${i}/m_src_axi_aclk - ad_connect sys_mem_resetn i_tx_dmac_${i}/m_src_axi_aresetn - - ad_connect TX_DUT_${i}/m_axis dac_dst_axis_${i}/s_axis - ad_connect TX_DUT_${i}/s_axis i_tx_dmac_${i}/m_axis - - ad_connect i_tx_dmac_${i}/m_axis_xfer_req TX_DUT_${i}/init_req - ad_connect gnd TX_DUT_${i}/sync_ext +ad_ip_instance axi4stream_vip dac_dst_axis [list \ + INTERFACE_MODE {SLAVE} \ + TDATA_NUM_BYTES 2 \ + HAS_TREADY {1} \ + HAS_TKEEP {1} \ + HAS_TLAST {1} \ +] +adi_sim_add_define "DAC_DST_AXIS=dac_dst_axis" - ad_ip_instance axi_vip dac_src_axi_pt_${i} $ddr_axi_pt_cfg - adi_sim_add_define "DAC_SRC_AXI_PT_${i}=dac_src_axi_pt_${i}" +ad_connect sys_dma_clk dac_dst_axis/aclk +ad_connect sys_dma_resetn dac_dst_axis/aresetn - ad_connect i_tx_dmac_${i}/m_src_axi dac_src_axi_pt_${i}/S_AXI - - ad_mem_hp0_interconnect sys_mem_clk dac_src_axi_pt_${i}/M_AXI - ad_connect sys_mem_resetn dac_src_axi_pt_${i}/aresetn -} +ad_connect adc_src_axis/m_axis dac_dst_axis/s_axis diff --git a/testbenches/ip/scoreboard/system_project.tcl b/testbenches/ip/scoreboard/system_project.tcl index cedbae72..89695af3 100644 --- a/testbenches/ip/scoreboard/system_project.tcl +++ b/testbenches/ip/scoreboard/system_project.tcl @@ -18,12 +18,9 @@ adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" source $ad_tb_dir/library/includes/sp_include_axis.tcl source $ad_tb_dir/library/includes/sp_include_scoreboard.tcl -source $ad_tb_dir/library/includes/sp_include_dmac.tcl -source $ad_tb_dir/library/includes/sp_include_data_offload.tcl # Add test files to the project adi_sim_project_files [list \ - "environment.sv" \ "tests/test_program.sv" \ ] diff --git a/testbenches/ip/scoreboard/tests/test_program.sv b/testbenches/ip/scoreboard/tests/test_program.sv index dd65c811..03809379 100644 --- a/testbenches/ip/scoreboard/tests/test_program.sv +++ b/testbenches/ip/scoreboard/tests/test_program.sv @@ -39,26 +39,17 @@ import logger_pkg::*; import test_harness_env_pkg::*; -import environment_pkg::*; import adi_axi_agent_pkg::*; import adi_axis_agent_pkg::*; -import dmac_api_pkg::*; -import data_offload_api_pkg::*; +import axi4stream_vip_pkg::*; +import m_axis_sequencer_pkg::*; +import scoreboard_pkg::*; import `PKGIFY(test_harness, mng_axi_vip)::*; import `PKGIFY(test_harness, ddr_axi_vip)::*; -import `PKGIFY(test_harness, adc_src_axis_0)::*; -import `PKGIFY(test_harness, dac_dst_axis_0)::*; -import `PKGIFY(test_harness, adc_dst_axi_pt_0)::*; -import `PKGIFY(test_harness, dac_src_axi_pt_0)::*; - -import `PKGIFY(test_harness, adc_src_axis_1)::*; -import `PKGIFY(test_harness, dac_dst_axis_1)::*; -import `PKGIFY(test_harness, adc_dst_axi_pt_1)::*; -import `PKGIFY(test_harness, dac_src_axi_pt_1)::*; - -`define ADC_TRANSFER_LENGTH 32'h600 +import `PKGIFY(test_harness, adc_src_axis)::*; +import `PKGIFY(test_harness, dac_dst_axis)::*; program test_program(); @@ -68,32 +59,15 @@ program test_program(); adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; - scoreboard_environment scb_env_0; - - adi_axis_master_agent #(`AXIS_VIP_PARAMS(test_harness, adc_src_axis_0)) adc_src_axis_agent_0; - adi_axis_slave_agent #(`AXIS_VIP_PARAMS(test_harness, dac_dst_axis_0)) dac_dst_axis_agent_0; - adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAMS(test_harness, adc_dst_axi_pt_0)) adc_dst_axi_pt_agent_0; - adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAMS(test_harness, dac_src_axi_pt_0)) dac_src_axi_pt_agent_0; - - scoreboard_environment scb_env_1; - - adi_axis_master_agent #(`AXIS_VIP_PARAMS(test_harness, adc_src_axis_1)) adc_src_axis_agent_1; - adi_axis_slave_agent #(`AXIS_VIP_PARAMS(test_harness, dac_dst_axis_1)) dac_dst_axis_agent_1; - adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAMS(test_harness, adc_dst_axi_pt_1)) adc_dst_axi_pt_agent_1; - adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAMS(test_harness, dac_src_axi_pt_1)) dac_src_axi_pt_agent_1; + adi_axis_master_agent #(`AXIS_VIP_PARAMS(test_harness, adc_src_axis)) adc_src_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAMS(test_harness, dac_dst_axis)) dac_dst_axis_agent; - dmac_api dmac_tx_0; - dmac_api dmac_rx_0; - dmac_api dmac_tx_1; - dmac_api dmac_rx_1; - - data_offload_api do_tx_0; - data_offload_api do_rx_0; - data_offload_api do_tx_1; - data_offload_api do_rx_1; + scoreboard #(logic [7:0]) scoreboard; initial begin + setLoggerVerbosity(ADI_VERBOSITY_NONE); + // create environment base_env = new("Base Environment", `TH.`SYS_CLK.inst.IF, @@ -107,94 +81,33 @@ program test_program(); `LINK(mng, base_env, mng) `LINK(ddr, base_env, ddr) - scb_env_0 = new("Scoreboard Environment 0"); - - adc_src_axis_agent_0 = new("", `TH.`ADC_SRC_AXIS_0.inst.IF); - dac_dst_axis_agent_0 = new("", `TH.`DAC_DST_AXIS_0.inst.IF); - adc_dst_axi_pt_agent_0 = new("", `TH.`ADC_DST_AXI_PT_0.inst.IF); - dac_src_axi_pt_agent_0 = new("", `TH.`DAC_SRC_AXI_PT_0.inst.IF); + adc_src_axis_agent = new("", `TH.`ADC_SRC_AXIS.inst.IF); + dac_dst_axis_agent = new("", `TH.`DAC_DST_AXIS.inst.IF); - `LINK(adc_src_axis_agent_0, scb_env_0, adc_src_axis_agent) - `LINK(dac_dst_axis_agent_0, scb_env_0, dac_dst_axis_agent) - `LINK(adc_dst_axi_pt_agent_0, scb_env_0, adc_dst_axi_pt_agent) - `LINK(dac_src_axi_pt_agent_0, scb_env_0, dac_src_axi_pt_agent) + scoreboard = new("Scoreboard"); - scb_env_1 = new("Scoreboard Environment 1"); + adc_src_axis_agent.master_sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); + adc_src_axis_agent.master_sequencer.add_xfer_descriptor_byte_count(32'h100, 1, 0); - adc_src_axis_agent_1 = new("", `TH.`ADC_SRC_AXIS_1.inst.IF); - dac_dst_axis_agent_1 = new("", `TH.`DAC_DST_AXIS_1.inst.IF); - adc_dst_axi_pt_agent_1 = new("", `TH.`ADC_DST_AXI_PT_1.inst.IF); - dac_src_axi_pt_agent_1 = new("", `TH.`DAC_SRC_AXI_PT_1.inst.IF); + dac_dst_axis_agent.slave_sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); - `LINK(adc_src_axis_agent_1, scb_env_1, adc_src_axis_agent) - `LINK(dac_dst_axis_agent_1, scb_env_1, dac_dst_axis_agent) - `LINK(adc_dst_axi_pt_agent_1, scb_env_1, adc_dst_axi_pt_agent) - `LINK(dac_src_axi_pt_agent_1, scb_env_1, dac_src_axi_pt_agent) - - dmac_tx_0 = new("DMAC TX 0", base_env.mng.master_sequencer, `TX_DMA_BA_0); - dmac_rx_0 = new("DMAC RX 0", base_env.mng.master_sequencer, `RX_DMA_BA_0); - dmac_tx_1 = new("DMAC TX 1", base_env.mng.master_sequencer, `TX_DMA_BA_1); - dmac_rx_1 = new("DMAC RX 1", base_env.mng.master_sequencer, `RX_DMA_BA_1); - - do_tx_0 = new("Data Offload TX 0", base_env.mng.master_sequencer, `TX_DOFF_BA_0); - do_rx_0 = new("Data Offload RX 0", base_env.mng.master_sequencer, `RX_DOFF_BA_0); - do_tx_1 = new("Data Offload TX 1", base_env.mng.master_sequencer, `TX_DOFF_BA_1); - do_rx_1 = new("Data Offload RX 1", base_env.mng.master_sequencer, `RX_DOFF_BA_1); - - //========================================================================= - // Setup generator/monitor stubs - //========================================================================= - - //========================================================================= - - setLoggerVerbosity(ADI_VERBOSITY_NONE); - base_env.start(); - scb_env_0.start(); - scb_env_1.start(); - + adc_src_axis_agent.start_master(); + dac_dst_axis_agent.start_slave(); base_env.sys_reset(); - - // configure environment sequencers - scb_env_0.configure(`ADC_TRANSFER_LENGTH); - scb_env_1.configure(`ADC_TRANSFER_LENGTH); - - `INFO(("Bring up IP from reset."), ADI_VERBOSITY_LOW); - systemBringUp(); - - //do_set_transfer_length(`ADC_TRANSFER_LENGTH); - do_set_transfer_length(`ADC_TRANSFER_LENGTH/64); - // Start the ADC/DAC stubs - `INFO(("Start the sequencer"), ADI_VERBOSITY_LOW); - scb_env_0.adc_src_axis_agent.master_sequencer.start(); - scb_env_1.adc_src_axis_agent.master_sequencer.start(); - - // Generate DMA transfers - `INFO(("Start RX DMA"), ADI_VERBOSITY_LOW); - rx_dma_transfer(dmac_rx_0, 32'h80000000, `ADC_TRANSFER_LENGTH); - rx_dma_transfer(dmac_rx_1, 32'h80000000, `ADC_TRANSFER_LENGTH); - - fork - scb_env_0.scoreboard_rx.wait_until_complete(); - scb_env_1.scoreboard_rx.wait_until_complete(); - join - - `INFO(("Initialize the memory"), ADI_VERBOSITY_LOW); - init_mem_64(32'h80000000, 1024); + adc_src_axis_agent.monitor.publisher.subscribe(scoreboard.subscriber_source); + dac_dst_axis_agent.monitor.publisher.subscribe(scoreboard.subscriber_sink); + + scoreboard.run(); - `INFO(("Start TX DMA"), ADI_VERBOSITY_LOW); - tx_dma_transfer(dmac_tx_0, 32'h80000000, 1024); - tx_dma_transfer(dmac_tx_1, 32'h80000000, 1024); + adc_src_axis_agent.master_sequencer.start(); + dac_dst_axis_agent.slave_sequencer.start(); #1us; - fork - scb_env_0.scoreboard_tx.wait_until_complete(); - scb_env_1.scoreboard_tx.wait_until_complete(); - join + + scoreboard.wait_until_complete(); - scb_env_0.stop(); - scb_env_1.stop(); base_env.stop(); `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); @@ -202,71 +115,4 @@ program test_program(); end - task systemBringUp(); - // bring up the Data Offload instances from reset - `INFO(("Bring up RX Data Offload 0"), ADI_VERBOSITY_LOW); - do_rx_0.deassert_reset(); - `INFO(("Bring up TX Data Offload 0"), ADI_VERBOSITY_LOW); - do_tx_0.deassert_reset(); - - `INFO(("Bring up RX Data Offload 1"), ADI_VERBOSITY_LOW); - do_rx_1.deassert_reset(); - `INFO(("Bring up TX Data Offload 1"), ADI_VERBOSITY_LOW); - do_tx_1.deassert_reset(); - - // Enable tx oneshot mode - do_tx_0.enable_oneshot_mode(); - do_tx_1.enable_oneshot_mode(); - - // bring up the DMAC instances from reset - `INFO(("Bring up RX DMAC 0"), ADI_VERBOSITY_LOW); - dmac_rx_0.enable_dma(); - `INFO(("Bring up TX DMAC 0"), ADI_VERBOSITY_LOW); - dmac_tx_0.enable_dma(); - - `INFO(("Bring up RX DMAC 1"), ADI_VERBOSITY_LOW); - dmac_rx_1.enable_dma(); - `INFO(("Bring up TX DMAC 1"), ADI_VERBOSITY_LOW); - dmac_tx_1.enable_dma(); - endtask - - task do_set_transfer_length(input int length); - do_rx_0.set_transfer_length(length); - do_rx_1.set_transfer_length(length); - endtask - - // RX DMA transfer generator - task rx_dma_transfer( - input dmac_api dmac, - input int xfer_addr, - input int xfer_length); - dmac.set_flags('b110); - dmac.set_dest_addr(xfer_addr); - dmac.set_lengths(xfer_length - 1, 0); - dmac.transfer_start(); - endtask - - // TX DMA transfer generator - task tx_dma_transfer( - input dmac_api dmac, - input int xfer_addr, - input int xfer_length); - dmac.set_flags('b010); // enable TLAST, CYCLIC - dmac.set_src_addr(xfer_addr); - dmac.set_lengths(xfer_length - 1, 0); - dmac.transfer_start(); - endtask - - // Memory initialization function for a 8byte DATA_WIDTH AXI4 bus - task init_mem_64( - input longint unsigned addr, - input int byte_length); - `INFO(("Initial address: %x", addr), ADI_VERBOSITY_LOW); - for (int i=0; i - - - - + + + + + + + - - - - - - + - - - - - - - - - + + - + - - - M_AXI - M_AXI + + + M_AXIS + M_AXIS - - RX - label - - - RX_DO - label - - - s_axis - s_axis - - - m_axis - m_axis - - - - RX_DMA - label - - - s_axis - s_axis - - - m_dest_axi - m_dest_axi - - - - TX - label - - - TX_DMA - label - - - m_src_axi - m_src_axi - - - m_axis - m_axis - - - - TX_DO - label - - - s_axis - s_axis - - - m_axis - m_axis - + + S_AXIS + S_AXIS From 1961396cd2af0c3fe6e3d709db9c3eaa0e527791 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Thu, 20 Feb 2025 13:02:32 +0200 Subject: [PATCH 33/37] scoreboard: Commented test program Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/scoreboard/tests/test_program.sv | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/testbenches/ip/scoreboard/tests/test_program.sv b/testbenches/ip/scoreboard/tests/test_program.sv index 03809379..200c0222 100644 --- a/testbenches/ip/scoreboard/tests/test_program.sv +++ b/testbenches/ip/scoreboard/tests/test_program.sv @@ -86,26 +86,31 @@ program test_program(); scoreboard = new("Scoreboard"); + // configure the sequencers adc_src_axis_agent.master_sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); adc_src_axis_agent.master_sequencer.add_xfer_descriptor_byte_count(32'h100, 1, 0); dac_dst_axis_agent.slave_sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + // start the environment base_env.start(); adc_src_axis_agent.start_master(); dac_dst_axis_agent.start_slave(); base_env.sys_reset(); + // subscribe and start the scoreboard adc_src_axis_agent.monitor.publisher.subscribe(scoreboard.subscriber_source); dac_dst_axis_agent.monitor.publisher.subscribe(scoreboard.subscriber_sink); scoreboard.run(); + // generate data adc_src_axis_agent.master_sequencer.start(); dac_dst_axis_agent.slave_sequencer.start(); #1us; + // wait for scoreboard to be empty on both sides scoreboard.wait_until_complete(); base_env.stop(); From bffecca999e676dbd6433883bac4b7c252dce808 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 17 Feb 2025 15:58:35 +0200 Subject: [PATCH 34/37] packet_filter: Initial commit - Added packet filter base class - Updated publisher with the filter class Signed-off-by: Istvan-Zsolt Szekely --- library/utilities/filter_pkg.sv | 58 ++++++++++++++++++++++++++++++++ library/utilities/pub_sub_pkg.sv | 28 ++++++++++++--- 2 files changed, 81 insertions(+), 5 deletions(-) create mode 100644 library/utilities/filter_pkg.sv diff --git a/library/utilities/filter_pkg.sv b/library/utilities/filter_pkg.sv new file mode 100644 index 00000000..8a7b702d --- /dev/null +++ b/library/utilities/filter_pkg.sv @@ -0,0 +1,58 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +package filter_pkg; + + import logger_pkg::*; + import adi_common_pkg::*; + + class adi_filter #(type data_type = int) extends adi_component; + + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + endfunction: new + + virtual function bit filter(input data_type data [$]); + return 1'b0; + endfunction: filter + + endclass: adi_filter + +endpackage diff --git a/library/utilities/pub_sub_pkg.sv b/library/utilities/pub_sub_pkg.sv index 96044b7f..a930baa3 100644 --- a/library/utilities/pub_sub_pkg.sv +++ b/library/utilities/pub_sub_pkg.sv @@ -66,30 +66,48 @@ package pub_sub_pkg; protected adi_subscriber #(data_type) subscriber_list[bit[15:0]]; + protected adi_filter #(data_type) filter; + function new( input string name, input adi_component parent = null); super.new(name, parent); endfunction: new + + function void setup_filter(input adi_filter #(data_type) filter); + this.filter = filter; + endfunction: setup_filter + + function void remove_filter(); + this.filter = null; + endfunction: remove_filter function void subscribe(input adi_subscriber #(data_type) subscriber); - if (this.subscriber_list.exists(subscriber.id)) + if (this.subscriber_list.exists(subscriber.id)) begin this.error($sformatf("Subscriber already on the list!")); - else + end else begin this.subscriber_list[subscriber.id] = subscriber; + end endfunction: subscribe function void unsubscribe(input adi_subscriber #(data_type) subscriber); - if (!this.subscriber_list.exists(subscriber.id)) + if (!this.subscriber_list.exists(subscriber.id)) begin this.error($sformatf("Subscriber does not exist on list!")); - else + end else begin this.subscriber_list.delete(subscriber.id); + end endfunction: unsubscribe function void notify(input data_type data [$]); - foreach (this.subscriber_list[i]) + if (this.filter != null) begin + if (!this.filter.filter(data)) begin + return; + end + end + foreach (this.subscriber_list[i]) begin this.subscriber_list[i].update(data); + end endfunction: notify endclass: adi_publisher From baf31fd766140e1babb45f6383419e1ee3b56527 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 17 Feb 2025 16:11:21 +0200 Subject: [PATCH 35/37] packet_filter: Add dependencies Signed-off-by: Istvan-Zsolt Szekely --- library/includes/Makeinclude_scoreboard.mk | 1 + library/includes/sp_include_scoreboard.tcl | 1 + library/utilities/pub_sub_pkg.sv | 1 + 3 files changed, 3 insertions(+) diff --git a/library/includes/Makeinclude_scoreboard.mk b/library/includes/Makeinclude_scoreboard.mk index 76c8c8b0..ea9eb5d7 100644 --- a/library/includes/Makeinclude_scoreboard.mk +++ b/library/includes/Makeinclude_scoreboard.mk @@ -3,6 +3,7 @@ #################################################################################### # All test-bench dependencies except test programs +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/filter_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/scoreboard.sv SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/scoreboard_pack.sv diff --git a/library/includes/sp_include_scoreboard.tcl b/library/includes/sp_include_scoreboard.tcl index 22fd1cc9..ebdacdf2 100644 --- a/library/includes/sp_include_scoreboard.tcl +++ b/library/includes/sp_include_scoreboard.tcl @@ -35,6 +35,7 @@ # Add test files to the project adi_sim_project_files [list \ + "$ad_tb_dir/library/utilities/filter_pkg.sv" \ "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ "$ad_tb_dir/library/drivers/common/scoreboard.sv" \ "$ad_tb_dir/library/drivers/common/scoreboard_pack.sv" \ diff --git a/library/utilities/pub_sub_pkg.sv b/library/utilities/pub_sub_pkg.sv index a930baa3..ecc1872f 100644 --- a/library/utilities/pub_sub_pkg.sv +++ b/library/utilities/pub_sub_pkg.sv @@ -39,6 +39,7 @@ package pub_sub_pkg; import logger_pkg::*; import adi_common_pkg::*; + import filter_pkg::*; class adi_subscriber #(type data_type = int) extends adi_component; From a878252c02eb0492ddd1eefe7ce48e7fb0943fb7 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Tue, 25 Feb 2025 17:05:38 +0200 Subject: [PATCH 36/37] packet_filter: Add sandbox testbench Signed-off-by: Istvan-Zsolt Szekely --- library/includes/Makeinclude_axi.mk | 1 + library/includes/Makeinclude_axis.mk | 1 + library/includes/Makeinclude_scoreboard.mk | 2 - library/includes/sp_include_axi.tcl | 1 + library/includes/sp_include_axis.tcl | 1 + library/includes/sp_include_scoreboard.tcl | 2 - library/vip/amd/axis/adi_axis_monitor.sv | 12 +- testbenches/ip/packet_filter/Makefile | 42 +++++ testbenches/ip/packet_filter/README.md | 27 ++++ testbenches/ip/packet_filter/cfgs/cfg1.tcl | 1 + testbenches/ip/packet_filter/system_bd.tcl | 62 +++++++ .../ip/packet_filter/system_project.tcl | 30 ++++ testbenches/ip/packet_filter/system_tb.sv | 45 ++++++ .../ip/packet_filter/tests/test_program.sv | 153 ++++++++++++++++++ testbenches/ip/packet_filter/waves/cfg1.wcfg | 53 ++++++ 15 files changed, 424 insertions(+), 9 deletions(-) create mode 100644 testbenches/ip/packet_filter/Makefile create mode 100644 testbenches/ip/packet_filter/README.md create mode 100644 testbenches/ip/packet_filter/cfgs/cfg1.tcl create mode 100644 testbenches/ip/packet_filter/system_bd.tcl create mode 100644 testbenches/ip/packet_filter/system_project.tcl create mode 100644 testbenches/ip/packet_filter/system_tb.sv create mode 100644 testbenches/ip/packet_filter/tests/test_program.sv create mode 100644 testbenches/ip/packet_filter/waves/cfg1.wcfg diff --git a/library/includes/Makeinclude_axi.mk b/library/includes/Makeinclude_axi.mk index 5db1b2d8..839f5c17 100644 --- a/library/includes/Makeinclude_axi.mk +++ b/library/includes/Makeinclude_axi.mk @@ -9,3 +9,4 @@ SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/s_axi_sequencer.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/adi_axi_monitor.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/axi_definitions.svh SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/filter_pkg.sv diff --git a/library/includes/Makeinclude_axis.mk b/library/includes/Makeinclude_axis.mk index 2ecbf0d1..75e2a261 100644 --- a/library/includes/Makeinclude_axis.mk +++ b/library/includes/Makeinclude_axis.mk @@ -9,3 +9,4 @@ SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/s_axis_sequencer.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/adi_axis_monitor.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/axis_definitions.svh SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/filter_pkg.sv diff --git a/library/includes/Makeinclude_scoreboard.mk b/library/includes/Makeinclude_scoreboard.mk index ea9eb5d7..a602c4ea 100644 --- a/library/includes/Makeinclude_scoreboard.mk +++ b/library/includes/Makeinclude_scoreboard.mk @@ -3,7 +3,5 @@ #################################################################################### # All test-bench dependencies except test programs -SV_DEPS += $(TB_LIBRARY_PATH)/utilities/filter_pkg.sv -SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/scoreboard.sv SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/scoreboard_pack.sv diff --git a/library/includes/sp_include_axi.tcl b/library/includes/sp_include_axi.tcl index 50885ff7..d3db8f7b 100644 --- a/library/includes/sp_include_axi.tcl +++ b/library/includes/sp_include_axi.tcl @@ -41,4 +41,5 @@ adi_sim_project_files [list \ "$ad_tb_dir/library/vip/amd/axi/adi_axi_monitor.sv" \ "$ad_tb_dir/library/vip/amd/axi/axi_definitions.svh" \ "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ + "$ad_tb_dir/library/utilities/filter_pkg.sv" \ ] diff --git a/library/includes/sp_include_axis.tcl b/library/includes/sp_include_axis.tcl index 28a261dd..774b05af 100644 --- a/library/includes/sp_include_axis.tcl +++ b/library/includes/sp_include_axis.tcl @@ -41,4 +41,5 @@ adi_sim_project_files [list \ "$ad_tb_dir/library/vip/amd/axis/adi_axis_monitor.sv" \ "$ad_tb_dir/library/vip/amd/axis/axis_definitions.svh" \ "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ + "$ad_tb_dir/library/utilities/filter_pkg.sv" \ ] diff --git a/library/includes/sp_include_scoreboard.tcl b/library/includes/sp_include_scoreboard.tcl index ebdacdf2..5a0c44c7 100644 --- a/library/includes/sp_include_scoreboard.tcl +++ b/library/includes/sp_include_scoreboard.tcl @@ -35,8 +35,6 @@ # Add test files to the project adi_sim_project_files [list \ - "$ad_tb_dir/library/utilities/filter_pkg.sv" \ - "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ "$ad_tb_dir/library/drivers/common/scoreboard.sv" \ "$ad_tb_dir/library/drivers/common/scoreboard_pack.sv" \ ] diff --git a/library/vip/amd/axis/adi_axis_monitor.sv b/library/vip/amd/axis/adi_axis_monitor.sv index 9a4386f9..becef6a9 100644 --- a/library/vip/amd/axis/adi_axis_monitor.sv +++ b/library/vip/amd/axis/adi_axis_monitor.sv @@ -118,7 +118,7 @@ package adi_axis_monitor_pkg; xil_axi4stream_data_beat data_beat; xil_axi4stream_strb_beat keep_beat; int num_bytes; - logic [7:0] axi_byte; + logic [7:0] axis_byte; logic [7:0] data_queue [$]; forever begin @@ -128,13 +128,15 @@ package adi_axis_monitor_pkg; data_beat = transaction.get_data_beat(); keep_beat = transaction.get_keep_beat(); for (int j=0; j_.tcl +CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) +#$(warning $(CFG_FILES)) + +# List of tests and configuration combinations that has to be run +# Format is: : +TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP)) +#TESTS += cfg1_mm2mm_default:directed_test +#TESTS += cfg1:test_program +#TESTS += cfg2_fsync:test_program +#TESTS += cfg2_fsync:test_frame_delay + +include $(ADI_TB_DIR)/scripts/project-sim.mk + +# usage : +# +# run specific test on a specific configuration in gui mode +# make CFG=cfg2_fsync TST=test_frame_delay MODE=gui +# +# run all test from a configuration +# make cfg1_mm2mm_default + +#################################################################################### +#################################################################################### diff --git a/testbenches/ip/packet_filter/README.md b/testbenches/ip/packet_filter/README.md new file mode 100644 index 00000000..f1495cb4 --- /dev/null +++ b/testbenches/ip/packet_filter/README.md @@ -0,0 +1,27 @@ +Usage : + +Run all tests in batch mode: + + make + + +Run all tests in GUI mode: + + make MODE=gui + + +Run specific test on a specific configuration in gui mode: + + make CFG= TST= MODE=gui + + +Run all test from a configuration: + + make + + +Where: + + * is a file from the cfgs directory without the tcl extension of format cfg\* + * is a file from the tests directory without the tcl extension + diff --git a/testbenches/ip/packet_filter/cfgs/cfg1.tcl b/testbenches/ip/packet_filter/cfgs/cfg1.tcl new file mode 100644 index 00000000..d040d253 --- /dev/null +++ b/testbenches/ip/packet_filter/cfgs/cfg1.tcl @@ -0,0 +1 @@ +global ad_project_params diff --git a/testbenches/ip/packet_filter/system_bd.tcl b/testbenches/ip/packet_filter/system_bd.tcl new file mode 100644 index 00000000..ec2ae2c4 --- /dev/null +++ b/testbenches/ip/packet_filter/system_bd.tcl @@ -0,0 +1,62 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. +# +# In this HDL repository, there are many different and unique modules, consisting +# of various HDL (Verilog or VHDL) components. The individual modules are +# developed independently, and may be accompanied by separate and unique license +# terms. +# +# The user should read each of these license terms, and understand the +# freedoms and responsibilities that he or she has by using this source/core. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. +# +# Redistribution and use of source or resulting binaries, with or without modification +# of this file, are permitted under one of the following two license terms: +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory +# of this repository (LICENSE_GPL2), and also online at: +# +# +# OR +# +# 2. An ADI specific BSD license, which can be found in the top level directory +# of this repository (LICENSE_ADIBSD), and also on-line at: +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +# This will allow to generate bit files and not release the source code, +# as long as it attaches to an ADI device. +# +# *************************************************************************** +# *************************************************************************** + +global ad_project_params + +ad_ip_instance axi4stream_vip adc_src_axis [list \ + INTERFACE_MODE {MASTER} \ + TDATA_NUM_BYTES 2 \ + HAS_TREADY {1} \ + HAS_TKEEP {1} \ + HAS_TLAST {1} \ +] +adi_sim_add_define "ADC_SRC_AXIS=adc_src_axis" + +ad_connect sys_dma_clk adc_src_axis/aclk +ad_connect sys_dma_resetn adc_src_axis/aresetn + +ad_ip_instance axi4stream_vip dac_dst_axis [list \ + INTERFACE_MODE {SLAVE} \ + TDATA_NUM_BYTES 2 \ + HAS_TREADY {1} \ + HAS_TKEEP {1} \ + HAS_TLAST {1} \ +] +adi_sim_add_define "DAC_DST_AXIS=dac_dst_axis" + +ad_connect sys_dma_clk dac_dst_axis/aclk +ad_connect sys_dma_resetn dac_dst_axis/aresetn + +ad_connect adc_src_axis/m_axis dac_dst_axis/s_axis diff --git a/testbenches/ip/packet_filter/system_project.tcl b/testbenches/ip/packet_filter/system_project.tcl new file mode 100644 index 00000000..89695af3 --- /dev/null +++ b/testbenches/ip/packet_filter/system_project.tcl @@ -0,0 +1,30 @@ +source ../../../scripts/adi_sim.tcl + +if {$argc < 1} { + puts "Expecting at least one argument that specifies the test configuration" + exit 1 +} else { + set cfg_file [lindex $argv 0] +} + +# Read config file +source "cfgs/${cfg_file}" + +# Set the project name +set project_name [file rootname $cfg_file] + +# Create the project +adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" + +source $ad_tb_dir/library/includes/sp_include_axis.tcl +source $ad_tb_dir/library/includes/sp_include_scoreboard.tcl + +# Add test files to the project +adi_sim_project_files [list \ + "tests/test_program.sv" \ +] + +#set a default test program +adi_sim_add_define "TEST_PROGRAM=test_program" + +adi_sim_generate $project_name diff --git a/testbenches/ip/packet_filter/system_tb.sv b/testbenches/ip/packet_filter/system_tb.sv new file mode 100644 index 00000000..2723b531 --- /dev/null +++ b/testbenches/ip/packet_filter/system_tb.sv @@ -0,0 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014 - 2022 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +`include "utils.svh" + +module system_tb(); + + `TEST_PROGRAM test(); + test_harness `TH (); + +endmodule diff --git a/testbenches/ip/packet_filter/tests/test_program.sv b/testbenches/ip/packet_filter/tests/test_program.sv new file mode 100644 index 00000000..1e99107e --- /dev/null +++ b/testbenches/ip/packet_filter/tests/test_program.sv @@ -0,0 +1,153 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" +`include "axi_definitions.svh" +`include "axis_definitions.svh" + +import logger_pkg::*; +import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; +import adi_axis_agent_pkg::*; +import axi4stream_vip_pkg::*; +import m_axis_sequencer_pkg::*; +import scoreboard_pkg::*; +import filter_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +import `PKGIFY(test_harness, adc_src_axis)::*; +import `PKGIFY(test_harness, dac_dst_axis)::*; + +program test_program(); + + // declare the class instances + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + + adi_axis_master_agent #(`AXIS_VIP_PARAMS(test_harness, adc_src_axis)) adc_src_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAMS(test_harness, dac_dst_axis)) dac_dst_axis_agent; + + scoreboard #(logic [7:0]) scoreboard; + + class filter_class extends adi_filter#(.data_type(logic [7:0])); + + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + endfunction: new + + virtual function bit filter(input data_type data [$]); + if (data.pop_front() == 8'h00) begin + this.info($sformatf("Packet filtered"), ADI_VERBOSITY_NONE); + return 1'b0; + end else begin + this.info($sformatf("Packet Not filtered"), ADI_VERBOSITY_NONE); + return 1'b1; + end + endfunction: filter + + endclass: filter_class + + filter_class filter; + + + initial begin + + setLoggerVerbosity(ADI_VERBOSITY_NONE); + + // create environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) + + adc_src_axis_agent = new("Source", `TH.`ADC_SRC_AXIS.inst.IF); + dac_dst_axis_agent = new("Destination", `TH.`DAC_DST_AXIS.inst.IF); + + filter = new("Filter"); + + adc_src_axis_agent.monitor.publisher.setup_filter(filter); + dac_dst_axis_agent.monitor.publisher.setup_filter(filter); + + scoreboard = new("Scoreboard"); + + // configure the sequencers + adc_src_axis_agent.master_sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); + adc_src_axis_agent.master_sequencer.add_xfer_descriptor_byte_count(32'h100, 1, 0); + + dac_dst_axis_agent.slave_sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + + // start the environment + base_env.start(); + adc_src_axis_agent.start_master(); + dac_dst_axis_agent.start_slave(); + base_env.sys_reset(); + + // subscribe and start the scoreboard + adc_src_axis_agent.monitor.publisher.subscribe(scoreboard.subscriber_source); + dac_dst_axis_agent.monitor.publisher.subscribe(scoreboard.subscriber_sink); + + scoreboard.run(); + + // generate data + adc_src_axis_agent.master_sequencer.start(); + dac_dst_axis_agent.slave_sequencer.start(); + + #1us; + + // wait for scoreboard to be empty on both sides + scoreboard.wait_until_complete(); + + base_env.stop(); + + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); + $finish(); + + end + +endprogram diff --git a/testbenches/ip/packet_filter/waves/cfg1.wcfg b/testbenches/ip/packet_filter/waves/cfg1.wcfg new file mode 100644 index 00000000..3a570f4d --- /dev/null +++ b/testbenches/ip/packet_filter/waves/cfg1.wcfg @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + M_AXIS + M_AXIS + + + S_AXIS + S_AXIS + + From 920634fa91d5aa148e993518dd727322faab85d3 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Wed, 26 Feb 2025 13:57:59 +0200 Subject: [PATCH 37/37] packet_processor: Initial commit - Created the base class and added it to the publisher class - Created a sandbox testbench for the packet processor - Updated the main library files to use the ADI FIFOs due to language limitations - Added a separate include set for publisher-subscriber, packet filter and processor classes Signed-off-by: Istvan-Zsolt Szekely --- library/drivers/common/scoreboard.sv | 13 +- library/includes/Makeinclude_axi.mk | 5 +- library/includes/Makeinclude_axis.mk | 5 +- library/includes/Makeinclude_publisher.mk | 9 + library/includes/sp_include_axi.tcl | 4 +- library/includes/sp_include_axis.tcl | 4 +- library/includes/sp_include_publisher.tcl | 42 +++++ library/utilities/adi_datatypes.sv | 66 ++++---- library/utilities/filter_pkg.sv | 5 +- library/utilities/packet_processor_pkg.sv | 59 +++++++ library/utilities/pub_sub_pkg.sv | 33 +++- library/vip/amd/axi/adi_axi_monitor.sv | 8 +- library/vip/amd/axis/adi_axis_monitor.sv | 7 +- .../ip/packet_filter/tests/test_program.sv | 5 +- testbenches/ip/packet_processor/Makefile | 42 +++++ testbenches/ip/packet_processor/README.md | 27 +++ testbenches/ip/packet_processor/cfgs/cfg1.tcl | 1 + testbenches/ip/packet_processor/system_bd.tcl | 62 +++++++ .../ip/packet_processor/system_project.tcl | 30 ++++ testbenches/ip/packet_processor/system_tb.sv | 45 +++++ .../ip/packet_processor/tests/test_program.sv | 158 ++++++++++++++++++ .../ip/packet_processor/waves/cfg1.wcfg | 53 ++++++ 22 files changed, 624 insertions(+), 59 deletions(-) create mode 100644 library/includes/Makeinclude_publisher.mk create mode 100644 library/includes/sp_include_publisher.tcl create mode 100644 library/utilities/packet_processor_pkg.sv create mode 100644 testbenches/ip/packet_processor/Makefile create mode 100644 testbenches/ip/packet_processor/README.md create mode 100644 testbenches/ip/packet_processor/cfgs/cfg1.tcl create mode 100644 testbenches/ip/packet_processor/system_bd.tcl create mode 100644 testbenches/ip/packet_processor/system_project.tcl create mode 100644 testbenches/ip/packet_processor/system_tb.sv create mode 100644 testbenches/ip/packet_processor/tests/test_program.sv create mode 100644 testbenches/ip/packet_processor/waves/cfg1.wcfg diff --git a/library/drivers/common/scoreboard.sv b/library/drivers/common/scoreboard.sv index b2d54f43..6682eade 100644 --- a/library/drivers/common/scoreboard.sv +++ b/library/drivers/common/scoreboard.sv @@ -39,6 +39,7 @@ package scoreboard_pkg; import logger_pkg::*; import adi_common_pkg::*; + import adi_datatypes_pkg::*; import pub_sub_pkg::*; class scoreboard #(type data_type = int) extends adi_component; @@ -47,7 +48,7 @@ package scoreboard_pkg; protected scoreboard #(data_type) scoreboard_ref; - protected data_type byte_stream [$]; + protected adi_fifo #(data_type) byte_stream; function new( input string name, @@ -57,12 +58,14 @@ package scoreboard_pkg; super.new(name, parent); this.scoreboard_ref = scoreboard_ref; + + byte_stream = new("Data queue", 0, this); endfunction: new - virtual function void update(input data_type data [$]); + virtual function void update(input adi_fifo #(data_type) data); this.info($sformatf("Data received: %d", data.size()), ADI_VERBOSITY_MEDIUM); while (data.size()) begin - this.byte_stream.push_back(data.pop_front()); + void'(this.byte_stream.push(data.pop())); end if (this.scoreboard_ref.get_enabled()) begin @@ -71,11 +74,11 @@ package scoreboard_pkg; endfunction: update function data_type get_data(); - return this.byte_stream.pop_front(); + return this.byte_stream.pop(); endfunction: get_data function void put_data(data_type data); - this.byte_stream.push_back(data); + void'(this.byte_stream.push(data)); endfunction: put_data function int get_size(); diff --git a/library/includes/Makeinclude_axi.mk b/library/includes/Makeinclude_axi.mk index 839f5c17..197443da 100644 --- a/library/includes/Makeinclude_axi.mk +++ b/library/includes/Makeinclude_axi.mk @@ -2,11 +2,12 @@ #################################################################################### #################################################################################### +# Makeincludes +include $(TB_LIBRARY_PATH)/includes/Makeinclude_publisher.mk + # All test-bench dependencies except test programs SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/adi_axi_agent.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/m_axi_sequencer.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/s_axi_sequencer.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/adi_axi_monitor.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/axi_definitions.svh -SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv -SV_DEPS += $(TB_LIBRARY_PATH)/utilities/filter_pkg.sv diff --git a/library/includes/Makeinclude_axis.mk b/library/includes/Makeinclude_axis.mk index 75e2a261..c1ab0298 100644 --- a/library/includes/Makeinclude_axis.mk +++ b/library/includes/Makeinclude_axis.mk @@ -2,11 +2,12 @@ #################################################################################### #################################################################################### +# Makeincludes +include $(TB_LIBRARY_PATH)/includes/Makeinclude_publisher.mk + # All test-bench dependencies except test programs SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/adi_axis_agent.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/m_axis_sequencer.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/s_axis_sequencer.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/adi_axis_monitor.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/axis_definitions.svh -SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv -SV_DEPS += $(TB_LIBRARY_PATH)/utilities/filter_pkg.sv diff --git a/library/includes/Makeinclude_publisher.mk b/library/includes/Makeinclude_publisher.mk new file mode 100644 index 00000000..bd9c22cb --- /dev/null +++ b/library/includes/Makeinclude_publisher.mk @@ -0,0 +1,9 @@ +## Copyright (C) 2024 Analog Devices, Inc. +#################################################################################### +#################################################################################### + +# All test-bench dependencies except test programs +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/filter_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/packet_processor_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/adi_datatypes.sv diff --git a/library/includes/sp_include_axi.tcl b/library/includes/sp_include_axi.tcl index d3db8f7b..9d308f10 100644 --- a/library/includes/sp_include_axi.tcl +++ b/library/includes/sp_include_axi.tcl @@ -33,6 +33,8 @@ # *************************************************************************** # *************************************************************************** +source $ad_tb_dir/library/includes/sp_include_publisher.tcl + # Add test files to the project adi_sim_project_files [list \ "$ad_tb_dir/library/vip/amd/axi/adi_axi_agent.sv" \ @@ -40,6 +42,4 @@ adi_sim_project_files [list \ "$ad_tb_dir/library/vip/amd/axi/s_axi_sequencer.sv" \ "$ad_tb_dir/library/vip/amd/axi/adi_axi_monitor.sv" \ "$ad_tb_dir/library/vip/amd/axi/axi_definitions.svh" \ - "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ - "$ad_tb_dir/library/utilities/filter_pkg.sv" \ ] diff --git a/library/includes/sp_include_axis.tcl b/library/includes/sp_include_axis.tcl index 774b05af..d02095f2 100644 --- a/library/includes/sp_include_axis.tcl +++ b/library/includes/sp_include_axis.tcl @@ -33,6 +33,8 @@ # *************************************************************************** # *************************************************************************** +source $ad_tb_dir/library/includes/sp_include_publisher.tcl + # Add test files to the project adi_sim_project_files [list \ "$ad_tb_dir/library/vip/amd/axis/adi_axis_agent.sv" \ @@ -40,6 +42,4 @@ adi_sim_project_files [list \ "$ad_tb_dir/library/vip/amd/axis/s_axis_sequencer.sv" \ "$ad_tb_dir/library/vip/amd/axis/adi_axis_monitor.sv" \ "$ad_tb_dir/library/vip/amd/axis/axis_definitions.svh" \ - "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ - "$ad_tb_dir/library/utilities/filter_pkg.sv" \ ] diff --git a/library/includes/sp_include_publisher.tcl b/library/includes/sp_include_publisher.tcl new file mode 100644 index 00000000..a280fb88 --- /dev/null +++ b/library/includes/sp_include_publisher.tcl @@ -0,0 +1,42 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +# +# In this HDL repository, there are many different and unique modules, consisting +# of various HDL (Verilog or VHDL) components. The individual modules are +# developed independently, and may be accompanied by separate and unique license +# terms. +# +# The user should read each of these license terms, and understand the +# freedoms and responsibilities that he or she has by using this source/core. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. +# +# Redistribution and use of source or resulting binaries, with or without modification +# of this file, are permitted under one of the following two license terms: +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory +# of this repository (LICENSE_GPL2), and also online at: +# +# +# OR +# +# 2. An ADI specific BSD license, which can be found in the top level directory +# of this repository (LICENSE_ADIBSD), and also on-line at: +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +# This will allow to generate bit files and not release the source code, +# as long as it attaches to an ADI device. +# +# *************************************************************************** +# *************************************************************************** + +# Add test files to the project +adi_sim_project_files [list \ + "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ + "$ad_tb_dir/library/utilities/filter_pkg.sv" \ + "$ad_tb_dir/library/utilities/packet_processor_pkg.sv" \ + "$ad_tb_dir/library/utilities/adi_datatypes.sv" \ +] diff --git a/library/utilities/adi_datatypes.sv b/library/utilities/adi_datatypes.sv index 73c63dc9..73e2fd07 100644 --- a/library/utilities/adi_datatypes.sv +++ b/library/utilities/adi_datatypes.sv @@ -42,7 +42,7 @@ package adi_datatypes_pkg; class adi_fifo #(type data_type = int) extends adi_component; - local data_type adi_fifo [$]; + local data_type fifo [$]; local int depth; function new( @@ -56,52 +56,53 @@ package adi_datatypes_pkg; endfunction: new function bit push(input data_type data); - if (this.adi_fifo.size() == this.depth && this.depth != 0) begin + if (this.fifo.size() == this.depth && this.depth != 0) begin + this.warning($sformatf("FIFO is full!")); return 1'b0; end else begin - this.adi_fifo.push_back(data); + this.fifo.push_back(data); return 1'b1; end endfunction: push function data_type pop(); - if (this.adi_fifo.size() == 0) begin - return null; - end else begin - return this.adi_fifo.pop_front(); + if (this.fifo.size() == 0) begin + this.warning($sformatf("FIFO is empty!")); end + return this.fifo.pop_front(); endfunction: pop function int room(); - return depth-this.adi_fifo.size(); + return depth-this.fifo.size(); endfunction: room function int size(); - return this.adi_fifo.size(); - endfunction: room + return this.fifo.size(); + endfunction: size - function void clear(); - this.adi_fifo.delete(); - endfunction: clear + function void delete(); + this.fifo.delete(); + endfunction: delete function bit insert( input int index, input data_type data); - if (this.adi_fifo.size() == this.depth && this.depth != 0) begin + if (this.fifo.size() == this.depth && this.depth != 0) begin + this.warning($sformatf("FIFO is full!")); return 1'b0; end else begin - this.adi_fifo.insert(index, data); + this.fifo.insert(index, data); return 1'b1; end - endfunction: clear + endfunction: insert endclass: adi_fifo class adi_lifo #(type data_type = int) extends adi_component; - local data_type adi_fifo [$]; + local data_type lifo [$]; local int depth; function new( @@ -115,45 +116,46 @@ package adi_datatypes_pkg; endfunction: new function bit push(input data_type data); - if (this.adi_fifo.size() == this.depth && this.depth != 0) begin + if (this.lifo.size() == this.depth && this.depth != 0) begin + this.warning($sformatf("LIFO is full!")); return 1'b0; end else begin - this.adi_fifo.push_front(data); + this.lifo.push_front(data); return 1'b1; end endfunction: push function data_type pop(); - if (this.adi_fifo.size() == 0) begin - return null; - end else begin - return this.adi_fifo.pop_front(); + if (this.lifo.size() == 0) begin + this.warning($sformatf("LIFO is empty!")); end + return this.lifo.pop_front(); endfunction: pop function int room(); - return depth-this.adi_fifo.size(); + return depth-this.lifo.size(); endfunction: room function int size(); - return this.adi_fifo.size(); - endfunction: room + return this.lifo.size(); + endfunction: size - function void clear(); - this.adi_fifo.delete(); - endfunction: clear + function void delete(); + this.lifo.delete(); + endfunction: delete function bit insert( input int index, input data_type data); - if (this.adi_fifo.size() == this.depth && this.depth != 0) begin + if (this.lifo.size() == this.depth && this.depth != 0) begin + this.warning($sformatf("LIFO is full!")); return 1'b0; end else begin - this.adi_fifo.insert(index, data); + this.lifo.insert(index, data); return 1'b1; end - endfunction: clear + endfunction: insert endclass: adi_lifo diff --git a/library/utilities/filter_pkg.sv b/library/utilities/filter_pkg.sv index 8a7b702d..2886d3c2 100644 --- a/library/utilities/filter_pkg.sv +++ b/library/utilities/filter_pkg.sv @@ -39,6 +39,7 @@ package filter_pkg; import logger_pkg::*; import adi_common_pkg::*; + import adi_datatypes_pkg::*; class adi_filter #(type data_type = int) extends adi_component; @@ -49,10 +50,10 @@ package filter_pkg; super.new(name, parent); endfunction: new - virtual function bit filter(input data_type data [$]); + virtual function bit filter(input adi_fifo #(data_type) data); return 1'b0; endfunction: filter endclass: adi_filter -endpackage +endpackage: filter_pkg diff --git a/library/utilities/packet_processor_pkg.sv b/library/utilities/packet_processor_pkg.sv new file mode 100644 index 00000000..c4a8b68b --- /dev/null +++ b/library/utilities/packet_processor_pkg.sv @@ -0,0 +1,59 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +package packet_processor_pkg; + + import logger_pkg::*; + import adi_common_pkg::*; + import adi_datatypes_pkg::*; + + class adi_packet_processor #(type data_type = int) extends adi_component; + + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + endfunction: new + + virtual function adi_fifo #(data_type) process_data(input adi_fifo #(data_type) data); + return data; + endfunction: process_data + + endclass: adi_packet_processor + +endpackage: packet_processor_pkg diff --git a/library/utilities/pub_sub_pkg.sv b/library/utilities/pub_sub_pkg.sv index ecc1872f..944e4b2c 100644 --- a/library/utilities/pub_sub_pkg.sv +++ b/library/utilities/pub_sub_pkg.sv @@ -39,7 +39,9 @@ package pub_sub_pkg; import logger_pkg::*; import adi_common_pkg::*; + import adi_datatypes_pkg::*; import filter_pkg::*; + import packet_processor_pkg::*; class adi_subscriber #(type data_type = int) extends adi_component; @@ -56,7 +58,7 @@ package pub_sub_pkg; this.id = this.last_id; endfunction: new - virtual function void update(input data_type data [$]); + virtual function void update(input adi_fifo #(data_type) data); this.fatal($sformatf("This function is not implemented!")); endfunction: update @@ -68,6 +70,7 @@ package pub_sub_pkg; protected adi_subscriber #(data_type) subscriber_list[bit[15:0]]; protected adi_filter #(data_type) filter; + protected adi_packet_processor #(data_type) packet_processor; function new( input string name, @@ -84,6 +87,14 @@ package pub_sub_pkg; this.filter = null; endfunction: remove_filter + function void setup_processor(input adi_packet_processor #(data_type) packet_processor); + this.packet_processor = packet_processor; + endfunction: setup_processor + + function void remove_processor(); + this.packet_processor = null; + endfunction: remove_processor + function void subscribe(input adi_subscriber #(data_type) subscriber); if (this.subscriber_list.exists(subscriber.id)) begin this.error($sformatf("Subscriber already on the list!")); @@ -100,17 +111,31 @@ package pub_sub_pkg; end endfunction: unsubscribe - function void notify(input data_type data [$]); + function void notify(input adi_fifo #(data_type) data); + adi_fifo #(data_type) processed_data; + if (this.filter != null) begin if (!this.filter.filter(data)) begin + this.info($sformatf("Data filtered"), ADI_VERBOSITY_HIGH); return; end end + + // data processing + if (this.packet_processor != null) begin + processed_data = this.packet_processor.process_data(data); + this.info($sformatf("Data processed"), ADI_VERBOSITY_HIGH); + end else begin + processed_data = data; + end + + // data publishing foreach (this.subscriber_list[i]) begin - this.subscriber_list[i].update(data); + this.subscriber_list[i].update(processed_data); end + this.info($sformatf("Data published"), ADI_VERBOSITY_HIGH); endfunction: notify endclass: adi_publisher -endpackage +endpackage: pub_sub_pkg diff --git a/library/vip/amd/axi/adi_axi_monitor.sv b/library/vip/amd/axi/adi_axi_monitor.sv index afcfb044..9398b136 100644 --- a/library/vip/amd/axi/adi_axi_monitor.sv +++ b/library/vip/amd/axi/adi_axi_monitor.sv @@ -40,6 +40,7 @@ package adi_axi_monitor_pkg; import axi_vip_pkg::*; import logger_pkg::*; import adi_vip_pkg::*; + import adi_datatypes_pkg::*; import pub_sub_pkg::*; @@ -121,7 +122,8 @@ package adi_axi_monitor_pkg; xil_axi_strb_beat strb_beat; int num_bytes; logic [7:0] axi_byte; - logic [7:0] data_queue [$]; + adi_fifo #(logic [7:0]) data_queue; + data_queue = new("Data queue", 0, this); forever begin this.monitor.item_collected_port.get(transaction); @@ -133,9 +135,9 @@ package adi_axi_monitor_pkg; axi_byte = data_beat[j*8+:8]; // put each beat into byte queues if (bit'(transaction.get_cmd_type()) == 1'b0) begin // READ - data_queue.push_back(axi_byte); + void'(data_queue.push(axi_byte)); end else if (strb_beat[j] || !this.monitor.vif_proxy.C_AXI_HAS_WSTRB) begin // WRITE - data_queue.push_back(axi_byte); + void'(data_queue.push(axi_byte)); end end this.info($sformatf("Caught an AXI4 transaction: %d", data_queue.size()), ADI_VERBOSITY_MEDIUM); diff --git a/library/vip/amd/axis/adi_axis_monitor.sv b/library/vip/amd/axis/adi_axis_monitor.sv index becef6a9..be5a65e7 100644 --- a/library/vip/amd/axis/adi_axis_monitor.sv +++ b/library/vip/amd/axis/adi_axis_monitor.sv @@ -40,6 +40,7 @@ package adi_axis_monitor_pkg; import axi4stream_vip_pkg::*; import logger_pkg::*; import adi_vip_pkg::*; + import adi_datatypes_pkg::*; import pub_sub_pkg::*; @@ -119,18 +120,18 @@ package adi_axis_monitor_pkg; xil_axi4stream_strb_beat keep_beat; int num_bytes; logic [7:0] axis_byte; - logic [7:0] data_queue [$]; + adi_fifo #(logic [7:0]) data_queue; + data_queue = new("Data queue", 0, this); forever begin this.monitor.item_collected_port.get(transaction); - // all bytes from a beat are valid num_bytes = transaction.get_data_width()/8; data_beat = transaction.get_data_beat(); keep_beat = transaction.get_keep_beat(); for (int j=0; j_.tcl +CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) +#$(warning $(CFG_FILES)) + +# List of tests and configuration combinations that has to be run +# Format is: : +TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP)) +#TESTS += cfg1_mm2mm_default:directed_test +#TESTS += cfg1:test_program +#TESTS += cfg2_fsync:test_program +#TESTS += cfg2_fsync:test_frame_delay + +include $(ADI_TB_DIR)/scripts/project-sim.mk + +# usage : +# +# run specific test on a specific configuration in gui mode +# make CFG=cfg2_fsync TST=test_frame_delay MODE=gui +# +# run all test from a configuration +# make cfg1_mm2mm_default + +#################################################################################### +#################################################################################### diff --git a/testbenches/ip/packet_processor/README.md b/testbenches/ip/packet_processor/README.md new file mode 100644 index 00000000..f1495cb4 --- /dev/null +++ b/testbenches/ip/packet_processor/README.md @@ -0,0 +1,27 @@ +Usage : + +Run all tests in batch mode: + + make + + +Run all tests in GUI mode: + + make MODE=gui + + +Run specific test on a specific configuration in gui mode: + + make CFG= TST= MODE=gui + + +Run all test from a configuration: + + make + + +Where: + + * is a file from the cfgs directory without the tcl extension of format cfg\* + * is a file from the tests directory without the tcl extension + diff --git a/testbenches/ip/packet_processor/cfgs/cfg1.tcl b/testbenches/ip/packet_processor/cfgs/cfg1.tcl new file mode 100644 index 00000000..d040d253 --- /dev/null +++ b/testbenches/ip/packet_processor/cfgs/cfg1.tcl @@ -0,0 +1 @@ +global ad_project_params diff --git a/testbenches/ip/packet_processor/system_bd.tcl b/testbenches/ip/packet_processor/system_bd.tcl new file mode 100644 index 00000000..ec2ae2c4 --- /dev/null +++ b/testbenches/ip/packet_processor/system_bd.tcl @@ -0,0 +1,62 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. +# +# In this HDL repository, there are many different and unique modules, consisting +# of various HDL (Verilog or VHDL) components. The individual modules are +# developed independently, and may be accompanied by separate and unique license +# terms. +# +# The user should read each of these license terms, and understand the +# freedoms and responsibilities that he or she has by using this source/core. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. +# +# Redistribution and use of source or resulting binaries, with or without modification +# of this file, are permitted under one of the following two license terms: +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory +# of this repository (LICENSE_GPL2), and also online at: +# +# +# OR +# +# 2. An ADI specific BSD license, which can be found in the top level directory +# of this repository (LICENSE_ADIBSD), and also on-line at: +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +# This will allow to generate bit files and not release the source code, +# as long as it attaches to an ADI device. +# +# *************************************************************************** +# *************************************************************************** + +global ad_project_params + +ad_ip_instance axi4stream_vip adc_src_axis [list \ + INTERFACE_MODE {MASTER} \ + TDATA_NUM_BYTES 2 \ + HAS_TREADY {1} \ + HAS_TKEEP {1} \ + HAS_TLAST {1} \ +] +adi_sim_add_define "ADC_SRC_AXIS=adc_src_axis" + +ad_connect sys_dma_clk adc_src_axis/aclk +ad_connect sys_dma_resetn adc_src_axis/aresetn + +ad_ip_instance axi4stream_vip dac_dst_axis [list \ + INTERFACE_MODE {SLAVE} \ + TDATA_NUM_BYTES 2 \ + HAS_TREADY {1} \ + HAS_TKEEP {1} \ + HAS_TLAST {1} \ +] +adi_sim_add_define "DAC_DST_AXIS=dac_dst_axis" + +ad_connect sys_dma_clk dac_dst_axis/aclk +ad_connect sys_dma_resetn dac_dst_axis/aresetn + +ad_connect adc_src_axis/m_axis dac_dst_axis/s_axis diff --git a/testbenches/ip/packet_processor/system_project.tcl b/testbenches/ip/packet_processor/system_project.tcl new file mode 100644 index 00000000..89695af3 --- /dev/null +++ b/testbenches/ip/packet_processor/system_project.tcl @@ -0,0 +1,30 @@ +source ../../../scripts/adi_sim.tcl + +if {$argc < 1} { + puts "Expecting at least one argument that specifies the test configuration" + exit 1 +} else { + set cfg_file [lindex $argv 0] +} + +# Read config file +source "cfgs/${cfg_file}" + +# Set the project name +set project_name [file rootname $cfg_file] + +# Create the project +adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" + +source $ad_tb_dir/library/includes/sp_include_axis.tcl +source $ad_tb_dir/library/includes/sp_include_scoreboard.tcl + +# Add test files to the project +adi_sim_project_files [list \ + "tests/test_program.sv" \ +] + +#set a default test program +adi_sim_add_define "TEST_PROGRAM=test_program" + +adi_sim_generate $project_name diff --git a/testbenches/ip/packet_processor/system_tb.sv b/testbenches/ip/packet_processor/system_tb.sv new file mode 100644 index 00000000..2723b531 --- /dev/null +++ b/testbenches/ip/packet_processor/system_tb.sv @@ -0,0 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014 - 2022 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +`include "utils.svh" + +module system_tb(); + + `TEST_PROGRAM test(); + test_harness `TH (); + +endmodule diff --git a/testbenches/ip/packet_processor/tests/test_program.sv b/testbenches/ip/packet_processor/tests/test_program.sv new file mode 100644 index 00000000..e04352e8 --- /dev/null +++ b/testbenches/ip/packet_processor/tests/test_program.sv @@ -0,0 +1,158 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" +`include "axi_definitions.svh" +`include "axis_definitions.svh" + +import logger_pkg::*; +import test_harness_env_pkg::*; +import adi_datatypes_pkg::*; +import adi_axi_agent_pkg::*; +import adi_axis_agent_pkg::*; +import axi4stream_vip_pkg::*; +import m_axis_sequencer_pkg::*; +import scoreboard_pkg::*; +import packet_processor_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +import `PKGIFY(test_harness, adc_src_axis)::*; +import `PKGIFY(test_harness, dac_dst_axis)::*; + +program test_program(); + + // declare the class instances + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + + adi_axis_master_agent #(`AXIS_VIP_PARAMS(test_harness, adc_src_axis)) adc_src_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAMS(test_harness, dac_dst_axis)) dac_dst_axis_agent; + + scoreboard #(logic [7:0]) scoreboard; + + class packet_processor_class extends adi_packet_processor#(.data_type(logic [7:0])); + + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + endfunction: new + + virtual function adi_fifo #(data_type) process_data(input adi_fifo #(data_type) data); + adi_fifo #(data_type) processed_data; + int fifo_depth = data.size(); + + processed_data = new("Packet processor", 0, this); + + for (int i=0; i + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + M_AXIS + M_AXIS + + + S_AXIS + S_AXIS + +