diff --git a/testbenches/project/adrv9026/Makefile b/testbenches/project/adrv9026/Makefile new file mode 100644 index 00000000..9860ad0d --- /dev/null +++ b/testbenches/project/adrv9026/Makefile @@ -0,0 +1,61 @@ +#################################################################################### +#################################################################################### +## Copyright (C) 2025 Analog Devices, Inc. +#################################################################################### +#################################################################################### + +# Makeincludes +include ../../../scripts/make_tb_path.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_common.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_data_offload.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_dmac.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_jesd.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_xcvr.mk + +# Remaining test-bench dependencies except test programs +SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_dac_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_common_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_adc_pkg.sv + +LIB_DEPS += axi_dmac +LIB_DEPS += data_offload +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +# default test program +TP := test_program + +# config files should have the following format +# cfg__.tcl +CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) +#$(warning $(CFG_FILES)) + +# List of tests and configuration combinations that has to be run +# Format is: : +TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP)) +#TESTS += cfg1:test_program + +include $(ADI_TB_DIR)/scripts/project-sim.mk + +# usage : +# +# run specific test on a specific configuration in gui mode +# make CFG=cfg2_fsync TST=test_frame_delay MODE=gui +# +# run all test from a configuration +# make cfg1_mm2mm_default + +#################################################################################### +#################################################################################### diff --git a/testbenches/project/adrv9026/README.md b/testbenches/project/adrv9026/README.md new file mode 100644 index 00000000..f1495cb4 --- /dev/null +++ b/testbenches/project/adrv9026/README.md @@ -0,0 +1,27 @@ +Usage : + +Run all tests in batch mode: + + make + + +Run all tests in GUI mode: + + make MODE=gui + + +Run specific test on a specific configuration in gui mode: + + make CFG= TST= MODE=gui + + +Run all test from a configuration: + + make + + +Where: + + * is a file from the cfgs directory without the tcl extension of format cfg\* + * is a file from the tests directory without the tcl extension + diff --git a/testbenches/project/adrv9026/cfgs/cfg1.tcl b/testbenches/project/adrv9026/cfgs/cfg1.tcl new file mode 100644 index 00000000..12e1e13e --- /dev/null +++ b/testbenches/project/adrv9026/cfgs/cfg1.tcl @@ -0,0 +1,27 @@ +global ad_project_params + +set ad_project_params(JESD_MODE) 8B10B + +set ad_project_params(REF_CLK_RATE) 500 +set ad_project_params(RX_LANE_RATE) 10 +set ad_project_params(TX_LANE_RATE) 10 + +set ad_project_params(RX_NUM_LINKS) 1 +set ad_project_params(TX_NUM_LINKS) 1 + +set ad_project_params(DAC_OFFLOAD_TYPE) 0 +set ad_project_params(DAC_OFFLOAD_SIZE) [expr 2*1024*1024] + +set ad_project_params(RX_JESD_M) 8 +set ad_project_params(RX_JESD_L) 4 +set ad_project_params(RX_JESD_S) 1 +set ad_project_params(RX_JESD_NP) 16 +set ad_project_params(RX_JESD_F) 4 +set ad_project_params(RX_JESD_K) 32 + +set ad_project_params(TX_JESD_M) 8 +set ad_project_params(TX_JESD_L) 4 +set ad_project_params(TX_JESD_S) 1 +set ad_project_params(TX_JESD_NP) 16 +set ad_project_params(TX_JESD_F) 4 +set ad_project_params(TX_JESD_K) 32 diff --git a/testbenches/project/adrv9026/system_bd.tcl b/testbenches/project/adrv9026/system_bd.tcl new file mode 100644 index 00000000..6a4a8b16 --- /dev/null +++ b/testbenches/project/adrv9026/system_bd.tcl @@ -0,0 +1,108 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +# +# In this HDL repository, there are many different and unique modules, consisting +# of various HDL (Verilog or VHDL) components. The individual modules are +# developed independently, and may be accompanied by separate and unique license +# terms. +# +# The user should read each of these license terms, and understand the +# freedoms and responsibilities that he or she has by using this source/core. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. +# +# Redistribution and use of source or resulting binaries, with or without modification +# of this file, are permitted under one of the following two license terms: +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory +# of this repository (LICENSE_GPL2), and also online at: +# +# +# OR +# +# 2. An ADI specific BSD license, which can be found in the top level directory +# of this repository (LICENSE_ADIBSD), and also on-line at: +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +# This will allow to generate bit files and not release the source code, +# as long as it attaches to an ADI device. +# +# *************************************************************************** +# *************************************************************************** + +global ad_project_params + +set dac_offload_type $ad_project_params(DAC_OFFLOAD_TYPE) +set dac_offload_size $ad_project_params(DAC_OFFLOAD_SIZE) + +# Ref clk +ad_ip_instance clk_vip ref_clk_vip [ list \ + INTERFACE_MODE {MASTER} \ + FREQ_HZ 250000000 \ +] +adi_sim_add_define "REF_CLK=ref_clk_vip" +create_bd_port -dir O ref_clk_out +ad_connect ref_clk_out ref_clk_vip/clk_out + +# Device clk +ad_ip_instance clk_vip device_clk_vip [ list \ + INTERFACE_MODE {MASTER} \ + FREQ_HZ 250000000 \ +] +adi_sim_add_define "DEVICE_CLK=device_clk_vip" +create_bd_port -dir O device_clk_out +ad_connect device_clk_out device_clk_vip/clk_out + +# SYSREF clk +ad_ip_instance clk_vip sysref_clk_vip [ list \ + INTERFACE_MODE {MASTER} \ + FREQ_HZ 5000000 \ +] +adi_sim_add_define "SYSREF_CLK=sysref_clk_vip" +create_bd_port -dir O sysref_clk_out +ad_connect sysref_clk_out sysref_clk_vip/clk_out + +# +# Block design under test +# + +source $ad_hdl_dir/projects/adrv9026/common/adrv9026_bd.tcl + +set RX_DMA 0x7C400000 +set_property offset $RX_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_adrv9026_rx_dma}] +adi_sim_add_define "RX_DMA_BA=[format "%d" ${RX_DMA}]" + +set RX_XCVR 0x44A60000 +set_property offset $RX_XCVR [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_adrv9026_rx_xcvr}] +adi_sim_add_define "RX_XCVR_BA=[format "%d" ${RX_XCVR}]" + +set TX_DMA 0x7C420000 +set_property offset $TX_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_adrv9026_tx_dma}] +adi_sim_add_define "TX_DMA_BA=[format "%d" ${TX_DMA}]" + +set TX_XCVR 0x44A80000 +set_property offset $TX_XCVR [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_adrv9026_tx_xcvr}] +adi_sim_add_define "TX_XCVR_BA=[format "%d" ${TX_XCVR}]" + +set AXI_JESD_RX 0x44AA0000 +set_property offset $AXI_JESD_RX [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_adrv9026_rx_jesd}] +adi_sim_add_define "AXI_JESD_RX_BA=[format "%d" ${AXI_JESD_RX}]" + +set ADC_TPL 0x44A00000 +set_property offset $ADC_TPL [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_rx_adrv9026_tpl_core}] +adi_sim_add_define "ADC_TPL_BA=[format "%d" ${ADC_TPL}]" + +set DAC_TPL 0x44A04000 +set_property offset $DAC_TPL [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_tx_adrv9026_tpl_core}] +adi_sim_add_define "DAC_TPL_BA=[format "%d" ${DAC_TPL}]" + +set AXI_JESD_TX 0x44A90000 +set_property offset $AXI_JESD_TX [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_adrv9026_tx_jesd}] +adi_sim_add_define "AXI_JESD_TX_BA=[format "%d" ${AXI_JESD_TX}]" + +set TX_OFFLOAD 0x7C430000 +set_property offset $TX_OFFLOAD [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_adrv9026_data_offload}] +adi_sim_add_define "TX_OFFLOAD_BA=[format "%d" ${TX_OFFLOAD}]" diff --git a/testbenches/project/adrv9026/system_project.tcl b/testbenches/project/adrv9026/system_project.tcl new file mode 100644 index 00000000..2a594ac2 --- /dev/null +++ b/testbenches/project/adrv9026/system_project.tcl @@ -0,0 +1,35 @@ +source ../../../scripts/adi_sim.tcl + +if {$argc < 1} { + puts "Expecting at least one argument that specifies the test configuration" + exit 1 +} else { + set cfg_file [lindex $argv 0] +} + +# Read common config file +source "cfgs/${cfg_file}" + +# Set the project name +set project_name [file rootname $cfg_file] + +# Create the project +adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" + +source $ad_tb_dir/library/includes/sp_include_data_offload.tcl +source $ad_tb_dir/library/includes/sp_include_dmac.tcl +source $ad_tb_dir/library/includes/sp_include_jesd.tcl +source $ad_tb_dir/library/includes/sp_include_xcvr.tcl + +# Add test files to the project +adi_sim_project_files [list \ + "$ad_tb_dir/library/regmaps/adi_regmap_dac_pkg.sv" \ + "$ad_tb_dir/library/regmaps/adi_regmap_common_pkg.sv" \ + "$ad_tb_dir/library/regmaps/adi_regmap_adc_pkg.sv" \ + "tests/test_program.sv" \ +] + +#set a default test program +adi_sim_add_define "TEST_PROGRAM=test_program" + +adi_sim_generate $project_name diff --git a/testbenches/project/adrv9026/system_tb.sv b/testbenches/project/adrv9026/system_tb.sv new file mode 100644 index 00000000..c47237c8 --- /dev/null +++ b/testbenches/project/adrv9026/system_tb.sv @@ -0,0 +1,74 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +`include "utils.svh" + +module system_tb(); + + `TEST_PROGRAM test(); + + test_harness `TH ( + .ref_clk_out (ref_clk), + .device_clk_out (device_clk), + .sysref_clk_out (sysref), + + .core_clk (device_clk), //-dir I + .rx_data_0_n (~data_0_n), //-dir I + .rx_data_0_p (~data_0_p), //-dir I + .rx_data_1_n (data_1_n), //-dir I + .rx_data_1_p (data_1_p), //-dir I + .rx_data_2_n (~data_2_n), //-dir I + .rx_data_2_p (~data_2_p), //-dir I + .rx_data_3_n (data_3_n), //-dir I + .rx_data_3_p (data_3_p), //-dir I + .tx_data_0_n (data_2_n), //-dir O + .tx_data_0_p (data_2_p), //-dir O + .tx_data_1_n (data_3_n), //-dir O + .tx_data_1_p (data_3_p), //-dir O + .tx_data_2_n (data_1_n), //-dir O + .tx_data_2_p (data_1_p), //-dir O + .tx_data_3_n (data_0_n), //-dir O + .tx_data_3_p (data_0_p), //-dir O + .rx_sync_0 (rx_sync_0), //-dir O + .tx_sync_0 (rx_sync_0), //-dir I + .rx_sysref_0 (sysref), //-dir I + .tx_sysref_0 (sysref), //-dir I + .rx_ref_clk_0 (ref_clk), //-dir I + .tx_ref_clk_0 (ref_clk) //-dir I + ); + +endmodule diff --git a/testbenches/project/adrv9026/tests/test_program.sv b/testbenches/project/adrv9026/tests/test_program.sv new file mode 100644 index 00000000..d80b86a7 --- /dev/null +++ b/testbenches/project/adrv9026/tests/test_program.sv @@ -0,0 +1,320 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +import test_harness_env_pkg::*; +import adi_regmap_pkg::*; +import axi_vip_pkg::*; +import axi4stream_vip_pkg::*; +import logger_pkg::*; +import adi_regmap_data_offload_pkg::*; +import adi_regmap_dmac_pkg::*; +import adi_regmap_jesd_tx_pkg::*; +import adi_regmap_jesd_rx_pkg::*; +import adi_regmap_common_pkg::*; +import adi_regmap_dac_pkg::*; +import adi_regmap_adc_pkg::*; +import adi_jesd204_pkg::*; +import adi_xcvr_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +program test_program; + + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + bit [31:0] val; + + jesd_link link; + rx_link_layer rx_ll; + tx_link_layer tx_ll; + xcvr rx_xcvr; + xcvr tx_xcvr; + + bit [31:0] lane_rate_khz = `RX_LANE_RATE*1000000; + longint unsigned lane_rate = lane_rate_khz*1000; + + initial begin + + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + setLoggerVerbosity(ADI_VERBOSITY_NONE); + + base_env.start(); + base_env.sys_reset(); + + link = new; + link.set_L(`RX_JESD_L); + link.set_M(`RX_JESD_M); + link.set_F(`RX_JESD_F); + link.set_S(`RX_JESD_S); + link.set_K(`RX_JESD_K); + link.set_N(`RX_JESD_NP); + link.set_NP(`RX_JESD_NP); + link.set_encoding(enc8b10b); + link.set_lane_rate(lane_rate); + + rx_ll = new("RX_LINK_LAYER", base_env.mng.sequencer, `AXI_JESD_RX_BA, link); + rx_ll.probe(); + + tx_ll = new("TX_LINK_LAYER", base_env.mng.sequencer, `AXI_JESD_TX_BA, link); + tx_ll.probe(); + + rx_xcvr = new("RX_XCVR", base_env.mng.sequencer, `RX_XCVR_BA); + rx_xcvr.probe(); + + tx_xcvr = new("TX_XCVR", base_env.mng.sequencer, `TX_XCVR_BA); + tx_xcvr.probe(); + + `TH.`REF_CLK.inst.IF.set_clk_frq(.user_frequency(`REF_CLK_RATE*1000000)); + `TH.`DEVICE_CLK.inst.IF.set_clk_frq(.user_frequency(rx_ll.calc_device_clk())); + `TH.`SYSREF_CLK.inst.IF.set_clk_frq(.user_frequency(rx_ll.calc_sysref_clk())); + `TH.`DMA_CLK.inst.IF.set_clk_frq(.user_frequency(rx_ll.calc_device_clk())); + + `TH.`REF_CLK.inst.IF.start_clock(); + `TH.`DEVICE_CLK.inst.IF.start_clock(); + `TH.`SYSREF_CLK.inst.IF.start_clock(); + + rx_xcvr.setup_clocks(lane_rate, + `REF_CLK_RATE*1000000); + + tx_xcvr.setup_clocks(lane_rate, + `REF_CLK_RATE*1000000); + + // ======================= + // JESD LINK TEST - DDS + // ======================= + jesd_link_test(1,0); + + // ======================= + // JESD LINK TEST - DMA + // ======================= + jesd_link_test(0,0); + + // ======================= + // JESD LINK TEST - DMA - TX BYPASS + // ======================= + jesd_link_test(0,1); + + base_env.stop(); + + `TH.`REF_CLK.inst.IF.stop_clock(); + `TH.`DEVICE_CLK.inst.IF.stop_clock(); + `TH.`SYSREF_CLK.inst.IF.stop_clock(); + + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish(); + + end + + // ----------------- + // + // ----------------- + task jesd_link_test(bit use_dds , + bit tx_bypass); + + `INFO(("======================="), ADI_VERBOSITY_LOW); + `INFO((" JESD TEST "+(use_dds ? "DDS" : "DMA")), ADI_VERBOSITY_LOW); + `INFO(("======================="), ADI_VERBOSITY_LOW); + + // ----------------------- + // TX PHY INIT + // ----------------------- + tx_xcvr.up(); + + // ----------------------- + // Configure TPL + // ----------------------- + for (int i = 0; i < `TX_JESD_M; i++) begin + if (use_dds) begin + // Select DDS as source + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); + // Configure tone amplitude and frequency + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h0fff)); + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); + end else begin + // Set DMA as source for DAC TPL + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + 'h40 * i + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); + end + end + + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + `SET_DAC_COMMON_REG_RSTN_RSTN(1)); + + if (use_dds) begin + // Sync DDS cores + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), + `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); + end + + // + // Configure Offload + // + // Offload bypass + base_env.mng.sequencer.RegWrite32(`TX_OFFLOAD_BA + GetAddrs(DO_CONTROL), + `SET_DO_CONTROL_OFFLOAD_BYPASS(tx_bypass)); + + if (~use_dds) begin + + // Init test data + for (int i=0;i<2048*2;i=i+2) begin + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(xil_axi_uint'(`DDR_BA+i*2), ((i+1) << 16) | i, 15); + end + // Configure TX DMA + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + `SET_DMAC_FLAGS_CYCLIC(tx_bypass) | + `SET_DMAC_FLAGS_TLAST(1)); + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + `SET_DMAC_X_LENGTH_X_LENGTH(32'h00001FFF)); + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA+32'h00000000)); + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + // Configure RX DMA + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), + `SET_DMAC_FLAGS_TLAST(1)); + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + `SET_DMAC_X_LENGTH_X_LENGTH(32'h000007FF)); + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00002000)); + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + // Wait until data propagates through the dma+offload + #5us; + end + + tx_ll.link_up(); + + // ----------------------- + // RX PHY INIT + // ----------------------- + rx_xcvr.up(); + + // ----------------------- + // Configure ADC TPL + // ----------------------- + for (int i = 0; i < `RX_JESD_M; i++) begin + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + 'h40 * i + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); + end + + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + `SET_ADC_COMMON_REG_RSTN_RSTN(1)); + + rx_ll.link_up(); + + rx_ll.wait_link_up(); + tx_ll.wait_link_up(); + + // Move data around for a while + #5us; + + if (~use_dds) begin + check_captured_data( + .address (`DDR_BA+'h00002000), + .length (1024), + .step (1), + .max_sample(4096) + ); + end + + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + `SET_DMAC_CONTROL_ENABLE(0)); + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + `SET_DMAC_CONTROL_ENABLE(0)); + + rx_ll.link_down(); + tx_ll.link_down(); + + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + `SET_ADC_COMMON_REG_RSTN_RSTN(0)); + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + `SET_DAC_COMMON_REG_RSTN_RSTN(0)); + + rx_xcvr.down(); + tx_xcvr.down(); + + `INFO(("======================="), ADI_VERBOSITY_LOW); + `INFO((" JESD LINK TEST DONE "), ADI_VERBOSITY_LOW); + `INFO(("======================="), ADI_VERBOSITY_LOW); + + endtask : jesd_link_test + + // Check captured data against incremental pattern based on first sample + // Pattern should be contiguous + task check_captured_data(bit [31:0] address, + int length = 1024, + int step = 1, + int max_sample = 2048 + ); + + bit [31:0] current_address; + bit [31:0] captured_word; + bit [31:0] reference_word; + bit [15:0] first; + + for (int i=0;i + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TX DMA + label + + + true + STYLE_ENUM_TRANSACTION + 0=blank 1=#D399FF 2=pink + 0=blank;1=Read;2=Write;3=Read/Write + true + turquoise + /system_tb/test_harness/axi_adrv9026_tx_dma/m_src_axi.readWriteSummary + UNSIGNEDDECRADIX + 36 + m_src_axi + m_src_axi + + + + TX DO + label + + + true + STYLE_ENUM_TRANSACTION + fff,fff=blank + true + #00E600 + /system_tb/test_harness/adrv9026_data_offload/s_axis.streamWaveData + 2 + /system_tb/test_harness/adrv9026_data_offload/s_axis.linkStarve + #99E600 + /system_tb/test_harness/adrv9026_data_offload/s_axis.linkStall + #E64C00 + /system_tb/test_harness/adrv9026_data_offload/s_axis.streamTooltipData + s_axis + s_axis + + + + true + STYLE_ENUM_TRANSACTION + fff,fff=blank + true + #00E600 + /system_tb/test_harness/adrv9026_data_offload/m_axis.streamWaveData + 2 + /system_tb/test_harness/adrv9026_data_offload/m_axis.linkStarve + #99E600 + /system_tb/test_harness/adrv9026_data_offload/m_axis.linkStall + #E64C00 + /system_tb/test_harness/adrv9026_data_offload/m_axis.streamTooltipData + m_axis + m_axis + + + + TX TPL + label + + + dac_enable_0[0:0] + dac_enable_0[0:0] + + + dac_enable_1[0:0] + dac_enable_1[0:0] + + + dac_valid_0[0:0] + dac_valid_0[0:0] + + + dac_valid_1[0:0] + dac_valid_1[0:0] + + + dac_data_0[127:0] + dac_data_0[127:0] + + + dac_data_1[127:0] + dac_data_1[127:0] + + + dac_dunf + dac_dunf + + + RX TPL + label + + + adc_enable_0[0:0] + adc_enable_0[0:0] + + + adc_valid_0[0:0] + adc_valid_0[0:0] + + + adc_data_0[255:0] + adc_data_0[255:0] + + + adc_dovf + adc_dovf + + + RX DMA + label + + + true + STYLE_ENUM_TRANSACTION + fff,fff=blank + true + #00E600 + /system_tb/test_harness/axi_adrv9026_rx_dma/s_axis.streamWaveData + 2 + /system_tb/test_harness/axi_adrv9026_rx_dma/s_axis.linkStarve + #99E600 + /system_tb/test_harness/axi_adrv9026_rx_dma/s_axis.linkStall + #E64C00 + /system_tb/test_harness/axi_adrv9026_rx_dma/s_axis.streamTooltipData + s_axis + s_axis + + + + true + STYLE_ENUM_TRANSACTION + 0=blank 1=#D399FF 2=pink + 0=blank;1=Read;2=Write;3=Read/Write + true + turquoise + /system_tb/test_harness/axi_adrv9026_rx_dma/m_dest_axi.readWriteSummary + UNSIGNEDDECRADIX + 36 + m_dest_axi + m_dest_axi + + + + TX DO SETTINGS + label + + + up_oneshot + up_oneshot + + + up_bypass + up_bypass + #00FF00 + true + +