From da66283197a576ea3519ceb16588bf8b28a8b84c Mon Sep 17 00:00:00 2001 From: Ionut Podgoreanu Date: Thu, 20 Nov 2025 16:23:55 +0200 Subject: [PATCH] dac_fmc_ebz: Add testbench Signed-off-by: Ionut Podgoreanu --- testbenches/project/dac_fmc_ebz/Makefile | 57 ++++ testbenches/project/dac_fmc_ebz/README.md | 27 ++ testbenches/project/dac_fmc_ebz/cfgs/cfg1.tcl | 15 + testbenches/project/dac_fmc_ebz/system_bd.tcl | 163 +++++++++++ .../project/dac_fmc_ebz/system_project.tcl | 37 +++ testbenches/project/dac_fmc_ebz/system_tb.sv | 110 +++++++ .../project/dac_fmc_ebz/tests/test_program.sv | 272 ++++++++++++++++++ .../project/dac_fmc_ebz/waves/cfg1.wcfg | 160 +++++++++++ 8 files changed, 841 insertions(+) create mode 100755 testbenches/project/dac_fmc_ebz/Makefile create mode 100755 testbenches/project/dac_fmc_ebz/README.md create mode 100644 testbenches/project/dac_fmc_ebz/cfgs/cfg1.tcl create mode 100755 testbenches/project/dac_fmc_ebz/system_bd.tcl create mode 100755 testbenches/project/dac_fmc_ebz/system_project.tcl create mode 100755 testbenches/project/dac_fmc_ebz/system_tb.sv create mode 100755 testbenches/project/dac_fmc_ebz/tests/test_program.sv create mode 100755 testbenches/project/dac_fmc_ebz/waves/cfg1.wcfg diff --git a/testbenches/project/dac_fmc_ebz/Makefile b/testbenches/project/dac_fmc_ebz/Makefile new file mode 100755 index 000000000..55535b21e --- /dev/null +++ b/testbenches/project/dac_fmc_ebz/Makefile @@ -0,0 +1,57 @@ +#################################################################################### +#################################################################################### +## Copyright (C) 2018-2025 Analog Devices, Inc. +#################################################################################### +#################################################################################### + +# Makeincludes +include ../../../scripts/make_tb_path.mk +include $(ADI_TB_DIR)/library/includes/Makeinclude_dmac.mk +include $(ADI_TB_DIR)/library/includes/Makeinclude_jesd.mk +include $(ADI_TB_DIR)/library/includes/Makeinclude_xcvr.mk + +# Remaining test-bench dependencies except test programs +SV_DEPS += $(ADI_TB_DIR)/library/regmaps/adi_regmap_dac_pkg.sv +SV_DEPS += $(ADI_TB_DIR)/library/regmaps/adi_regmap_common_pkg.sv +SV_DEPS += $(ADI_TB_DIR)/library/regmaps/adi_regmap_adc_pkg.sv + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += data_offload +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + + +# list of test programs +TP := $(notdir $(basename $(wildcard tests/*.sv))) + +# config files should have the following format +# cfg__.tcl +CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) + +# List of tests and configuration combinations that has to be run +# Format is: : +TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(addprefix $(cfg):, $(TP))) + +include $(ADI_TB_DIR)/scripts/project-sim.mk + +# usage : +# +# run specific test on a specific configuration in gui mode +# make CFG= TST= MODE=gui +# +# run all test from a configuration +# make + +#################################################################################### +#################################################################################### diff --git a/testbenches/project/dac_fmc_ebz/README.md b/testbenches/project/dac_fmc_ebz/README.md new file mode 100755 index 000000000..f1495cb4e --- /dev/null +++ b/testbenches/project/dac_fmc_ebz/README.md @@ -0,0 +1,27 @@ +Usage : + +Run all tests in batch mode: + + make + + +Run all tests in GUI mode: + + make MODE=gui + + +Run specific test on a specific configuration in gui mode: + + make CFG= TST= MODE=gui + + +Run all test from a configuration: + + make + + +Where: + + * is a file from the cfgs directory without the tcl extension of format cfg\* + * is a file from the tests directory without the tcl extension + diff --git a/testbenches/project/dac_fmc_ebz/cfgs/cfg1.tcl b/testbenches/project/dac_fmc_ebz/cfgs/cfg1.tcl new file mode 100644 index 000000000..19a832894 --- /dev/null +++ b/testbenches/project/dac_fmc_ebz/cfgs/cfg1.tcl @@ -0,0 +1,15 @@ +global ad_project_params + +set ad_project_params(REF_CLK_RATE) 500 +set ad_project_params(LANE_RATE) 10 +set ad_project_params(NUM_LINKS) 1 + +set ad_project_params(DAC_OFFLOAD_TYPE) 0 +set ad_project_params(DAC_OFFLOAD_SIZE) [expr 256*1024] + +set ad_project_params(JESD_M) 4 +set ad_project_params(JESD_L) 4 +set ad_project_params(JESD_S) 1 +set ad_project_params(JESD_NP) 16 +set ad_project_params(JESD_F) 2 +set ad_project_params(JESD_K) 32 diff --git a/testbenches/project/dac_fmc_ebz/system_bd.tcl b/testbenches/project/dac_fmc_ebz/system_bd.tcl new file mode 100755 index 000000000..dad605123 --- /dev/null +++ b/testbenches/project/dac_fmc_ebz/system_bd.tcl @@ -0,0 +1,163 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +# +# In this HDL repository, there are many different and unique modules, consisting +# of various HDL (Verilog or VHDL) components. The individual modules are +# developed independently, and may be accompanied by separate and unique license +# terms. +# +# The user should read each of these license terms, and understand the +# freedoms and responsibilities that he or she has by using this source/core. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. +# +# Redistribution and use of source or resulting binaries, with or without modification +# of this file, are permitted under one of the following two license terms: +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory +# of this repository (LICENSE_GPL2), and also online at: +# +# +# OR +# +# 2. An ADI specific BSD license, which can be found in the top level directory +# of this repository (LICENSE_ADIBSD), and also on-line at: +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +# This will allow to generate bit files and not release the source code, +# as long as it attaches to an ADI device. +# +# *************************************************************************** +# *************************************************************************** + +global ad_project_params + +source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl + +set DATAPATH_WIDTH 4 +set TX_MAX_LANES 8 + +set dac_offload_type $ad_project_params(DAC_OFFLOAD_TYPE) +set dac_offload_size $ad_project_params(DAC_OFFLOAD_SIZE) + +set LANE_RATE $ad_project_params(LANE_RATE) + +set TX_NUM_OF_LANES $ad_project_params(JESD_L) +set TX_NUM_OF_CONVERTERS $ad_project_params(JESD_M) +set TX_SAMPLES_PER_FRAME $ad_project_params(JESD_S) +set TX_SAMPLE_WIDTH $ad_project_params(JESD_NP) +set TX_JESD_F $ad_project_params(JESD_F) + +set LL_OUT_BYTES [expr max($TX_JESD_F,$DATAPATH_WIDTH)] + +adi_sim_add_define LL_OUT_BYTES=$LL_OUT_BYTES + +# Ref clk +ad_ip_instance clk_vip ref_clk_vip [ list \ + INTERFACE_MODE {MASTER} \ + FREQ_HZ 250000000 \ +] +adi_sim_add_define "REF_CLK=ref_clk_vip" +create_bd_port -dir O ref_clk_out +ad_connect ref_clk_out ref_clk_vip/clk_out + +# Rx Device clk +ad_ip_instance clk_vip rx_device_clk_vip [ list \ + INTERFACE_MODE {MASTER} \ + FREQ_HZ 250000000 \ +] +adi_sim_add_define "RX_DEVICE_CLK=rx_device_clk_vip" +create_bd_port -dir O rx_device_clk_out +ad_connect rx_device_clk_out rx_device_clk_vip/clk_out + +# SYSREF clk +ad_ip_instance clk_vip sysref_clk_vip [ list \ + INTERFACE_MODE {MASTER} \ + FREQ_HZ 5000000 \ +] +adi_sim_add_define "SYSREF_CLK=sysref_clk_vip" +create_bd_port -dir O sysref_clk_out +ad_connect sysref_clk_out sysref_clk_vip/clk_out + +# +# Block design under test +# + +create_bd_port -dir I -type clk ref_clk_ex +create_bd_port -dir I -type clk rx_device_clk +create_bd_port -dir I -type clk sysref + +set_property CONFIG.FREQ_HZ 250000000 [get_bd_ports rx_device_clk] + +for {set i 0} {$i < $TX_MAX_LANES} {incr i} { +create_bd_port -dir I rx_data1_${i}_n +create_bd_port -dir I rx_data1_${i}_p +} + +source $ad_hdl_dir/projects/dac_fmc_ebz/common/dac_fmc_ebz_bd.tcl + +source $ad_tb_dir/library/drivers/jesd/jesd_exerciser.tcl + +create_jesd_exerciser rx_jesd_exerciser 0 1 $LANE_RATE $TX_NUM_OF_CONVERTERS $TX_NUM_OF_LANES $TX_SAMPLES_PER_FRAME $TX_SAMPLE_WIDTH +create_bd_cell -type container -reference rx_jesd_exerciser i_rx_jesd_exerciser + +# Rx exerciser +for {set i 0} {$i < $TX_NUM_OF_LANES} {incr i} { + ad_connect rx_data1_${i}_n i_rx_jesd_exerciser/rx_data_${i}_n + ad_connect rx_data1_${i}_p i_rx_jesd_exerciser/rx_data_${i}_p +} +ad_connect sysref i_rx_jesd_exerciser/rx_sysref_0 + +ad_connect $sys_cpu_clk i_rx_jesd_exerciser/sys_cpu_clk +ad_connect $sys_cpu_resetn i_rx_jesd_exerciser/sys_cpu_resetn + +ad_connect rx_device_clk i_rx_jesd_exerciser/device_clk +ad_connect rx_device_clk i_rx_jesd_exerciser/link_clk +ad_connect ref_clk_ex i_rx_jesd_exerciser/ref_clk + +set_property -dict [list CONFIG.NUM_MI {8}] [get_bd_cells axi_axi_interconnect] +ad_connect i_rx_jesd_exerciser/S00_AXI_0 axi_axi_interconnect/M07_AXI +ad_connect sys_cpu_clk axi_axi_interconnect/M07_ACLK +ad_connect sys_cpu_resetn axi_axi_interconnect/M07_ARESETN + +create_bd_port -dir O ex_rx_sync +ad_connect ex_rx_sync i_rx_jesd_exerciser/rx_sync_0 + +assign_bd_address + +set DUT_AXI_XCVR_TX 0x44A60000 +set_property offset $DUT_AXI_XCVR_TX [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_dac_jesd204_xcvr}] +adi_sim_add_define "DUT_AXI_XCVR_TX_BA=[format "%d" ${DUT_AXI_XCVR_TX}]" + +set DAC_TPL 0x44A04000 +set_property offset $DAC_TPL [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_dac_jesd204_transport}] +adi_sim_add_define "DAC_TPL_BA=[format "%d" ${DAC_TPL}]" + +set AXI_JESD_TX 0x44A90000 +set_property offset $AXI_JESD_TX [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_dac_jesd204_link}] +adi_sim_add_define "AXI_JESD_TX_BA=[format "%d" ${AXI_JESD_TX}]" + + +set TX_DMA 0x7C420000 +set_property offset $TX_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_dac_dma}] +adi_sim_add_define "TX_DMA_BA=[format "%d" ${TX_DMA}]" + +set TX_OFFLOAD 0x7C430000 +set_property offset $TX_OFFLOAD [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_dac_data_offload}] +adi_sim_add_define "TX_OFFLOAD_BA=[format "%d" ${TX_OFFLOAD}]" + + +set EX_AXI_XCVR_RX 0x44A20000 +set_property offset $EX_AXI_XCVR_RX [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_axi_xcvr_axi_lite}] +adi_sim_add_define "EX_AXI_XCVR_RX_BA=[format "%d" ${EX_AXI_XCVR_RX}]" + +set EX_ADC_TPL 0x44A30000 +set_property offset $EX_ADC_TPL [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_adc_tpl_core_axi_lite}] +adi_sim_add_define "EX_ADC_TPL_BA=[format "%d" ${EX_ADC_TPL}]" + +set EX_AXI_JESD_RX 0x44A10000 +set_property offset $EX_AXI_JESD_RX [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_rx_axi_axi_lite}] +adi_sim_add_define "EX_AXI_JESD_RX_BA=[format "%d" ${EX_AXI_JESD_RX}]" diff --git a/testbenches/project/dac_fmc_ebz/system_project.tcl b/testbenches/project/dac_fmc_ebz/system_project.tcl new file mode 100755 index 000000000..ab49da331 --- /dev/null +++ b/testbenches/project/dac_fmc_ebz/system_project.tcl @@ -0,0 +1,37 @@ +source ../../../scripts/adi_sim.tcl + +if {$argc < 1} { + puts "Expecting at least one argument that specifies the test configuration" + exit 1 +} else { + set cfg_file [lindex $argv 0] +} + +# Read config file +source "cfgs/${cfg_file}" + +# Set the project name +set project_name [file rootname $cfg_file] + +# Set to use SmartConnect or AXI Interconnect +set use_smartconnect 0 + +# Create the project +adi_sim_project_xilinx $project_name "xczu9eg-ffvb1156-2-e" + +source $ad_tb_dir/library/includes/sp_include_dmac.tcl +source $ad_tb_dir/library/includes/sp_include_jesd.tcl +source $ad_tb_dir/library/includes/sp_include_xcvr.tcl + +# Add test files to the project +adi_sim_project_files [list \ + "$ad_tb_dir/library/regmaps/adi_regmap_dac_pkg.sv" \ + "$ad_tb_dir/library/regmaps/adi_regmap_common_pkg.sv" \ + "$ad_tb_dir/library/regmaps/adi_regmap_adc_pkg.sv" \ + "tests/test_program.sv" \ +] + +#set a default test program +adi_sim_add_define "TEST_PROGRAM=test_program" + +adi_sim_generate $project_name diff --git a/testbenches/project/dac_fmc_ebz/system_tb.sv b/testbenches/project/dac_fmc_ebz/system_tb.sv new file mode 100755 index 000000000..689d35794 --- /dev/null +++ b/testbenches/project/dac_fmc_ebz/system_tb.sv @@ -0,0 +1,110 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +`include "utils.svh" + +module system_tb(); + + localparam TX_SAMPLES_PER_CHANNEL = (`JESD_L*`LL_OUT_BYTES*8) / `JESD_M / `JESD_NP; + localparam TX_DMA_NP = `JESD_NP == 12 ? 16 : `JESD_NP; + + reg [`JESD_M*TX_SAMPLES_PER_CHANNEL*TX_DMA_NP-1:0] tx_ex_dac_data = 'h0; + + wire rx_sync; + + wire [7:0] dut2ex_serial_lane_n; + wire [7:0] dut2ex_serial_lane_p; + + `TEST_PROGRAM test(); + + test_harness `TH ( + .tx_ref_clk_0(ref_clk_ex), + .tx_ref_clk_4(ref_clk_ex), + .ref_clk_out(ref_clk_ex), + .rx_device_clk_out(rx_device_clk), + .sysref_clk_out(sysref), + + .rx_device_clk(rx_device_clk), + .ref_clk_ex(ref_clk_ex), + .sysref(sysref), + .tx_sysref_0(sysref), + + .tx_sync_0(rx_sync), + .ex_rx_sync(rx_sync), + + .rx_data1_0_n(~dut2ex_serial_lane_n[0]), + .rx_data1_0_p(~dut2ex_serial_lane_p[0]), + .rx_data1_1_n(~dut2ex_serial_lane_n[1]), + .rx_data1_1_p(~dut2ex_serial_lane_p[1]), + .rx_data1_2_n(~dut2ex_serial_lane_n[2]), + .rx_data1_2_p(~dut2ex_serial_lane_p[2]), + .rx_data1_3_n(~dut2ex_serial_lane_n[3]), + .rx_data1_3_p(~dut2ex_serial_lane_p[3]), + .rx_data1_4_n(dut2ex_serial_lane_n[4]), + .rx_data1_4_p(dut2ex_serial_lane_p[4]), + .rx_data1_5_n(dut2ex_serial_lane_n[5]), + .rx_data1_5_p(dut2ex_serial_lane_p[5]), + .rx_data1_6_n(dut2ex_serial_lane_n[6]), + .rx_data1_6_p(dut2ex_serial_lane_p[6]), + .rx_data1_7_n(dut2ex_serial_lane_n[7]), + .rx_data1_7_p(dut2ex_serial_lane_p[7]), + + .tx_data_0_n(dut2ex_serial_lane_n[0]), + .tx_data_0_p(dut2ex_serial_lane_p[0]), + .tx_data_1_n(dut2ex_serial_lane_n[1]), + .tx_data_1_p(dut2ex_serial_lane_p[1]), + .tx_data_2_n(dut2ex_serial_lane_n[2]), + .tx_data_2_p(dut2ex_serial_lane_p[2]), + .tx_data_3_n(dut2ex_serial_lane_n[3]), + .tx_data_3_p(dut2ex_serial_lane_p[3]), + .tx_data_4_n(dut2ex_serial_lane_n[4]), + .tx_data_4_p(dut2ex_serial_lane_p[4]), + .tx_data_5_n(dut2ex_serial_lane_n[5]), + .tx_data_5_p(dut2ex_serial_lane_p[5]), + .tx_data_6_n(dut2ex_serial_lane_n[6]), + .tx_data_6_p(dut2ex_serial_lane_p[6]), + .tx_data_7_n(dut2ex_serial_lane_n[7]), + .tx_data_7_p(dut2ex_serial_lane_p[7]) + + //.dac_data_0(tx_ex_dac_data[RX_SAMPLES_PER_CHANNEL*RX_DMA_NP*0 +: RX_SAMPLES_PER_CHANNEL*RX_DMA_NP]), + //.dac_data_1(tx_ex_dac_data[RX_SAMPLES_PER_CHANNEL*RX_DMA_NP*1 +: RX_SAMPLES_PER_CHANNEL*RX_DMA_NP]), + //.dac_data_2(tx_ex_dac_data[RX_SAMPLES_PER_CHANNEL*RX_DMA_NP*2 +: RX_SAMPLES_PER_CHANNEL*RX_DMA_NP]), + //.dac_data_3(tx_ex_dac_data[RX_SAMPLES_PER_CHANNEL*RX_DMA_NP*3 +: RX_SAMPLES_PER_CHANNEL*RX_DMA_NP]) + ); + +endmodule + diff --git a/testbenches/project/dac_fmc_ebz/tests/test_program.sv b/testbenches/project/dac_fmc_ebz/tests/test_program.sv new file mode 100755 index 000000000..109ac1440 --- /dev/null +++ b/testbenches/project/dac_fmc_ebz/tests/test_program.sv @@ -0,0 +1,272 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +import test_harness_env_pkg::*; +import adi_axi_agent_pkg::*; +import adi_regmap_pkg::*; +import axi_vip_pkg::*; +import axi4stream_vip_pkg::*; +import logger_pkg::*; +import adi_regmap_dmac_pkg::*; +import adi_regmap_jesd_tx_pkg::*; +import adi_regmap_jesd_rx_pkg::*; +import adi_regmap_common_pkg::*; +import adi_regmap_dac_pkg::*; +import adi_regmap_adc_pkg::*; +import adi_jesd204_pkg::*; +import adi_xcvr_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +`define LINK_MODE 2 +`define MODE_8B10B 1 +`define MODE_64B66B 2 + +`define fmod(A, B) (A - (B * $floor(A / B))) + +program test_program; + + test_harness_env base_env; + + adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; + + bit [31:0] lane_rate_khz = `LANE_RATE*1000000; + longint lane_rate = lane_rate_khz*1000; + + real rx_device_clk, sysref_clk; + + jesd_link tx_link; + jesd_link rx_link; + + rx_link_layer ex_rx_ll; + tx_link_layer ex_tx_ll; + xcvr ex_rx_xcvr; + xcvr ex_tx_xcvr; + + rx_link_layer dut_rx_ll; + tx_link_layer dut_tx_ll; + xcvr dut_rx_xcvr; + xcvr dut_tx_xcvr; + + initial begin + + //creating environment + base_env = new( + .name("Base Environment"), + .sys_clk_vip_if(`TH.`SYS_CLK.inst.IF), + .dma_clk_vip_if(`TH.`DMA_CLK.inst.IF), + .ddr_clk_vip_if(`TH.`DDR_CLK.inst.IF), + .sys_rst_vip_if(`TH.`SYS_RST.inst.IF), + .irq_base_address(`IRQ_C_BA), + .irq_vip_if(`TH.`IRQ.inst.inst.IF.vif)); + + mng = new("", `TH.`MNG_AXI.inst.IF); + ddr = new("", `TH.`DDR_AXI.inst.IF); + + `LINK(mng, base_env, mng) + `LINK(ddr, base_env, ddr) + + setLoggerVerbosity(ADI_VERBOSITY_NONE); + + base_env.start(); + base_env.sys_reset(); + + tx_link = new; + tx_link.set_L(`JESD_L); + tx_link.set_M(`JESD_M); + tx_link.set_F(`JESD_F); + tx_link.set_S(`JESD_S); + tx_link.set_K(32); + tx_link.set_N(`JESD_NP); + tx_link.set_NP(`JESD_NP); + tx_link.set_encoding(enc8b10b); + tx_link.set_lane_rate(lane_rate); + + ex_rx_ll = new("EX RX_LINK_LAYER", base_env.mng.master_sequencer, `EX_AXI_JESD_RX_BA, tx_link); + ex_rx_ll.probe(); + + ex_rx_xcvr = new("EX RX_XCVR", base_env.mng.master_sequencer, `EX_AXI_XCVR_RX_BA); + ex_rx_xcvr.probe(); + + dut_tx_xcvr = new("DUT TX_XCVR", base_env.mng.master_sequencer, `DUT_AXI_XCVR_TX_BA); + dut_tx_xcvr.probe(); + + dut_tx_ll = new("DUT TX_LINK_LAYER", base_env.mng.master_sequencer, `AXI_JESD_TX_BA, tx_link); + dut_tx_ll.probe(); + + `TH.`REF_CLK.inst.IF.set_clk_frq(.user_frequency(`REF_CLK_RATE*1000000)); + + rx_device_clk = ex_rx_ll.calc_device_clk(); + sysref_clk = ex_rx_ll.calc_sysref_clk(); + + `TH.`RX_DEVICE_CLK.inst.IF.set_clk_frq(rx_device_clk); + `TH.`SYSREF_CLK.inst.IF.set_clk_frq(.user_frequency(sysref_clk)); + + `TH.`REF_CLK.inst.IF.start_clock(); + `TH.`RX_DEVICE_CLK.inst.IF.start_clock(); + `TH.`SYSREF_CLK.inst.IF.start_clock(); + + ex_rx_xcvr.setup_clocks(lane_rate, + `REF_CLK_RATE*1000000); + + dut_tx_xcvr.setup_clocks(lane_rate, + `REF_CLK_RATE*1000000, '{QPLL0, QPLL1}); + + tx_tpl_test(.use_dds(0)); + + base_env.stop(); + + `TH.`REF_CLK.inst.IF.stop_clock(); + `TH.`RX_DEVICE_CLK.inst.IF.stop_clock(); + `TH.`SYSREF_CLK.inst.IF.stop_clock(); + + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish(); + + end + + task tx_tpl_test(int use_dds); + if (!use_dds) begin + for (int i=0;i<2048*2 ;i=i+2) begin + base_env.ddr.slave_sequencer.BackdoorWrite32(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,15); + end + + // Configure TX DMA + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + `SET_DMAC_FLAGS_TLAST(1)); + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + `SET_DMAC_X_LENGTH_X_LENGTH(32'h00000FFF)); + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA+32'h00000000)); + base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + #5us; + end + + for (int i = 0; i < `JESD_M; i++) begin + if (use_dds) begin + // Select DDS as source + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); + // Configure tone amplitude and frequency + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h0fff)); + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); + + end else begin + // Set DMA as source for DAC TPL + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+'h40*i+GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); + end + end + + for (int i = 0; i < `JESD_M; i++) begin + base_env.mng.master_sequencer.RegWrite32(`EX_ADC_TPL_BA+'h40*i+GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); + end + + + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_RSTN), + `SET_DAC_COMMON_REG_RSTN_RSTN(1)); + base_env.mng.master_sequencer.RegWrite32(`EX_ADC_TPL_BA+GetAddrs(ADC_COMMON_REG_RSTN), + `SET_ADC_COMMON_REG_RSTN_RSTN(1)); + + if (use_dds) begin + // Sync DDS cores + base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_CNTRL_1), + `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); + end + + // ----------------------- + // bringup DUT TX path + // ----------------------- + dut_tx_xcvr.up(); + dut_tx_ll.link_up(); + + ex_rx_xcvr.up(); + ex_rx_ll.link_up(); + + dut_tx_ll.wait_link_up(); + ex_rx_ll.wait_link_up(); + + #10us; + + ex_rx_xcvr.down(); + dut_tx_xcvr.down(); + endtask + + task check_captured_data(bit [31:0] address, + int length = 1024, + int step = 1, + int max_sample = 2048 + ); + + bit [31:0] current_address; + bit [31:0] captured_word; + bit [31:0] reference_word; + bit [7:0] first, second; + + for (int i=0;i 20 && captured_word !== reference_word) begin + `ERROR(("Address 0x%h Expected 0x%h found 0x%h",current_address,reference_word,captured_word)); + end + end + end + endtask + +endprogram diff --git a/testbenches/project/dac_fmc_ebz/waves/cfg1.wcfg b/testbenches/project/dac_fmc_ebz/waves/cfg1.wcfg new file mode 100755 index 000000000..244f4709f --- /dev/null +++ b/testbenches/project/dac_fmc_ebz/waves/cfg1.wcfg @@ -0,0 +1,160 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DUT TX + label + + + sync[0:0] + sync[0:0] + + + sync_1[0:0] + sync_1[0:0] + + + rx_phy0_rxdata[31:0] + rx_phy0_rxdata[31:0] + + + link_clk + link_clk + + + device_clk + device_clk + + + rx_device_clk + rx_device_clk + + + rx_device_clk_out + rx_device_clk_out + + + tx_device_clk_out + tx_device_clk_out + + + rx_axi_core_reset + rx_axi_core_reset + + + rx_axi_device_reset + rx_axi_device_reset + + + rx_data_tdata[127:0] + rx_data_tdata[127:0] + + + rx_data_tvalid + rx_data_tvalid + + + Ex Rx + label + + + rx_sysref_0 + rx_sysref_0 + + + sysref_1 + sysref_1 + + + rx_data_0[31:0] + rx_data_0[31:0] + + + rx_header_0[1:0] + rx_header_0[1:0] + + + rx_block_sync_0 + rx_block_sync_0 + + + rx_data_tdata[127:0] + rx_data_tdata[127:0] + + + rx_data_tvalid + rx_data_tvalid + + + Ex Tx + label + + + device_clk + device_clk + + + link_clk + link_clk + + + tx_data_tready + tx_data_tready + + + tx_phy0_txdata[31:0] + tx_phy0_txdata[31:0] + + + tx_phy0_txheader[1:0] + tx_phy0_txheader[1:0] + + + tx_0_p + tx_0_p + + + DUT RX + label + +