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kyyalama2AWScsaralay
kyyalama2
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AWScsaralay
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Update cl_synth_aws.xdc constraints to address async clocks in sh_ddr.sv (#674) (#522)
* Update cl_synth_aws.xdc constraints to address async clocks in sh_ddr.sv * cl_synth_aws.xdc: Apply constraints "quietly" so it doesnt throw warnings on CLs that dont have DDRs Co-authored-by: AWScsaralay <[email protected]>
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‎hdk/common/shell_v04261818/build/constraints/cl_synth_aws.xdc‎

Lines changed: 50 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,56 @@ set_max_delay -datapath_only \
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-to [get_clocks -of_objects [get_pins SH_DDR/ddr_cores.DDR4_*/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0]] \
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[get_property PERIOD [get_clocks -of_objects [get_ports clk_main_a0]]]
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set asyncFFs [get_cells -quiet -hier -filter {NAME =~ WRAPPER_INST/CL/SH_DDR/*sync_wr_rst/in_q_reg[0] || NAME =~ WRAPPER_INST/CL/SH_DDR/*sync_wr_rst/sync_out_reg[0]}]
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set asyncFFs [get_cells -quiet -hier -filter {\
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NAME =~ *SH_DDR/*sync_wr_rst/in_q_reg[0] || \
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NAME =~ *SH_DDR/*sync_wr_rst/sync_out_reg[0] ||\
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NAME =~ *SH_DDR/*sync_rd_rst/in_q_reg[0] || \
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NAME =~ *SH_DDR/*sync_rd_rst/sync_out_reg[0] \
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}]
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set asyncFFPins [get_pins -quiet -filter REF_PIN_NAME==CLR -of $asyncFFs]
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set_false_path -quiet -to $asyncFFPins
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set_property -quiet ASYNC_REG true $asyncFFs
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#
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# False Paths for Synchronizers inside sh_ddr.sv
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#
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set syncCells [get_cells -quiet -hierarchical -filter {\
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NAME =~ *SH_DDR/*DDR_STAT_INC_SYNC0/in_q_reg* || \
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NAME =~ *SH_DDR/*DDR_STAT_INC_SYNC1/in_q_reg* || \
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NAME =~ *SH_DDR/*DDR_STAT_INC_SYNC2/in_q_reg* || \
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NAME =~ *SH_DDR/*SAVE_RST_TO_DDR_SYNC/in_q_reg* || \
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NAME =~ *SH_DDR/*SAVE_RST_FROM_DDR_SYNC/in_q_reg* || \
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NAME =~ *SH_DDR/*CCF_XSDB_*/CCF_CTL/sync_write_ptr_rd/in_q_reg* || \
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NAME =~ *SH_DDR/*CCF_XSDB_*/CCF_CTL/sync_read_ptr_wr/in_q_reg* || \
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NAME =~ *SH_DDR/*CCF_DDR_STAT_*/CCF_CTL/sync_write_ptr_rd/in_q_reg* || \
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NAME =~ *SH_DDR/*CCF_DDR_STAT_*/CCF_CTL/sync_read_ptr_wr/in_q_reg* \
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}]
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set syncPins [get_pins -quiet -filter {REF_PIN_NAME==D} -of_objects $syncCells]
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set_false_path -quiet -to $syncPins
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# Set ASYNC_REG property on syncrhonizer flops.
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set syncOutCells [get_cells -quiet -hierarchical -filter {\
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NAME =~ *SH_DDR/*DDR_STAT_INC_SYNC0/sync_out_reg* || \
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NAME =~ *SH_DDR/*DDR_STAT_INC_SYNC1/sync_out_reg* || \
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NAME =~ *SH_DDR/*DDR_STAT_INC_SYNC2/sync_out_reg* || \
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NAME =~ *SH_DDR/*SAVE_RST_TO_DDR_SYNC/sync_out_reg* || \
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NAME =~ *SH_DDR/*SAVE_RST_FROM_DDR_SYNC/sync_out_reg* || \
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NAME =~ *SH_DDR/*CCF_XSDB_*/CCF_CTL/sync_write_ptr_rd/sync_out_reg* || \
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NAME =~ *SH_DDR/*CCF_XSDB_*/CCF_CTL/sync_read_ptr_wr/sync_out_reg* || \
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NAME =~ *SH_DDR/*CCF_DDR_STAT_*/CCF_CTL/sync_write_ptr_rd/sync_out_reg* || \
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NAME =~ *SH_DDR/*CCF_DDR_STAT_*/CCF_CTL/sync_read_ptr_wr/sync_out_reg* \
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}]
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set_property -quiet ASYNC_REG true $syncCells $syncOutCells
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#
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# CDC False Paths in sh_ddr.sv
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#
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set fromPins [get_pins -quiet -filter {REF_PIN_NAME==CLK} -of_objects [get_cells -quiet -hierarchical -filter {\
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NAME =~ *SH_DDR/*CCF_XSDB_*/ram_reg* || \
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NAME =~ *SH_DDR/*CCF_DDR_STAT_*/ram_reg* \
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}]]
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set toPins [get_pins -quiet -filter {REF_PIN_NAME==D} -of_objects [get_cells -hierarchical -quiet -filter {\
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NAME =~ *SH_DDR/*CCF_XSDB_*/rd_do_reg* || \
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NAME =~ *SH_DDR/*CCF_DDR_STAT_*/rd_do_reg* \
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}]]
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set_false_path -quiet -from $fromPins -to $toPins

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