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lines changed Original file line number Diff line number Diff line change @@ -83,6 +83,11 @@ static int secp256k1_context_is_proper(const secp256k1_context* ctx) {
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}
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void secp256k1_selftest (void ) {
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+ if (!SECP256K1_CHECKMEM_RUNNING ()) {
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+ if (!secp256k1_selftest_cpuid ()) {
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+ secp256k1_callback_call (& default_error_callback , "required CPU flags are not present." );
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+ }
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+ }
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if (!secp256k1_selftest_passes ()) {
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secp256k1_callback_call (& default_error_callback , "self test failed" );
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}
Original file line number Diff line number Diff line change @@ -25,6 +25,31 @@ static int secp256k1_selftest_sha256(void) {
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return secp256k1_memcmp_var (out , output32 , 32 ) == 0 ;
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}
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+ static int secp256k1_selftest_cpuid (void ) {
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+ int ret = 1 ;
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+
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+ #if defined(USE_ASM_X86_64 )
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+ // getting the CPU flags from the cpu, more information in the Intel manual,
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+ // Table 3-8 Information Returned by CPUID instruction (3-194, Vol.2A)
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+ const int CPU_FLAG_ENUMERATION = 7 ;
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+ const int LEAF_NODE_ZERO = 0 ;
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+
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+ // for the cpu self test, we need BMI2 and ADX support
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+ const int BIT_ADX = 19 ;
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+ const int BIT_BMI2 = 8 ;
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+ int flags = 0 ;
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+ __asm__ __volatile__("cpuid\n"
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+ : "=b" (flags )
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+ : "a" (CPU_FLAG_ENUMERATION ), "c" (LEAF_NODE_ZERO )
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+ : "rdx" , "rbx" , "cc" );
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+
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+ int has_adx = (flags >> BIT_ADX ) & 1 ;
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+ int has_bmi2 = (flags >> BIT_BMI2 ) & 1 ;
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+ ret = has_adx && has_bmi2 ;
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+ #endif
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+ return ret ;
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+ }
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+
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static int secp256k1_selftest_passes (void ) {
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return secp256k1_selftest_sha256 ();
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}
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