The ic_bank_way_clken_final_up output port is undriven in our design.
In el2_ifu_lc_mem.sv if pt.ICACHE_WAYPACK != 0 ic_b_sram_en_up is undriven.
You can see our Veer EL2 Core here: https://github.com/chipsalliance/caliptra-ss/tree/main/src/riscv_core/veer_el2/rtl