Fix lint warnings

Author: domenicw

src/isa/riscv_csr_instr.sv

@@ -46,25 +46,25 @@ class riscv_csr_instr extends riscv_instr;
     }
   }
 
-  constraint csr_csrrw {
+  constraint csr_csrrw_c {
     if (instr_name == CSRRW || instr_name == CSRRWI) {
       write_csr == 1'b1;
     }
   }
 
-  constraint csr_csrrsc {
+  constraint csr_csrrsc_c {
     if (instr_name == CSRRS || instr_name == CSRRC) {
       (write_csr == 1'b1) || rs1 == 0;
     }
   }
 
-  constraint csr_csrrsci {
+  constraint csr_csrrsci_c {
     if(instr_name == CSRRSI || instr_name == CSRRCI) {
       (write_csr == 1'b1) || imm == 0;
     }
   }
 
-  constraint order {
+  constraint order_c {
     // Choose a CSR before deciding whether we want to write to the CSR values. Then choose whether
     // to read or write before choosing the rs1 and imm values. This ensures read-only accesses to
     // read-only CSRs with similar probability to other CSR accesses and ensures a reasonable write

src/riscv_asm_program_gen.sv

@@ -581,17 +581,18 @@ class riscv_asm_program_gen extends uvm_object;
           `uvm_fatal(`gfn, "Couldn't find a memory region big enough to initialize the vector registers")
 
         for (int v = 0; v < NUM_VEC_GPR; v++) begin
-					// Select random region
+          // Select random region
           int region = $urandom_range(0, valid_mem_region.size()-1);
-					// Get valid start offset in region
+          // Get valid start offset in region
           int offset = $urandom_range(0, (valid_mem_region[region].size_in_bytes - (cfg.vector_cfg.vlen / 8)) /
-																					(sew / 8)) * (sew / 8);
-					// Generate load
+                                          (sew / 8)) * (sew / 8);
+          // Generate load
           instr_stream.push_back($sformatf("%0sla x%0d, %0s+%0d", indent, cfg.gpr[0],
                                            valid_mem_region[region].name, offset));
           instr_stream.push_back($sformatf("%0svle%0d.v v%0d, (x%0d)", indent, sew, v, cfg.gpr[0]));
         end
       end
+      default: ;
     endcase
 
     // Initialize vector CSRs

src/riscv_illegal_instr.sv

@@ -142,7 +142,7 @@ class riscv_illegal_instr extends uvm_object;
     }
   }
 
-  constraint legal_rv32_c_slli {
+  constraint legal_rv32_c_slli_c {
     if ((c_msb == 3'b000) && (c_op == 2'b10) && (XLEN == 32)) {
       if (exception == kReservedCompressedInstr) {
         instr_bin[12] == 1;

src/riscv_instr_stream.sv

@@ -330,7 +330,8 @@ class riscv_rand_instr_stream extends riscv_instr_stream;
       // For every current vtype config, there will always be a legal vlmul when vsew
       // is reduced, since there is always space for at least one element in a fractional
       // register. So setting to smallest vsew here is always possible.
-      if (!cfg.vector_cfg.vtype.fractional_lmul && vsew/8 > cfg.vector_cfg.vtype.vsew/cfg.vector_cfg.vtype.vlmul) begin
+      if (!cfg.vector_cfg.vtype.fractional_lmul &&
+          vsew/8 > cfg.vector_cfg.vtype.vsew/cfg.vector_cfg.vtype.vlmul) begin
         vsew = 8;
       end
       // Calculate new vlmul and update vtype, while vl remains constant

src/riscv_load_store_instr_lib.sv

@@ -523,11 +523,11 @@ endclass
 class riscv_vector_load_store_instr_stream extends riscv_mem_access_stream;
 
   // List of vector load/store instructions (grouped into different address modes)
-  localparam riscv_instr_name_t unit_strided[] = {VLE_V, VSE_V, VLEFF_V,
-                                                  VLM_V, VSM_V, VLRE_V, VSR_V,
-                                                  VLSEGE_V, VSSEGE_V, VLSEGEFF_V};
-  localparam riscv_instr_name_t strided[]      = {VLSE_V, VSSE_V, VLSSEGE_V, VSSSEGE_V};
-  localparam riscv_instr_name_t indexed[]      = {VLUXEI_V, VLOXEI_V, VSUXEI_V, VSOXEI_V,
+  localparam riscv_instr_name_t UnitStrided[] = {VLE_V, VSE_V, VLEFF_V,
+                                                 VLM_V, VSM_V, VLRE_V, VSR_V,
+                                                 VLSEGE_V, VSSEGE_V, VLSEGEFF_V};
+  localparam riscv_instr_name_t Strided[]      = {VLSE_V, VSSE_V, VLSSEGE_V, VSSSEGE_V};
+  localparam riscv_instr_name_t Indexed[]      = {VLUXEI_V, VLOXEI_V, VSUXEI_V, VSOXEI_V,
                                                   VLUXSEGEI_V, VLOXSEGEI_V, VSUXSEGEI_V, VSOXSEGEI_V};
 
   // Types of vector load/store address modes
@@ -642,20 +642,20 @@ class riscv_vector_load_store_instr_stream extends riscv_mem_access_stream;
     super.pre_randomize();
 
     // Build list of allowed address modes (according to unsupported_instr list)
-    foreach(unit_strided[i]) begin
-      if (!(unit_strided[i] inside {unsupported_instr})) begin
+    foreach(UnitStrided[i]) begin
+      if (!(UnitStrided[i] inside {unsupported_instr})) begin
         allowed_address_modes = {allowed_address_modes, UNIT_STRIDED};
         break;
       end
     end
-    foreach(strided[i]) begin
-      if (!(strided[i] inside {unsupported_instr})) begin
+    foreach(Strided[i]) begin
+      if (!(Strided[i] inside {unsupported_instr})) begin
         allowed_address_modes = {allowed_address_modes, STRIDED};
         break;
       end
     end
-    foreach(indexed[i]) begin
-      if (!(indexed[i] inside {unsupported_instr})) begin
+    foreach(Indexed[i]) begin
+      if (!(Indexed[i] inside {unsupported_instr})) begin
         allowed_address_modes = {allowed_address_modes, INDEXED};
         break;
       end
@@ -758,14 +758,15 @@ class riscv_vector_load_store_instr_stream extends riscv_mem_access_stream;
     // Get instructions for selected address mode
     case (address_mode)
       UNIT_STRIDED : begin
-        possible_instr = {unit_strided};
+        possible_instr = {UnitStrided};
       end
       STRIDED : begin
-        possible_instr = {strided};
+        possible_instr = {Strided};
       end
       INDEXED : begin
-        possible_instr = {indexed};
+        possible_instr = {Indexed};
       end
+      default: ;
     endcase
 
     // Filter out illegal instructions for current config