[rtl] disable chaining.

qinjun-li · qinjun-li · commit 7db7dcddf0f3 · 2024-11-20T17:52:19.000+08:00
diff --git a/t1/src/T1.scala b/t1/src/T1.scala
@@ -657,10 +657,8 @@ class T1(val parameter: T1Parameter)
     )
   )
 
-  val freeOR: Bool = VecInit(slots.map(_.state.idle)).asUInt.orR
-
   /** slot is ready to accept new instructions. */
-  val slotReady: Bool = Mux(specialInstruction, slots.map(_.state.idle).last, freeOR)
+  val slotReady: Bool = VecInit(slots.map(_.state.idle)).asUInt.andR
 
   val source1Select: UInt =
     Mux(

Original file line number	Diff line number	Diff line change
`@@ -657,10 +657,8 @@ class T1(val parameter: T1Parameter)`
`657`	`657`	`)`
`658`	`658`	`)`
`659`	`659`
`660`		`- val freeOR: Bool = VecInit(slots.map(_.state.idle)).asUInt.orR`
`661`		`-`
`662`	`660`	`/** slot is ready to accept new instructions. */`
`663`		`- val slotReady: Bool = Mux(specialInstruction, slots.map(_.state.idle).last, freeOR)`
	`661`	`+ val slotReady: Bool = VecInit(slots.map(_.state.idle)).asUInt.andR`
`664`	`662`
`665`	`663`	`val source1Select: UInt =`
`666`	`664`	`Mux(`