Release Plan

[sequencer]

Since T1 is mature, we are going to release T1 for a software and FPGA public review, artifacts includes:

• Docker environment with compiler support, includes bundled LLVM and a simple runtime libraries and some demos;
• Static linked Verilated Emulator;
• Packaged pre-synthesised Xilinx IP;
• FPGA bitstream for candelabra board;

Due to the limitation of EDA world, the release flow will be in-house, but published in public, without providing the Verilog to end users.