CAM-based Chaining Check

[sequencer]

Currently for each instruction, it may have 3/2 read and 1 write, it will find the chaining record --in the granularity of laneDatapath--. use this record to check all instructions.
If increasing the chainingSize, since it's all-to-all check, it leads to O(n^2) area(timing) for the chaining check, thus we cannot increase chainingSize.

inst0 -> rs0, rs1, rd(rs2)
inst1 -> rs0, rs1, rd(rs2)
inst2 -> rs0, rs1, rd(rs2)
inst3 -> rs0, rs1, rd(rs2)

inst1.rs0,inst1.rs1 RAW inst0.rd
inst1.rd WAR inst0.rs0, inst0.rs1
inst1.rd WAW inst0.rd

inst2.rs0,inst2.rs1 RAW inst0.rd, inst1.rd
inst2.rd WAR inst0.rs0, inst0.rs1, inst1.rs0, inst1.rs1
inst2.rd WAW inst0.rd, inst1.rd

inst3.rs0,inst3.rs1 RAW inst0.rd, inst1.rd, inst2.rd
inst3.rd WAR inst0.rs0, inst0.rs1, inst1.rs0, inst1.rs1, inst2.rs0, inst2.rs1
inst3.rd WAW inst0.rd, inst1.rd, inst2.rd

Fanin:
For each read port:
RAW: 2 * chainingSize -> chainingSize * chainingSize
For each write port:
WAR: 1 * chainingSize -> 2 * chainingSize * chainingSize
WAW: 1 * chainingSize -> chainingSize * chainingSize