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Merge pull request #1085 from diffblue/sva-until-to-ltl
convert `s_until` and `s_until_with` to LTL
2 parents 0ab525a + 774bc02 commit 5e8e457

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CORE
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s_until1.sv
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--smv-netlist
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^LTLSPEC \(\!node144\) U node151$
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^LTLSPEC \(1\) U node158$
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^EXIT=0$
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^SIGNAL=0$
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--
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module main(input clk);
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// count up from 0 to 10
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reg [7:0] counter = 0;
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always_ff @(posedge clk)
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if(counter == 10)
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counter = 0;
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else
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counter = counter + 1;
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// expected to pass
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initial p0: assert property ($past(counter)<=counter s_until counter==10);
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// expected to fail
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initial p1: assert property (1 s_until counter==11);
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endmodule

regression/verilog/SVA/s_until1.desc

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CORE
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s_until1.sv
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--bound 11
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^\[.*\] \$past\(main\.counter\) <= main\.counter s_until main\.counter == 10: PROVED up to bound 11$
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^\[.*\] 1 s_until main\.counter == 11: REFUTED$
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^EXIT=10$
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^SIGNAL=0$
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--

regression/verilog/SVA/s_until1.sv

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module main(input clk);
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// count up from 0 to 10
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reg [7:0] counter = 0;
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always_ff @(posedge clk)
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if(counter == 10)
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counter = 0;
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else
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counter = counter + 1;
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// expected to pass
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initial p0: assert property ($past(counter)<=counter s_until counter==10);
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// expected to fail
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initial p1: assert property (1 s_until counter==11);
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endmodule

src/temporal-logic/temporal_logic.cpp

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@@ -338,6 +338,27 @@ std::optional<exprt> SVA_to_LTL(exprt expr)
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else
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return {};
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}
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else if(expr.id() == ID_sva_s_until)
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{
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auto &until = to_sva_s_until_expr(expr);
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auto rec_lhs = SVA_to_LTL(until.lhs());
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auto rec_rhs = SVA_to_LTL(until.rhs());
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if(rec_lhs.has_value() && rec_rhs.has_value())
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return U_exprt{rec_lhs.value(), rec_rhs.value()};
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else
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return {};
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}
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else if(expr.id() == ID_sva_s_until_with)
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{
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// This is release with swapped operands
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auto &until_with = to_sva_s_until_with_expr(expr);
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auto rec_lhs = SVA_to_LTL(until_with.lhs());
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auto rec_rhs = SVA_to_LTL(until_with.rhs());
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if(rec_lhs.has_value() && rec_rhs.has_value())
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return R_exprt{rec_rhs.value(), rec_lhs.value()}; // swapped
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else
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return {};
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}
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else if(!has_temporal_operator(expr))
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{
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return expr;

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