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allow component 0 implicit, alt glyphs for jack
1 parent e06fad2 commit 44df3c9

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3 files changed

+41
-27
lines changed

3 files changed

+41
-27
lines changed

schemascii/components.py

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
from .errors import DiagramSyntaxError, BOMError
55

66

7-
SMALL_COMPONENT_OR_BOM = re.compile(r'#*([A-Z]+)(\d+|\.\w+)(:[^\s]+)?#*')
7+
SMALL_COMPONENT_OR_BOM = re.compile(r'#*([A-Z]+)(\d*|\.\w+)(:[^\s]+)?#*')
88

99

1010
def find_small(grid: Grid) -> tuple[list[Cbox], list[BOMData]]:
@@ -14,13 +14,14 @@ def find_small(grid: Grid) -> tuple[list[Cbox], list[BOMData]]:
1414
boms: list[BOMData] = []
1515
for i, line in enumerate(grid.lines):
1616
for m in SMALL_COMPONENT_OR_BOM.finditer(line):
17+
ident = m.group(2) or '0'
1718
if m.group(3):
1819
boms.append(BOMData(m.group(1),
19-
m.group(2), m.group(3)[1:]))
20+
ident, m.group(3)[1:]))
2021
else:
2122
components.append(Cbox(complex(m.start(), i),
2223
complex(m.end() - 1, i),
23-
m.group(1), m.group(2)))
24+
m.group(1), ident))
2425
for z in range(*m.span(0)):
2526
grid.setmask(complex(z, i))
2627
return components, boms

schemascii/components_render.py

Lines changed: 36 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,8 @@
55
from .utils import (Cbox, Terminal, BOMData, XML, Side, arrow_points,
66
polylinegon, id_text, make_text_point,
77
bunch_o_lines, deep_transform, make_plus, make_variable,
8-
sort_counterclockwise, light_arrows, sort_for_flags, is_clockwise)
8+
sort_counterclockwise, light_arrows, sort_for_flags,
9+
is_clockwise)
910
from .errors import TerminalsError, BOMError, UnsupportedComponentError
1011

1112
# pylint: disable=unbalanced-tuple-unpacking
@@ -309,26 +310,35 @@ def jack(
309310
bom_data: BOMData,
310311
**options):
311312
"""Draw a jack connector or plug.
312-
bom:label"""
313+
bom:label[,{circle/input/output}]"""
313314
scale = options["scale"]
314-
sc_t1 = terminals[0].pt * scale
315-
sc_t2 = sc_t1 + rect(scale, SIDE_TO_ANGLE_MAP[terminals[0].side])
316-
sc_text_pt = sc_t2 + rect(scale * 2, SIDE_TO_ANGLE_MAP[terminals[0].side])
315+
t1 = terminals[0].pt
316+
t2 = t1 + rect(1, SIDE_TO_ANGLE_MAP[terminals[0].side])
317+
sc_t2 = t2 * scale
318+
sc_text_pt = sc_t2 + rect(scale, SIDE_TO_ANGLE_MAP[terminals[0].side])
319+
style = "input" if terminals[0].side in (
320+
Side.LEFT, Side.TOP) else "output"
321+
if any(bom_data.data.endswith(x)
322+
for x in (",circle", ",input", ",output")):
323+
style = bom_data.data.split(",")[-1]
324+
bom_data = BOMData(bom_data.type, bom_data.id,
325+
bom_data.data.rstrip("cirlenputo")
326+
.removesuffix(","))
327+
if style == "circle":
328+
return (
329+
bunch_o_lines([(t1, t2)], **options)
330+
+ XML.circle(
331+
cx=sc_t2.real,
332+
cy=sc_t2.imag,
333+
r=scale / 4,
334+
stroke__width=options["stroke_width"],
335+
stroke=options["stroke"],
336+
fill="transparent")
337+
+ id_text(box, bom_data, terminals, None, sc_text_pt, **options))
338+
if style == "output":
339+
t1, t2 = t2, t1
317340
return (
318-
XML.line(
319-
x1=sc_t1.real,
320-
x2=sc_t2.real,
321-
y1=sc_t1.imag,
322-
y2=sc_t2.imag,
323-
stroke__width=options["stroke_width"],
324-
stroke=options["stroke"])
325-
+ XML.circle(
326-
cx=sc_t2.real,
327-
cy=sc_t2.imag,
328-
r=scale / 4,
329-
stroke__width=options["stroke_width"],
330-
stroke=options["stroke"],
331-
fill="transparent")
341+
bunch_o_lines(arrow_points(t1, t2), **options)
332342
+ id_text(box, bom_data, terminals, None, sc_text_pt, **options))
333343

334344

@@ -343,7 +353,8 @@ def transistor(
343353
"""Draw a bipolar transistor (PNP/NPN) or FET (NFET/PFET).
344354
bom:{npn/pnp/nfet/pfet}:part-number
345355
flags:s=source,d=drain,g=gate,e=emitter,c=collector,b=base"""
346-
if not any(bom_data.data.lower().startswith(x) for x in ("pnp:", "npn:", "nfet:", "pfet:")):
356+
if not any(bom_data.data.lower().startswith(x) for x in (
357+
"pnp:", "npn:", "nfet:", "pfet:")):
347358
raise BOMError(
348359
f"Need type of transistor for {box.type}{box.id}")
349360
silicon_type, part_num = bom_data.data.split(":")
@@ -380,7 +391,8 @@ def transistor(
380391
arr = arr[1], arr[0]
381392
out_lines.extend([
382393
*arrow_points(*arr),
383-
(mid - rect(.8, theta), mid - rect(.8, theta) + rect(.7, thetaquarter)),
394+
(mid - rect(.8, theta), mid - rect(.8, theta)
395+
+ rect(.7, thetaquarter)),
384396
(mid + rect(1, theta) + rect(.7, thetaquarter),
385397
mid - rect(1, theta) + rect(.7, thetaquarter)),
386398
(mid + rect(.5, theta) + rect(1, thetaquarter),
@@ -393,7 +405,8 @@ def transistor(
393405
arr = arr[1], arr[0]
394406
out_lines.extend([
395407
*arrow_points(*arr),
396-
(mid - rect(.8, theta), mid - rect(.4, theta) + rect(1, thetaquarter)),
408+
(mid - rect(.8, theta), mid - rect(.4, theta)
409+
+ rect(1, thetaquarter)),
397410
(mid + rect(1, theta) + rect(1, thetaquarter),
398411
mid - rect(1, theta) + rect(1, thetaquarter)),
399412
])
@@ -412,7 +425,7 @@ def transistor(
412425
# + is on the top unless otherwise noted
413426
# terminals will be connected at (0, -1) and (0, 1) relative to the paths here
414427
# if they aren't the path will be transformed
415-
twoterminals = {
428+
{
416429
# fuse
417430
'F': 'M0-.9A.1.1 0 000-1.1.1.1 0 000-.9ZM0-1Q.5-.5 0 0T0 1Q-.5.5 0 0T0-1ZM0 1.1A.1.1 0 000 .9.1.1 0 000 1.1Z',
418431
# jumper pads

supported-components.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,5 +16,5 @@ and run scripts/docs.py to re-generate this file.
1616
| `B`, `BT`, `BAT` | Draw a battery cell. | `volts[,amp-hours]` | `+` = positive |
1717
| `D`, `LED`, `CR`, `IR` | Draw a diode or LED. | `part-number` | `+` = positive |
1818
| `U`, `IC` | Draw an IC. | `part-number[,pin1-label[,pin2-label[,...]]]` | |
19-
| `J`, `P` | Draw a jack connector or plug. | `label` | |
19+
| `J`, `P` | Draw a jack connector or plug. | `label[,{circle/input/output}]` | |
2020
| `Q`, `MOSFET`, `MOS`, `FET` | Draw a bipolar transistor (PNP/NPN) or FET (NFET/PFET). | `{npn/pnp/nfet/pfet}:part-number` | `s` = source<br>`d` = drain<br>`g` = gate<br>`e` = emitter<br>`c` = collector<br>`b` = base |

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