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[LoongArch] Pre-commit tests for tls-desc scheduling. NFC (llvm#121538)
Code sequence for tls-desc in large code model is not expected to be scheduled according to psABI 2.30. A later commit will fix it.
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llvm/test/CodeGen/LoongArch/psabi-restricted-scheduling.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=medium --relocation-model=pic --post-RA-scheduler=0 < %s \
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; RUN: | FileCheck %s --check-prefix=MEDIUM_NO_SCH
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; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=medium --relocation-model=pic --post-RA-scheduler=1 < %s \
@@ -7,6 +6,14 @@
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; RUN: | FileCheck %s --check-prefix=LARGE_NO_SCH
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; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=large --relocation-model=pic --post-RA-scheduler=1 < %s \
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; RUN: | FileCheck %s --check-prefix=LARGE_SCH
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; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=medium --relocation-model=pic --enable-tlsdesc \
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; RUN: --post-RA-scheduler=0 < %s | FileCheck %s --check-prefix=MEDIUMDESC_NO_SCH
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; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=medium --relocation-model=pic --enable-tlsdesc \
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; RUN: --post-RA-scheduler=1 < %s | FileCheck %s --check-prefix=MEDIUMDESC_SCH
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; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=large --relocation-model=pic --enable-tlsdesc \
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; RUN: --post-RA-scheduler=0 < %s | FileCheck %s --check-prefix=LARGEDESC_NO_SCH
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; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=large --relocation-model=pic --enable-tlsdesc \
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; RUN: --post-RA-scheduler=1 < %s | FileCheck %s --check-prefix=LARGEDESC_SCH
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@g = dso_local global i64 zeroinitializer, align 4
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@G = global i64 zeroinitializer, align 4
@@ -194,3 +201,69 @@ define void @foo() nounwind {
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%v_ie = load volatile i64, ptr @ie
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ret void
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}
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define void @baz() nounwind {
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; MEDIUMDESC_NO_SCH-LABEL: baz:
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; MEDIUMDESC_NO_SCH: # %bb.0:
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; MEDIUMDESC_NO_SCH-NEXT: addi.d $sp, $sp, -16
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; MEDIUMDESC_NO_SCH-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
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; MEDIUMDESC_NO_SCH-NEXT: pcalau12i $a0, %desc_pc_hi20(gd)
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; MEDIUMDESC_NO_SCH-NEXT: addi.d $a0, $a0, %desc_pc_lo12(gd)
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; MEDIUMDESC_NO_SCH-NEXT: ld.d $ra, $a0, %desc_ld(gd)
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; MEDIUMDESC_NO_SCH-NEXT: jirl $ra, $ra, %desc_call(gd)
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; MEDIUMDESC_NO_SCH-NEXT: add.d $a0, $a0, $tp
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; MEDIUMDESC_NO_SCH-NEXT: ld.d $zero, $a0, 0
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; MEDIUMDESC_NO_SCH-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
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; MEDIUMDESC_NO_SCH-NEXT: addi.d $sp, $sp, 16
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; MEDIUMDESC_NO_SCH-NEXT: ret
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;
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; MEDIUMDESC_SCH-LABEL: baz:
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; MEDIUMDESC_SCH: # %bb.0:
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; MEDIUMDESC_SCH-NEXT: addi.d $sp, $sp, -16
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; MEDIUMDESC_SCH-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
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; MEDIUMDESC_SCH-NEXT: pcalau12i $a0, %desc_pc_hi20(gd)
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; MEDIUMDESC_SCH-NEXT: addi.d $a0, $a0, %desc_pc_lo12(gd)
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; MEDIUMDESC_SCH-NEXT: ld.d $ra, $a0, %desc_ld(gd)
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; MEDIUMDESC_SCH-NEXT: jirl $ra, $ra, %desc_call(gd)
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; MEDIUMDESC_SCH-NEXT: add.d $a0, $a0, $tp
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; MEDIUMDESC_SCH-NEXT: ld.d $zero, $a0, 0
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; MEDIUMDESC_SCH-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
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; MEDIUMDESC_SCH-NEXT: addi.d $sp, $sp, 16
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; MEDIUMDESC_SCH-NEXT: ret
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;
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; LARGEDESC_NO_SCH-LABEL: baz:
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; LARGEDESC_NO_SCH: # %bb.0:
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; LARGEDESC_NO_SCH-NEXT: addi.d $sp, $sp, -16
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; LARGEDESC_NO_SCH-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
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; LARGEDESC_NO_SCH-NEXT: pcalau12i $a0, %desc_pc_hi20(gd)
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; LARGEDESC_NO_SCH-NEXT: addi.d $a1, $zero, %desc_pc_lo12(gd)
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; LARGEDESC_NO_SCH-NEXT: lu32i.d $a1, %desc64_pc_lo20(gd)
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; LARGEDESC_NO_SCH-NEXT: lu52i.d $a1, $a1, %desc64_pc_hi12(gd)
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; LARGEDESC_NO_SCH-NEXT: add.d $a0, $a0, $a1
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; LARGEDESC_NO_SCH-NEXT: ld.d $ra, $a0, %desc_ld(gd)
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; LARGEDESC_NO_SCH-NEXT: jirl $ra, $ra, %desc_call(gd)
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; LARGEDESC_NO_SCH-NEXT: add.d $a0, $a0, $tp
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; LARGEDESC_NO_SCH-NEXT: ld.d $zero, $a0, 0
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; LARGEDESC_NO_SCH-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
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; LARGEDESC_NO_SCH-NEXT: addi.d $sp, $sp, 16
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; LARGEDESC_NO_SCH-NEXT: ret
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;
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; LARGEDESC_SCH-LABEL: baz:
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; LARGEDESC_SCH: # %bb.0:
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; LARGEDESC_SCH-NEXT: addi.d $sp, $sp, -16
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; LARGEDESC_SCH-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
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; LARGEDESC_SCH-NEXT: addi.d $a1, $zero, %desc_pc_lo12(gd)
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; LARGEDESC_SCH-NEXT: pcalau12i $a0, %desc_pc_hi20(gd)
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; LARGEDESC_SCH-NEXT: lu32i.d $a1, %desc64_pc_lo20(gd)
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; LARGEDESC_SCH-NEXT: lu52i.d $a1, $a1, %desc64_pc_hi12(gd)
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; LARGEDESC_SCH-NEXT: add.d $a0, $a0, $a1
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; LARGEDESC_SCH-NEXT: ld.d $ra, $a0, %desc_ld(gd)
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; LARGEDESC_SCH-NEXT: jirl $ra, $ra, %desc_call(gd)
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; LARGEDESC_SCH-NEXT: add.d $a0, $a0, $tp
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; LARGEDESC_SCH-NEXT: ld.d $zero, $a0, 0
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; LARGEDESC_SCH-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
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; LARGEDESC_SCH-NEXT: addi.d $sp, $sp, 16
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; LARGEDESC_SCH-NEXT: ret
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%v_gd = load volatile i64, ptr @gd
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ret void
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}

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