Describe C2 clock tree, remove TIMG APB clock gate node

Author: bugadani

esp-hal/src/clock/mod.rs

@@ -1201,32 +1201,23 @@ impl Clocks {
 impl Clocks {
     /// Configure the CPU clock speed.
     pub(crate) fn configure(cpu_clock_speed: CpuClock) -> Self {
-        let xtal_freq = Self::measure_xtal_frequency();
-
-        let apb_freq;
-        if cpu_clock_speed != CpuClock::default() {
-            let pll_freq = PllClock::Pll480MHz;
+        use crate::soc::clocks::{ClockTree, request_cpu_clk};
 
-            if cpu_clock_speed.mhz() <= xtal_freq.mhz() {
-                apb_freq = ApbClock::ApbFreqOther(cpu_clock_speed.mhz());
-                clocks_ll::esp32c2_rtc_update_to_xtal(xtal_freq, 1);
-                clocks_ll::esp32c2_rtc_apb_freq_update(apb_freq);
-            } else {
-                apb_freq = ApbClock::ApbFreq40MHz;
-                clocks_ll::esp32c2_rtc_bbpll_enable();
-                clocks_ll::esp32c2_rtc_bbpll_configure(xtal_freq, pll_freq);
-                clocks_ll::esp32c2_rtc_freq_to_pll_mhz(cpu_clock_speed);
-                clocks_ll::esp32c2_rtc_apb_freq_update(apb_freq);
-            }
-        } else {
-            apb_freq = ApbClock::ApbFreq40MHz;
+        // TODO: expose the whole new enum for custom options
+        match cpu_clock_speed {
+            CpuClock::_80MHz => crate::soc::clocks::CpuClock::_80MHz,
+            CpuClock::_120MHz => crate::soc::clocks::CpuClock::_120MHz,
         }
+        .configure();
 
-        Self {
-            cpu_clock: cpu_clock_speed.frequency(),
-            apb_clock: apb_freq.frequency(),
-            xtal_clock: xtal_freq.frequency(),
-        }
+        ClockTree::with(|clocks| {
+            request_cpu_clk(clocks);
+            Self {
+                cpu_clock: Rate::from_hz(crate::soc::clocks::cpu_clk_frequency(clocks)),
+                apb_clock: Rate::from_hz(crate::soc::clocks::apb_clk_frequency(clocks)),
+                xtal_clock: Rate::from_hz(crate::soc::clocks::xtl_clk_frequency(clocks)),
+            }
+        })
     }
 }
 

esp-hal/src/soc/esp32/clocks.rs

@@ -45,6 +45,7 @@ pub(crate) enum CpuClock {
 impl CpuClock {
     pub(crate) fn configure(self) {
         // Resolve presets
+        // TODO: set some defaults to RTC clocks
         let mut config = match self {
             CpuClock::_80MHz => ClockConfig {
                 xtl_clk: None,
@@ -102,12 +103,12 @@ fn detect_xtal_freq(clocks: &mut ClockTree) -> XtlClkConfig {
 
     // Just an assumption for things to not panic.
     configure_xtl_clk(clocks, XtlClkConfig::_40);
+    // TIMG0 counter is clocked from the APB clock, make sure APB_CLK == XTL_CLK
     configure_syscon_pre_div(clocks, SysconPreDivConfig(0));
     configure_cpu_clk(clocks, CpuClkConfig::Xtal);
 
-    // Without the peripheral clock, we can't write peripheral registers.
-    configure_timg0_peripheral_clock(clocks, Timg0PeripheralClockConfig::ApbClk);
-    request_timg0_peripheral_clock(clocks);
+    // By default the TIMG0 bus clock is running. Do not create a peripehral guard as dropping it
+    // would reset the timer, and it would enable its WDT.
 
     // Make sure the process doesn't time out due to some spooky configuration.
     #[cfg(not(esp32))]
@@ -146,7 +147,6 @@ fn detect_xtal_freq(clocks: &mut ClockTree) -> XtlClkConfig {
         .rtccalicfg()
         .modify(|_, w| w.rtc_cali_start().clear_bit());
     release_timg0_calibration_clock(clocks);
-    release_timg0_peripheral_clock(clocks);
 
     let mhz = (cali_value * (calibration_clock_frequency / SLOW_CLOCK_CYCLES)) / 1_000_000;
     if mhz.abs_diff(40) < mhz.abs_diff(26) {
@@ -462,10 +462,10 @@ fn configure_cpu_clk_impl(
     ets_update_cpu_frequency_rom(cpu_freq.as_mhz());
 
     let apb_freq = Rate::from_hz(apb_clk_frequency(clocks));
-    update_cpu_frequency(apb_freq);
+    update_apb_frequency(apb_freq);
 }
 
-fn update_cpu_frequency(freq: Rate) {
+fn update_apb_frequency(freq: Rate) {
     let freq_shifted = (freq.as_hz() >> 12) & 0xFFFF;
     let value = freq_shifted | (freq_shifted << 16);
     LPWR::regs()
@@ -567,19 +567,6 @@ fn configure_rtc_fast_clk_impl(
     });
 }
 
-fn enable_timg0_peripheral_clock_impl(_clocks: &mut ClockTree, _en: bool) {
-    // TODO: currently managed by PeripheralClockControl. Perhaps these function impls should be
-    // generated?
-}
-
-fn configure_timg0_peripheral_clock_impl(
-    _clocks: &mut ClockTree,
-    _old_selector: Option<Timg0PeripheralClockConfig>,
-    _new_selector: Timg0PeripheralClockConfig,
-) {
-    // TIMG on ESP32 can only use a single clock source, it doesn't need to be configured.
-}
-
 fn enable_timg0_calibration_clock_impl(_clocks: &mut ClockTree, _en: bool) {
     // Nothing to do, calibration clocks can only be selected. They are gated by the CALI_START bit,
     // which is managed by the calibration process.
@@ -605,19 +592,6 @@ fn configure_timg0_calibration_clock_impl(
         .modify(|_, w| unsafe { w.rtc_cali_clk_sel().bits(new_selector.cali_clk_sel_bits()) });
 }
 
-fn enable_timg1_peripheral_clock_impl(_clocks: &mut ClockTree, _en: bool) {
-    // TODO: currently managed by PeripheralClockControl. Perhaps these function impls should be
-    // generated?
-}
-
-fn configure_timg1_peripheral_clock_impl(
-    _clocks: &mut ClockTree,
-    _old_selector: Option<Timg0PeripheralClockConfig>,
-    _new_selector: Timg0PeripheralClockConfig,
-) {
-    // TIMG on ESP32 can only use a single clock source, it doesn't need to be configured.
-}
-
 fn enable_timg1_calibration_clock_impl(_clocks: &mut ClockTree, _en: bool) {
     // Nothing to do, calibration clocks can only be selected. They are gated by the CALI_START bit,
     // which is managed by the calibration process.