Fix formatting

Author: bugadani

esp-hal/src/clock/clocks_ll/esp32c2.rs

@@ -4,132 +4,6 @@ use crate::{
     soc::regi2c,
 };
 
-const I2C_BBPLL_OC_DCHGP_LSB: u32 = 4;
-const I2C_BBPLL_OC_DHREF_SEL_LSB: u32 = 4;
-const I2C_BBPLL_OC_DLREF_SEL_LSB: u32 = 6;
-
-pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllClock) {
-    let div_ref: u8;
-    let div7_0: u8;
-    let dr1: u8;
-    let dr3: u8;
-    let dchgp: u8;
-    let dcur: u8;
-    let dbias: u8;
-
-    // Set this register to let the digital part know 480M PLL is used
-    SYSTEM::regs()
-        .cpu_per_conf()
-        .modify(|_, w| w.pll_freq_sel().set_bit());
-
-    I2C_ANA_MST::regs().ana_conf0().modify(|_, w| {
-        w.bbpll_stop_force_high().clear_bit();
-        w.bbpll_stop_force_low().set_bit()
-    });
-
-    // Configure 480M PLL
-    match xtal_freq {
-        XtalClock::_26M => {
-            div_ref = 12;
-            div7_0 = 236;
-            dr1 = 4;
-            dr3 = 4;
-            dchgp = 0;
-            dcur = 0;
-            dbias = 2;
-        }
-        XtalClock::_40M => {
-            div_ref = 0;
-            div7_0 = 8;
-            dr1 = 0;
-            dr3 = 0;
-            dchgp = 5;
-            dcur = 3;
-            dbias = 2;
-        }
-    }
-
-    regi2c::I2C_BBPLL_REG4.write_reg(0x6b);
-
-    let i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref;
-    let i2c_bbpll_dcur =
-        (1 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
-
-    regi2c::I2C_BBPLL_OC_REF.write_reg(i2c_bbpll_lref);
-    regi2c::I2C_BBPLL_OC_DIV_REG.write_reg(div7_0);
-    regi2c::I2C_BBPLL_OC_DR1.write_field(dr1);
-    regi2c::I2C_BBPLL_OC_DR3.write_field(dr3);
-    regi2c::I2C_BBPLL_REG6.write_reg(i2c_bbpll_dcur);
-    regi2c::I2C_BBPLL_OC_VCO_DBIAS.write_field(dbias);
-
-    // WAIT CALIBRATION DONE
-    while I2C_ANA_MST::regs()
-        .ana_conf0()
-        .read()
-        .bbpll_cal_done()
-        .bit_is_clear()
-    {}
-
-    // workaround bbpll calibration might stop early
-    crate::rom::ets_delay_us(10);
-
-    // Stop BBPLL self-calibration
-    I2C_ANA_MST::regs().ana_conf0().modify(|_, w| {
-        w.bbpll_stop_force_high().set_bit();
-        w.bbpll_stop_force_low().clear_bit()
-    });
-}
-
-pub(crate) fn esp32c2_rtc_bbpll_enable() {
-    LPWR::regs().options0().modify(|_, w| {
-        w.bb_i2c_force_pd().clear_bit();
-        w.bbpll_force_pd().clear_bit();
-        w.bbpll_i2c_force_pd().clear_bit()
-    });
-}
-
-pub(crate) fn esp32c2_rtc_update_to_xtal(freq: XtalClock, div: u32) {
-    crate::rom::ets_update_cpu_frequency_rom(freq.mhz());
-
-    // Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0)
-    // first.
-    SYSTEM::regs().sysclk_conf().modify(|_, w| unsafe {
-        w.pre_div_cnt().bits(0);
-        w.pre_div_cnt().bits((div - 1) as u16)
-    });
-
-    // No need to adjust the REF_TICK
-
-    // Switch clock source
-    SYSTEM::regs()
-        .sysclk_conf()
-        .modify(|_, w| unsafe { w.soc_clk_sel().bits(0) });
-}
-
-pub(crate) fn esp32c2_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) {
-    SYSTEM::regs().sysclk_conf().modify(|_, w| unsafe {
-        w.pre_div_cnt().bits(0);
-        w.soc_clk_sel().bits(1)
-    });
-    SYSTEM::regs().cpu_per_conf().modify(|_, w| unsafe {
-        w.cpuperiod_sel().bits(match cpu_clock_speed {
-            CpuClock::_80MHz => 0,
-            CpuClock::_120MHz => 1,
-        })
-    });
-
-    crate::rom::ets_update_cpu_frequency_rom(cpu_clock_speed.mhz());
-}
-
-pub(crate) fn esp32c2_rtc_apb_freq_update(apb_freq: ApbClock) {
-    let value = ((apb_freq.hz() >> 12) & u16::MAX as u32)
-        | (((apb_freq.hz() >> 12) & u16::MAX as u32) << 16);
-
-    LPWR::regs()
-        .store5()
-        .modify(|_, w| unsafe { w.data().bits(value) });
-}
-
 // Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10,
 // 19, 20, 21, 22, 23
 const SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M: u32 = 0x78078F;

esp-metadata-generated/src/_generated_esp32.rs

@@ -1348,8 +1348,8 @@ macro_rules! define_clock_tree_types {
         /// Clock tree configuration.
         ///
         /// The fields of this struct are optional, with the following caveats:
-        /// - If `XTL_CLK` is not specified, the crystal frequency will be
-        ///   automatically detected if possible.
+        /// - If `XTL_CLK` is not specified, the crystal frequency will be automatically detected if
+        ///   possible.
         /// - The CPU and its upstream clock nodes will be set to a default configuration.
         /// - Other unspecified clock sources will not be useable by peripherals.
         #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]

esp-metadata-generated/src/_generated_esp32c2.rs

@@ -1087,8 +1087,8 @@ macro_rules! define_clock_tree_types {
         /// Clock tree configuration.
         ///
         /// The fields of this struct are optional, with the following caveats:
-        /// - If `XTL_CLK` is not specified, the crystal frequency will be
-        ///   automatically detected if possible.
+        /// - If `XTL_CLK` is not specified, the crystal frequency will be automatically detected if
+        ///   possible.
         /// - The CPU and its upstream clock nodes will be set to a default configuration.
         /// - Other unspecified clock sources will not be useable by peripherals.
         #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]

esp-metadata-generated/src/_generated_esp32c3.rs

@@ -304,8 +304,8 @@ macro_rules! define_clock_tree_types {
         /// Clock tree configuration.
         ///
         /// The fields of this struct are optional, with the following caveats:
-        /// - If `XTL_CLK` is not specified, the crystal frequency will be
-        ///   automatically detected if possible.
+        /// - If `XTL_CLK` is not specified, the crystal frequency will be automatically detected if
+        ///   possible.
         /// - The CPU and its upstream clock nodes will be set to a default configuration.
         /// - Other unspecified clock sources will not be useable by peripherals.
         #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]

esp-metadata-generated/src/_generated_esp32c6.rs

@@ -310,8 +310,8 @@ macro_rules! define_clock_tree_types {
         /// Clock tree configuration.
         ///
         /// The fields of this struct are optional, with the following caveats:
-        /// - If `XTL_CLK` is not specified, the crystal frequency will be
-        ///   automatically detected if possible.
+        /// - If `XTL_CLK` is not specified, the crystal frequency will be automatically detected if
+        ///   possible.
         /// - The CPU and its upstream clock nodes will be set to a default configuration.
         /// - Other unspecified clock sources will not be useable by peripherals.
         #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]

esp-metadata-generated/src/_generated_esp32h2.rs

@@ -295,8 +295,8 @@ macro_rules! define_clock_tree_types {
         /// Clock tree configuration.
         ///
         /// The fields of this struct are optional, with the following caveats:
-        /// - If `XTL_CLK` is not specified, the crystal frequency will be
-        ///   automatically detected if possible.
+        /// - If `XTL_CLK` is not specified, the crystal frequency will be automatically detected if
+        ///   possible.
         /// - The CPU and its upstream clock nodes will be set to a default configuration.
         /// - Other unspecified clock sources will not be useable by peripherals.
         #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]

esp-metadata-generated/src/_generated_esp32s2.rs

@@ -295,8 +295,8 @@ macro_rules! define_clock_tree_types {
         /// Clock tree configuration.
         ///
         /// The fields of this struct are optional, with the following caveats:
-        /// - If `XTL_CLK` is not specified, the crystal frequency will be
-        ///   automatically detected if possible.
+        /// - If `XTL_CLK` is not specified, the crystal frequency will be automatically detected if
+        ///   possible.
         /// - The CPU and its upstream clock nodes will be set to a default configuration.
         /// - Other unspecified clock sources will not be useable by peripherals.
         #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]

esp-metadata-generated/src/_generated_esp32s3.rs

@@ -298,8 +298,8 @@ macro_rules! define_clock_tree_types {
         /// Clock tree configuration.
         ///
         /// The fields of this struct are optional, with the following caveats:
-        /// - If `XTL_CLK` is not specified, the crystal frequency will be
-        ///   automatically detected if possible.
+        /// - If `XTL_CLK` is not specified, the crystal frequency will be automatically detected if
+        ///   possible.
         /// - The CPU and its upstream clock nodes will be set to a default configuration.
         /// - Other unspecified clock sources will not be useable by peripherals.
         #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]

esp-metadata/src/cfg/soc.rs

@@ -270,8 +270,8 @@ impl SystemClocks {
                     /// Clock tree configuration.
                     ///
                     /// The fields of this struct are optional, with the following caveats:
-                    /// - If `XTL_CLK` is not specified, the crystal frequency will be
-                    ///   automatically detected if possible.
+                    /// - If `XTL_CLK` is not specified, the crystal frequency will be automatically detected if
+                    ///   possible.
                     /// - The CPU and its upstream clock nodes will be set to a default configuration.
                     /// - Other unspecified clock sources will not be useable by peripherals.
                     #[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]

xtask/src/lib.rs

@@ -824,14 +824,17 @@ fn format_package_path(
     }
 
     cargo_args.push("--".into());
-    if let Some(rules) = format_rules {
-        cargo_args.push(format!("--config-path={}", rules.display()));
+    let mut config_file_path = PathBuf::new();
+    let config_file = if let Some(rules) = format_rules {
+        rules
     } else {
-        cargo_args.push(format!(
-            "--config-path={}/rustfmt.toml",
-            workspace.display()
-        ));
-    }
+        config_file_path = package_path.join("rustfmt.toml");
+        if !config_file_path.exists() {
+            config_file_path = workspace.join("rustfmt.toml");
+        }
+        &config_file_path
+    };
+    cargo_args.push(format!("--config-path={}", config_file.display()));
     cargo_args.extend(source_files);
 
     log::debug!("{cargo_args:#?}");