Fix undef-bug.ll phi case

Author: Michael Skvortsov

llvm/lib/Target/TVM/TVMStack.cpp

@@ -288,6 +288,15 @@ void Stack::printElement(raw_ostream &OS, const StackVreg &Vreg) const {
     OS << "x";
     return;
   }
+  unsigned Reg = Vreg.VirtReg;
+  if (Reg &&
+      !TargetRegisterInfo::isStackSlot(Reg) &&
+      !TargetRegisterInfo::isVirtualRegister(Reg) &&
+      TRI &&
+      Reg >= TRI->getNumRegs()) {
+    OS << "?";
+    return;
+  }
   OS << printReg(Vreg.VirtReg, TRI, 0, MRI);
   if (Vreg.DbgVar) {
     OS << "(" << Vreg.DbgVar->getName() << ")";

llvm/lib/Target/TVM/TVMStackFixup.cpp

@@ -95,7 +95,8 @@ StackFixup StackFixup::Diff(const Stack &to, const Stack &from) {
 
   // Generate changes to re-order
   assert(llvm::size(unmaskedTo) == llvm::size(curStack));
-  generateVagonXchgs(rv, curStack, unmaskedTo);
+  if (llvm::size(curStack) > 0)
+    generateVagonXchgs(rv, curStack, unmaskedTo);
   rv.optimize();
   return rv;
 }
@@ -225,6 +226,7 @@ void StackFixup::generateVagonXchgs(StackFixup &rv, const Stack &from,
 
   auto Tr = Train::build(curStack, to);
   auto restVagons = llvm::make_range(Tr.Vagons.begin(), Tr.Vagons.end());
+  assert(restVagons.begin() != restVagons.end());
   auto V = *restVagons.begin();
   if (V.DeepIdx + 1 == Sz && !V.Inverted) {
     restVagons = drop_begin(restVagons, 1);