Weight Pruning on FPGA

[Smitashree-code]

I have applied sparsity API weight pruning and synthesized both pruned and unpruned models using hls4ml targeting a Xilinx FPGA. The pruned model achieved an 11% reduction in DSP48 usage, indicating reduced multiply-accumulate (MAC) operations.

However, the overall reduction in flip-flops (FFs) and look-up tables (LUTs) was minimal (<2%), and BRAM usage slightly increased.