arc64: gdb: Add support of prologue tests for HS5x

Remove tests for unsupported SUB_S c,b,u3 instruction and
mark LP tests as xfail for HS5x targets. LP is supported
only by HS5x in ARCv3 but it's not implemented in GNU
tools yet.

In addition make ENTER tests save 13 general purpose registers
instead of 14. ARCv3's ENTER instruction can save GPRs from
R14 to R27 (ARCv2's one saves from R13 to R26). The last one
is FP (frame pointer) and it's possible to save FP twice:

    enter_s (16 + 14)

16 stands for FP bit and 14 stands for R14-R27 set. That
behavior is documented in PRM:

    This use case is not illegal but serves no useful purpose.

However, it's not recommended to use ENTER that way and saving
FP twice can break GDB's frame unwinder (information about saved
registers may be incomplete). It's necessary to rewrite
unwinder's logic to make him detect FP which is saved twice.

Signed-off-by: Yuriy Kolerov <[email protected]>

Author: kolerov

gdb/testsuite/gdb.arch/arc-analyze-prologue.S

@@ -155,14 +155,18 @@ noncallee_saved_regs_gp_push:
 	add	sp,sp,8
 
 ; LP_COUNT is treated like a normal register.
+; HS6x does not have loop instructions and registers but HS5x does. However,
+; it's not supported by GNU tools yet.
 
+#ifndef __ARCV3__
 .align 4
 noncallee_saved_regs_lp_count:
 	push	r25
 	push	lp_count
 	add	r0, r1, r2
 	j.d	[blink]
 	add	sp,sp,8
+#endif
 
 ; BLINK is saved, but after an instruction that is not part of prologue.
 ; Currently arc_analyze_prologue stops analisys at the first intstruction
@@ -277,7 +281,11 @@ enter_s_r15:
 
 .align 4
 enter_s_all:
+#ifdef __ARCV3__
+	enter_s	(32 + 16 + 13)
+#else
 	enter_s	(32 + 16 + 14)
+#endif
 	add	r0,r1,r2
 	j.d	[blink]
 	add	sp,sp,64
@@ -415,7 +423,10 @@ predicated_insn:
 	j	[blink]
 
 ; Loops should halt prologue analysis.
+; HS6x does not have loop instructions and registers but HS5x does. However,
+; it's not supported by GNU tools yet.
 
+#ifndef __ARCV3__
 .align 4
 loop_in_prologue:
 	push r25
@@ -430,6 +441,7 @@ loop_in_prologue:
 	add sp,sp,8
 	pop r25
 	j   [blink]
+#endif
 
 ; Store of a constant value (not a register).
 
@@ -660,14 +672,17 @@ push_s_prologue:
 	j	[blink]
 
 ; Check for SUB_S c,b,u3 presence - it doesn't affect prologue.
+; ARCv3 targets does not have this instruction.
 
+#ifndef __ARCV3__
 .align 4
 sub_s_cbu3:
 	push_s	r13
 	sub_s	r0,r1,3
 	push_s	r14
 	add	sp,sp,8
 	j	[blink]
+#endif
 
 ; Check for SUB_S b,b,c presence - it doesn't affect prologue.
 
@@ -844,7 +859,9 @@ main:
 	bl	@noncallee_saved_regs_r12_push
 	bl	@noncallee_saved_regs_r2_push
 	bl	@noncallee_saved_regs_gp_push
+#ifndef __ARCV3__
 	bl	@noncallee_saved_regs_lp_count
+#endif
 	bl	@noncallee_saved_regs_blink_out_of_prologue
 	bl	@arg_regs_fp
 	bl	@arg_regs_fp_mov_s
@@ -862,7 +879,9 @@ main:
 	bl	@jump_in_prologue
 	bl	@cond_jump_in_prologue
 	bl	@predicated_insn
+#ifndef __ARCV3__
 	bl	@loop_in_prologue
+#endif
 	bl	@store_constant
 	bl	@st_c_limm
 	bl	@st_ab_writeback
@@ -881,7 +900,9 @@ main:
 	bl	@r_relative_store_unknown
 	bl	@st_s_r0gp
 	bl	@push_s_prologue
+#ifndef __ARCV3__
 	bl	@sub_s_cbu3
+#endif
 	bl	@sub_s_bbc
 	bl	@sub_s_bbu5
 	bl	@sub_0bc

gdb/testsuite/gdb.arch/arc-analyze-prologue.exp

@@ -33,6 +33,27 @@ if ![runto_main] {
     return 0
 }
 
+proc get_arc_defines { } {
+    global target_info board_info decimal
+
+    set target_board [target_info name]
+    set compiler [board_info $target_board compiler]
+    set multilib ""
+
+    if { [board_info $target_board exists multilib_flags] } {
+	set multilib "[board_info $target_board multilib_flags]"
+    }
+
+    set options "$multilib -dM -E -"
+    return [eval exec "$compiler $options < /dev/null"]
+}
+
+set arc_defines [get_arc_defines]
+regexp "#define __SIZEOF_POINTER__ ($decimal)" $arc_defines -> arc_reg_size
+set is_arcv3 [regexp "__ARCV3__" $arc_defines]
+set is_arcv3_arc32 [regexp "__ARC64_ARCH32__" $arc_defines]
+set is_arcv3_arc64 [regexp "__ARC64_ARCH64__" $arc_defines]
+
 # Convert list of saved registers and their offsets to a GDB string.
 proc saved_regs_to_str { savedregs funcname } {
     set str ""
@@ -109,7 +130,15 @@ prologue_test "noncallee_saved_regs_r12_st" { {r12 0} {r13 4} }
 prologue_test "noncallee_saved_regs_r12_push" { {r12 0} {r13 4} }
 prologue_test "noncallee_saved_regs_r2_push" { {r2 0} {r13 4} }
 prologue_test "noncallee_saved_regs_gp_push" { {r25 4} {gp 0} }
-prologue_test "noncallee_saved_regs_lp_count" { {r25 4} {lp_count 0} }
+# HS6x does not have loop instructions and registers but HS5x does. However,
+# it's not supported by GNU tools yet.
+if { !$is_arcv3 } {
+    prologue_test "noncallee_saved_regs_lp_count" { {r25 4} {lp_count 0} }
+} else {
+    if { $is_arcv3_arc32 } {
+	xfail "noncallee_saved_regs_lp_count: loops are not implemented for HS5x yet"
+    }
+}
 prologue_test "noncallee_saved_regs_blink_out_of_prologue" { {r25 8} {gp 4} \
     {blink 0}}
 # Argument registers are not reported as "saved" regs.
@@ -120,14 +149,28 @@ prologue_test "enter_s_nop"
 prologue_test "enter_s_blink" { {blink 0} }
 prologue_test "enter_s_fp" { {fp 0} } 0
 # Layout of registers as stored by enter_s doesn't conform to ARC ABI.
-prologue_test "enter_s_r13" { {r13 4} {fp 8} {blink 0} } 0
-prologue_test "enter_s_r15" { {r13 0} {r14 4} {r15 8} } 0
+if { $is_arcv3 } {
+    prologue_test "enter_s_r13" { {r14 8} {fp 0} {blink 4} } 0
+} else {
+    prologue_test "enter_s_r13" { {r13 4} {fp 8} {blink 0} } 0
+}
+if { $is_arcv3 } {
+    prologue_test "enter_s_r15" { {r14 0} {r15 4} {r16 8} } 0
+} else {
+    prologue_test "enter_s_r15" { {r13 0} {r14 4} {r15 8} } 0
+}
 # This enter_s saves GP, however because it is not a "calle-saved register",
 # GDB will not report it as "saved register" (but maybe it should). GP is at
 # offset 56.
-prologue_test "enter_s_all" { {r13 4} {r14 8} {r15 12} {r16 16} {r17 20} \
-    {r18 24} {r19 28} {r20 32} {r21 36} {r22 40} {r23 44} {r24 48} {r25 52} \
-    {gp 56} {fp 60} {blink 0} } 0
+if { $is_arcv3 } {
+    prologue_test "enter_s_all" { {r14 8} {r15 12} {r16 16} {r17 20} {r18 24} \
+	{r19 28} {r20 32} {r21 36} {r22 40} {r23 44} {r24 48} {r25 52} \
+	{r26 56} {fp 0} {blink 4} } 0
+} else {
+    prologue_test "enter_s_all" { {r13 4} {r14 8} {r15 12} {r16 16} {r17 20} \
+	{r18 24} {r19 28} {r20 32} {r21 36} {r22 40} {r23 44} {r24 48} \
+	{r25 52} {gp 56} {fp 60} {blink 0} } 0
+}
 
 # Test more levels of backtrace.
 gdb_breakpoint nested_prologue_inner temporary
@@ -154,7 +197,15 @@ prologue_test "cond_branch_in_prologue" { {r13 4} }
 prologue_test "jump_in_prologue" { {r13 0} }
 prologue_test "cond_jump_in_prologue" { {r13 4} }
 prologue_test "predicated_insn" { {r13 8} {r15 0} }
-prologue_test "loop_in_prologue" { {r25 4} {lp_count 0} }
+# HS6x does not have loop instructions and registers but HS5x does. However,
+# it's not supported by GNU tools yet.
+if { !$is_arcv3 } {
+    prologue_test "loop_in_prologue" { {r25 4} {lp_count 0} }
+} else {
+    if { $is_arcv3_arc32 } {
+	xfail "loop_in_prologue: loops are not implemented for HS5x yet"
+    }
+}
 prologue_test "store_constant" { {r13 8} {r14 4} }
 prologue_test "st_c_limm" { {r15 0} }
 prologue_test "st_ab_writeback" { {r13 8} {r14 4} {r15 0} }
@@ -174,7 +225,10 @@ prologue_test "r_relative_store_unknown" { {r13 8} }
 prologue_test "st_s_r0gp" { {r13 8} }
 prologue_test "push_s_prologue" { {r0 28} {r1 16} {r2 4} {r3 24} {r12 32} \
     {r13 20} {r14 12} {r15 8} {blink 0}}
-prologue_test "sub_s_cbu3" { {r13 4} {r14 0} }
+# ARCv3 targets does not have this instruction.
+if { !$is_arcv3 } {
+    prologue_test "sub_s_cbu3" { {r13 4} {r14 0} }
+}
 prologue_test "sub_s_bbc" { {r1 4} {r13 12} {r14 0} }
 prologue_test "sub_s_bbu5" { {r13 8} {r14 0} }
 prologue_test "sub_0bc" { {r13 4} {r14 0} }